3 * athlon / K7 / K8 / Family 10h model-specific MSR operations
5 * @remark Copyright 2002-2009 OProfile authors
6 * @remark Read the file COPYING
9 * @author Philippe Elie
10 * @author Graydon Hoare
11 * @author Robert Richter <robert.richter@amd.com>
12 * @author Barry Kasindorf <barry.kasindorf@amd.com>
13 * @author Jason Yeh <jason.yeh@amd.com>
14 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
17 #include <linux/oprofile.h>
18 #include <linux/device.h>
19 #include <linux/pci.h>
20 #include <linux/percpu.h>
22 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/cpufeature.h>
29 #include "op_x86_model.h"
30 #include "op_counter.h"
32 #define NUM_COUNTERS 4
33 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
34 #define NUM_VIRT_COUNTERS 32
36 #define NUM_VIRT_COUNTERS NUM_COUNTERS
39 #define OP_EVENT_MASK 0x0FFF
40 #define OP_CTR_OVERFLOW (1ULL<<31)
42 #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
44 static unsigned long reset_value[NUM_VIRT_COUNTERS];
46 #define IBS_FETCH_SIZE 6
47 #define IBS_OP_SIZE 12
52 unsigned long op_enabled;
53 unsigned long fetch_enabled;
54 unsigned long max_cnt_fetch;
55 unsigned long max_cnt_op;
56 unsigned long rand_en;
57 unsigned long dispatched_ops;
58 unsigned long branch_target;
64 unsigned long sample_size;
67 static struct ibs_config ibs_config;
68 static struct ibs_state ibs_state;
71 * IBS cpuid feature detection
74 #define IBS_CPUID_FEATURES 0x8000001b
77 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
78 * bit 0 is used to indicate the existence of IBS.
80 #define IBS_CAPS_AVAIL (1U<<0)
81 #define IBS_CAPS_FETCHSAM (1U<<1)
82 #define IBS_CAPS_OPSAM (1U<<2)
83 #define IBS_CAPS_RDWROPCNT (1U<<3)
84 #define IBS_CAPS_OPCNT (1U<<4)
85 #define IBS_CAPS_BRNTRGT (1U<<5)
86 #define IBS_CAPS_OPCNTEXT (1U<<6)
88 #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
96 #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
97 #define IBSCTL_LVT_OFFSET_MASK 0x0F
100 * IBS randomization macros
102 #define IBS_RANDOM_BITS 12
103 #define IBS_RANDOM_MASK ((1ULL << IBS_RANDOM_BITS) - 1)
104 #define IBS_RANDOM_MAXCNT_OFFSET (1ULL << (IBS_RANDOM_BITS - 5))
106 static u32 get_ibs_caps(void)
109 unsigned int max_level;
111 if (!boot_cpu_has(X86_FEATURE_IBS))
114 /* check IBS cpuid feature flags */
115 max_level = cpuid_eax(0x80000000);
116 if (max_level < IBS_CPUID_FEATURES)
117 return IBS_CAPS_DEFAULT;
119 ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
120 if (!(ibs_caps & IBS_CAPS_AVAIL))
121 /* cpuid flags not valid */
122 return IBS_CAPS_DEFAULT;
128 * 16-bit Linear Feedback Shift Register (LFSR)
131 * Feedback polynomial = X + X + X + X + 1
133 static unsigned int lfsr_random(void)
135 static unsigned int lfsr_value = 0xF00D;
138 /* Compute next bit to shift in */
139 bit = ((lfsr_value >> 0) ^
142 (lfsr_value >> 5)) & 0x0001;
144 /* Advance to next register value */
145 lfsr_value = (lfsr_value >> 1) | (bit << 15);
151 * IBS software randomization
153 * The IBS periodic op counter is randomized in software. The lower 12
154 * bits of the 20 bit counter are randomized. IbsOpCurCnt is
155 * initialized with a 12 bit random value.
157 static inline u64 op_amd_randomize_ibs_op(u64 val)
159 unsigned int random = lfsr_random();
161 if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
163 * Work around if the hw can not write to IbsOpCurCnt
165 * Randomize the lower 8 bits of the 16 bit
166 * IbsOpMaxCnt [15:0] value in the range of -128 to
167 * +127 by adding/subtracting an offset to the
168 * maximum count (IbsOpMaxCnt).
170 * To avoid over or underflows and protect upper bits
171 * starting at bit 16, the initial value for
172 * IbsOpMaxCnt must fit in the range from 0x0081 to
175 val += (s8)(random >> 4);
177 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
183 op_amd_handle_ibs(struct pt_regs * const regs,
184 struct op_msrs const * const msrs)
187 struct op_entry entry;
192 if (ibs_config.fetch_enabled) {
193 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
194 if (ctl & IBS_FETCH_VAL) {
195 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
196 oprofile_write_reserve(&entry, regs, val,
197 IBS_FETCH_CODE, IBS_FETCH_SIZE);
198 oprofile_add_data64(&entry, val);
199 oprofile_add_data64(&entry, ctl);
200 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
201 oprofile_add_data64(&entry, val);
202 oprofile_write_commit(&entry);
204 /* reenable the IRQ */
205 ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
206 ctl |= IBS_FETCH_ENABLE;
207 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
211 if (ibs_config.op_enabled) {
212 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
213 if (ctl & IBS_OP_VAL) {
214 rdmsrl(MSR_AMD64_IBSOPRIP, val);
215 oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE,
216 ibs_state.sample_size);
217 oprofile_add_data64(&entry, val);
218 rdmsrl(MSR_AMD64_IBSOPDATA, val);
219 oprofile_add_data64(&entry, val);
220 rdmsrl(MSR_AMD64_IBSOPDATA2, val);
221 oprofile_add_data64(&entry, val);
222 rdmsrl(MSR_AMD64_IBSOPDATA3, val);
223 oprofile_add_data64(&entry, val);
224 rdmsrl(MSR_AMD64_IBSDCLINAD, val);
225 oprofile_add_data64(&entry, val);
226 rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
227 oprofile_add_data64(&entry, val);
228 if (ibs_state.branch_target) {
229 rdmsrl(MSR_AMD64_IBSBRTARGET, val);
230 oprofile_add_data(&entry, (unsigned long)val);
232 oprofile_write_commit(&entry);
234 /* reenable the IRQ */
235 ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
236 wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
241 static inline void op_amd_start_ibs(void)
248 memset(&ibs_state, 0, sizeof(ibs_state));
251 * Note: Since the max count settings may out of range we
252 * write back the actual used values so that userland can read
256 if (ibs_config.fetch_enabled) {
257 val = ibs_config.max_cnt_fetch >> 4;
258 val = min(val, IBS_FETCH_MAX_CNT);
259 ibs_config.max_cnt_fetch = val << 4;
260 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
261 val |= IBS_FETCH_ENABLE;
262 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
265 if (ibs_config.op_enabled) {
266 val = ibs_config.max_cnt_op >> 4;
267 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
269 * IbsOpCurCnt not supported. See
270 * op_amd_randomize_ibs_op() for details.
272 val = clamp(val, 0x0081ULL, 0xFF80ULL);
273 ibs_config.max_cnt_op = val << 4;
276 * The start value is randomized with a
277 * positive offset, we need to compensate it
278 * with the half of the randomized range. Also
281 val += IBS_RANDOM_MAXCNT_OFFSET;
282 if (ibs_caps & IBS_CAPS_OPCNTEXT)
283 val = min(val, IBS_OP_MAX_CNT_EXT);
285 val = min(val, IBS_OP_MAX_CNT);
286 ibs_config.max_cnt_op =
287 (val - IBS_RANDOM_MAXCNT_OFFSET) << 4;
289 val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT);
290 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
291 val |= IBS_OP_ENABLE;
292 ibs_state.ibs_op_ctl = val;
293 ibs_state.sample_size = IBS_OP_SIZE;
294 if (ibs_config.branch_target) {
295 ibs_state.branch_target = 1;
296 ibs_state.sample_size++;
298 val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
299 wrmsrl(MSR_AMD64_IBSOPCTL, val);
303 static void op_amd_stop_ibs(void)
308 if (ibs_config.fetch_enabled)
309 /* clear max count and enable */
310 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
312 if (ibs_config.op_enabled)
313 /* clear max count and enable */
314 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
317 static inline int eilvt_is_available(int offset)
319 /* check if we may assign a vector */
320 return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
323 static inline int ibs_eilvt_valid(void)
328 rdmsrl(MSR_AMD64_IBSCTL, val);
329 if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
330 pr_err(FW_BUG "cpu %d, invalid IBS "
331 "interrupt offset %d (MSR%08X=0x%016llx)",
332 smp_processor_id(), offset,
333 MSR_AMD64_IBSCTL, val);
337 offset = val & IBSCTL_LVT_OFFSET_MASK;
339 if (eilvt_is_available(offset))
342 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d "
343 "not available (MSR%08X=0x%016llx)",
344 smp_processor_id(), offset,
345 MSR_AMD64_IBSCTL, val);
350 static inline int get_ibs_offset(void)
354 rdmsrl(MSR_AMD64_IBSCTL, val);
355 if (!(val & IBSCTL_LVT_OFFSET_VALID))
358 return val & IBSCTL_LVT_OFFSET_MASK;
361 static void setup_APIC_ibs(void)
365 offset = get_ibs_offset();
369 if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
372 pr_warn("oprofile: IBS APIC setup failed on cpu #%d\n",
376 static void clear_APIC_ibs(void)
380 offset = get_ibs_offset();
382 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
385 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
387 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
388 struct op_msrs const * const msrs)
393 /* enable active counters */
394 for (i = 0; i < NUM_COUNTERS; ++i) {
395 int virt = op_x86_phys_to_virt(i);
396 if (!reset_value[virt])
398 rdmsrl(msrs->controls[i].addr, val);
399 val &= model->reserved;
400 val |= op_x86_get_ctrl(model, &counter_config[virt]);
401 wrmsrl(msrs->controls[i].addr, val);
407 /* functions for op_amd_spec */
409 static void op_amd_shutdown(struct op_msrs const * const msrs)
413 for (i = 0; i < NUM_COUNTERS; ++i) {
414 if (!msrs->counters[i].addr)
416 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
417 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
421 static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
425 for (i = 0; i < NUM_COUNTERS; i++) {
426 if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
428 if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
429 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
432 /* both registers must be reserved */
433 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
434 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
437 if (!counter_config[i].enabled)
439 op_x86_warn_reserved(i);
440 op_amd_shutdown(msrs);
447 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
448 struct op_msrs const * const msrs)
453 /* setup reset_value */
454 for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
455 if (counter_config[i].enabled
456 && msrs->counters[op_x86_virt_to_phys(i)].addr)
457 reset_value[i] = counter_config[i].count;
462 /* clear all counters */
463 for (i = 0; i < NUM_COUNTERS; ++i) {
464 if (!msrs->controls[i].addr)
466 rdmsrl(msrs->controls[i].addr, val);
467 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
468 op_x86_warn_in_use(i);
469 val &= model->reserved;
470 wrmsrl(msrs->controls[i].addr, val);
472 * avoid a false detection of ctr overflows in NMI
475 wrmsrl(msrs->counters[i].addr, -1LL);
478 /* enable active counters */
479 for (i = 0; i < NUM_COUNTERS; ++i) {
480 int virt = op_x86_phys_to_virt(i);
481 if (!reset_value[virt])
484 /* setup counter registers */
485 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
487 /* setup control registers */
488 rdmsrl(msrs->controls[i].addr, val);
489 val &= model->reserved;
490 val |= op_x86_get_ctrl(model, &counter_config[virt]);
491 wrmsrl(msrs->controls[i].addr, val);
498 static void op_amd_cpu_shutdown(void)
504 static int op_amd_check_ctrs(struct pt_regs * const regs,
505 struct op_msrs const * const msrs)
510 for (i = 0; i < NUM_COUNTERS; ++i) {
511 int virt = op_x86_phys_to_virt(i);
512 if (!reset_value[virt])
514 rdmsrl(msrs->counters[i].addr, val);
515 /* bit is clear if overflowed: */
516 if (val & OP_CTR_OVERFLOW)
518 oprofile_add_sample(regs, virt);
519 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
522 op_amd_handle_ibs(regs, msrs);
524 /* See op_model_ppro.c */
528 static void op_amd_start(struct op_msrs const * const msrs)
533 for (i = 0; i < NUM_COUNTERS; ++i) {
534 if (!reset_value[op_x86_phys_to_virt(i)])
536 rdmsrl(msrs->controls[i].addr, val);
537 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
538 wrmsrl(msrs->controls[i].addr, val);
544 static void op_amd_stop(struct op_msrs const * const msrs)
550 * Subtle: stop on all counters to avoid race with setting our
553 for (i = 0; i < NUM_COUNTERS; ++i) {
554 if (!reset_value[op_x86_phys_to_virt(i)])
556 rdmsrl(msrs->controls[i].addr, val);
557 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
558 wrmsrl(msrs->controls[i].addr, val);
564 static int setup_ibs_ctl(int ibs_eilvt_off)
566 struct pci_dev *cpu_cfg;
573 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
574 PCI_DEVICE_ID_AMD_10H_NB_MISC,
579 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
580 | IBSCTL_LVT_OFFSET_VALID);
581 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
582 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
583 pci_dev_put(cpu_cfg);
584 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
585 "IBSCTL = 0x%08x\n", value);
591 printk(KERN_DEBUG "No CPU node configured for IBS\n");
598 static int force_ibs_eilvt_setup(void)
603 /* find the next free available EILVT entry */
604 for (i = 1; i < 4; i++) {
605 if (!eilvt_is_available(i))
607 ret = setup_ibs_ctl(i);
613 printk(KERN_DEBUG "No EILVT entry available\n");
618 static int __init_ibs_nmi(void)
622 if (ibs_eilvt_valid())
625 ret = force_ibs_eilvt_setup();
629 if (!ibs_eilvt_valid())
632 pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
637 /* initialize the APIC for the IBS interrupts if available */
638 static void init_ibs(void)
640 ibs_caps = get_ibs_caps();
645 if (__init_ibs_nmi()) {
650 printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
654 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
656 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
661 /* architecture specific files */
662 if (create_arch_files)
663 ret = create_arch_files(sb, root);
671 /* model specific files */
673 /* setup some reasonable defaults */
674 memset(&ibs_config, 0, sizeof(ibs_config));
675 ibs_config.max_cnt_fetch = 250000;
676 ibs_config.max_cnt_op = 250000;
678 if (ibs_caps & IBS_CAPS_FETCHSAM) {
679 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
680 oprofilefs_create_ulong(sb, dir, "enable",
681 &ibs_config.fetch_enabled);
682 oprofilefs_create_ulong(sb, dir, "max_count",
683 &ibs_config.max_cnt_fetch);
684 oprofilefs_create_ulong(sb, dir, "rand_enable",
685 &ibs_config.rand_en);
688 if (ibs_caps & IBS_CAPS_OPSAM) {
689 dir = oprofilefs_mkdir(sb, root, "ibs_op");
690 oprofilefs_create_ulong(sb, dir, "enable",
691 &ibs_config.op_enabled);
692 oprofilefs_create_ulong(sb, dir, "max_count",
693 &ibs_config.max_cnt_op);
694 if (ibs_caps & IBS_CAPS_OPCNT)
695 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
696 &ibs_config.dispatched_ops);
697 if (ibs_caps & IBS_CAPS_BRNTRGT)
698 oprofilefs_create_ulong(sb, dir, "branch_target",
699 &ibs_config.branch_target);
705 static int op_amd_init(struct oprofile_operations *ops)
708 create_arch_files = ops->create_files;
709 ops->create_files = setup_ibs_files;
713 struct op_x86_model_spec op_amd_spec = {
714 .num_counters = NUM_COUNTERS,
715 .num_controls = NUM_COUNTERS,
716 .num_virt_counters = NUM_VIRT_COUNTERS,
717 .reserved = MSR_AMD_EVENTSEL_RESERVED,
718 .event_mask = OP_EVENT_MASK,
720 .fill_in_addresses = &op_amd_fill_in_addresses,
721 .setup_ctrs = &op_amd_setup_ctrs,
722 .cpu_down = &op_amd_cpu_shutdown,
723 .check_ctrs = &op_amd_check_ctrs,
724 .start = &op_amd_start,
725 .stop = &op_amd_stop,
726 .shutdown = &op_amd_shutdown,
727 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
728 .switch_ctrl = &op_mux_switch_ctrl,