arch/x86/oprofile/op_model_amd.c

   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf
  13  */
  14
  15 #include <linux/oprofile.h>
  16 #include <linux/device.h>
  17 #include <linux/pci.h>
  18
  19 #include <asm/ptrace.h>
  20 #include <asm/msr.h>
  21 #include <asm/nmi.h>
  22
  23 #include "op_x86_model.h"
  24 #include "op_counter.h"
  25 #include "../../../drivers/oprofile/cpu_buffer.h"
  26
  27 #define NUM_COUNTERS 4
  28 #define NUM_CONTROLS 4
  29
  30 #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
  31 #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
  32 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
  33 #define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
  34
  35 #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
  36 #define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
  37 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
  38 #define CTRL_SET_ACTIVE(n) (n |= (1<<22))
  39 #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
  40 #define CTRL_CLEAR_LO(x) (x &= (1<<21))
  41 #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
  42 #define CTRL_SET_ENABLE(val) (val |= 1<<20)
  43 #define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
  44 #define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
  45 #define CTRL_SET_UM(val, m) (val |= (m << 8))
  46 #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
  47 #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
  48 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
  49 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
  50
  51 static unsigned long reset_value[NUM_COUNTERS];
  52
  53 #ifdef CONFIG_OPROFILE_IBS
  54
  55 /* IbsFetchCtl bits/masks */
  56 #define IBS_FETCH_HIGH_VALID_BIT        (1UL << 17)     /* bit 49 */
  57 #define IBS_FETCH_HIGH_ENABLE           (1UL << 16)     /* bit 48 */
  58 #define IBS_FETCH_LOW_MAX_CNT_MASK      0x0000FFFFUL    /* MaxCnt mask */
  59
  60 /*IbsOpCtl bits */
  61 #define IBS_OP_LOW_VALID_BIT            (1ULL<<18)      /* bit 18 */
  62 #define IBS_OP_LOW_ENABLE               (1ULL<<17)      /* bit 17 */
  63
  64 /*
  65  * The function interface needs to be fixed, something like add
  66  * data. Should then be added to linux/oprofile.h.
  67  */
  68 extern
  69 void oprofile_add_data(struct op_entry *entry, struct pt_regs * const regs,
  70                        unsigned long pc, int code, int size);
  71
  72 #define IBS_FETCH_SIZE  6
  73 #define IBS_OP_SIZE     12
  74
  75 static int has_ibs;     /* AMD Family10h and later */
  76
  77 struct op_ibs_config {
  78         unsigned long op_enabled;
  79         unsigned long fetch_enabled;
  80         unsigned long max_cnt_fetch;
  81         unsigned long max_cnt_op;
  82         unsigned long rand_en;
  83         unsigned long dispatched_ops;
  84 };
  85
  86 static struct op_ibs_config ibs_config;
  87
  88 #endif
  89
  90 /* functions for op_amd_spec */
  91
  92 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
  93 {
  94         int i;
  95
  96         for (i = 0; i < NUM_COUNTERS; i++) {
  97                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
  98                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
  99                 else
 100                         msrs->counters[i].addr = 0;
 101         }
 102
 103         for (i = 0; i < NUM_CONTROLS; i++) {
 104                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
 105                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
 106                 else
 107                         msrs->controls[i].addr = 0;
 108         }
 109 }
 110
 111
 112 static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
 113 {
 114         unsigned int low, high;
 115         int i;
 116
 117         /* clear all counters */
 118         for (i = 0 ; i < NUM_CONTROLS; ++i) {
 119                 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
 120                         continue;
 121                 CTRL_READ(low, high, msrs, i);
 122                 CTRL_CLEAR_LO(low);
 123                 CTRL_CLEAR_HI(high);
 124                 CTRL_WRITE(low, high, msrs, i);
 125         }
 126
 127         /* avoid a false detection of ctr overflows in NMI handler */
 128         for (i = 0; i < NUM_COUNTERS; ++i) {
 129                 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
 130                         continue;
 131                 CTR_WRITE(1, msrs, i);
 132         }
 133
 134         /* enable active counters */
 135         for (i = 0; i < NUM_COUNTERS; ++i) {
 136                 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
 137                         reset_value[i] = counter_config[i].count;
 138
 139                         CTR_WRITE(counter_config[i].count, msrs, i);
 140
 141                         CTRL_READ(low, high, msrs, i);
 142                         CTRL_CLEAR_LO(low);
 143                         CTRL_CLEAR_HI(high);
 144                         CTRL_SET_ENABLE(low);
 145                         CTRL_SET_USR(low, counter_config[i].user);
 146                         CTRL_SET_KERN(low, counter_config[i].kernel);
 147                         CTRL_SET_UM(low, counter_config[i].unit_mask);
 148                         CTRL_SET_EVENT_LOW(low, counter_config[i].event);
 149                         CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
 150                         CTRL_SET_HOST_ONLY(high, 0);
 151                         CTRL_SET_GUEST_ONLY(high, 0);
 152
 153                         CTRL_WRITE(low, high, msrs, i);
 154                 } else {
 155                         reset_value[i] = 0;
 156                 }
 157         }
 158 }
 159
 160 #ifdef CONFIG_OPROFILE_IBS
 161
 162 static inline int
 163 op_amd_handle_ibs(struct pt_regs * const regs,
 164                   struct op_msrs const * const msrs)
 165 {
 166         u32 low, high;
 167         u64 msr;
 168         struct op_entry entry;
 169
 170         if (!has_ibs)
 171                 return 1;
 172
 173         if (ibs_config.fetch_enabled) {
 174                 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 175                 if (high & IBS_FETCH_HIGH_VALID_BIT) {
 176                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr);
 177                         oprofile_add_data(&entry, regs, msr, IBS_FETCH_CODE,
 178                                           IBS_FETCH_SIZE);
 179                         op_cpu_buffer_add_data(&entry, (u32)msr);
 180                         op_cpu_buffer_add_data(&entry, (u32)(msr >> 32));
 181                         op_cpu_buffer_add_data(&entry, low);
 182                         op_cpu_buffer_add_data(&entry, high);
 183                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr);
 184                         op_cpu_buffer_add_data(&entry, (u32)msr);
 185                         op_cpu_buffer_add_data(&entry, (u32)(msr >> 32));
 186                         op_cpu_buffer_write_commit(&entry);
 187
 188                         /* reenable the IRQ */
 189                         high &= ~IBS_FETCH_HIGH_VALID_BIT;
 190                         high |= IBS_FETCH_HIGH_ENABLE;
 191                         low &= IBS_FETCH_LOW_MAX_CNT_MASK;
 192                         wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 193                 }
 194         }
 195
 196         if (ibs_config.op_enabled) {
 197                 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
 198                 if (low & IBS_OP_LOW_VALID_BIT) {
 199                         rdmsrl(MSR_AMD64_IBSOPRIP, msr);
 200                         oprofile_add_data(&entry, regs, msr, IBS_OP_CODE,
 201                                           IBS_OP_SIZE);
 202                         op_cpu_buffer_add_data(&entry, (u32)msr);
 203                         op_cpu_buffer_add_data(&entry, (u32)(msr >> 32));
 204                         rdmsrl(MSR_AMD64_IBSOPDATA, msr);
 205                         op_cpu_buffer_add_data(&entry, (u32)msr);
 206                         op_cpu_buffer_add_data(&entry, (u32)(msr >> 32));
 207                         rdmsrl(MSR_AMD64_IBSOPDATA2, msr);
 208                         op_cpu_buffer_add_data(&entry, (u32)msr);
 209                         op_cpu_buffer_add_data(&entry, (u32)(msr >> 32));
 210                         rdmsrl(MSR_AMD64_IBSOPDATA3, msr);
 211                         op_cpu_buffer_add_data(&entry, (u32)msr);
 212                         op_cpu_buffer_add_data(&entry, (u32)(msr >> 32));
 213                         rdmsrl(MSR_AMD64_IBSDCLINAD, msr);
 214                         op_cpu_buffer_add_data(&entry, (u32)msr);
 215                         op_cpu_buffer_add_data(&entry, (u32)(msr >> 32));
 216                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr);
 217                         op_cpu_buffer_add_data(&entry, (u32)msr);
 218                         op_cpu_buffer_add_data(&entry, (u32)(msr >> 32));
 219                         op_cpu_buffer_write_commit(&entry);
 220
 221                         /* reenable the IRQ */
 222                         high = 0;
 223                         low &= ~IBS_OP_LOW_VALID_BIT;
 224                         low |= IBS_OP_LOW_ENABLE;
 225                         wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 226                 }
 227         }
 228
 229         return 1;
 230 }
 231
 232 #endif
 233
 234 static int op_amd_check_ctrs(struct pt_regs * const regs,
 235                              struct op_msrs const * const msrs)
 236 {
 237         unsigned int low, high;
 238         int i;
 239
 240         for (i = 0 ; i < NUM_COUNTERS; ++i) {
 241                 if (!reset_value[i])
 242                         continue;
 243                 CTR_READ(low, high, msrs, i);
 244                 if (CTR_OVERFLOWED(low)) {
 245                         oprofile_add_sample(regs, i);
 246                         CTR_WRITE(reset_value[i], msrs, i);
 247                 }
 248         }
 249
 250 #ifdef CONFIG_OPROFILE_IBS
 251         op_amd_handle_ibs(regs, msrs);
 252 #endif
 253
 254         /* See op_model_ppro.c */
 255         return 1;
 256 }
 257
 258 static void op_amd_start(struct op_msrs const * const msrs)
 259 {
 260         unsigned int low, high;
 261         int i;
 262         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 263                 if (reset_value[i]) {
 264                         CTRL_READ(low, high, msrs, i);
 265                         CTRL_SET_ACTIVE(low);
 266                         CTRL_WRITE(low, high, msrs, i);
 267                 }
 268         }
 269
 270 #ifdef CONFIG_OPROFILE_IBS
 271         if (has_ibs && ibs_config.fetch_enabled) {
 272                 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
 273                 high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
 274                         + IBS_FETCH_HIGH_ENABLE;
 275                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 276         }
 277
 278         if (has_ibs && ibs_config.op_enabled) {
 279                 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
 280                         + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
 281                         + IBS_OP_LOW_ENABLE;
 282                 high = 0;
 283                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 284         }
 285 #endif
 286 }
 287
 288
 289 static void op_amd_stop(struct op_msrs const * const msrs)
 290 {
 291         unsigned int low, high;
 292         int i;
 293
 294         /*
 295          * Subtle: stop on all counters to avoid race with setting our
 296          * pm callback
 297          */
 298         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 299                 if (!reset_value[i])
 300                         continue;
 301                 CTRL_READ(low, high, msrs, i);
 302                 CTRL_SET_INACTIVE(low);
 303                 CTRL_WRITE(low, high, msrs, i);
 304         }
 305
 306 #ifdef CONFIG_OPROFILE_IBS
 307         if (has_ibs && ibs_config.fetch_enabled) {
 308                 /* clear max count and enable */
 309                 low = 0;
 310                 high = 0;
 311                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 312         }
 313
 314         if (has_ibs && ibs_config.op_enabled) {
 315                 /* clear max count and enable */
 316                 low = 0;
 317                 high = 0;
 318                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 319         }
 320 #endif
 321 }
 322
 323 static void op_amd_shutdown(struct op_msrs const * const msrs)
 324 {
 325         int i;
 326
 327         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 328                 if (CTR_IS_RESERVED(msrs, i))
 329                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 330         }
 331         for (i = 0 ; i < NUM_CONTROLS ; ++i) {
 332                 if (CTRL_IS_RESERVED(msrs, i))
 333                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 334         }
 335 }
 336
 337 #ifdef CONFIG_OPROFILE_IBS
 338
 339 static u8 ibs_eilvt_off;
 340
 341 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
 342 {
 343         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 344 }
 345
 346 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
 347 {
 348         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 349 }
 350
 351 static int init_ibs_nmi(void)
 352 {
 353 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 354 #define IBSCTL                          0x1cc
 355         struct pci_dev *cpu_cfg;
 356         int nodes;
 357         u32 value = 0;
 358
 359         /* per CPU setup */
 360         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
 361
 362         nodes = 0;
 363         cpu_cfg = NULL;
 364         do {
 365                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 366                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 367                                          cpu_cfg);
 368                 if (!cpu_cfg)
 369                         break;
 370                 ++nodes;
 371                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 372                                        | IBSCTL_LVTOFFSETVAL);
 373                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 374                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 375                         pci_dev_put(cpu_cfg);
 376                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 377                                 "IBSCTL = 0x%08x", value);
 378                         return 1;
 379                 }
 380         } while (1);
 381
 382         if (!nodes) {
 383                 printk(KERN_DEBUG "No CPU node configured for IBS");
 384                 return 1;
 385         }
 386
 387 #ifdef CONFIG_NUMA
 388         /* Sanity check */
 389         /* Works only for 64bit with proper numa implementation. */
 390         if (nodes != num_possible_nodes()) {
 391                 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
 392                         "found: %d, expected %d",
 393                         nodes, num_possible_nodes());
 394                 return 1;
 395         }
 396 #endif
 397         return 0;
 398 }
 399
 400 /* uninitialize the APIC for the IBS interrupts if needed */
 401 static void clear_ibs_nmi(void)
 402 {
 403         if (has_ibs)
 404                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
 405 }
 406
 407 /* initialize the APIC for the IBS interrupts if available */
 408 static void ibs_init(void)
 409 {
 410         has_ibs = boot_cpu_has(X86_FEATURE_IBS);
 411
 412         if (!has_ibs)
 413                 return;
 414
 415         if (init_ibs_nmi()) {
 416                 has_ibs = 0;
 417                 return;
 418         }
 419
 420         printk(KERN_INFO "oprofile: AMD IBS detected\n");
 421 }
 422
 423 static void ibs_exit(void)
 424 {
 425         if (!has_ibs)
 426                 return;
 427
 428         clear_ibs_nmi();
 429 }
 430
 431 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 432
 433 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 434 {
 435         struct dentry *dir;
 436         int ret = 0;
 437
 438         /* architecture specific files */
 439         if (create_arch_files)
 440                 ret = create_arch_files(sb, root);
 441
 442         if (ret)
 443                 return ret;
 444
 445         if (!has_ibs)
 446                 return ret;
 447
 448         /* model specific files */
 449
 450         /* setup some reasonable defaults */
 451         ibs_config.max_cnt_fetch = 250000;
 452         ibs_config.fetch_enabled = 0;
 453         ibs_config.max_cnt_op = 250000;
 454         ibs_config.op_enabled = 0;
 455         ibs_config.dispatched_ops = 1;
 456
 457         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 458         oprofilefs_create_ulong(sb, dir, "enable",
 459                                 &ibs_config.fetch_enabled);
 460         oprofilefs_create_ulong(sb, dir, "max_count",
 461                                 &ibs_config.max_cnt_fetch);
 462         oprofilefs_create_ulong(sb, dir, "rand_enable",
 463                                 &ibs_config.rand_en);
 464
 465         dir = oprofilefs_mkdir(sb, root, "ibs_op");
 466         oprofilefs_create_ulong(sb, dir, "enable",
 467                                 &ibs_config.op_enabled);
 468         oprofilefs_create_ulong(sb, dir, "max_count",
 469                                 &ibs_config.max_cnt_op);
 470         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 471                                 &ibs_config.dispatched_ops);
 472
 473         return 0;
 474 }
 475
 476 static int op_amd_init(struct oprofile_operations *ops)
 477 {
 478         ibs_init();
 479         create_arch_files = ops->create_files;
 480         ops->create_files = setup_ibs_files;
 481         return 0;
 482 }
 483
 484 static void op_amd_exit(void)
 485 {
 486         ibs_exit();
 487 }
 488
 489 #else
 490
 491 /* no IBS support */
 492
 493 static int op_amd_init(struct oprofile_operations *ops)
 494 {
 495         return 0;
 496 }
 497
 498 static void op_amd_exit(void) {}
 499
 500 #endif /* CONFIG_OPROFILE_IBS */
 501
 502 struct op_x86_model_spec const op_amd_spec = {
 503         .init                   = op_amd_init,
 504         .exit                   = op_amd_exit,
 505         .num_counters           = NUM_COUNTERS,
 506         .num_controls           = NUM_CONTROLS,
 507         .fill_in_addresses      = &op_amd_fill_in_addresses,
 508         .setup_ctrs             = &op_amd_setup_ctrs,
 509         .check_ctrs             = &op_amd_check_ctrs,
 510         .start                  = &op_amd_start,
 511         .stop                   = &op_amd_stop,
 512         .shutdown               = &op_amd_shutdown
 513 };