3 * athlon / K7 / K8 / Family 10h model-specific MSR operations
5 * @remark Copyright 2002-2009 OProfile authors
6 * @remark Read the file COPYING
9 * @author Philippe Elie
10 * @author Graydon Hoare
11 * @author Robert Richter <robert.richter@amd.com>
12 * @author Barry Kasindorf <barry.kasindorf@amd.com>
13 * @author Jason Yeh <jason.yeh@amd.com>
14 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
17 #include <linux/oprofile.h>
18 #include <linux/device.h>
19 #include <linux/pci.h>
20 #include <linux/percpu.h>
22 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/cpufeature.h>
29 #include "op_x86_model.h"
30 #include "op_counter.h"
32 #define NUM_COUNTERS 4
33 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
34 #define NUM_VIRT_COUNTERS 32
36 #define NUM_VIRT_COUNTERS NUM_COUNTERS
39 #define OP_EVENT_MASK 0x0FFF
40 #define OP_CTR_OVERFLOW (1ULL<<31)
42 #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
44 static unsigned long reset_value[NUM_VIRT_COUNTERS];
46 #define IBS_FETCH_SIZE 6
47 #define IBS_OP_SIZE 12
51 struct op_ibs_config {
52 unsigned long op_enabled;
53 unsigned long fetch_enabled;
54 unsigned long max_cnt_fetch;
55 unsigned long max_cnt_op;
56 unsigned long rand_en;
57 unsigned long dispatched_ops;
60 static struct op_ibs_config ibs_config;
61 static u64 ibs_op_ctl;
64 * IBS cpuid feature detection
67 #define IBS_CPUID_FEATURES 0x8000001b
70 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
71 * bit 0 is used to indicate the existence of IBS.
73 #define IBS_CAPS_AVAIL (1U<<0)
74 #define IBS_CAPS_RDWROPCNT (1U<<3)
75 #define IBS_CAPS_OPCNT (1U<<4)
81 #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
82 #define IBSCTL_LVT_OFFSET_MASK 0x0F
85 * IBS randomization macros
87 #define IBS_RANDOM_BITS 12
88 #define IBS_RANDOM_MASK ((1ULL << IBS_RANDOM_BITS) - 1)
89 #define IBS_RANDOM_MAXCNT_OFFSET (1ULL << (IBS_RANDOM_BITS - 5))
91 static u32 get_ibs_caps(void)
94 unsigned int max_level;
96 if (!boot_cpu_has(X86_FEATURE_IBS))
99 /* check IBS cpuid feature flags */
100 max_level = cpuid_eax(0x80000000);
101 if (max_level < IBS_CPUID_FEATURES)
102 return IBS_CAPS_AVAIL;
104 ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
105 if (!(ibs_caps & IBS_CAPS_AVAIL))
106 /* cpuid flags not valid */
107 return IBS_CAPS_AVAIL;
113 * 16-bit Linear Feedback Shift Register (LFSR)
116 * Feedback polynomial = X + X + X + X + 1
118 static unsigned int lfsr_random(void)
120 static unsigned int lfsr_value = 0xF00D;
123 /* Compute next bit to shift in */
124 bit = ((lfsr_value >> 0) ^
127 (lfsr_value >> 5)) & 0x0001;
129 /* Advance to next register value */
130 lfsr_value = (lfsr_value >> 1) | (bit << 15);
136 * IBS software randomization
138 * The IBS periodic op counter is randomized in software. The lower 12
139 * bits of the 20 bit counter are randomized. IbsOpCurCnt is
140 * initialized with a 12 bit random value.
142 static inline u64 op_amd_randomize_ibs_op(u64 val)
144 unsigned int random = lfsr_random();
146 if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
148 * Work around if the hw can not write to IbsOpCurCnt
150 * Randomize the lower 8 bits of the 16 bit
151 * IbsOpMaxCnt [15:0] value in the range of -128 to
152 * +127 by adding/subtracting an offset to the
153 * maximum count (IbsOpMaxCnt).
155 * To avoid over or underflows and protect upper bits
156 * starting at bit 16, the initial value for
157 * IbsOpMaxCnt must fit in the range from 0x0081 to
160 val += (s8)(random >> 4);
162 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
168 op_amd_handle_ibs(struct pt_regs * const regs,
169 struct op_msrs const * const msrs)
172 struct op_entry entry;
177 if (ibs_config.fetch_enabled) {
178 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
179 if (ctl & IBS_FETCH_VAL) {
180 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
181 oprofile_write_reserve(&entry, regs, val,
182 IBS_FETCH_CODE, IBS_FETCH_SIZE);
183 oprofile_add_data64(&entry, val);
184 oprofile_add_data64(&entry, ctl);
185 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
186 oprofile_add_data64(&entry, val);
187 oprofile_write_commit(&entry);
189 /* reenable the IRQ */
190 ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
191 ctl |= IBS_FETCH_ENABLE;
192 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
196 if (ibs_config.op_enabled) {
197 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
198 if (ctl & IBS_OP_VAL) {
199 rdmsrl(MSR_AMD64_IBSOPRIP, val);
200 oprofile_write_reserve(&entry, regs, val,
201 IBS_OP_CODE, IBS_OP_SIZE);
202 oprofile_add_data64(&entry, val);
203 rdmsrl(MSR_AMD64_IBSOPDATA, val);
204 oprofile_add_data64(&entry, val);
205 rdmsrl(MSR_AMD64_IBSOPDATA2, val);
206 oprofile_add_data64(&entry, val);
207 rdmsrl(MSR_AMD64_IBSOPDATA3, val);
208 oprofile_add_data64(&entry, val);
209 rdmsrl(MSR_AMD64_IBSDCLINAD, val);
210 oprofile_add_data64(&entry, val);
211 rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
212 oprofile_add_data64(&entry, val);
213 oprofile_write_commit(&entry);
215 /* reenable the IRQ */
216 ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
217 wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
222 static inline void op_amd_start_ibs(void)
229 if (ibs_config.fetch_enabled) {
230 val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT;
231 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
232 val |= IBS_FETCH_ENABLE;
233 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
236 if (ibs_config.op_enabled) {
237 ibs_op_ctl = ibs_config.max_cnt_op >> 4;
238 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
240 * IbsOpCurCnt not supported. See
241 * op_amd_randomize_ibs_op() for details.
243 ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
246 * The start value is randomized with a
247 * positive offset, we need to compensate it
248 * with the half of the randomized range. Also
251 ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
254 if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
255 ibs_op_ctl |= IBS_OP_CNT_CTL;
256 ibs_op_ctl |= IBS_OP_ENABLE;
257 val = op_amd_randomize_ibs_op(ibs_op_ctl);
258 wrmsrl(MSR_AMD64_IBSOPCTL, val);
262 static void op_amd_stop_ibs(void)
267 if (ibs_config.fetch_enabled)
268 /* clear max count and enable */
269 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
271 if (ibs_config.op_enabled)
272 /* clear max count and enable */
273 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
276 static inline int eilvt_is_available(int offset)
278 /* check if we may assign a vector */
279 return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
282 static inline int ibs_eilvt_valid(void)
287 rdmsrl(MSR_AMD64_IBSCTL, val);
288 offset = val & IBSCTL_LVT_OFFSET_MASK;
290 if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
291 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
292 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
296 if (!eilvt_is_available(offset)) {
297 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
298 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
305 static inline int get_ibs_offset(void)
309 rdmsrl(MSR_AMD64_IBSCTL, val);
310 if (!(val & IBSCTL_LVT_OFFSET_VALID))
313 return val & IBSCTL_LVT_OFFSET_MASK;
316 static void setup_APIC_ibs(void)
320 offset = get_ibs_offset();
324 if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
327 pr_warn("oprofile: IBS APIC setup failed on cpu #%d\n",
331 static void clear_APIC_ibs(void)
335 offset = get_ibs_offset();
337 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
340 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
342 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
343 struct op_msrs const * const msrs)
348 /* enable active counters */
349 for (i = 0; i < NUM_COUNTERS; ++i) {
350 int virt = op_x86_phys_to_virt(i);
351 if (!reset_value[virt])
353 rdmsrl(msrs->controls[i].addr, val);
354 val &= model->reserved;
355 val |= op_x86_get_ctrl(model, &counter_config[virt]);
356 wrmsrl(msrs->controls[i].addr, val);
362 /* functions for op_amd_spec */
364 static void op_amd_shutdown(struct op_msrs const * const msrs)
368 for (i = 0; i < NUM_COUNTERS; ++i) {
369 if (!msrs->counters[i].addr)
371 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
372 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
376 static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
380 for (i = 0; i < NUM_COUNTERS; i++) {
381 if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
383 if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
384 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
387 /* both registers must be reserved */
388 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
389 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
392 if (!counter_config[i].enabled)
394 op_x86_warn_reserved(i);
395 op_amd_shutdown(msrs);
402 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
403 struct op_msrs const * const msrs)
408 /* setup reset_value */
409 for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
410 if (counter_config[i].enabled
411 && msrs->counters[op_x86_virt_to_phys(i)].addr)
412 reset_value[i] = counter_config[i].count;
417 /* clear all counters */
418 for (i = 0; i < NUM_COUNTERS; ++i) {
419 if (!msrs->controls[i].addr)
421 rdmsrl(msrs->controls[i].addr, val);
422 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
423 op_x86_warn_in_use(i);
424 val &= model->reserved;
425 wrmsrl(msrs->controls[i].addr, val);
427 * avoid a false detection of ctr overflows in NMI
430 wrmsrl(msrs->counters[i].addr, -1LL);
433 /* enable active counters */
434 for (i = 0; i < NUM_COUNTERS; ++i) {
435 int virt = op_x86_phys_to_virt(i);
436 if (!reset_value[virt])
439 /* setup counter registers */
440 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
442 /* setup control registers */
443 rdmsrl(msrs->controls[i].addr, val);
444 val &= model->reserved;
445 val |= op_x86_get_ctrl(model, &counter_config[virt]);
446 wrmsrl(msrs->controls[i].addr, val);
453 static void op_amd_cpu_shutdown(void)
459 static int op_amd_check_ctrs(struct pt_regs * const regs,
460 struct op_msrs const * const msrs)
465 for (i = 0; i < NUM_COUNTERS; ++i) {
466 int virt = op_x86_phys_to_virt(i);
467 if (!reset_value[virt])
469 rdmsrl(msrs->counters[i].addr, val);
470 /* bit is clear if overflowed: */
471 if (val & OP_CTR_OVERFLOW)
473 oprofile_add_sample(regs, virt);
474 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
477 op_amd_handle_ibs(regs, msrs);
479 /* See op_model_ppro.c */
483 static void op_amd_start(struct op_msrs const * const msrs)
488 for (i = 0; i < NUM_COUNTERS; ++i) {
489 if (!reset_value[op_x86_phys_to_virt(i)])
491 rdmsrl(msrs->controls[i].addr, val);
492 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
493 wrmsrl(msrs->controls[i].addr, val);
499 static void op_amd_stop(struct op_msrs const * const msrs)
505 * Subtle: stop on all counters to avoid race with setting our
508 for (i = 0; i < NUM_COUNTERS; ++i) {
509 if (!reset_value[op_x86_phys_to_virt(i)])
511 rdmsrl(msrs->controls[i].addr, val);
512 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
513 wrmsrl(msrs->controls[i].addr, val);
519 static int setup_ibs_ctl(int ibs_eilvt_off)
521 struct pci_dev *cpu_cfg;
528 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
529 PCI_DEVICE_ID_AMD_10H_NB_MISC,
534 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
535 | IBSCTL_LVT_OFFSET_VALID);
536 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
537 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
538 pci_dev_put(cpu_cfg);
539 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
540 "IBSCTL = 0x%08x\n", value);
546 printk(KERN_DEBUG "No CPU node configured for IBS\n");
553 static int force_ibs_eilvt_setup(void)
558 /* find the next free available EILVT entry */
559 for (i = 1; i < 4; i++) {
560 if (!eilvt_is_available(i))
562 ret = setup_ibs_ctl(i);
568 printk(KERN_DEBUG "No EILVT entry available\n");
573 static int __init_ibs_nmi(void)
577 if (ibs_eilvt_valid())
580 ret = force_ibs_eilvt_setup();
584 if (!ibs_eilvt_valid())
587 pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
592 /* initialize the APIC for the IBS interrupts if available */
593 static void init_ibs(void)
595 ibs_caps = get_ibs_caps();
600 if (__init_ibs_nmi()) {
605 printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
609 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
611 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
616 /* architecture specific files */
617 if (create_arch_files)
618 ret = create_arch_files(sb, root);
626 /* model specific files */
628 /* setup some reasonable defaults */
629 ibs_config.max_cnt_fetch = 250000;
630 ibs_config.fetch_enabled = 0;
631 ibs_config.max_cnt_op = 250000;
632 ibs_config.op_enabled = 0;
633 ibs_config.dispatched_ops = 0;
635 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
636 oprofilefs_create_ulong(sb, dir, "enable",
637 &ibs_config.fetch_enabled);
638 oprofilefs_create_ulong(sb, dir, "max_count",
639 &ibs_config.max_cnt_fetch);
640 oprofilefs_create_ulong(sb, dir, "rand_enable",
641 &ibs_config.rand_en);
643 dir = oprofilefs_mkdir(sb, root, "ibs_op");
644 oprofilefs_create_ulong(sb, dir, "enable",
645 &ibs_config.op_enabled);
646 oprofilefs_create_ulong(sb, dir, "max_count",
647 &ibs_config.max_cnt_op);
648 if (ibs_caps & IBS_CAPS_OPCNT)
649 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
650 &ibs_config.dispatched_ops);
655 static int op_amd_init(struct oprofile_operations *ops)
658 create_arch_files = ops->create_files;
659 ops->create_files = setup_ibs_files;
663 struct op_x86_model_spec op_amd_spec = {
664 .num_counters = NUM_COUNTERS,
665 .num_controls = NUM_COUNTERS,
666 .num_virt_counters = NUM_VIRT_COUNTERS,
667 .reserved = MSR_AMD_EVENTSEL_RESERVED,
668 .event_mask = OP_EVENT_MASK,
670 .fill_in_addresses = &op_amd_fill_in_addresses,
671 .setup_ctrs = &op_amd_setup_ctrs,
672 .cpu_down = &op_amd_cpu_shutdown,
673 .check_ctrs = &op_amd_check_ctrs,
674 .start = &op_amd_start,
675 .stop = &op_amd_stop,
676 .shutdown = &op_amd_shutdown,
677 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
678 .switch_ctrl = &op_mux_switch_ctrl,