4 * @remark Copyright 2002-2009 OProfile authors
5 * @remark Read the file COPYING
7 * @author John Levon <levon@movementarian.org>
8 * @author Robert Richter <robert.richter@amd.com>
9 * @author Barry Kasindorf <barry.kasindorf@amd.com>
10 * @author Jason Yeh <jason.yeh@amd.com>
11 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
14 #include <linux/init.h>
15 #include <linux/notifier.h>
16 #include <linux/smp.h>
17 #include <linux/oprofile.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/slab.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kdebug.h>
22 #include <linux/cpu.h>
27 #include "op_counter.h"
28 #include "op_x86_model.h"
30 static struct op_x86_model_spec *model;
31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
34 /* must be protected with get_online_cpus()/put_online_cpus(): */
35 static int nmi_enabled;
36 static int ctr_running;
38 struct op_counter_config counter_config[OP_MAX_COUNTER];
40 /* common functions */
42 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
43 struct op_counter_config *counter_config)
46 u16 event = (u16)counter_config->event;
48 val |= ARCH_PERFMON_EVENTSEL_INT;
49 val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
50 val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
51 val |= (counter_config->unit_mask & 0xFF) << 8;
52 counter_config->extra &= (ARCH_PERFMON_EVENTSEL_INV |
53 ARCH_PERFMON_EVENTSEL_EDGE |
54 ARCH_PERFMON_EVENTSEL_CMASK);
55 val |= counter_config->extra;
56 event &= model->event_mask ? model->event_mask : 0xFF;
58 val |= (event & 0x0F00) << 24;
64 static int profile_exceptions_notify(struct notifier_block *self,
65 unsigned long val, void *data)
67 struct die_args *args = (struct die_args *)data;
68 int ret = NOTIFY_DONE;
73 model->check_ctrs(args->regs, &__get_cpu_var(cpu_msrs));
74 else if (!nmi_enabled)
77 model->stop(&__get_cpu_var(cpu_msrs));
86 static void nmi_cpu_save_registers(struct op_msrs *msrs)
88 struct op_msr *counters = msrs->counters;
89 struct op_msr *controls = msrs->controls;
92 for (i = 0; i < model->num_counters; ++i) {
94 rdmsrl(counters[i].addr, counters[i].saved);
97 for (i = 0; i < model->num_controls; ++i) {
99 rdmsrl(controls[i].addr, controls[i].saved);
103 static void nmi_cpu_start(void *dummy)
105 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
112 static int nmi_start(void)
116 /* make ctr_running visible to the nmi handler: */
118 on_each_cpu(nmi_cpu_start, NULL, 1);
123 static void nmi_cpu_stop(void *dummy)
125 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
132 static void nmi_stop(void)
135 on_each_cpu(nmi_cpu_stop, NULL, 1);
140 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
142 static DEFINE_PER_CPU(int, switch_index);
144 static inline int has_mux(void)
146 return !!model->switch_ctrl;
149 inline int op_x86_phys_to_virt(int phys)
151 return __this_cpu_read(switch_index) + phys;
154 inline int op_x86_virt_to_phys(int virt)
156 return virt % model->num_counters;
159 static void nmi_shutdown_mux(void)
166 for_each_possible_cpu(i) {
167 kfree(per_cpu(cpu_msrs, i).multiplex);
168 per_cpu(cpu_msrs, i).multiplex = NULL;
169 per_cpu(switch_index, i) = 0;
173 static int nmi_setup_mux(void)
175 size_t multiplex_size =
176 sizeof(struct op_msr) * model->num_virt_counters;
182 for_each_possible_cpu(i) {
183 per_cpu(cpu_msrs, i).multiplex =
184 kzalloc(multiplex_size, GFP_KERNEL);
185 if (!per_cpu(cpu_msrs, i).multiplex)
192 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
195 struct op_msr *multiplex = msrs->multiplex;
200 for (i = 0; i < model->num_virt_counters; ++i) {
201 if (counter_config[i].enabled) {
202 multiplex[i].saved = -(u64)counter_config[i].count;
204 multiplex[i].saved = 0;
208 per_cpu(switch_index, cpu) = 0;
211 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
213 struct op_msr *counters = msrs->counters;
214 struct op_msr *multiplex = msrs->multiplex;
217 for (i = 0; i < model->num_counters; ++i) {
218 int virt = op_x86_phys_to_virt(i);
219 if (counters[i].addr)
220 rdmsrl(counters[i].addr, multiplex[virt].saved);
224 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
226 struct op_msr *counters = msrs->counters;
227 struct op_msr *multiplex = msrs->multiplex;
230 for (i = 0; i < model->num_counters; ++i) {
231 int virt = op_x86_phys_to_virt(i);
232 if (counters[i].addr)
233 wrmsrl(counters[i].addr, multiplex[virt].saved);
237 static void nmi_cpu_switch(void *dummy)
239 int cpu = smp_processor_id();
240 int si = per_cpu(switch_index, cpu);
241 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
244 nmi_cpu_save_mpx_registers(msrs);
246 /* move to next set */
247 si += model->num_counters;
248 if ((si >= model->num_virt_counters) || (counter_config[si].count == 0))
249 per_cpu(switch_index, cpu) = 0;
251 per_cpu(switch_index, cpu) = si;
253 model->switch_ctrl(model, msrs);
254 nmi_cpu_restore_mpx_registers(msrs);
261 * Quick check to see if multiplexing is necessary.
262 * The check should be sufficient since counters are used
265 static int nmi_multiplex_on(void)
267 return counter_config[model->num_counters].count ? 0 : -EINVAL;
270 static int nmi_switch_event(void)
273 return -ENOSYS; /* not implemented */
274 if (nmi_multiplex_on() < 0)
275 return -EINVAL; /* not necessary */
279 on_each_cpu(nmi_cpu_switch, NULL, 1);
285 static inline void mux_init(struct oprofile_operations *ops)
288 ops->switch_events = nmi_switch_event;
291 static void mux_clone(int cpu)
296 memcpy(per_cpu(cpu_msrs, cpu).multiplex,
297 per_cpu(cpu_msrs, 0).multiplex,
298 sizeof(struct op_msr) * model->num_virt_counters);
303 inline int op_x86_phys_to_virt(int phys) { return phys; }
304 inline int op_x86_virt_to_phys(int virt) { return virt; }
305 static inline void nmi_shutdown_mux(void) { }
306 static inline int nmi_setup_mux(void) { return 1; }
308 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
309 static inline void mux_init(struct oprofile_operations *ops) { }
310 static void mux_clone(int cpu) { }
314 static void free_msrs(void)
317 for_each_possible_cpu(i) {
318 kfree(per_cpu(cpu_msrs, i).counters);
319 per_cpu(cpu_msrs, i).counters = NULL;
320 kfree(per_cpu(cpu_msrs, i).controls);
321 per_cpu(cpu_msrs, i).controls = NULL;
326 static int allocate_msrs(void)
328 size_t controls_size = sizeof(struct op_msr) * model->num_controls;
329 size_t counters_size = sizeof(struct op_msr) * model->num_counters;
332 for_each_possible_cpu(i) {
333 per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
335 if (!per_cpu(cpu_msrs, i).counters)
337 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
339 if (!per_cpu(cpu_msrs, i).controls)
343 if (!nmi_setup_mux())
353 static void nmi_cpu_setup(void *dummy)
355 int cpu = smp_processor_id();
356 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
357 nmi_cpu_save_registers(msrs);
358 spin_lock(&oprofilefs_lock);
359 model->setup_ctrs(model, msrs);
360 nmi_cpu_setup_mux(cpu, msrs);
361 spin_unlock(&oprofilefs_lock);
362 per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
363 apic_write(APIC_LVTPC, APIC_DM_NMI);
366 static struct notifier_block profile_exceptions_nb = {
367 .notifier_call = profile_exceptions_notify,
369 .priority = NMI_LOCAL_LOW_PRIOR,
372 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
374 struct op_msr *counters = msrs->counters;
375 struct op_msr *controls = msrs->controls;
378 for (i = 0; i < model->num_controls; ++i) {
379 if (controls[i].addr)
380 wrmsrl(controls[i].addr, controls[i].saved);
383 for (i = 0; i < model->num_counters; ++i) {
384 if (counters[i].addr)
385 wrmsrl(counters[i].addr, counters[i].saved);
389 static void nmi_cpu_shutdown(void *dummy)
392 int cpu = smp_processor_id();
393 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
395 /* restoring APIC_LVTPC can trigger an apic error because the delivery
396 * mode and vector nr combination can be illegal. That's by design: on
397 * power on apic lvt contain a zero vector nr which are legal only for
398 * NMI delivery mode. So inhibit apic err before restoring lvtpc
400 v = apic_read(APIC_LVTERR);
401 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
402 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
403 apic_write(APIC_LVTERR, v);
404 nmi_cpu_restore_registers(msrs);
409 static void nmi_cpu_up(void *dummy)
412 nmi_cpu_setup(dummy);
414 nmi_cpu_start(dummy);
417 static void nmi_cpu_down(void *dummy)
422 nmi_cpu_shutdown(dummy);
425 static int nmi_create_files(struct super_block *sb, struct dentry *root)
429 for (i = 0; i < model->num_virt_counters; ++i) {
433 /* quick little hack to _not_ expose a counter if it is not
434 * available for use. This should protect userspace app.
435 * NOTE: assumes 1:1 mapping here (that counters are organized
436 * sequentially in their struct assignment).
438 if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
441 snprintf(buf, sizeof(buf), "%d", i);
442 dir = oprofilefs_mkdir(sb, root, buf);
443 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
444 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
445 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
446 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
447 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
448 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
449 oprofilefs_create_ulong(sb, dir, "extra", &counter_config[i].extra);
455 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
458 int cpu = (unsigned long)data;
460 case CPU_DOWN_FAILED:
462 smp_call_function_single(cpu, nmi_cpu_up, NULL, 0);
464 case CPU_DOWN_PREPARE:
465 smp_call_function_single(cpu, nmi_cpu_down, NULL, 1);
471 static struct notifier_block oprofile_cpu_nb = {
472 .notifier_call = oprofile_cpu_notifier
475 static int nmi_setup(void)
480 if (!allocate_msrs())
483 /* We need to serialize save and setup for HT because the subset
484 * of msrs are distinct for save and setup operations
487 /* Assume saved/restored counters are the same on all CPUs */
488 err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
492 for_each_possible_cpu(cpu) {
496 memcpy(per_cpu(cpu_msrs, cpu).counters,
497 per_cpu(cpu_msrs, 0).counters,
498 sizeof(struct op_msr) * model->num_counters);
500 memcpy(per_cpu(cpu_msrs, cpu).controls,
501 per_cpu(cpu_msrs, 0).controls,
502 sizeof(struct op_msr) * model->num_controls);
509 /* make variables visible to the nmi handler: */
511 err = register_die_notifier(&profile_exceptions_nb);
516 register_cpu_notifier(&oprofile_cpu_nb);
518 /* make nmi_enabled visible to the nmi handler: */
520 on_each_cpu(nmi_cpu_setup, NULL, 1);
529 static void nmi_shutdown(void)
531 struct op_msrs *msrs;
534 unregister_cpu_notifier(&oprofile_cpu_nb);
535 on_each_cpu(nmi_cpu_shutdown, NULL, 1);
539 /* make variables visible to the nmi handler: */
541 unregister_die_notifier(&profile_exceptions_nb);
542 msrs = &get_cpu_var(cpu_msrs);
543 model->shutdown(msrs);
545 put_cpu_var(cpu_msrs);
550 static int nmi_suspend(void)
552 /* Only one CPU left, just stop that one */
553 if (nmi_enabled == 1)
558 static void nmi_resume(void)
560 if (nmi_enabled == 1)
564 static struct syscore_ops oprofile_syscore_ops = {
565 .resume = nmi_resume,
566 .suspend = nmi_suspend,
569 static void __init init_suspend_resume(void)
571 register_syscore_ops(&oprofile_syscore_ops);
574 static void exit_suspend_resume(void)
576 unregister_syscore_ops(&oprofile_syscore_ops);
581 static inline void init_suspend_resume(void) { }
582 static inline void exit_suspend_resume(void) { }
584 #endif /* CONFIG_PM */
586 static int __init p4_init(char **cpu_type)
588 __u8 cpu_model = boot_cpu_data.x86_model;
590 if (cpu_model > 6 || cpu_model == 5)
594 *cpu_type = "i386/p4";
598 switch (smp_num_siblings) {
600 *cpu_type = "i386/p4";
605 *cpu_type = "i386/p4-ht";
606 model = &op_p4_ht2_spec;
611 printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
612 printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
616 static int force_arch_perfmon;
617 static int force_cpu_type(const char *str, struct kernel_param *kp)
619 if (!strcmp(str, "arch_perfmon")) {
620 force_arch_perfmon = 1;
621 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
626 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
628 static int __init ppro_init(char **cpu_type)
630 __u8 cpu_model = boot_cpu_data.x86_model;
631 struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
633 if (force_arch_perfmon && cpu_has_arch_perfmon)
637 * Documentation on identifying Intel processors by CPU family
638 * and model can be found in the Intel Software Developer's
641 * http://www.intel.com/products/processor/manuals/
643 * As of May 2010 the documentation for this was in the:
644 * "Intel 64 and IA-32 Architectures Software Developer's
645 * Manual Volume 3B: System Programming Guide", "Table B-1
646 * CPUID Signature Values of DisplayFamily_DisplayModel".
650 *cpu_type = "i386/ppro";
653 *cpu_type = "i386/pii";
657 *cpu_type = "i386/piii";
661 *cpu_type = "i386/p6_mobile";
664 *cpu_type = "i386/core";
670 *cpu_type = "i386/core_2";
675 spec = &op_arch_perfmon_spec;
676 *cpu_type = "i386/core_i7";
679 *cpu_type = "i386/atom";
690 int __init op_nmi_init(struct oprofile_operations *ops)
692 __u8 vendor = boot_cpu_data.x86_vendor;
693 __u8 family = boot_cpu_data.x86;
694 char *cpu_type = NULL;
702 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
706 cpu_type = "i386/athlon";
710 * Actually it could be i386/hammer too, but
711 * give user space an consistent name.
713 cpu_type = "x86-64/hammer";
716 cpu_type = "x86-64/family10";
719 cpu_type = "x86-64/family11h";
722 cpu_type = "x86-64/family12h";
725 cpu_type = "x86-64/family14h";
728 cpu_type = "x86-64/family15h";
733 model = &op_amd_spec;
736 case X86_VENDOR_INTEL:
743 /* A P6-class processor */
745 ppro_init(&cpu_type);
755 if (!cpu_has_arch_perfmon)
758 /* use arch perfmon as fallback */
759 cpu_type = "i386/arch_perfmon";
760 model = &op_arch_perfmon_spec;
767 /* default values, can be overwritten by model */
768 ops->create_files = nmi_create_files;
769 ops->setup = nmi_setup;
770 ops->shutdown = nmi_shutdown;
771 ops->start = nmi_start;
772 ops->stop = nmi_stop;
773 ops->cpu_type = cpu_type;
776 ret = model->init(ops);
780 if (!model->num_virt_counters)
781 model->num_virt_counters = model->num_counters;
785 init_suspend_resume();
787 printk(KERN_INFO "oprofile: using NMI interrupt.\n");
791 void op_nmi_exit(void)
793 exit_suspend_resume();