arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2009 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  10  * @author Jason Yeh <jason.yeh@amd.com>
  11  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/notifier.h>
  16 #include <linux/smp.h>
  17 #include <linux/oprofile.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/slab.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/cpu.h>
  23 #include <asm/nmi.h>
  24 #include <asm/msr.h>
  25 #include <asm/apic.h>
  26
  27 #include "op_counter.h"
  28 #include "op_x86_model.h"
  29
  30 static struct op_x86_model_spec *model;
  31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  33
  34 /* 0 == registered but off, 1 == registered and on */
  35 static int nmi_enabled = 0;
  36
  37 struct op_counter_config counter_config[OP_MAX_COUNTER];
  38
  39 /* common functions */
  40
  41 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
  42                     struct op_counter_config *counter_config)
  43 {
  44         u64 val = 0;
  45         u16 event = (u16)counter_config->event;
  46
  47         val |= ARCH_PERFMON_EVENTSEL_INT;
  48         val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
  49         val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
  50         val |= (counter_config->unit_mask & 0xFF) << 8;
  51         event &= model->event_mask ? model->event_mask : 0xFF;
  52         val |= event & 0xFF;
  53         val |= (event & 0x0F00) << 24;
  54
  55         return val;
  56 }
  57
  58
  59 static int profile_exceptions_notify(struct notifier_block *self,
  60                                      unsigned long val, void *data)
  61 {
  62         struct die_args *args = (struct die_args *)data;
  63         int ret = NOTIFY_DONE;
  64         int cpu = smp_processor_id();
  65
  66         switch (val) {
  67         case DIE_NMI:
  68         case DIE_NMI_IPI:
  69                 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
  70                 ret = NOTIFY_STOP;
  71                 break;
  72         default:
  73                 break;
  74         }
  75         return ret;
  76 }
  77
  78 static void nmi_cpu_save_registers(struct op_msrs *msrs)
  79 {
  80         struct op_msr *counters = msrs->counters;
  81         struct op_msr *controls = msrs->controls;
  82         unsigned int i;
  83
  84         for (i = 0; i < model->num_counters; ++i) {
  85                 if (counters[i].addr)
  86                         rdmsrl(counters[i].addr, counters[i].saved);
  87         }
  88
  89         for (i = 0; i < model->num_controls; ++i) {
  90                 if (controls[i].addr)
  91                         rdmsrl(controls[i].addr, controls[i].saved);
  92         }
  93 }
  94
  95 static void nmi_cpu_start(void *dummy)
  96 {
  97         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
  98         if (!msrs->controls)
  99                 WARN_ON_ONCE(1);
 100         else
 101                 model->start(msrs);
 102 }
 103
 104 static int nmi_start(void)
 105 {
 106         on_each_cpu(nmi_cpu_start, NULL, 1);
 107         return 0;
 108 }
 109
 110 static void nmi_cpu_stop(void *dummy)
 111 {
 112         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 113         if (!msrs->controls)
 114                 WARN_ON_ONCE(1);
 115         else
 116                 model->stop(msrs);
 117 }
 118
 119 static void nmi_stop(void)
 120 {
 121         on_each_cpu(nmi_cpu_stop, NULL, 1);
 122 }
 123
 124 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 125
 126 static DEFINE_PER_CPU(int, switch_index);
 127
 128 static inline int has_mux(void)
 129 {
 130         return !!model->switch_ctrl;
 131 }
 132
 133 inline int op_x86_phys_to_virt(int phys)
 134 {
 135         return __get_cpu_var(switch_index) + phys;
 136 }
 137
 138 inline int op_x86_virt_to_phys(int virt)
 139 {
 140         return virt % model->num_counters;
 141 }
 142
 143 static void nmi_shutdown_mux(void)
 144 {
 145         int i;
 146
 147         if (!has_mux())
 148                 return;
 149
 150         for_each_possible_cpu(i) {
 151                 kfree(per_cpu(cpu_msrs, i).multiplex);
 152                 per_cpu(cpu_msrs, i).multiplex = NULL;
 153                 per_cpu(switch_index, i) = 0;
 154         }
 155 }
 156
 157 static int nmi_setup_mux(void)
 158 {
 159         size_t multiplex_size =
 160                 sizeof(struct op_msr) * model->num_virt_counters;
 161         int i;
 162
 163         if (!has_mux())
 164                 return 1;
 165
 166         for_each_possible_cpu(i) {
 167                 per_cpu(cpu_msrs, i).multiplex =
 168                         kzalloc(multiplex_size, GFP_KERNEL);
 169                 if (!per_cpu(cpu_msrs, i).multiplex)
 170                         return 0;
 171         }
 172
 173         return 1;
 174 }
 175
 176 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
 177 {
 178         int i;
 179         struct op_msr *multiplex = msrs->multiplex;
 180
 181         if (!has_mux())
 182                 return;
 183
 184         for (i = 0; i < model->num_virt_counters; ++i) {
 185                 if (counter_config[i].enabled) {
 186                         multiplex[i].saved = -(u64)counter_config[i].count;
 187                 } else {
 188                         multiplex[i].saved = 0;
 189                 }
 190         }
 191
 192         per_cpu(switch_index, cpu) = 0;
 193 }
 194
 195 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
 196 {
 197         struct op_msr *counters = msrs->counters;
 198         struct op_msr *multiplex = msrs->multiplex;
 199         int i;
 200
 201         for (i = 0; i < model->num_counters; ++i) {
 202                 int virt = op_x86_phys_to_virt(i);
 203                 if (counters[i].addr)
 204                         rdmsrl(counters[i].addr, multiplex[virt].saved);
 205         }
 206 }
 207
 208 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
 209 {
 210         struct op_msr *counters = msrs->counters;
 211         struct op_msr *multiplex = msrs->multiplex;
 212         int i;
 213
 214         for (i = 0; i < model->num_counters; ++i) {
 215                 int virt = op_x86_phys_to_virt(i);
 216                 if (counters[i].addr)
 217                         wrmsrl(counters[i].addr, multiplex[virt].saved);
 218         }
 219 }
 220
 221 static void nmi_cpu_switch(void *dummy)
 222 {
 223         int cpu = smp_processor_id();
 224         int si = per_cpu(switch_index, cpu);
 225         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 226
 227         nmi_cpu_stop(NULL);
 228         nmi_cpu_save_mpx_registers(msrs);
 229
 230         /* move to next set */
 231         si += model->num_counters;
 232         if ((si >= model->num_virt_counters) || (counter_config[si].count == 0))
 233                 per_cpu(switch_index, cpu) = 0;
 234         else
 235                 per_cpu(switch_index, cpu) = si;
 236
 237         model->switch_ctrl(model, msrs);
 238         nmi_cpu_restore_mpx_registers(msrs);
 239
 240         nmi_cpu_start(NULL);
 241 }
 242
 243
 244 /*
 245  * Quick check to see if multiplexing is necessary.
 246  * The check should be sufficient since counters are used
 247  * in ordre.
 248  */
 249 static int nmi_multiplex_on(void)
 250 {
 251         return counter_config[model->num_counters].count ? 0 : -EINVAL;
 252 }
 253
 254 static int nmi_switch_event(void)
 255 {
 256         if (!has_mux())
 257                 return -ENOSYS;         /* not implemented */
 258         if (nmi_multiplex_on() < 0)
 259                 return -EINVAL;         /* not necessary */
 260
 261         on_each_cpu(nmi_cpu_switch, NULL, 1);
 262
 263         return 0;
 264 }
 265
 266 static inline void mux_init(struct oprofile_operations *ops)
 267 {
 268         if (has_mux())
 269                 ops->switch_events = nmi_switch_event;
 270 }
 271
 272 static void mux_clone(int cpu)
 273 {
 274         if (!has_mux())
 275                 return;
 276
 277         memcpy(per_cpu(cpu_msrs, cpu).multiplex,
 278                per_cpu(cpu_msrs, 0).multiplex,
 279                sizeof(struct op_msr) * model->num_virt_counters);
 280 }
 281
 282 #else
 283
 284 inline int op_x86_phys_to_virt(int phys) { return phys; }
 285 inline int op_x86_virt_to_phys(int virt) { return virt; }
 286 static inline void nmi_shutdown_mux(void) { }
 287 static inline int nmi_setup_mux(void) { return 1; }
 288 static inline void
 289 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
 290 static inline void mux_init(struct oprofile_operations *ops) { }
 291 static void mux_clone(int cpu) { }
 292
 293 #endif
 294
 295 static void free_msrs(void)
 296 {
 297         int i;
 298         for_each_possible_cpu(i) {
 299                 kfree(per_cpu(cpu_msrs, i).counters);
 300                 per_cpu(cpu_msrs, i).counters = NULL;
 301                 kfree(per_cpu(cpu_msrs, i).controls);
 302                 per_cpu(cpu_msrs, i).controls = NULL;
 303         }
 304         nmi_shutdown_mux();
 305 }
 306
 307 static int allocate_msrs(void)
 308 {
 309         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 310         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 311
 312         int i;
 313         for_each_possible_cpu(i) {
 314                 per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
 315                                                         GFP_KERNEL);
 316                 if (!per_cpu(cpu_msrs, i).counters)
 317                         goto fail;
 318                 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
 319                                                         GFP_KERNEL);
 320                 if (!per_cpu(cpu_msrs, i).controls)
 321                         goto fail;
 322         }
 323
 324         if (!nmi_setup_mux())
 325                 goto fail;
 326
 327         return 1;
 328
 329 fail:
 330         free_msrs();
 331         return 0;
 332 }
 333
 334 static void nmi_cpu_setup(void *dummy)
 335 {
 336         int cpu = smp_processor_id();
 337         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 338         nmi_cpu_save_registers(msrs);
 339         spin_lock(&oprofilefs_lock);
 340         model->setup_ctrs(model, msrs);
 341         nmi_cpu_setup_mux(cpu, msrs);
 342         spin_unlock(&oprofilefs_lock);
 343         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 344         apic_write(APIC_LVTPC, APIC_DM_NMI);
 345 }
 346
 347 static struct notifier_block profile_exceptions_nb = {
 348         .notifier_call = profile_exceptions_notify,
 349         .next = NULL,
 350         .priority = 2
 351 };
 352
 353 static int nmi_setup(void)
 354 {
 355         int err = 0;
 356         int cpu;
 357
 358         if (!allocate_msrs())
 359                 return -ENOMEM;
 360
 361         /* We need to serialize save and setup for HT because the subset
 362          * of msrs are distinct for save and setup operations
 363          */
 364
 365         /* Assume saved/restored counters are the same on all CPUs */
 366         err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 367         if (err)
 368                 goto fail;
 369
 370         for_each_possible_cpu(cpu) {
 371                 if (!cpu)
 372                         continue;
 373
 374                 memcpy(per_cpu(cpu_msrs, cpu).counters,
 375                        per_cpu(cpu_msrs, 0).counters,
 376                        sizeof(struct op_msr) * model->num_counters);
 377
 378                 memcpy(per_cpu(cpu_msrs, cpu).controls,
 379                        per_cpu(cpu_msrs, 0).controls,
 380                        sizeof(struct op_msr) * model->num_controls);
 381
 382                 mux_clone(cpu);
 383         }
 384
 385         err = register_die_notifier(&profile_exceptions_nb);
 386         if (err)
 387                 goto fail;
 388
 389         on_each_cpu(nmi_cpu_setup, NULL, 1);
 390         nmi_enabled = 1;
 391         return 0;
 392 fail:
 393         free_msrs();
 394         return err;
 395 }
 396
 397 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 398 {
 399         struct op_msr *counters = msrs->counters;
 400         struct op_msr *controls = msrs->controls;
 401         unsigned int i;
 402
 403         for (i = 0; i < model->num_controls; ++i) {
 404                 if (controls[i].addr)
 405                         wrmsrl(controls[i].addr, controls[i].saved);
 406         }
 407
 408         for (i = 0; i < model->num_counters; ++i) {
 409                 if (counters[i].addr)
 410                         wrmsrl(counters[i].addr, counters[i].saved);
 411         }
 412 }
 413
 414 static void nmi_cpu_shutdown(void *dummy)
 415 {
 416         unsigned int v;
 417         int cpu = smp_processor_id();
 418         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 419
 420         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 421          * mode and vector nr combination can be illegal. That's by design: on
 422          * power on apic lvt contain a zero vector nr which are legal only for
 423          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 424          */
 425         v = apic_read(APIC_LVTERR);
 426         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 427         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 428         apic_write(APIC_LVTERR, v);
 429         nmi_cpu_restore_registers(msrs);
 430 }
 431
 432 static void nmi_shutdown(void)
 433 {
 434         struct op_msrs *msrs;
 435
 436         nmi_enabled = 0;
 437         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 438         unregister_die_notifier(&profile_exceptions_nb);
 439         msrs = &get_cpu_var(cpu_msrs);
 440         model->shutdown(msrs);
 441         free_msrs();
 442         put_cpu_var(cpu_msrs);
 443 }
 444
 445 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 446 {
 447         unsigned int i;
 448
 449         for (i = 0; i < model->num_virt_counters; ++i) {
 450                 struct dentry *dir;
 451                 char buf[4];
 452
 453                 /* quick little hack to _not_ expose a counter if it is not
 454                  * available for use.  This should protect userspace app.
 455                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 456                  *        sequentially in their struct assignment).
 457                  */
 458                 if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
 459                         continue;
 460
 461                 snprintf(buf,  sizeof(buf), "%d", i);
 462                 dir = oprofilefs_mkdir(sb, root, buf);
 463                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 464                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 465                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 466                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 467                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 468                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 469         }
 470
 471         return 0;
 472 }
 473
 474 #ifdef CONFIG_SMP
 475 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
 476                                  void *data)
 477 {
 478         int cpu = (unsigned long)data;
 479         switch (action) {
 480         case CPU_DOWN_FAILED:
 481         case CPU_ONLINE:
 482                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
 483                 break;
 484         case CPU_DOWN_PREPARE:
 485                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
 486                 break;
 487         }
 488         return NOTIFY_DONE;
 489 }
 490
 491 static struct notifier_block oprofile_cpu_nb = {
 492         .notifier_call = oprofile_cpu_notifier
 493 };
 494 #endif
 495
 496 #ifdef CONFIG_PM
 497
 498 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
 499 {
 500         /* Only one CPU left, just stop that one */
 501         if (nmi_enabled == 1)
 502                 nmi_cpu_stop(NULL);
 503         return 0;
 504 }
 505
 506 static int nmi_resume(struct sys_device *dev)
 507 {
 508         if (nmi_enabled == 1)
 509                 nmi_cpu_start(NULL);
 510         return 0;
 511 }
 512
 513 static struct sysdev_class oprofile_sysclass = {
 514         .name           = "oprofile",
 515         .resume         = nmi_resume,
 516         .suspend        = nmi_suspend,
 517 };
 518
 519 static struct sys_device device_oprofile = {
 520         .id     = 0,
 521         .cls    = &oprofile_sysclass,
 522 };
 523
 524 static int __init init_sysfs(void)
 525 {
 526         int error;
 527
 528         error = sysdev_class_register(&oprofile_sysclass);
 529         if (!error)
 530                 error = sysdev_register(&device_oprofile);
 531         return error;
 532 }
 533
 534 static void exit_sysfs(void)
 535 {
 536         sysdev_unregister(&device_oprofile);
 537         sysdev_class_unregister(&oprofile_sysclass);
 538 }
 539
 540 #else
 541 #define init_sysfs() do { } while (0)
 542 #define exit_sysfs() do { } while (0)
 543 #endif /* CONFIG_PM */
 544
 545 static int __init p4_init(char **cpu_type)
 546 {
 547         __u8 cpu_model = boot_cpu_data.x86_model;
 548
 549         if (cpu_model > 6 || cpu_model == 5)
 550                 return 0;
 551
 552 #ifndef CONFIG_SMP
 553         *cpu_type = "i386/p4";
 554         model = &op_p4_spec;
 555         return 1;
 556 #else
 557         switch (smp_num_siblings) {
 558         case 1:
 559                 *cpu_type = "i386/p4";
 560                 model = &op_p4_spec;
 561                 return 1;
 562
 563         case 2:
 564                 *cpu_type = "i386/p4-ht";
 565                 model = &op_p4_ht2_spec;
 566                 return 1;
 567         }
 568 #endif
 569
 570         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 571         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 572         return 0;
 573 }
 574
 575 static int force_arch_perfmon;
 576 static int force_cpu_type(const char *str, struct kernel_param *kp)
 577 {
 578         if (!strcmp(str, "arch_perfmon")) {
 579                 force_arch_perfmon = 1;
 580                 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
 581         }
 582
 583         return 0;
 584 }
 585 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
 586
 587 static int __init ppro_init(char **cpu_type)
 588 {
 589         __u8 cpu_model = boot_cpu_data.x86_model;
 590         struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
 591
 592         if (force_arch_perfmon && cpu_has_arch_perfmon)
 593                 return 0;
 594
 595         switch (cpu_model) {
 596         case 0 ... 2:
 597                 *cpu_type = "i386/ppro";
 598                 break;
 599         case 3 ... 5:
 600                 *cpu_type = "i386/pii";
 601                 break;
 602         case 6 ... 8:
 603         case 10 ... 11:
 604                 *cpu_type = "i386/piii";
 605                 break;
 606         case 9:
 607         case 13:
 608                 *cpu_type = "i386/p6_mobile";
 609                 break;
 610         case 14:
 611                 *cpu_type = "i386/core";
 612                 break;
 613         case 15: case 23:
 614                 *cpu_type = "i386/core_2";
 615                 break;
 616         case 0x2e:
 617         case 26:
 618                 spec = &op_arch_perfmon_spec;
 619                 *cpu_type = "i386/core_i7";
 620                 break;
 621         case 28:
 622                 *cpu_type = "i386/atom";
 623                 break;
 624         default:
 625                 /* Unknown */
 626                 return 0;
 627         }
 628
 629         model = spec;
 630         return 1;
 631 }
 632
 633 /* in order to get sysfs right */
 634 static int using_nmi;
 635
 636 int __init op_nmi_init(struct oprofile_operations *ops)
 637 {
 638         __u8 vendor = boot_cpu_data.x86_vendor;
 639         __u8 family = boot_cpu_data.x86;
 640         char *cpu_type = NULL;
 641         int ret = 0;
 642
 643         if (!cpu_has_apic)
 644                 return -ENODEV;
 645
 646         switch (vendor) {
 647         case X86_VENDOR_AMD:
 648                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 649
 650                 switch (family) {
 651                 case 6:
 652                         cpu_type = "i386/athlon";
 653                         break;
 654                 case 0xf:
 655                         /*
 656                          * Actually it could be i386/hammer too, but
 657                          * give user space an consistent name.
 658                          */
 659                         cpu_type = "x86-64/hammer";
 660                         break;
 661                 case 0x10:
 662                         cpu_type = "x86-64/family10";
 663                         break;
 664                 case 0x11:
 665                         cpu_type = "x86-64/family11h";
 666                         break;
 667                 default:
 668                         return -ENODEV;
 669                 }
 670                 model = &op_amd_spec;
 671                 break;
 672
 673         case X86_VENDOR_INTEL:
 674                 switch (family) {
 675                         /* Pentium IV */
 676                 case 0xf:
 677                         p4_init(&cpu_type);
 678                         break;
 679
 680                         /* A P6-class processor */
 681                 case 6:
 682                         ppro_init(&cpu_type);
 683                         break;
 684
 685                 default:
 686                         break;
 687                 }
 688
 689                 if (cpu_type)
 690                         break;
 691
 692                 if (!cpu_has_arch_perfmon)
 693                         return -ENODEV;
 694
 695                 /* use arch perfmon as fallback */
 696                 cpu_type = "i386/arch_perfmon";
 697                 model = &op_arch_perfmon_spec;
 698                 break;
 699
 700         default:
 701                 return -ENODEV;
 702         }
 703
 704 #ifdef CONFIG_SMP
 705         register_cpu_notifier(&oprofile_cpu_nb);
 706 #endif
 707         /* default values, can be overwritten by model */
 708         ops->create_files       = nmi_create_files;
 709         ops->setup              = nmi_setup;
 710         ops->shutdown           = nmi_shutdown;
 711         ops->start              = nmi_start;
 712         ops->stop               = nmi_stop;
 713         ops->cpu_type           = cpu_type;
 714
 715         if (model->init)
 716                 ret = model->init(ops);
 717         if (ret)
 718                 return ret;
 719
 720         if (!model->num_virt_counters)
 721                 model->num_virt_counters = model->num_counters;
 722
 723         mux_init(ops);
 724
 725         init_sysfs();
 726         using_nmi = 1;
 727         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 728         return 0;
 729 }
 730
 731 void op_nmi_exit(void)
 732 {
 733         if (using_nmi) {
 734                 exit_sysfs();
 735 #ifdef CONFIG_SMP
 736                 unregister_cpu_notifier(&oprofile_cpu_nb);
 737 #endif
 738         }
 739         if (model->exit)
 740                 model->exit();
 741 }