4 * @remark Copyright 2002-2009 OProfile authors
5 * @remark Read the file COPYING
7 * @author John Levon <levon@movementarian.org>
8 * @author Robert Richter <robert.richter@amd.com>
9 * @author Barry Kasindorf <barry.kasindorf@amd.com>
10 * @author Jason Yeh <jason.yeh@amd.com>
11 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
14 #include <linux/init.h>
15 #include <linux/notifier.h>
16 #include <linux/smp.h>
17 #include <linux/oprofile.h>
18 #include <linux/sysdev.h>
19 #include <linux/slab.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kdebug.h>
22 #include <linux/cpu.h>
27 #include "op_counter.h"
28 #include "op_x86_model.h"
30 static struct op_x86_model_spec *model;
31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
34 /* 0 == registered but off, 1 == registered and on */
35 static int nmi_enabled = 0;
37 struct op_counter_config counter_config[OP_MAX_COUNTER];
39 /* common functions */
41 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
42 struct op_counter_config *counter_config)
45 u16 event = (u16)counter_config->event;
47 val |= ARCH_PERFMON_EVENTSEL_INT;
48 val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
49 val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
50 val |= (counter_config->unit_mask & 0xFF) << 8;
51 event &= model->event_mask ? model->event_mask : 0xFF;
53 val |= (event & 0x0F00) << 24;
59 static int profile_exceptions_notify(struct notifier_block *self,
60 unsigned long val, void *data)
62 struct die_args *args = (struct die_args *)data;
63 int ret = NOTIFY_DONE;
64 int cpu = smp_processor_id();
69 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
78 static void nmi_cpu_save_registers(struct op_msrs *msrs)
80 struct op_msr *counters = msrs->counters;
81 struct op_msr *controls = msrs->controls;
84 for (i = 0; i < model->num_counters; ++i) {
86 rdmsrl(counters[i].addr, counters[i].saved);
89 for (i = 0; i < model->num_controls; ++i) {
91 rdmsrl(controls[i].addr, controls[i].saved);
95 static void nmi_cpu_start(void *dummy)
97 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
101 static int nmi_start(void)
103 on_each_cpu(nmi_cpu_start, NULL, 1);
107 static void nmi_cpu_stop(void *dummy)
109 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
113 static void nmi_stop(void)
115 on_each_cpu(nmi_cpu_stop, NULL, 1);
118 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
120 static DEFINE_PER_CPU(int, switch_index);
122 static inline int has_mux(void)
124 return !!model->switch_ctrl;
127 inline int op_x86_phys_to_virt(int phys)
129 return __get_cpu_var(switch_index) + phys;
132 inline int op_x86_virt_to_phys(int virt)
134 return virt % model->num_counters;
137 static void nmi_shutdown_mux(void)
144 for_each_possible_cpu(i) {
145 kfree(per_cpu(cpu_msrs, i).multiplex);
146 per_cpu(cpu_msrs, i).multiplex = NULL;
147 per_cpu(switch_index, i) = 0;
151 static int nmi_setup_mux(void)
153 size_t multiplex_size =
154 sizeof(struct op_msr) * model->num_virt_counters;
160 for_each_possible_cpu(i) {
161 per_cpu(cpu_msrs, i).multiplex =
162 kzalloc(multiplex_size, GFP_KERNEL);
163 if (!per_cpu(cpu_msrs, i).multiplex)
170 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
173 struct op_msr *multiplex = msrs->multiplex;
178 for (i = 0; i < model->num_virt_counters; ++i) {
179 if (counter_config[i].enabled) {
180 multiplex[i].saved = -(u64)counter_config[i].count;
182 multiplex[i].saved = 0;
186 per_cpu(switch_index, cpu) = 0;
189 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
191 struct op_msr *counters = msrs->counters;
192 struct op_msr *multiplex = msrs->multiplex;
195 for (i = 0; i < model->num_counters; ++i) {
196 int virt = op_x86_phys_to_virt(i);
197 if (counters[i].addr)
198 rdmsrl(counters[i].addr, multiplex[virt].saved);
202 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
204 struct op_msr *counters = msrs->counters;
205 struct op_msr *multiplex = msrs->multiplex;
208 for (i = 0; i < model->num_counters; ++i) {
209 int virt = op_x86_phys_to_virt(i);
210 if (counters[i].addr)
211 wrmsrl(counters[i].addr, multiplex[virt].saved);
215 static void nmi_cpu_switch(void *dummy)
217 int cpu = smp_processor_id();
218 int si = per_cpu(switch_index, cpu);
219 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
222 nmi_cpu_save_mpx_registers(msrs);
224 /* move to next set */
225 si += model->num_counters;
226 if ((si >= model->num_virt_counters) || (counter_config[si].count == 0))
227 per_cpu(switch_index, cpu) = 0;
229 per_cpu(switch_index, cpu) = si;
231 model->switch_ctrl(model, msrs);
232 nmi_cpu_restore_mpx_registers(msrs);
239 * Quick check to see if multiplexing is necessary.
240 * The check should be sufficient since counters are used
243 static int nmi_multiplex_on(void)
245 return counter_config[model->num_counters].count ? 0 : -EINVAL;
248 static int nmi_switch_event(void)
251 return -ENOSYS; /* not implemented */
252 if (nmi_multiplex_on() < 0)
253 return -EINVAL; /* not necessary */
255 on_each_cpu(nmi_cpu_switch, NULL, 1);
260 static inline void mux_init(struct oprofile_operations *ops)
263 ops->switch_events = nmi_switch_event;
266 static void mux_clone(int cpu)
271 memcpy(per_cpu(cpu_msrs, cpu).multiplex,
272 per_cpu(cpu_msrs, 0).multiplex,
273 sizeof(struct op_msr) * model->num_virt_counters);
278 inline int op_x86_phys_to_virt(int phys) { return phys; }
279 inline int op_x86_virt_to_phys(int virt) { return virt; }
280 static inline void nmi_shutdown_mux(void) { }
281 static inline int nmi_setup_mux(void) { return 1; }
283 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
284 static inline void mux_init(struct oprofile_operations *ops) { }
285 static void mux_clone(int cpu) { }
289 static void free_msrs(void)
292 for_each_possible_cpu(i) {
293 kfree(per_cpu(cpu_msrs, i).counters);
294 per_cpu(cpu_msrs, i).counters = NULL;
295 kfree(per_cpu(cpu_msrs, i).controls);
296 per_cpu(cpu_msrs, i).controls = NULL;
301 static int allocate_msrs(void)
303 size_t controls_size = sizeof(struct op_msr) * model->num_controls;
304 size_t counters_size = sizeof(struct op_msr) * model->num_counters;
307 for_each_possible_cpu(i) {
308 per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
310 if (!per_cpu(cpu_msrs, i).counters)
312 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
314 if (!per_cpu(cpu_msrs, i).controls)
318 if (!nmi_setup_mux())
328 static void nmi_cpu_setup(void *dummy)
330 int cpu = smp_processor_id();
331 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
332 nmi_cpu_save_registers(msrs);
333 spin_lock(&oprofilefs_lock);
334 model->setup_ctrs(model, msrs);
335 nmi_cpu_setup_mux(cpu, msrs);
336 spin_unlock(&oprofilefs_lock);
337 per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
338 apic_write(APIC_LVTPC, APIC_DM_NMI);
341 static struct notifier_block profile_exceptions_nb = {
342 .notifier_call = profile_exceptions_notify,
347 static int nmi_setup(void)
352 if (!allocate_msrs())
355 /* We need to serialize save and setup for HT because the subset
356 * of msrs are distinct for save and setup operations
359 /* Assume saved/restored counters are the same on all CPUs */
360 err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
364 for_each_possible_cpu(cpu) {
368 memcpy(per_cpu(cpu_msrs, cpu).counters,
369 per_cpu(cpu_msrs, 0).counters,
370 sizeof(struct op_msr) * model->num_counters);
372 memcpy(per_cpu(cpu_msrs, cpu).controls,
373 per_cpu(cpu_msrs, 0).controls,
374 sizeof(struct op_msr) * model->num_controls);
379 err = register_die_notifier(&profile_exceptions_nb);
383 on_each_cpu(nmi_cpu_setup, NULL, 1);
391 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
393 struct op_msr *counters = msrs->counters;
394 struct op_msr *controls = msrs->controls;
397 for (i = 0; i < model->num_controls; ++i) {
398 if (controls[i].addr)
399 wrmsrl(controls[i].addr, controls[i].saved);
402 for (i = 0; i < model->num_counters; ++i) {
403 if (counters[i].addr)
404 wrmsrl(counters[i].addr, counters[i].saved);
408 static void nmi_cpu_shutdown(void *dummy)
411 int cpu = smp_processor_id();
412 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
414 /* restoring APIC_LVTPC can trigger an apic error because the delivery
415 * mode and vector nr combination can be illegal. That's by design: on
416 * power on apic lvt contain a zero vector nr which are legal only for
417 * NMI delivery mode. So inhibit apic err before restoring lvtpc
419 v = apic_read(APIC_LVTERR);
420 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
421 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
422 apic_write(APIC_LVTERR, v);
423 nmi_cpu_restore_registers(msrs);
426 static void nmi_shutdown(void)
428 struct op_msrs *msrs;
431 on_each_cpu(nmi_cpu_shutdown, NULL, 1);
432 unregister_die_notifier(&profile_exceptions_nb);
433 msrs = &get_cpu_var(cpu_msrs);
434 model->shutdown(msrs);
436 put_cpu_var(cpu_msrs);
439 static int nmi_create_files(struct super_block *sb, struct dentry *root)
443 for (i = 0; i < model->num_virt_counters; ++i) {
447 /* quick little hack to _not_ expose a counter if it is not
448 * available for use. This should protect userspace app.
449 * NOTE: assumes 1:1 mapping here (that counters are organized
450 * sequentially in their struct assignment).
452 if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
455 snprintf(buf, sizeof(buf), "%d", i);
456 dir = oprofilefs_mkdir(sb, root, buf);
457 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
458 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
459 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
460 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
461 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
462 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
469 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
472 int cpu = (unsigned long)data;
474 case CPU_DOWN_FAILED:
476 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
478 case CPU_DOWN_PREPARE:
479 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
485 static struct notifier_block oprofile_cpu_nb = {
486 .notifier_call = oprofile_cpu_notifier
492 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
494 /* Only one CPU left, just stop that one */
495 if (nmi_enabled == 1)
500 static int nmi_resume(struct sys_device *dev)
502 if (nmi_enabled == 1)
507 static struct sysdev_class oprofile_sysclass = {
509 .resume = nmi_resume,
510 .suspend = nmi_suspend,
513 static struct sys_device device_oprofile = {
515 .cls = &oprofile_sysclass,
518 static int __init init_sysfs(void)
522 error = sysdev_class_register(&oprofile_sysclass);
524 error = sysdev_register(&device_oprofile);
528 static void exit_sysfs(void)
530 sysdev_unregister(&device_oprofile);
531 sysdev_class_unregister(&oprofile_sysclass);
535 #define init_sysfs() do { } while (0)
536 #define exit_sysfs() do { } while (0)
537 #endif /* CONFIG_PM */
539 static int __init p4_init(char **cpu_type)
541 __u8 cpu_model = boot_cpu_data.x86_model;
543 if (cpu_model > 6 || cpu_model == 5)
547 *cpu_type = "i386/p4";
551 switch (smp_num_siblings) {
553 *cpu_type = "i386/p4";
558 *cpu_type = "i386/p4-ht";
559 model = &op_p4_ht2_spec;
564 printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
565 printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
569 static int force_arch_perfmon;
570 static int force_cpu_type(const char *str, struct kernel_param *kp)
572 if (!strcmp(str, "arch_perfmon")) {
573 force_arch_perfmon = 1;
574 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
579 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
581 static int __init ppro_init(char **cpu_type)
583 __u8 cpu_model = boot_cpu_data.x86_model;
584 struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
586 if (force_arch_perfmon && cpu_has_arch_perfmon)
591 *cpu_type = "i386/ppro";
594 *cpu_type = "i386/pii";
598 *cpu_type = "i386/piii";
602 *cpu_type = "i386/p6_mobile";
605 *cpu_type = "i386/core";
608 *cpu_type = "i386/core_2";
612 spec = &op_arch_perfmon_spec;
613 *cpu_type = "i386/core_i7";
616 *cpu_type = "i386/atom";
627 /* in order to get sysfs right */
628 static int using_nmi;
630 int __init op_nmi_init(struct oprofile_operations *ops)
632 __u8 vendor = boot_cpu_data.x86_vendor;
633 __u8 family = boot_cpu_data.x86;
634 char *cpu_type = NULL;
642 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
646 cpu_type = "i386/athlon";
650 * Actually it could be i386/hammer too, but
651 * give user space an consistent name.
653 cpu_type = "x86-64/hammer";
656 cpu_type = "x86-64/family10";
659 cpu_type = "x86-64/family11h";
664 model = &op_amd_spec;
667 case X86_VENDOR_INTEL:
674 /* A P6-class processor */
676 ppro_init(&cpu_type);
686 if (!cpu_has_arch_perfmon)
689 /* use arch perfmon as fallback */
690 cpu_type = "i386/arch_perfmon";
691 model = &op_arch_perfmon_spec;
699 register_cpu_notifier(&oprofile_cpu_nb);
701 /* default values, can be overwritten by model */
702 ops->create_files = nmi_create_files;
703 ops->setup = nmi_setup;
704 ops->shutdown = nmi_shutdown;
705 ops->start = nmi_start;
706 ops->stop = nmi_stop;
707 ops->cpu_type = cpu_type;
710 ret = model->init(ops);
714 if (!model->num_virt_counters)
715 model->num_virt_counters = model->num_counters;
721 printk(KERN_INFO "oprofile: using NMI interrupt.\n");
725 void op_nmi_exit(void)
730 unregister_cpu_notifier(&oprofile_cpu_nb);