2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
10 #include <linux/interrupt.h>
11 #include <linux/seq_file.h>
12 #include <linux/debugfs.h>
13 #include <linux/pfn.h>
14 #include <linux/percpu.h>
15 #include <linux/gfp.h>
18 #include <asm/processor.h>
19 #include <asm/tlbflush.h>
20 #include <asm/sections.h>
21 #include <asm/setup.h>
22 #include <asm/uaccess.h>
23 #include <asm/pgalloc.h>
24 #include <asm/proto.h>
28 * The current flushing context - we pass it instead of 5 arguments:
37 unsigned force_split : 1;
43 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
44 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
45 * entries change the page attribute in parallel to some other cpu
46 * splitting a large page entry along with changing the attribute.
48 static DEFINE_SPINLOCK(cpa_lock);
50 #define CPA_FLUSHTLB 1
52 #define CPA_PAGES_ARRAY 4
55 static unsigned long direct_pages_count[PG_LEVEL_NUM];
57 void update_page_count(int level, unsigned long pages)
61 /* Protect against CPA */
62 spin_lock_irqsave(&pgd_lock, flags);
63 direct_pages_count[level] += pages;
64 spin_unlock_irqrestore(&pgd_lock, flags);
67 static void split_page_count(int level)
69 direct_pages_count[level]--;
70 direct_pages_count[level - 1] += PTRS_PER_PTE;
73 void arch_report_meminfo(struct seq_file *m)
75 seq_printf(m, "DirectMap4k: %8lu kB\n",
76 direct_pages_count[PG_LEVEL_4K] << 2);
77 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
78 seq_printf(m, "DirectMap2M: %8lu kB\n",
79 direct_pages_count[PG_LEVEL_2M] << 11);
81 seq_printf(m, "DirectMap4M: %8lu kB\n",
82 direct_pages_count[PG_LEVEL_2M] << 12);
86 seq_printf(m, "DirectMap1G: %8lu kB\n",
87 direct_pages_count[PG_LEVEL_1G] << 20);
91 static inline void split_page_count(int level) { }
96 static inline unsigned long highmap_start_pfn(void)
98 return __pa(_text) >> PAGE_SHIFT;
101 static inline unsigned long highmap_end_pfn(void)
103 return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
108 #ifdef CONFIG_DEBUG_PAGEALLOC
109 # define debug_pagealloc 1
111 # define debug_pagealloc 0
115 within(unsigned long addr, unsigned long start, unsigned long end)
117 return addr >= start && addr < end;
125 * clflush_cache_range - flush a cache range with clflush
126 * @addr: virtual start address
127 * @size: number of bytes to flush
129 * clflush is an unordered instruction which needs fencing with mfence
130 * to avoid ordering issues.
132 void clflush_cache_range(void *vaddr, unsigned int size)
134 void *vend = vaddr + size - 1;
138 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
141 * Flush any possible final partial cacheline:
147 EXPORT_SYMBOL_GPL(clflush_cache_range);
149 static void __cpa_flush_all(void *arg)
151 unsigned long cache = (unsigned long)arg;
154 * Flush all to work around Errata in early athlons regarding
155 * large page flushing.
159 if (cache && boot_cpu_data.x86 >= 4)
163 static void cpa_flush_all(unsigned long cache)
165 BUG_ON(irqs_disabled());
167 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
170 static void __cpa_flush_range(void *arg)
173 * We could optimize that further and do individual per page
174 * tlb invalidates for a low number of pages. Caveat: we must
175 * flush the high aliases on 64bit as well.
180 static void cpa_flush_range(unsigned long start, int numpages, int cache)
182 unsigned int i, level;
185 BUG_ON(irqs_disabled());
186 WARN_ON(PAGE_ALIGN(start) != start);
188 on_each_cpu(__cpa_flush_range, NULL, 1);
194 * We only need to flush on one CPU,
195 * clflush is a MESI-coherent instruction that
196 * will cause all other CPUs to flush the same
199 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
200 pte_t *pte = lookup_address(addr, &level);
203 * Only flush present addresses:
205 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
206 clflush_cache_range((void *) addr, PAGE_SIZE);
210 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
211 int in_flags, struct page **pages)
213 unsigned int i, level;
214 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
216 BUG_ON(irqs_disabled());
218 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
220 if (!cache || do_wbinvd)
224 * We only need to flush on one CPU,
225 * clflush is a MESI-coherent instruction that
226 * will cause all other CPUs to flush the same
229 for (i = 0; i < numpages; i++) {
233 if (in_flags & CPA_PAGES_ARRAY)
234 addr = (unsigned long)page_address(pages[i]);
238 pte = lookup_address(addr, &level);
241 * Only flush present addresses:
243 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
244 clflush_cache_range((void *)addr, PAGE_SIZE);
249 * Certain areas of memory on x86 require very specific protection flags,
250 * for example the BIOS area or kernel text. Callers don't always get this
251 * right (again, ioremap() on BIOS memory is not uncommon) so this function
252 * checks and fixes these known static required protection bits.
254 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
257 pgprot_t forbidden = __pgprot(0);
260 * The BIOS area between 640k and 1Mb needs to be executable for
261 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
263 if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
264 pgprot_val(forbidden) |= _PAGE_NX;
267 * The kernel text needs to be executable for obvious reasons
268 * Does not cover __inittext since that is gone later on. On
269 * 64bit we do not enforce !NX on the low mapping
271 if (within(address, (unsigned long)_text, (unsigned long)_etext))
272 pgprot_val(forbidden) |= _PAGE_NX;
275 * The .rodata section needs to be read-only. Using the pfn
276 * catches all aliases.
278 if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
279 __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
280 pgprot_val(forbidden) |= _PAGE_RW;
282 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
284 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
285 * kernel text mappings for the large page aligned text, rodata sections
286 * will be always read-only. For the kernel identity mappings covering
287 * the holes caused by this alignment can be anything that user asks.
289 * This will preserve the large page mappings for kernel text/data
292 if (kernel_set_to_readonly &&
293 within(address, (unsigned long)_text,
294 (unsigned long)__end_rodata_hpage_align)) {
298 * Don't enforce the !RW mapping for the kernel text mapping,
299 * if the current mapping is already using small page mapping.
300 * No need to work hard to preserve large page mappings in this
303 * This also fixes the Linux Xen paravirt guest boot failure
304 * (because of unexpected read-only mappings for kernel identity
305 * mappings). In this paravirt guest case, the kernel text
306 * mapping and the kernel identity mapping share the same
307 * page-table pages. Thus we can't really use different
308 * protections for the kernel text and identity mappings. Also,
309 * these shared mappings are made of small page mappings.
310 * Thus this don't enforce !RW mapping for small page kernel
311 * text mapping logic will help Linux Xen parvirt guest boot
314 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
315 pgprot_val(forbidden) |= _PAGE_RW;
319 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
325 * Lookup the page table entry for a virtual address. Return a pointer
326 * to the entry and the level of the mapping.
328 * Note: We return pud and pmd either when the entry is marked large
329 * or when the present bit is not set. Otherwise we would return a
330 * pointer to a nonexisting mapping.
332 pte_t *lookup_address(unsigned long address, unsigned int *level)
334 pgd_t *pgd = pgd_offset_k(address);
338 *level = PG_LEVEL_NONE;
343 pud = pud_offset(pgd, address);
347 *level = PG_LEVEL_1G;
348 if (pud_large(*pud) || !pud_present(*pud))
351 pmd = pmd_offset(pud, address);
355 *level = PG_LEVEL_2M;
356 if (pmd_large(*pmd) || !pmd_present(*pmd))
359 *level = PG_LEVEL_4K;
361 return pte_offset_kernel(pmd, address);
363 EXPORT_SYMBOL_GPL(lookup_address);
366 * Set the new pmd in all the pgds we know about:
368 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
371 set_pte_atomic(kpte, pte);
373 if (!SHARED_KERNEL_PMD) {
376 list_for_each_entry(page, &pgd_list, lru) {
381 pgd = (pgd_t *)page_address(page) + pgd_index(address);
382 pud = pud_offset(pgd, address);
383 pmd = pmd_offset(pud, address);
384 set_pte_atomic((pte_t *)pmd, pte);
391 try_preserve_large_page(pte_t *kpte, unsigned long address,
392 struct cpa_data *cpa)
394 unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn;
395 pte_t new_pte, old_pte, *tmp;
396 pgprot_t old_prot, new_prot;
400 if (cpa->force_split)
403 spin_lock_irqsave(&pgd_lock, flags);
405 * Check for races, another CPU might have split this page
408 tmp = lookup_address(address, &level);
414 psize = PMD_PAGE_SIZE;
415 pmask = PMD_PAGE_MASK;
419 psize = PUD_PAGE_SIZE;
420 pmask = PUD_PAGE_MASK;
429 * Calculate the number of pages, which fit into this large
430 * page starting at address:
432 nextpage_addr = (address + psize) & pmask;
433 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
434 if (numpages < cpa->numpages)
435 cpa->numpages = numpages;
438 * We are safe now. Check whether the new pgprot is the same:
441 old_prot = new_prot = pte_pgprot(old_pte);
443 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
444 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
447 * old_pte points to the large page base address. So we need
448 * to add the offset of the virtual address:
450 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
453 new_prot = static_protections(new_prot, address, pfn);
456 * We need to check the full range, whether
457 * static_protection() requires a different pgprot for one of
458 * the pages in the range we try to preserve:
460 addr = address + PAGE_SIZE;
462 for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) {
463 pgprot_t chk_prot = static_protections(new_prot, addr, pfn);
465 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
470 * If there are no changes, return. maxpages has been updated
473 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
479 * We need to change the attributes. Check, whether we can
480 * change the large page in one go. We request a split, when
481 * the address is not aligned and the number of pages is
482 * smaller than the number of pages in the large page. Note
483 * that we limited the number of possible pages already to
484 * the number of pages in the large page.
486 if (address == (nextpage_addr - psize) && cpa->numpages == numpages) {
488 * The address is aligned and the number of pages
489 * covers the full page.
491 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
492 __set_pmd_pte(kpte, address, new_pte);
493 cpa->flags |= CPA_FLUSHTLB;
498 spin_unlock_irqrestore(&pgd_lock, flags);
503 static int split_large_page(pte_t *kpte, unsigned long address)
505 unsigned long flags, pfn, pfninc = 1;
506 unsigned int i, level;
511 if (!debug_pagealloc)
512 spin_unlock(&cpa_lock);
513 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
514 if (!debug_pagealloc)
515 spin_lock(&cpa_lock);
519 spin_lock_irqsave(&pgd_lock, flags);
521 * Check for races, another CPU might have split this page
524 tmp = lookup_address(address, &level);
528 pbase = (pte_t *)page_address(base);
529 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
530 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
532 * If we ever want to utilize the PAT bit, we need to
533 * update this function to make sure it's converted from
534 * bit 12 to bit 7 when we cross from the 2MB level to
537 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
540 if (level == PG_LEVEL_1G) {
541 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
542 pgprot_val(ref_prot) |= _PAGE_PSE;
547 * Get the target pfn from the original entry:
549 pfn = pte_pfn(*kpte);
550 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
551 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
553 if (address >= (unsigned long)__va(0) &&
554 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
555 split_page_count(level);
558 if (address >= (unsigned long)__va(1UL<<32) &&
559 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
560 split_page_count(level);
564 * Install the new, split up pagetable.
566 * We use the standard kernel pagetable protections for the new
567 * pagetable protections, the actual ptes set above control the
568 * primary protection behavior:
570 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
573 * Intel Atom errata AAH41 workaround.
575 * The real fix should be in hw or in a microcode update, but
576 * we also probabilistically try to reduce the window of having
577 * a large TLB mixed with 4K TLBs while instruction fetches are
586 * If we dropped out via the lookup_address check under
587 * pgd_lock then stick the page back into the pool:
591 spin_unlock_irqrestore(&pgd_lock, flags);
596 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
600 * Ignore all non primary paths.
606 * Ignore the NULL PTE for kernel identity mapping, as it is expected
608 * Also set numpages to '1' indicating that we processed cpa req for
609 * one virtual address page and its pfn. TBD: numpages can be set based
610 * on the initial value and the level returned by lookup_address().
612 if (within(vaddr, PAGE_OFFSET,
613 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
615 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
618 WARN(1, KERN_WARNING "CPA: called for zero pte. "
619 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
626 static int __change_page_attr(struct cpa_data *cpa, int primary)
628 unsigned long address;
631 pte_t *kpte, old_pte;
633 if (cpa->flags & CPA_PAGES_ARRAY) {
634 struct page *page = cpa->pages[cpa->curpage];
635 if (unlikely(PageHighMem(page)))
637 address = (unsigned long)page_address(page);
638 } else if (cpa->flags & CPA_ARRAY)
639 address = cpa->vaddr[cpa->curpage];
641 address = *cpa->vaddr;
643 kpte = lookup_address(address, &level);
645 return __cpa_process_fault(cpa, address, primary);
648 if (!pte_val(old_pte))
649 return __cpa_process_fault(cpa, address, primary);
651 if (level == PG_LEVEL_4K) {
653 pgprot_t new_prot = pte_pgprot(old_pte);
654 unsigned long pfn = pte_pfn(old_pte);
656 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
657 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
659 new_prot = static_protections(new_prot, address, pfn);
662 * We need to keep the pfn from the existing PTE,
663 * after all we're only going to change it's attributes
664 * not the memory it points to
666 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
669 * Do we really change anything ?
671 if (pte_val(old_pte) != pte_val(new_pte)) {
672 set_pte_atomic(kpte, new_pte);
673 cpa->flags |= CPA_FLUSHTLB;
680 * Check, whether we can keep the large page intact
681 * and just change the pte:
683 do_split = try_preserve_large_page(kpte, address, cpa);
685 * When the range fits into the existing large page,
686 * return. cp->numpages and cpa->tlbflush have been updated in
693 * We have to split the large page:
695 err = split_large_page(kpte, address);
698 * Do a global flush tlb after splitting the large page
699 * and before we do the actual change page attribute in the PTE.
701 * With out this, we violate the TLB application note, that says
702 * "The TLBs may contain both ordinary and large-page
703 * translations for a 4-KByte range of linear addresses. This
704 * may occur if software modifies the paging structures so that
705 * the page size used for the address range changes. If the two
706 * translations differ with respect to page frame or attributes
707 * (e.g., permissions), processor behavior is undefined and may
708 * be implementation-specific."
710 * We do this global tlb flush inside the cpa_lock, so that we
711 * don't allow any other cpu, with stale tlb entries change the
712 * page attribute in parallel, that also falls into the
713 * just split large page entry.
722 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
724 static int cpa_process_alias(struct cpa_data *cpa)
726 struct cpa_data alias_cpa;
727 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
731 if (cpa->pfn >= max_pfn_mapped)
735 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
739 * No need to redo, when the primary call touched the direct
742 if (cpa->flags & CPA_PAGES_ARRAY) {
743 struct page *page = cpa->pages[cpa->curpage];
744 if (unlikely(PageHighMem(page)))
746 vaddr = (unsigned long)page_address(page);
747 } else if (cpa->flags & CPA_ARRAY)
748 vaddr = cpa->vaddr[cpa->curpage];
752 if (!(within(vaddr, PAGE_OFFSET,
753 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
756 alias_cpa.vaddr = &laddr;
757 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
759 ret = __change_page_attr_set_clr(&alias_cpa, 0);
766 * If the primary call didn't touch the high mapping already
767 * and the physical address is inside the kernel map, we need
768 * to touch the high mapped kernel as well:
770 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
771 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
772 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
773 __START_KERNEL_map - phys_base;
775 alias_cpa.vaddr = &temp_cpa_vaddr;
776 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
779 * The high mapping range is imprecise, so ignore the
782 __change_page_attr_set_clr(&alias_cpa, 0);
789 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
791 int ret, numpages = cpa->numpages;
795 * Store the remaining nr of pages for the large page
796 * preservation check.
798 cpa->numpages = numpages;
799 /* for array changes, we can't use large page */
800 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
803 if (!debug_pagealloc)
804 spin_lock(&cpa_lock);
805 ret = __change_page_attr(cpa, checkalias);
806 if (!debug_pagealloc)
807 spin_unlock(&cpa_lock);
812 ret = cpa_process_alias(cpa);
818 * Adjust the number of pages with the result of the
819 * CPA operation. Either a large page has been
820 * preserved or a single page update happened.
822 BUG_ON(cpa->numpages > numpages);
823 numpages -= cpa->numpages;
824 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
827 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
833 static inline int cache_attr(pgprot_t attr)
835 return pgprot_val(attr) &
836 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
839 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
840 pgprot_t mask_set, pgprot_t mask_clr,
841 int force_split, int in_flag,
845 int ret, cache, checkalias;
846 unsigned long baddr = 0;
849 * Check, if we are requested to change a not supported
852 mask_set = canon_pgprot(mask_set);
853 mask_clr = canon_pgprot(mask_clr);
854 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
857 /* Ensure we are PAGE_SIZE aligned */
858 if (in_flag & CPA_ARRAY) {
860 for (i = 0; i < numpages; i++) {
861 if (addr[i] & ~PAGE_MASK) {
862 addr[i] &= PAGE_MASK;
866 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
868 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
869 * No need to cehck in that case
871 if (*addr & ~PAGE_MASK) {
874 * People should not be passing in unaligned addresses:
879 * Save address for cache flush. *addr is modified in the call
880 * to __change_page_attr_set_clr() below.
885 /* Must avoid aliasing mappings in the highmem code */
892 cpa.numpages = numpages;
893 cpa.mask_set = mask_set;
894 cpa.mask_clr = mask_clr;
897 cpa.force_split = force_split;
899 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
900 cpa.flags |= in_flag;
902 /* No alias checking for _NX bit modifications */
903 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
905 ret = __change_page_attr_set_clr(&cpa, checkalias);
908 * Check whether we really changed something:
910 if (!(cpa.flags & CPA_FLUSHTLB))
914 * No need to flush, when we did not set any of the caching
917 cache = cache_attr(mask_set);
920 * On success we use clflush, when the CPU supports it to
921 * avoid the wbindv. If the CPU does not support it and in the
922 * error case we fall back to cpa_flush_all (which uses
925 if (!ret && cpu_has_clflush) {
926 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
927 cpa_flush_array(addr, numpages, cache,
930 cpa_flush_range(baddr, numpages, cache);
932 cpa_flush_all(cache);
938 static inline int change_page_attr_set(unsigned long *addr, int numpages,
939 pgprot_t mask, int array)
941 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
942 (array ? CPA_ARRAY : 0), NULL);
945 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
946 pgprot_t mask, int array)
948 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
949 (array ? CPA_ARRAY : 0), NULL);
952 static inline int cpa_set_pages_array(struct page **pages, int numpages,
955 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
956 CPA_PAGES_ARRAY, pages);
959 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
962 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
963 CPA_PAGES_ARRAY, pages);
966 int _set_memory_uc(unsigned long addr, int numpages)
969 * for now UC MINUS. see comments in ioremap_nocache()
971 return change_page_attr_set(&addr, numpages,
972 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
975 int set_memory_uc(unsigned long addr, int numpages)
980 * for now UC MINUS. see comments in ioremap_nocache()
982 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
983 _PAGE_CACHE_UC_MINUS, NULL);
987 ret = _set_memory_uc(addr, numpages);
994 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
998 EXPORT_SYMBOL(set_memory_uc);
1000 int _set_memory_array(unsigned long *addr, int addrinarray,
1001 unsigned long new_type)
1007 * for now UC MINUS. see comments in ioremap_nocache()
1009 for (i = 0; i < addrinarray; i++) {
1010 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
1016 ret = change_page_attr_set(addr, addrinarray,
1017 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
1019 if (!ret && new_type == _PAGE_CACHE_WC)
1020 ret = change_page_attr_set_clr(addr, addrinarray,
1021 __pgprot(_PAGE_CACHE_WC),
1022 __pgprot(_PAGE_CACHE_MASK),
1023 0, CPA_ARRAY, NULL);
1030 for (j = 0; j < i; j++)
1031 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1036 int set_memory_array_uc(unsigned long *addr, int addrinarray)
1038 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS);
1040 EXPORT_SYMBOL(set_memory_array_uc);
1042 int set_memory_array_wc(unsigned long *addr, int addrinarray)
1044 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC);
1046 EXPORT_SYMBOL(set_memory_array_wc);
1048 int _set_memory_wc(unsigned long addr, int numpages)
1051 unsigned long addr_copy = addr;
1053 ret = change_page_attr_set(&addr, numpages,
1054 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1056 ret = change_page_attr_set_clr(&addr_copy, numpages,
1057 __pgprot(_PAGE_CACHE_WC),
1058 __pgprot(_PAGE_CACHE_MASK),
1064 int set_memory_wc(unsigned long addr, int numpages)
1069 return set_memory_uc(addr, numpages);
1071 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1072 _PAGE_CACHE_WC, NULL);
1076 ret = _set_memory_wc(addr, numpages);
1083 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1087 EXPORT_SYMBOL(set_memory_wc);
1089 int _set_memory_wb(unsigned long addr, int numpages)
1091 return change_page_attr_clear(&addr, numpages,
1092 __pgprot(_PAGE_CACHE_MASK), 0);
1095 int set_memory_wb(unsigned long addr, int numpages)
1099 ret = _set_memory_wb(addr, numpages);
1103 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1106 EXPORT_SYMBOL(set_memory_wb);
1108 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1113 ret = change_page_attr_clear(addr, addrinarray,
1114 __pgprot(_PAGE_CACHE_MASK), 1);
1118 for (i = 0; i < addrinarray; i++)
1119 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1123 EXPORT_SYMBOL(set_memory_array_wb);
1125 int set_memory_x(unsigned long addr, int numpages)
1127 if (!(__supported_pte_mask & _PAGE_NX))
1130 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1132 EXPORT_SYMBOL(set_memory_x);
1134 int set_memory_nx(unsigned long addr, int numpages)
1136 if (!(__supported_pte_mask & _PAGE_NX))
1139 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1141 EXPORT_SYMBOL(set_memory_nx);
1143 int set_memory_ro(unsigned long addr, int numpages)
1145 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1147 EXPORT_SYMBOL_GPL(set_memory_ro);
1149 int set_memory_rw(unsigned long addr, int numpages)
1151 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1153 EXPORT_SYMBOL_GPL(set_memory_rw);
1155 int set_memory_np(unsigned long addr, int numpages)
1157 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1160 int set_memory_4k(unsigned long addr, int numpages)
1162 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1163 __pgprot(0), 1, 0, NULL);
1166 int set_pages_uc(struct page *page, int numpages)
1168 unsigned long addr = (unsigned long)page_address(page);
1170 return set_memory_uc(addr, numpages);
1172 EXPORT_SYMBOL(set_pages_uc);
1174 static int _set_pages_array(struct page **pages, int addrinarray,
1175 unsigned long new_type)
1177 unsigned long start;
1183 for (i = 0; i < addrinarray; i++) {
1184 if (PageHighMem(pages[i]))
1186 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1187 end = start + PAGE_SIZE;
1188 if (reserve_memtype(start, end, new_type, NULL))
1192 ret = cpa_set_pages_array(pages, addrinarray,
1193 __pgprot(_PAGE_CACHE_UC_MINUS));
1194 if (!ret && new_type == _PAGE_CACHE_WC)
1195 ret = change_page_attr_set_clr(NULL, addrinarray,
1196 __pgprot(_PAGE_CACHE_WC),
1197 __pgprot(_PAGE_CACHE_MASK),
1198 0, CPA_PAGES_ARRAY, pages);
1201 return 0; /* Success */
1204 for (i = 0; i < free_idx; i++) {
1205 if (PageHighMem(pages[i]))
1207 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1208 end = start + PAGE_SIZE;
1209 free_memtype(start, end);
1214 int set_pages_array_uc(struct page **pages, int addrinarray)
1216 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS);
1218 EXPORT_SYMBOL(set_pages_array_uc);
1220 int set_pages_array_wc(struct page **pages, int addrinarray)
1222 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC);
1224 EXPORT_SYMBOL(set_pages_array_wc);
1226 int set_pages_wb(struct page *page, int numpages)
1228 unsigned long addr = (unsigned long)page_address(page);
1230 return set_memory_wb(addr, numpages);
1232 EXPORT_SYMBOL(set_pages_wb);
1234 int set_pages_array_wb(struct page **pages, int addrinarray)
1237 unsigned long start;
1241 retval = cpa_clear_pages_array(pages, addrinarray,
1242 __pgprot(_PAGE_CACHE_MASK));
1246 for (i = 0; i < addrinarray; i++) {
1247 if (PageHighMem(pages[i]))
1249 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1250 end = start + PAGE_SIZE;
1251 free_memtype(start, end);
1256 EXPORT_SYMBOL(set_pages_array_wb);
1258 int set_pages_x(struct page *page, int numpages)
1260 unsigned long addr = (unsigned long)page_address(page);
1262 return set_memory_x(addr, numpages);
1264 EXPORT_SYMBOL(set_pages_x);
1266 int set_pages_nx(struct page *page, int numpages)
1268 unsigned long addr = (unsigned long)page_address(page);
1270 return set_memory_nx(addr, numpages);
1272 EXPORT_SYMBOL(set_pages_nx);
1274 int set_pages_ro(struct page *page, int numpages)
1276 unsigned long addr = (unsigned long)page_address(page);
1278 return set_memory_ro(addr, numpages);
1281 int set_pages_rw(struct page *page, int numpages)
1283 unsigned long addr = (unsigned long)page_address(page);
1285 return set_memory_rw(addr, numpages);
1288 #ifdef CONFIG_DEBUG_PAGEALLOC
1290 static int __set_pages_p(struct page *page, int numpages)
1292 unsigned long tempaddr = (unsigned long) page_address(page);
1293 struct cpa_data cpa = { .vaddr = &tempaddr,
1294 .numpages = numpages,
1295 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1296 .mask_clr = __pgprot(0),
1300 * No alias checking needed for setting present flag. otherwise,
1301 * we may need to break large pages for 64-bit kernel text
1302 * mappings (this adds to complexity if we want to do this from
1303 * atomic context especially). Let's keep it simple!
1305 return __change_page_attr_set_clr(&cpa, 0);
1308 static int __set_pages_np(struct page *page, int numpages)
1310 unsigned long tempaddr = (unsigned long) page_address(page);
1311 struct cpa_data cpa = { .vaddr = &tempaddr,
1312 .numpages = numpages,
1313 .mask_set = __pgprot(0),
1314 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1318 * No alias checking needed for setting not present flag. otherwise,
1319 * we may need to break large pages for 64-bit kernel text
1320 * mappings (this adds to complexity if we want to do this from
1321 * atomic context especially). Let's keep it simple!
1323 return __change_page_attr_set_clr(&cpa, 0);
1326 void kernel_map_pages(struct page *page, int numpages, int enable)
1328 if (PageHighMem(page))
1331 debug_check_no_locks_freed(page_address(page),
1332 numpages * PAGE_SIZE);
1336 * If page allocator is not up yet then do not call c_p_a():
1338 if (!debug_pagealloc_enabled)
1342 * The return value is ignored as the calls cannot fail.
1343 * Large pages for identity mappings are not used at boot time
1344 * and hence no memory allocations during large page split.
1347 __set_pages_p(page, numpages);
1349 __set_pages_np(page, numpages);
1352 * We should perform an IPI and flush all tlbs,
1353 * but that can deadlock->flush only current cpu:
1358 #ifdef CONFIG_HIBERNATION
1360 bool kernel_page_present(struct page *page)
1365 if (PageHighMem(page))
1368 pte = lookup_address((unsigned long)page_address(page), &level);
1369 return (pte_val(*pte) & _PAGE_PRESENT);
1372 #endif /* CONFIG_HIBERNATION */
1374 #endif /* CONFIG_DEBUG_PAGEALLOC */
1377 * The testcases use internal knowledge of the implementation that shouldn't
1378 * be exposed to the rest of the kernel. Include these directly here.
1380 #ifdef CONFIG_CPA_DEBUG
1381 #include "pageattr-test.c"