1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
11 #include <asm/fsp/fsp_support.h>
14 DECLARE_GLOBAL_DATA_PTR;
21 static const struct fsp_framebuffer {
26 } fsp_framebuffer_format_map[] = {
27 [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
28 [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
31 static int save_vesa_mode(struct vesa_mode_info *vesa)
33 const struct hob_graphics_info *ginfo;
34 const struct fsp_framebuffer *fbinfo;
36 ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
39 * If there is no graphics info structure, bail out and keep
40 * running on the serial console.
42 * Note: on some platforms (eg: Braswell), the FSP will not produce
43 * the graphics info HOB unless you plug some cables to the display
44 * interface (eg: HDMI) on the board.
47 debug("FSP graphics hand-off block not found\n");
51 vesa->x_resolution = ginfo->width;
52 vesa->y_resolution = ginfo->height;
53 vesa->bits_per_pixel = 32;
54 vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
55 vesa->phys_base_ptr = ginfo->fb_base;
57 if (ginfo->pixel_format >= pixel_bitmask) {
58 debug("FSP set unknown framebuffer format: %d\n",
62 fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format];
63 vesa->red_mask_size = fbinfo->red.size;
64 vesa->red_mask_pos = fbinfo->red.pos;
65 vesa->green_mask_size = fbinfo->green.size;
66 vesa->green_mask_pos = fbinfo->green.pos;
67 vesa->blue_mask_size = fbinfo->blue.size;
68 vesa->blue_mask_pos = fbinfo->blue.pos;
69 vesa->reserved_mask_size = fbinfo->rsvd.size;
70 vesa->reserved_mask_pos = fbinfo->rsvd.pos;
75 static int fsp_video_probe(struct udevice *dev)
77 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
78 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
79 struct vesa_mode_info *vesa = &mode_info.vesa;
87 /* Initialize vesa_mode_info structure */
88 ret = save_vesa_mode(vesa);
93 * The framebuffer base address in the FSP graphics info HOB reflects
94 * the value assigned by the FSP. After PCI enumeration the framebuffer
95 * base address may be relocated. Let's get the updated one from device.
97 * For IGD, it seems to be always on BAR2.
99 vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
101 ret = vbe_setup_video_priv(vesa, uc_priv, plat);
105 mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
108 printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
109 vesa->bits_per_pixel);
114 printf("No video mode configured in FSP!\n");
118 static const struct udevice_id fsp_video_ids[] = {
119 { .compatible = "fsp-fb" },
123 U_BOOT_DRIVER(fsp_video) = {
126 .of_match = fsp_video_ids,
127 .probe = fsp_video_probe,
130 static struct pci_device_id fsp_video_supported[] = {
131 { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) },
135 U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported);