2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
34 #include <linux/vmalloc.h>
35 #include <linux/module.h>
36 #include <linux/mman.h>
37 #include <linux/highmem.h>
38 #include <linux/iommu.h>
39 #include <linux/intel-iommu.h>
40 #include <linux/cpufreq.h>
41 #include <linux/user-return-notifier.h>
42 #include <linux/srcu.h>
43 #include <linux/slab.h>
44 #include <linux/perf_event.h>
45 #include <linux/uaccess.h>
46 #include <trace/events/kvm.h>
48 #define CREATE_TRACE_POINTS
51 #include <asm/debugreg.h>
58 #include <asm/pvclock.h>
59 #include <asm/div64.h>
61 #define MAX_IO_MSRS 256
62 #define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66 #define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
73 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
75 #define KVM_MAX_MCE_BANKS 32
76 #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
83 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
85 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
88 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
91 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
92 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
95 struct kvm_x86_ops *kvm_x86_ops;
96 EXPORT_SYMBOL_GPL(kvm_x86_ops);
99 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
101 #define KVM_NR_SHARED_MSRS 16
103 struct kvm_shared_msrs_global {
105 u32 msrs[KVM_NR_SHARED_MSRS];
108 struct kvm_shared_msrs {
109 struct user_return_notifier urn;
111 struct kvm_shared_msr_values {
114 } values[KVM_NR_SHARED_MSRS];
117 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
120 struct kvm_stats_debugfs_item debugfs_entries[] = {
121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
133 { "hypercalls", VCPU_STAT(hypercalls) },
134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
141 { "irq_injections", VCPU_STAT(irq_injections) },
142 { "nmi_injections", VCPU_STAT(nmi_injections) },
143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
150 { "mmu_unsync", VM_STAT(mmu_unsync) },
151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
152 { "largepages", VM_STAT(lpages) },
156 u64 __read_mostly host_xcr0;
158 static inline u32 bit(int bitno)
160 return 1 << (bitno & 31);
163 static void kvm_on_user_return(struct user_return_notifier *urn)
166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
168 struct kvm_shared_msr_values *values;
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
181 static void shared_msr_update(unsigned slot, u32 msr)
183 struct kvm_shared_msrs *smsr;
186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
198 void kvm_define_shared_msr(unsigned slot, u32 msr)
200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
206 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
208 static void kvm_shared_msr_cpu_online(void)
212 for (i = 0; i < shared_msrs_global.nr; ++i)
213 shared_msr_update(i, shared_msrs_global.msrs[i]);
216 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
230 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
232 static void drop_user_return_notifiers(void *ignore)
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
240 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
242 if (irqchip_in_kernel(vcpu->kvm))
243 return vcpu->arch.apic_base;
245 return vcpu->arch.apic_base;
247 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
249 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
255 vcpu->arch.apic_base = data;
257 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259 #define EXCPT_BENIGN 0
260 #define EXCPT_CONTRIBUTORY 1
263 static int exception_class(int vector)
273 return EXCPT_CONTRIBUTORY;
280 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
281 unsigned nr, bool has_error, u32 error_code,
287 kvm_make_request(KVM_REQ_EVENT, vcpu);
289 if (!vcpu->arch.exception.pending) {
291 vcpu->arch.exception.pending = true;
292 vcpu->arch.exception.has_error_code = has_error;
293 vcpu->arch.exception.nr = nr;
294 vcpu->arch.exception.error_code = error_code;
295 vcpu->arch.exception.reinject = reinject;
299 /* to check exception */
300 prev_nr = vcpu->arch.exception.nr;
301 if (prev_nr == DF_VECTOR) {
302 /* triple fault -> shutdown */
303 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
306 class1 = exception_class(prev_nr);
307 class2 = exception_class(nr);
308 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
309 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
310 /* generate double fault per SDM Table 5-5 */
311 vcpu->arch.exception.pending = true;
312 vcpu->arch.exception.has_error_code = true;
313 vcpu->arch.exception.nr = DF_VECTOR;
314 vcpu->arch.exception.error_code = 0;
316 /* replace previous exception with a new one in a hope
317 that instruction re-execution will regenerate lost
322 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324 kvm_multiple_exception(vcpu, nr, false, 0, false);
326 EXPORT_SYMBOL_GPL(kvm_queue_exception);
328 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330 kvm_multiple_exception(vcpu, nr, false, 0, true);
332 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334 void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
336 unsigned error_code = vcpu->arch.fault.error_code;
338 ++vcpu->stat.pf_guest;
339 vcpu->arch.cr2 = vcpu->arch.fault.address;
340 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
343 void kvm_propagate_fault(struct kvm_vcpu *vcpu)
345 if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
346 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
348 vcpu->arch.mmu.inject_page_fault(vcpu);
350 vcpu->arch.fault.nested = false;
353 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
355 kvm_make_request(KVM_REQ_EVENT, vcpu);
356 vcpu->arch.nmi_pending = 1;
358 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
360 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
362 kvm_multiple_exception(vcpu, nr, true, error_code, false);
364 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
366 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368 kvm_multiple_exception(vcpu, nr, true, error_code, true);
370 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
373 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
374 * a #GP and return false.
376 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
378 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
380 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
383 EXPORT_SYMBOL_GPL(kvm_require_cpl);
386 * This function will be used to read from the physical memory of the currently
387 * running guest. The difference to kvm_read_guest_page is that this function
388 * can read from guest physical or from the guest's guest physical memory.
390 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
391 gfn_t ngfn, void *data, int offset, int len,
397 ngpa = gfn_to_gpa(ngfn);
398 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
399 if (real_gfn == UNMAPPED_GVA)
402 real_gfn = gpa_to_gfn(real_gfn);
404 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
406 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
408 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
409 void *data, int offset, int len, u32 access)
411 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
412 data, offset, len, access);
416 * Load the pae pdptrs. Return true is they are all valid.
418 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
420 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
421 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
424 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
426 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
427 offset * sizeof(u64), sizeof(pdpte),
428 PFERR_USER_MASK|PFERR_WRITE_MASK);
433 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
434 if (is_present_gpte(pdpte[i]) &&
435 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
442 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
443 __set_bit(VCPU_EXREG_PDPTR,
444 (unsigned long *)&vcpu->arch.regs_avail);
445 __set_bit(VCPU_EXREG_PDPTR,
446 (unsigned long *)&vcpu->arch.regs_dirty);
451 EXPORT_SYMBOL_GPL(load_pdptrs);
453 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
455 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
461 if (is_long_mode(vcpu) || !is_pae(vcpu))
464 if (!test_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail))
468 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
469 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
470 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
471 PFERR_USER_MASK | PFERR_WRITE_MASK);
474 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
480 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
482 unsigned long old_cr0 = kvm_read_cr0(vcpu);
483 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
484 X86_CR0_CD | X86_CR0_NW;
489 if (cr0 & 0xffffffff00000000UL)
493 cr0 &= ~CR0_RESERVED_BITS;
495 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
498 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
501 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
503 if ((vcpu->arch.efer & EFER_LME)) {
508 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
513 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
518 kvm_x86_ops->set_cr0(vcpu, cr0);
520 if ((cr0 ^ old_cr0) & update_bits)
521 kvm_mmu_reset_context(vcpu);
524 EXPORT_SYMBOL_GPL(kvm_set_cr0);
526 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
528 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
530 EXPORT_SYMBOL_GPL(kvm_lmsw);
532 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
536 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
537 if (index != XCR_XFEATURE_ENABLED_MASK)
540 if (kvm_x86_ops->get_cpl(vcpu) != 0)
542 if (!(xcr0 & XSTATE_FP))
544 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
546 if (xcr0 & ~host_xcr0)
548 vcpu->arch.xcr0 = xcr0;
549 vcpu->guest_xcr0_loaded = 0;
553 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
555 if (__kvm_set_xcr(vcpu, index, xcr)) {
556 kvm_inject_gp(vcpu, 0);
561 EXPORT_SYMBOL_GPL(kvm_set_xcr);
563 static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
565 struct kvm_cpuid_entry2 *best;
567 best = kvm_find_cpuid_entry(vcpu, 1, 0);
568 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
571 static void update_cpuid(struct kvm_vcpu *vcpu)
573 struct kvm_cpuid_entry2 *best;
575 best = kvm_find_cpuid_entry(vcpu, 1, 0);
579 /* Update OSXSAVE bit */
580 if (cpu_has_xsave && best->function == 0x1) {
581 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
582 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
583 best->ecx |= bit(X86_FEATURE_OSXSAVE);
587 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
589 unsigned long old_cr4 = kvm_read_cr4(vcpu);
590 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
592 if (cr4 & CR4_RESERVED_BITS)
595 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
598 if (is_long_mode(vcpu)) {
599 if (!(cr4 & X86_CR4_PAE))
601 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
602 && ((cr4 ^ old_cr4) & pdptr_bits)
603 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
606 if (cr4 & X86_CR4_VMXE)
609 kvm_x86_ops->set_cr4(vcpu, cr4);
611 if ((cr4 ^ old_cr4) & pdptr_bits)
612 kvm_mmu_reset_context(vcpu);
614 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
619 EXPORT_SYMBOL_GPL(kvm_set_cr4);
621 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
623 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
624 kvm_mmu_sync_roots(vcpu);
625 kvm_mmu_flush_tlb(vcpu);
629 if (is_long_mode(vcpu)) {
630 if (cr3 & CR3_L_MODE_RESERVED_BITS)
634 if (cr3 & CR3_PAE_RESERVED_BITS)
636 if (is_paging(vcpu) &&
637 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
641 * We don't check reserved bits in nonpae mode, because
642 * this isn't enforced, and VMware depends on this.
647 * Does the new cr3 value map to physical memory? (Note, we
648 * catch an invalid cr3 even in real-mode, because it would
649 * cause trouble later on when we turn on paging anyway.)
651 * A real CPU would silently accept an invalid cr3 and would
652 * attempt to use it - with largely undefined (and often hard
653 * to debug) behavior on the guest side.
655 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
657 vcpu->arch.cr3 = cr3;
658 vcpu->arch.mmu.new_cr3(vcpu);
661 EXPORT_SYMBOL_GPL(kvm_set_cr3);
663 int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
665 if (cr8 & CR8_RESERVED_BITS)
667 if (irqchip_in_kernel(vcpu->kvm))
668 kvm_lapic_set_tpr(vcpu, cr8);
670 vcpu->arch.cr8 = cr8;
674 void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
676 if (__kvm_set_cr8(vcpu, cr8))
677 kvm_inject_gp(vcpu, 0);
679 EXPORT_SYMBOL_GPL(kvm_set_cr8);
681 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
683 if (irqchip_in_kernel(vcpu->kvm))
684 return kvm_lapic_get_cr8(vcpu);
686 return vcpu->arch.cr8;
688 EXPORT_SYMBOL_GPL(kvm_get_cr8);
690 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
694 vcpu->arch.db[dr] = val;
695 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
696 vcpu->arch.eff_db[dr] = val;
699 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
703 if (val & 0xffffffff00000000ULL)
705 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
708 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
712 if (val & 0xffffffff00000000ULL)
714 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
715 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
716 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
717 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
725 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
729 res = __kvm_set_dr(vcpu, dr, val);
731 kvm_queue_exception(vcpu, UD_VECTOR);
733 kvm_inject_gp(vcpu, 0);
737 EXPORT_SYMBOL_GPL(kvm_set_dr);
739 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
743 *val = vcpu->arch.db[dr];
746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
750 *val = vcpu->arch.dr6;
753 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
757 *val = vcpu->arch.dr7;
764 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
766 if (_kvm_get_dr(vcpu, dr, val)) {
767 kvm_queue_exception(vcpu, UD_VECTOR);
772 EXPORT_SYMBOL_GPL(kvm_get_dr);
775 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
776 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
778 * This list is modified at module load time to reflect the
779 * capabilities of the host cpu. This capabilities test skips MSRs that are
780 * kvm-specific. Those are put in the beginning of the list.
783 #define KVM_SAVE_MSRS_BEGIN 7
784 static u32 msrs_to_save[] = {
785 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
786 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
787 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
788 HV_X64_MSR_APIC_ASSIST_PAGE,
789 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
792 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
794 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
797 static unsigned num_msrs_to_save;
799 static u32 emulated_msrs[] = {
800 MSR_IA32_MISC_ENABLE,
805 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
807 u64 old_efer = vcpu->arch.efer;
809 if (efer & efer_reserved_bits)
813 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
816 if (efer & EFER_FFXSR) {
817 struct kvm_cpuid_entry2 *feat;
819 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
820 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
824 if (efer & EFER_SVME) {
825 struct kvm_cpuid_entry2 *feat;
827 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
828 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
833 efer |= vcpu->arch.efer & EFER_LMA;
835 kvm_x86_ops->set_efer(vcpu, efer);
837 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
838 kvm_mmu_reset_context(vcpu);
840 /* Update reserved bits */
841 if ((efer ^ old_efer) & EFER_NX)
842 kvm_mmu_reset_context(vcpu);
847 void kvm_enable_efer_bits(u64 mask)
849 efer_reserved_bits &= ~mask;
851 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
855 * Writes msr value into into the appropriate "register".
856 * Returns 0 on success, non-0 otherwise.
857 * Assumes vcpu_load() was already called.
859 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
861 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
865 * Adapt set_msr() to msr_io()'s calling convention
867 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
869 return kvm_set_msr(vcpu, index, *data);
872 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
876 struct pvclock_wall_clock wc;
877 struct timespec boot;
882 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
887 ++version; /* first time write, random junk */
891 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
894 * The guest calculates current wall clock time by adding
895 * system time (updated by kvm_write_guest_time below) to the
896 * wall clock specified here. guest system time equals host
897 * system time for us, thus we must fill in host boot time here.
901 wc.sec = boot.tv_sec;
902 wc.nsec = boot.tv_nsec;
903 wc.version = version;
905 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
908 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
911 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
913 uint32_t quotient, remainder;
915 /* Don't try to replace with do_div(), this one calculates
916 * "(dividend << 32) / divisor" */
918 : "=a" (quotient), "=d" (remainder)
919 : "0" (0), "1" (dividend), "r" (divisor) );
923 static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
925 uint64_t nsecs = 1000000000LL;
930 tps64 = tsc_khz * 1000LL;
931 while (tps64 > nsecs*2) {
936 tps32 = (uint32_t)tps64;
937 while (tps32 <= (uint32_t)nsecs) {
942 hv_clock->tsc_shift = shift;
943 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
945 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
946 __func__, tsc_khz, hv_clock->tsc_shift,
947 hv_clock->tsc_to_system_mul);
950 static inline u64 get_kernel_ns(void)
954 WARN_ON(preemptible());
956 monotonic_to_bootbased(&ts);
957 return timespec_to_ns(&ts);
960 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
962 static inline int kvm_tsc_changes_freq(void)
965 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
966 cpufreq_quick_get(cpu) != 0;
971 static inline u64 nsec_to_cycles(u64 nsec)
975 WARN_ON(preemptible());
976 if (kvm_tsc_changes_freq())
977 printk_once(KERN_WARNING
978 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
979 ret = nsec * __get_cpu_var(cpu_tsc_khz);
980 do_div(ret, USEC_PER_SEC);
984 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
986 struct kvm *kvm = vcpu->kvm;
987 u64 offset, ns, elapsed;
991 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
992 offset = data - native_read_tsc();
993 ns = get_kernel_ns();
994 elapsed = ns - kvm->arch.last_tsc_nsec;
995 sdiff = data - kvm->arch.last_tsc_write;
1000 * Special case: close write to TSC within 5 seconds of
1001 * another CPU is interpreted as an attempt to synchronize
1002 * The 5 seconds is to accomodate host load / swapping as
1003 * well as any reset of TSC during the boot process.
1005 * In that case, for a reliable TSC, we can match TSC offsets,
1006 * or make a best guest using elapsed value.
1008 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1009 elapsed < 5ULL * NSEC_PER_SEC) {
1010 if (!check_tsc_unstable()) {
1011 offset = kvm->arch.last_tsc_offset;
1012 pr_debug("kvm: matched tsc offset for %llu\n", data);
1014 u64 delta = nsec_to_cycles(elapsed);
1016 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1018 ns = kvm->arch.last_tsc_nsec;
1020 kvm->arch.last_tsc_nsec = ns;
1021 kvm->arch.last_tsc_write = data;
1022 kvm->arch.last_tsc_offset = offset;
1023 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1024 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1026 /* Reset of TSC must disable overshoot protection below */
1027 vcpu->arch.hv_clock.tsc_timestamp = 0;
1029 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1031 static int kvm_write_guest_time(struct kvm_vcpu *v)
1033 unsigned long flags;
1034 struct kvm_vcpu_arch *vcpu = &v->arch;
1036 unsigned long this_tsc_khz;
1037 s64 kernel_ns, max_kernel_ns;
1040 if ((!vcpu->time_page))
1043 /* Keep irq disabled to prevent changes to the clock */
1044 local_irq_save(flags);
1045 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
1046 kernel_ns = get_kernel_ns();
1047 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1048 local_irq_restore(flags);
1050 if (unlikely(this_tsc_khz == 0)) {
1051 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1056 * Time as measured by the TSC may go backwards when resetting the base
1057 * tsc_timestamp. The reason for this is that the TSC resolution is
1058 * higher than the resolution of the other clock scales. Thus, many
1059 * possible measurments of the TSC correspond to one measurement of any
1060 * other clock, and so a spread of values is possible. This is not a
1061 * problem for the computation of the nanosecond clock; with TSC rates
1062 * around 1GHZ, there can only be a few cycles which correspond to one
1063 * nanosecond value, and any path through this code will inevitably
1064 * take longer than that. However, with the kernel_ns value itself,
1065 * the precision may be much lower, down to HZ granularity. If the
1066 * first sampling of TSC against kernel_ns ends in the low part of the
1067 * range, and the second in the high end of the range, we can get:
1069 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1071 * As the sampling errors potentially range in the thousands of cycles,
1072 * it is possible such a time value has already been observed by the
1073 * guest. To protect against this, we must compute the system time as
1074 * observed by the guest and ensure the new system time is greater.
1077 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1078 max_kernel_ns = vcpu->last_guest_tsc -
1079 vcpu->hv_clock.tsc_timestamp;
1080 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1081 vcpu->hv_clock.tsc_to_system_mul,
1082 vcpu->hv_clock.tsc_shift);
1083 max_kernel_ns += vcpu->last_kernel_ns;
1086 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1087 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
1088 vcpu->hw_tsc_khz = this_tsc_khz;
1091 if (max_kernel_ns > kernel_ns)
1092 kernel_ns = max_kernel_ns;
1094 /* With all the info we got, fill in the values */
1095 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1096 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1097 vcpu->last_kernel_ns = kernel_ns;
1098 vcpu->last_guest_tsc = tsc_timestamp;
1099 vcpu->hv_clock.flags = 0;
1102 * The interface expects us to write an even number signaling that the
1103 * update is finished. Since the guest won't see the intermediate
1104 * state, we just increase by 2 at the end.
1106 vcpu->hv_clock.version += 2;
1108 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1110 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1111 sizeof(vcpu->hv_clock));
1113 kunmap_atomic(shared_kaddr, KM_USER0);
1115 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1119 static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1121 struct kvm_vcpu_arch *vcpu = &v->arch;
1123 if (!vcpu->time_page)
1125 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1129 static bool msr_mtrr_valid(unsigned msr)
1132 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1133 case MSR_MTRRfix64K_00000:
1134 case MSR_MTRRfix16K_80000:
1135 case MSR_MTRRfix16K_A0000:
1136 case MSR_MTRRfix4K_C0000:
1137 case MSR_MTRRfix4K_C8000:
1138 case MSR_MTRRfix4K_D0000:
1139 case MSR_MTRRfix4K_D8000:
1140 case MSR_MTRRfix4K_E0000:
1141 case MSR_MTRRfix4K_E8000:
1142 case MSR_MTRRfix4K_F0000:
1143 case MSR_MTRRfix4K_F8000:
1144 case MSR_MTRRdefType:
1145 case MSR_IA32_CR_PAT:
1153 static bool valid_pat_type(unsigned t)
1155 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1158 static bool valid_mtrr_type(unsigned t)
1160 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1163 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1167 if (!msr_mtrr_valid(msr))
1170 if (msr == MSR_IA32_CR_PAT) {
1171 for (i = 0; i < 8; i++)
1172 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1175 } else if (msr == MSR_MTRRdefType) {
1178 return valid_mtrr_type(data & 0xff);
1179 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1180 for (i = 0; i < 8 ; i++)
1181 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1186 /* variable MTRRs */
1187 return valid_mtrr_type(data & 0xff);
1190 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1192 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1194 if (!mtrr_valid(vcpu, msr, data))
1197 if (msr == MSR_MTRRdefType) {
1198 vcpu->arch.mtrr_state.def_type = data;
1199 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1200 } else if (msr == MSR_MTRRfix64K_00000)
1202 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1203 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1204 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1205 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1206 else if (msr == MSR_IA32_CR_PAT)
1207 vcpu->arch.pat = data;
1208 else { /* Variable MTRRs */
1209 int idx, is_mtrr_mask;
1212 idx = (msr - 0x200) / 2;
1213 is_mtrr_mask = msr - 0x200 - 2 * idx;
1216 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1219 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1223 kvm_mmu_reset_context(vcpu);
1227 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1229 u64 mcg_cap = vcpu->arch.mcg_cap;
1230 unsigned bank_num = mcg_cap & 0xff;
1233 case MSR_IA32_MCG_STATUS:
1234 vcpu->arch.mcg_status = data;
1236 case MSR_IA32_MCG_CTL:
1237 if (!(mcg_cap & MCG_CTL_P))
1239 if (data != 0 && data != ~(u64)0)
1241 vcpu->arch.mcg_ctl = data;
1244 if (msr >= MSR_IA32_MC0_CTL &&
1245 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1246 u32 offset = msr - MSR_IA32_MC0_CTL;
1247 /* only 0 or all 1s can be written to IA32_MCi_CTL
1248 * some Linux kernels though clear bit 10 in bank 4 to
1249 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1250 * this to avoid an uncatched #GP in the guest
1252 if ((offset & 0x3) == 0 &&
1253 data != 0 && (data | (1 << 10)) != ~(u64)0)
1255 vcpu->arch.mce_banks[offset] = data;
1263 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1265 struct kvm *kvm = vcpu->kvm;
1266 int lm = is_long_mode(vcpu);
1267 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1268 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1269 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1270 : kvm->arch.xen_hvm_config.blob_size_32;
1271 u32 page_num = data & ~PAGE_MASK;
1272 u64 page_addr = data & PAGE_MASK;
1277 if (page_num >= blob_size)
1280 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1284 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1286 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1295 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1297 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1300 static bool kvm_hv_msr_partition_wide(u32 msr)
1304 case HV_X64_MSR_GUEST_OS_ID:
1305 case HV_X64_MSR_HYPERCALL:
1313 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1315 struct kvm *kvm = vcpu->kvm;
1318 case HV_X64_MSR_GUEST_OS_ID:
1319 kvm->arch.hv_guest_os_id = data;
1320 /* setting guest os id to zero disables hypercall page */
1321 if (!kvm->arch.hv_guest_os_id)
1322 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1324 case HV_X64_MSR_HYPERCALL: {
1329 /* if guest os id is not set hypercall should remain disabled */
1330 if (!kvm->arch.hv_guest_os_id)
1332 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1333 kvm->arch.hv_hypercall = data;
1336 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1337 addr = gfn_to_hva(kvm, gfn);
1338 if (kvm_is_error_hva(addr))
1340 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1341 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1342 if (copy_to_user((void __user *)addr, instructions, 4))
1344 kvm->arch.hv_hypercall = data;
1348 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1349 "data 0x%llx\n", msr, data);
1355 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1358 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1361 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1362 vcpu->arch.hv_vapic = data;
1365 addr = gfn_to_hva(vcpu->kvm, data >>
1366 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1367 if (kvm_is_error_hva(addr))
1369 if (clear_user((void __user *)addr, PAGE_SIZE))
1371 vcpu->arch.hv_vapic = data;
1374 case HV_X64_MSR_EOI:
1375 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1376 case HV_X64_MSR_ICR:
1377 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1378 case HV_X64_MSR_TPR:
1379 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1381 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1382 "data 0x%llx\n", msr, data);
1389 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1393 return set_efer(vcpu, data);
1395 data &= ~(u64)0x40; /* ignore flush filter disable */
1396 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1398 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1403 case MSR_FAM10H_MMIO_CONF_BASE:
1405 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1410 case MSR_AMD64_NB_CFG:
1412 case MSR_IA32_DEBUGCTLMSR:
1414 /* We support the non-activated case already */
1416 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1417 /* Values other than LBR and BTF are vendor-specific,
1418 thus reserved and should throw a #GP */
1421 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1424 case MSR_IA32_UCODE_REV:
1425 case MSR_IA32_UCODE_WRITE:
1426 case MSR_VM_HSAVE_PA:
1427 case MSR_AMD64_PATCH_LOADER:
1429 case 0x200 ... 0x2ff:
1430 return set_msr_mtrr(vcpu, msr, data);
1431 case MSR_IA32_APICBASE:
1432 kvm_set_apic_base(vcpu, data);
1434 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1435 return kvm_x2apic_msr_write(vcpu, msr, data);
1436 case MSR_IA32_MISC_ENABLE:
1437 vcpu->arch.ia32_misc_enable_msr = data;
1439 case MSR_KVM_WALL_CLOCK_NEW:
1440 case MSR_KVM_WALL_CLOCK:
1441 vcpu->kvm->arch.wall_clock = data;
1442 kvm_write_wall_clock(vcpu->kvm, data);
1444 case MSR_KVM_SYSTEM_TIME_NEW:
1445 case MSR_KVM_SYSTEM_TIME: {
1446 if (vcpu->arch.time_page) {
1447 kvm_release_page_dirty(vcpu->arch.time_page);
1448 vcpu->arch.time_page = NULL;
1451 vcpu->arch.time = data;
1453 /* we verify if the enable bit is set... */
1457 /* ...but clean it before doing the actual write */
1458 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1460 vcpu->arch.time_page =
1461 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1463 if (is_error_page(vcpu->arch.time_page)) {
1464 kvm_release_page_clean(vcpu->arch.time_page);
1465 vcpu->arch.time_page = NULL;
1468 kvm_request_guest_time_update(vcpu);
1471 case MSR_IA32_MCG_CTL:
1472 case MSR_IA32_MCG_STATUS:
1473 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1474 return set_msr_mce(vcpu, msr, data);
1476 /* Performance counters are not protected by a CPUID bit,
1477 * so we should check all of them in the generic path for the sake of
1478 * cross vendor migration.
1479 * Writing a zero into the event select MSRs disables them,
1480 * which we perfectly emulate ;-). Any other value should be at least
1481 * reported, some guests depend on them.
1483 case MSR_P6_EVNTSEL0:
1484 case MSR_P6_EVNTSEL1:
1485 case MSR_K7_EVNTSEL0:
1486 case MSR_K7_EVNTSEL1:
1487 case MSR_K7_EVNTSEL2:
1488 case MSR_K7_EVNTSEL3:
1490 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1491 "0x%x data 0x%llx\n", msr, data);
1493 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1494 * so we ignore writes to make it happy.
1496 case MSR_P6_PERFCTR0:
1497 case MSR_P6_PERFCTR1:
1498 case MSR_K7_PERFCTR0:
1499 case MSR_K7_PERFCTR1:
1500 case MSR_K7_PERFCTR2:
1501 case MSR_K7_PERFCTR3:
1502 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1503 "0x%x data 0x%llx\n", msr, data);
1505 case MSR_K7_CLK_CTL:
1507 * Ignore all writes to this no longer documented MSR.
1508 * Writes are only relevant for old K7 processors,
1509 * all pre-dating SVM, but a recommended workaround from
1510 * AMD for these chips. It is possible to speicify the
1511 * affected processor models on the command line, hence
1512 * the need to ignore the workaround.
1515 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1516 if (kvm_hv_msr_partition_wide(msr)) {
1518 mutex_lock(&vcpu->kvm->lock);
1519 r = set_msr_hyperv_pw(vcpu, msr, data);
1520 mutex_unlock(&vcpu->kvm->lock);
1523 return set_msr_hyperv(vcpu, msr, data);
1526 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1527 return xen_hvm_config(vcpu, data);
1529 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1533 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1540 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1544 * Reads an msr value (of 'msr_index') into 'pdata'.
1545 * Returns 0 on success, non-0 otherwise.
1546 * Assumes vcpu_load() was already called.
1548 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1550 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1553 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1555 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1557 if (!msr_mtrr_valid(msr))
1560 if (msr == MSR_MTRRdefType)
1561 *pdata = vcpu->arch.mtrr_state.def_type +
1562 (vcpu->arch.mtrr_state.enabled << 10);
1563 else if (msr == MSR_MTRRfix64K_00000)
1565 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1566 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1567 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1568 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1569 else if (msr == MSR_IA32_CR_PAT)
1570 *pdata = vcpu->arch.pat;
1571 else { /* Variable MTRRs */
1572 int idx, is_mtrr_mask;
1575 idx = (msr - 0x200) / 2;
1576 is_mtrr_mask = msr - 0x200 - 2 * idx;
1579 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1582 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1589 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1592 u64 mcg_cap = vcpu->arch.mcg_cap;
1593 unsigned bank_num = mcg_cap & 0xff;
1596 case MSR_IA32_P5_MC_ADDR:
1597 case MSR_IA32_P5_MC_TYPE:
1600 case MSR_IA32_MCG_CAP:
1601 data = vcpu->arch.mcg_cap;
1603 case MSR_IA32_MCG_CTL:
1604 if (!(mcg_cap & MCG_CTL_P))
1606 data = vcpu->arch.mcg_ctl;
1608 case MSR_IA32_MCG_STATUS:
1609 data = vcpu->arch.mcg_status;
1612 if (msr >= MSR_IA32_MC0_CTL &&
1613 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1614 u32 offset = msr - MSR_IA32_MC0_CTL;
1615 data = vcpu->arch.mce_banks[offset];
1624 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1627 struct kvm *kvm = vcpu->kvm;
1630 case HV_X64_MSR_GUEST_OS_ID:
1631 data = kvm->arch.hv_guest_os_id;
1633 case HV_X64_MSR_HYPERCALL:
1634 data = kvm->arch.hv_hypercall;
1637 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1645 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1650 case HV_X64_MSR_VP_INDEX: {
1653 kvm_for_each_vcpu(r, v, vcpu->kvm)
1658 case HV_X64_MSR_EOI:
1659 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1660 case HV_X64_MSR_ICR:
1661 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1662 case HV_X64_MSR_TPR:
1663 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1665 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1672 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1677 case MSR_IA32_PLATFORM_ID:
1678 case MSR_IA32_UCODE_REV:
1679 case MSR_IA32_EBL_CR_POWERON:
1680 case MSR_IA32_DEBUGCTLMSR:
1681 case MSR_IA32_LASTBRANCHFROMIP:
1682 case MSR_IA32_LASTBRANCHTOIP:
1683 case MSR_IA32_LASTINTFROMIP:
1684 case MSR_IA32_LASTINTTOIP:
1687 case MSR_VM_HSAVE_PA:
1688 case MSR_P6_PERFCTR0:
1689 case MSR_P6_PERFCTR1:
1690 case MSR_P6_EVNTSEL0:
1691 case MSR_P6_EVNTSEL1:
1692 case MSR_K7_EVNTSEL0:
1693 case MSR_K7_PERFCTR0:
1694 case MSR_K8_INT_PENDING_MSG:
1695 case MSR_AMD64_NB_CFG:
1696 case MSR_FAM10H_MMIO_CONF_BASE:
1700 data = 0x500 | KVM_NR_VAR_MTRR;
1702 case 0x200 ... 0x2ff:
1703 return get_msr_mtrr(vcpu, msr, pdata);
1704 case 0xcd: /* fsb frequency */
1708 * MSR_EBC_FREQUENCY_ID
1709 * Conservative value valid for even the basic CPU models.
1710 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1711 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1712 * and 266MHz for model 3, or 4. Set Core Clock
1713 * Frequency to System Bus Frequency Ratio to 1 (bits
1714 * 31:24) even though these are only valid for CPU
1715 * models > 2, however guests may end up dividing or
1716 * multiplying by zero otherwise.
1718 case MSR_EBC_FREQUENCY_ID:
1721 case MSR_IA32_APICBASE:
1722 data = kvm_get_apic_base(vcpu);
1724 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1725 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1727 case MSR_IA32_MISC_ENABLE:
1728 data = vcpu->arch.ia32_misc_enable_msr;
1730 case MSR_IA32_PERF_STATUS:
1731 /* TSC increment by tick */
1733 /* CPU multiplier */
1734 data |= (((uint64_t)4ULL) << 40);
1737 data = vcpu->arch.efer;
1739 case MSR_KVM_WALL_CLOCK:
1740 case MSR_KVM_WALL_CLOCK_NEW:
1741 data = vcpu->kvm->arch.wall_clock;
1743 case MSR_KVM_SYSTEM_TIME:
1744 case MSR_KVM_SYSTEM_TIME_NEW:
1745 data = vcpu->arch.time;
1747 case MSR_IA32_P5_MC_ADDR:
1748 case MSR_IA32_P5_MC_TYPE:
1749 case MSR_IA32_MCG_CAP:
1750 case MSR_IA32_MCG_CTL:
1751 case MSR_IA32_MCG_STATUS:
1752 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1753 return get_msr_mce(vcpu, msr, pdata);
1754 case MSR_K7_CLK_CTL:
1756 * Provide expected ramp-up count for K7. All other
1757 * are set to zero, indicating minimum divisors for
1760 * This prevents guest kernels on AMD host with CPU
1761 * type 6, model 8 and higher from exploding due to
1762 * the rdmsr failing.
1766 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1767 if (kvm_hv_msr_partition_wide(msr)) {
1769 mutex_lock(&vcpu->kvm->lock);
1770 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1771 mutex_unlock(&vcpu->kvm->lock);
1774 return get_msr_hyperv(vcpu, msr, pdata);
1778 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1781 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1789 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1792 * Read or write a bunch of msrs. All parameters are kernel addresses.
1794 * @return number of msrs set successfully.
1796 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1797 struct kvm_msr_entry *entries,
1798 int (*do_msr)(struct kvm_vcpu *vcpu,
1799 unsigned index, u64 *data))
1803 idx = srcu_read_lock(&vcpu->kvm->srcu);
1804 for (i = 0; i < msrs->nmsrs; ++i)
1805 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1807 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1813 * Read or write a bunch of msrs. Parameters are user addresses.
1815 * @return number of msrs set successfully.
1817 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1818 int (*do_msr)(struct kvm_vcpu *vcpu,
1819 unsigned index, u64 *data),
1822 struct kvm_msrs msrs;
1823 struct kvm_msr_entry *entries;
1828 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1832 if (msrs.nmsrs >= MAX_IO_MSRS)
1836 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1837 entries = kmalloc(size, GFP_KERNEL);
1842 if (copy_from_user(entries, user_msrs->entries, size))
1845 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1850 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1861 int kvm_dev_ioctl_check_extension(long ext)
1866 case KVM_CAP_IRQCHIP:
1868 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1869 case KVM_CAP_SET_TSS_ADDR:
1870 case KVM_CAP_EXT_CPUID:
1871 case KVM_CAP_CLOCKSOURCE:
1873 case KVM_CAP_NOP_IO_DELAY:
1874 case KVM_CAP_MP_STATE:
1875 case KVM_CAP_SYNC_MMU:
1876 case KVM_CAP_REINJECT_CONTROL:
1877 case KVM_CAP_IRQ_INJECT_STATUS:
1878 case KVM_CAP_ASSIGN_DEV_IRQ:
1880 case KVM_CAP_IOEVENTFD:
1882 case KVM_CAP_PIT_STATE2:
1883 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
1884 case KVM_CAP_XEN_HVM:
1885 case KVM_CAP_ADJUST_CLOCK:
1886 case KVM_CAP_VCPU_EVENTS:
1887 case KVM_CAP_HYPERV:
1888 case KVM_CAP_HYPERV_VAPIC:
1889 case KVM_CAP_HYPERV_SPIN:
1890 case KVM_CAP_PCI_SEGMENT:
1891 case KVM_CAP_DEBUGREGS:
1892 case KVM_CAP_X86_ROBUST_SINGLESTEP:
1896 case KVM_CAP_COALESCED_MMIO:
1897 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1900 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1902 case KVM_CAP_NR_VCPUS:
1905 case KVM_CAP_NR_MEMSLOTS:
1906 r = KVM_MEMORY_SLOTS;
1908 case KVM_CAP_PV_MMU: /* obsolete */
1915 r = KVM_MAX_MCE_BANKS;
1928 long kvm_arch_dev_ioctl(struct file *filp,
1929 unsigned int ioctl, unsigned long arg)
1931 void __user *argp = (void __user *)arg;
1935 case KVM_GET_MSR_INDEX_LIST: {
1936 struct kvm_msr_list __user *user_msr_list = argp;
1937 struct kvm_msr_list msr_list;
1941 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1944 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1945 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1948 if (n < msr_list.nmsrs)
1951 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1952 num_msrs_to_save * sizeof(u32)))
1954 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
1956 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1961 case KVM_GET_SUPPORTED_CPUID: {
1962 struct kvm_cpuid2 __user *cpuid_arg = argp;
1963 struct kvm_cpuid2 cpuid;
1966 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1968 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1969 cpuid_arg->entries);
1974 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1979 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1982 mce_cap = KVM_MCE_CAP_SUPPORTED;
1984 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1996 static void wbinvd_ipi(void *garbage)
2001 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2003 return vcpu->kvm->arch.iommu_domain &&
2004 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2007 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2009 /* Address WBINVD may be executed by guest */
2010 if (need_emulate_wbinvd(vcpu)) {
2011 if (kvm_x86_ops->has_wbinvd_exit())
2012 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2013 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2014 smp_call_function_single(vcpu->cpu,
2015 wbinvd_ipi, NULL, 1);
2018 kvm_x86_ops->vcpu_load(vcpu, cpu);
2019 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2020 /* Make sure TSC doesn't go backwards */
2021 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2022 native_read_tsc() - vcpu->arch.last_host_tsc;
2024 mark_tsc_unstable("KVM discovered backwards TSC");
2025 if (check_tsc_unstable())
2026 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2027 kvm_migrate_timers(vcpu);
2032 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2034 kvm_x86_ops->vcpu_put(vcpu);
2035 kvm_put_guest_fpu(vcpu);
2036 vcpu->arch.last_host_tsc = native_read_tsc();
2039 static int is_efer_nx(void)
2041 unsigned long long efer = 0;
2043 rdmsrl_safe(MSR_EFER, &efer);
2044 return efer & EFER_NX;
2047 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2050 struct kvm_cpuid_entry2 *e, *entry;
2053 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2054 e = &vcpu->arch.cpuid_entries[i];
2055 if (e->function == 0x80000001) {
2060 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
2061 entry->edx &= ~(1 << 20);
2062 printk(KERN_INFO "kvm: guest NX capability removed\n");
2066 /* when an old userspace process fills a new kernel module */
2067 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2068 struct kvm_cpuid *cpuid,
2069 struct kvm_cpuid_entry __user *entries)
2072 struct kvm_cpuid_entry *cpuid_entries;
2075 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2078 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2082 if (copy_from_user(cpuid_entries, entries,
2083 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2085 for (i = 0; i < cpuid->nent; i++) {
2086 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2087 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2088 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2089 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2090 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2091 vcpu->arch.cpuid_entries[i].index = 0;
2092 vcpu->arch.cpuid_entries[i].flags = 0;
2093 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2094 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2095 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2097 vcpu->arch.cpuid_nent = cpuid->nent;
2098 cpuid_fix_nx_cap(vcpu);
2100 kvm_apic_set_version(vcpu);
2101 kvm_x86_ops->cpuid_update(vcpu);
2105 vfree(cpuid_entries);
2110 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
2111 struct kvm_cpuid2 *cpuid,
2112 struct kvm_cpuid_entry2 __user *entries)
2117 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2120 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
2121 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
2123 vcpu->arch.cpuid_nent = cpuid->nent;
2124 kvm_apic_set_version(vcpu);
2125 kvm_x86_ops->cpuid_update(vcpu);
2133 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
2134 struct kvm_cpuid2 *cpuid,
2135 struct kvm_cpuid_entry2 __user *entries)
2140 if (cpuid->nent < vcpu->arch.cpuid_nent)
2143 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
2144 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
2149 cpuid->nent = vcpu->arch.cpuid_nent;
2153 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2156 entry->function = function;
2157 entry->index = index;
2158 cpuid_count(entry->function, entry->index,
2159 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
2163 #define F(x) bit(X86_FEATURE_##x)
2165 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2166 u32 index, int *nent, int maxnent)
2168 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
2169 #ifdef CONFIG_X86_64
2170 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2172 unsigned f_lm = F(LM);
2174 unsigned f_gbpages = 0;
2177 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
2180 const u32 kvm_supported_word0_x86_features =
2181 F(FPU) | F(VME) | F(DE) | F(PSE) |
2182 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2183 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2184 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2185 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2186 0 /* Reserved, DS, ACPI */ | F(MMX) |
2187 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2188 0 /* HTT, TM, Reserved, PBE */;
2189 /* cpuid 0x80000001.edx */
2190 const u32 kvm_supported_word1_x86_features =
2191 F(FPU) | F(VME) | F(DE) | F(PSE) |
2192 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2193 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2194 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2195 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2196 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
2197 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
2198 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2200 const u32 kvm_supported_word4_x86_features =
2201 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
2202 0 /* DS-CPL, VMX, SMX, EST */ |
2203 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2204 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2205 0 /* Reserved, DCA */ | F(XMM4_1) |
2206 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
2207 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
2208 /* cpuid 0x80000001.ecx */
2209 const u32 kvm_supported_word6_x86_features =
2210 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
2211 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2212 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2213 0 /* SKINIT */ | 0 /* WDT */;
2215 /* all calls to cpuid_count() should be made on the same cpu */
2217 do_cpuid_1_ent(entry, function, index);
2222 entry->eax = min(entry->eax, (u32)0xd);
2225 entry->edx &= kvm_supported_word0_x86_features;
2226 entry->ecx &= kvm_supported_word4_x86_features;
2227 /* we support x2apic emulation even if host does not support
2228 * it since we emulate x2apic in software */
2229 entry->ecx |= F(X2APIC);
2231 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2232 * may return different values. This forces us to get_cpu() before
2233 * issuing the first command, and also to emulate this annoying behavior
2234 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2236 int t, times = entry->eax & 0xff;
2238 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2239 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2240 for (t = 1; t < times && *nent < maxnent; ++t) {
2241 do_cpuid_1_ent(&entry[t], function, 0);
2242 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2247 /* function 4 and 0xb have additional index. */
2251 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2252 /* read more entries until cache_type is zero */
2253 for (i = 1; *nent < maxnent; ++i) {
2254 cache_type = entry[i - 1].eax & 0x1f;
2257 do_cpuid_1_ent(&entry[i], function, i);
2259 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2267 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2268 /* read more entries until level_type is zero */
2269 for (i = 1; *nent < maxnent; ++i) {
2270 level_type = entry[i - 1].ecx & 0xff00;
2273 do_cpuid_1_ent(&entry[i], function, i);
2275 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2283 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2284 for (i = 1; *nent < maxnent; ++i) {
2285 if (entry[i - 1].eax == 0 && i != 2)
2287 do_cpuid_1_ent(&entry[i], function, i);
2289 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2294 case KVM_CPUID_SIGNATURE: {
2295 char signature[12] = "KVMKVMKVM\0\0";
2296 u32 *sigptr = (u32 *)signature;
2298 entry->ebx = sigptr[0];
2299 entry->ecx = sigptr[1];
2300 entry->edx = sigptr[2];
2303 case KVM_CPUID_FEATURES:
2304 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2305 (1 << KVM_FEATURE_NOP_IO_DELAY) |
2306 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2307 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
2313 entry->eax = min(entry->eax, 0x8000001a);
2316 entry->edx &= kvm_supported_word1_x86_features;
2317 entry->ecx &= kvm_supported_word6_x86_features;
2321 kvm_x86_ops->set_supported_cpuid(function, entry);
2328 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
2329 struct kvm_cpuid_entry2 __user *entries)
2331 struct kvm_cpuid_entry2 *cpuid_entries;
2332 int limit, nent = 0, r = -E2BIG;
2335 if (cpuid->nent < 1)
2337 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2338 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
2340 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2344 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2345 limit = cpuid_entries[0].eax;
2346 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2347 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2348 &nent, cpuid->nent);
2350 if (nent >= cpuid->nent)
2353 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2354 limit = cpuid_entries[nent - 1].eax;
2355 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2356 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2357 &nent, cpuid->nent);
2362 if (nent >= cpuid->nent)
2365 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2369 if (nent >= cpuid->nent)
2372 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2376 if (nent >= cpuid->nent)
2380 if (copy_to_user(entries, cpuid_entries,
2381 nent * sizeof(struct kvm_cpuid_entry2)))
2387 vfree(cpuid_entries);
2392 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2393 struct kvm_lapic_state *s)
2395 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2400 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2401 struct kvm_lapic_state *s)
2403 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2404 kvm_apic_post_state_restore(vcpu);
2405 update_cr8_intercept(vcpu);
2410 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2411 struct kvm_interrupt *irq)
2413 if (irq->irq < 0 || irq->irq >= 256)
2415 if (irqchip_in_kernel(vcpu->kvm))
2418 kvm_queue_interrupt(vcpu, irq->irq, false);
2419 kvm_make_request(KVM_REQ_EVENT, vcpu);
2424 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2426 kvm_inject_nmi(vcpu);
2431 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2432 struct kvm_tpr_access_ctl *tac)
2436 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2440 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2444 unsigned bank_num = mcg_cap & 0xff, bank;
2447 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2449 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2452 vcpu->arch.mcg_cap = mcg_cap;
2453 /* Init IA32_MCG_CTL to all 1s */
2454 if (mcg_cap & MCG_CTL_P)
2455 vcpu->arch.mcg_ctl = ~(u64)0;
2456 /* Init IA32_MCi_CTL to all 1s */
2457 for (bank = 0; bank < bank_num; bank++)
2458 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2463 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2464 struct kvm_x86_mce *mce)
2466 u64 mcg_cap = vcpu->arch.mcg_cap;
2467 unsigned bank_num = mcg_cap & 0xff;
2468 u64 *banks = vcpu->arch.mce_banks;
2470 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2473 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2474 * reporting is disabled
2476 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2477 vcpu->arch.mcg_ctl != ~(u64)0)
2479 banks += 4 * mce->bank;
2481 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2482 * reporting is disabled for the bank
2484 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2486 if (mce->status & MCI_STATUS_UC) {
2487 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2488 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2489 printk(KERN_DEBUG "kvm: set_mce: "
2490 "injects mce exception while "
2491 "previous one is in progress!\n");
2492 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2495 if (banks[1] & MCI_STATUS_VAL)
2496 mce->status |= MCI_STATUS_OVER;
2497 banks[2] = mce->addr;
2498 banks[3] = mce->misc;
2499 vcpu->arch.mcg_status = mce->mcg_status;
2500 banks[1] = mce->status;
2501 kvm_queue_exception(vcpu, MC_VECTOR);
2502 } else if (!(banks[1] & MCI_STATUS_VAL)
2503 || !(banks[1] & MCI_STATUS_UC)) {
2504 if (banks[1] & MCI_STATUS_VAL)
2505 mce->status |= MCI_STATUS_OVER;
2506 banks[2] = mce->addr;
2507 banks[3] = mce->misc;
2508 banks[1] = mce->status;
2510 banks[1] |= MCI_STATUS_OVER;
2514 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2515 struct kvm_vcpu_events *events)
2517 events->exception.injected =
2518 vcpu->arch.exception.pending &&
2519 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2520 events->exception.nr = vcpu->arch.exception.nr;
2521 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2522 events->exception.error_code = vcpu->arch.exception.error_code;
2524 events->interrupt.injected =
2525 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2526 events->interrupt.nr = vcpu->arch.interrupt.nr;
2527 events->interrupt.soft = 0;
2528 events->interrupt.shadow =
2529 kvm_x86_ops->get_interrupt_shadow(vcpu,
2530 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2532 events->nmi.injected = vcpu->arch.nmi_injected;
2533 events->nmi.pending = vcpu->arch.nmi_pending;
2534 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2536 events->sipi_vector = vcpu->arch.sipi_vector;
2538 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2539 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2540 | KVM_VCPUEVENT_VALID_SHADOW);
2543 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2544 struct kvm_vcpu_events *events)
2546 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2547 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2548 | KVM_VCPUEVENT_VALID_SHADOW))
2551 vcpu->arch.exception.pending = events->exception.injected;
2552 vcpu->arch.exception.nr = events->exception.nr;
2553 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2554 vcpu->arch.exception.error_code = events->exception.error_code;
2556 vcpu->arch.interrupt.pending = events->interrupt.injected;
2557 vcpu->arch.interrupt.nr = events->interrupt.nr;
2558 vcpu->arch.interrupt.soft = events->interrupt.soft;
2559 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2560 kvm_pic_clear_isr_ack(vcpu->kvm);
2561 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2562 kvm_x86_ops->set_interrupt_shadow(vcpu,
2563 events->interrupt.shadow);
2565 vcpu->arch.nmi_injected = events->nmi.injected;
2566 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2567 vcpu->arch.nmi_pending = events->nmi.pending;
2568 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2570 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2571 vcpu->arch.sipi_vector = events->sipi_vector;
2573 kvm_make_request(KVM_REQ_EVENT, vcpu);
2578 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2579 struct kvm_debugregs *dbgregs)
2581 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2582 dbgregs->dr6 = vcpu->arch.dr6;
2583 dbgregs->dr7 = vcpu->arch.dr7;
2587 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2588 struct kvm_debugregs *dbgregs)
2593 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2594 vcpu->arch.dr6 = dbgregs->dr6;
2595 vcpu->arch.dr7 = dbgregs->dr7;
2600 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2601 struct kvm_xsave *guest_xsave)
2604 memcpy(guest_xsave->region,
2605 &vcpu->arch.guest_fpu.state->xsave,
2608 memcpy(guest_xsave->region,
2609 &vcpu->arch.guest_fpu.state->fxsave,
2610 sizeof(struct i387_fxsave_struct));
2611 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2616 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2617 struct kvm_xsave *guest_xsave)
2620 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2623 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2624 guest_xsave->region, xstate_size);
2626 if (xstate_bv & ~XSTATE_FPSSE)
2628 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2629 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2634 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2635 struct kvm_xcrs *guest_xcrs)
2637 if (!cpu_has_xsave) {
2638 guest_xcrs->nr_xcrs = 0;
2642 guest_xcrs->nr_xcrs = 1;
2643 guest_xcrs->flags = 0;
2644 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2645 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2648 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2649 struct kvm_xcrs *guest_xcrs)
2656 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2659 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2660 /* Only support XCR0 currently */
2661 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2662 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2663 guest_xcrs->xcrs[0].value);
2671 long kvm_arch_vcpu_ioctl(struct file *filp,
2672 unsigned int ioctl, unsigned long arg)
2674 struct kvm_vcpu *vcpu = filp->private_data;
2675 void __user *argp = (void __user *)arg;
2678 struct kvm_lapic_state *lapic;
2679 struct kvm_xsave *xsave;
2680 struct kvm_xcrs *xcrs;
2686 case KVM_GET_LAPIC: {
2688 if (!vcpu->arch.apic)
2690 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2695 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2699 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2704 case KVM_SET_LAPIC: {
2706 if (!vcpu->arch.apic)
2708 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2713 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
2715 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2721 case KVM_INTERRUPT: {
2722 struct kvm_interrupt irq;
2725 if (copy_from_user(&irq, argp, sizeof irq))
2727 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2734 r = kvm_vcpu_ioctl_nmi(vcpu);
2740 case KVM_SET_CPUID: {
2741 struct kvm_cpuid __user *cpuid_arg = argp;
2742 struct kvm_cpuid cpuid;
2745 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2747 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2752 case KVM_SET_CPUID2: {
2753 struct kvm_cpuid2 __user *cpuid_arg = argp;
2754 struct kvm_cpuid2 cpuid;
2757 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2759 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2760 cpuid_arg->entries);
2765 case KVM_GET_CPUID2: {
2766 struct kvm_cpuid2 __user *cpuid_arg = argp;
2767 struct kvm_cpuid2 cpuid;
2770 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2772 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2773 cpuid_arg->entries);
2777 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2783 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2786 r = msr_io(vcpu, argp, do_set_msr, 0);
2788 case KVM_TPR_ACCESS_REPORTING: {
2789 struct kvm_tpr_access_ctl tac;
2792 if (copy_from_user(&tac, argp, sizeof tac))
2794 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2798 if (copy_to_user(argp, &tac, sizeof tac))
2803 case KVM_SET_VAPIC_ADDR: {
2804 struct kvm_vapic_addr va;
2807 if (!irqchip_in_kernel(vcpu->kvm))
2810 if (copy_from_user(&va, argp, sizeof va))
2813 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2816 case KVM_X86_SETUP_MCE: {
2820 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2822 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2825 case KVM_X86_SET_MCE: {
2826 struct kvm_x86_mce mce;
2829 if (copy_from_user(&mce, argp, sizeof mce))
2831 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2834 case KVM_GET_VCPU_EVENTS: {
2835 struct kvm_vcpu_events events;
2837 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2840 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2845 case KVM_SET_VCPU_EVENTS: {
2846 struct kvm_vcpu_events events;
2849 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2852 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2855 case KVM_GET_DEBUGREGS: {
2856 struct kvm_debugregs dbgregs;
2858 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2861 if (copy_to_user(argp, &dbgregs,
2862 sizeof(struct kvm_debugregs)))
2867 case KVM_SET_DEBUGREGS: {
2868 struct kvm_debugregs dbgregs;
2871 if (copy_from_user(&dbgregs, argp,
2872 sizeof(struct kvm_debugregs)))
2875 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2878 case KVM_GET_XSAVE: {
2879 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2884 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2887 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2892 case KVM_SET_XSAVE: {
2893 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2899 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2902 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2905 case KVM_GET_XCRS: {
2906 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2911 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2914 if (copy_to_user(argp, u.xcrs,
2915 sizeof(struct kvm_xcrs)))
2920 case KVM_SET_XCRS: {
2921 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2927 if (copy_from_user(u.xcrs, argp,
2928 sizeof(struct kvm_xcrs)))
2931 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2942 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2946 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2948 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2952 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2955 kvm->arch.ept_identity_map_addr = ident_addr;
2959 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2960 u32 kvm_nr_mmu_pages)
2962 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2965 mutex_lock(&kvm->slots_lock);
2966 spin_lock(&kvm->mmu_lock);
2968 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2969 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2971 spin_unlock(&kvm->mmu_lock);
2972 mutex_unlock(&kvm->slots_lock);
2976 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2978 return kvm->arch.n_max_mmu_pages;
2981 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2986 switch (chip->chip_id) {
2987 case KVM_IRQCHIP_PIC_MASTER:
2988 memcpy(&chip->chip.pic,
2989 &pic_irqchip(kvm)->pics[0],
2990 sizeof(struct kvm_pic_state));
2992 case KVM_IRQCHIP_PIC_SLAVE:
2993 memcpy(&chip->chip.pic,
2994 &pic_irqchip(kvm)->pics[1],
2995 sizeof(struct kvm_pic_state));
2997 case KVM_IRQCHIP_IOAPIC:
2998 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3007 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3012 switch (chip->chip_id) {
3013 case KVM_IRQCHIP_PIC_MASTER:
3014 raw_spin_lock(&pic_irqchip(kvm)->lock);
3015 memcpy(&pic_irqchip(kvm)->pics[0],
3017 sizeof(struct kvm_pic_state));
3018 raw_spin_unlock(&pic_irqchip(kvm)->lock);
3020 case KVM_IRQCHIP_PIC_SLAVE:
3021 raw_spin_lock(&pic_irqchip(kvm)->lock);
3022 memcpy(&pic_irqchip(kvm)->pics[1],
3024 sizeof(struct kvm_pic_state));
3025 raw_spin_unlock(&pic_irqchip(kvm)->lock);
3027 case KVM_IRQCHIP_IOAPIC:
3028 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3034 kvm_pic_update_irq(pic_irqchip(kvm));
3038 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3042 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3043 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3044 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3048 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3052 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3053 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3054 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3055 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3059 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3063 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3064 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3065 sizeof(ps->channels));
3066 ps->flags = kvm->arch.vpit->pit_state.flags;
3067 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3071 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3073 int r = 0, start = 0;
3074 u32 prev_legacy, cur_legacy;
3075 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3076 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3077 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3078 if (!prev_legacy && cur_legacy)
3080 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3081 sizeof(kvm->arch.vpit->pit_state.channels));
3082 kvm->arch.vpit->pit_state.flags = ps->flags;
3083 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3084 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3088 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3089 struct kvm_reinject_control *control)
3091 if (!kvm->arch.vpit)
3093 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3094 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3095 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3100 * Get (and clear) the dirty memory log for a memory slot.
3102 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3103 struct kvm_dirty_log *log)
3106 struct kvm_memory_slot *memslot;
3108 unsigned long is_dirty = 0;
3110 mutex_lock(&kvm->slots_lock);
3113 if (log->slot >= KVM_MEMORY_SLOTS)
3116 memslot = &kvm->memslots->memslots[log->slot];
3118 if (!memslot->dirty_bitmap)
3121 n = kvm_dirty_bitmap_bytes(memslot);
3123 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3124 is_dirty = memslot->dirty_bitmap[i];
3126 /* If nothing is dirty, don't bother messing with page tables. */
3128 struct kvm_memslots *slots, *old_slots;
3129 unsigned long *dirty_bitmap;
3131 spin_lock(&kvm->mmu_lock);
3132 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3133 spin_unlock(&kvm->mmu_lock);
3136 dirty_bitmap = vmalloc(n);
3139 memset(dirty_bitmap, 0, n);
3142 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3144 vfree(dirty_bitmap);
3147 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3148 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3150 old_slots = kvm->memslots;
3151 rcu_assign_pointer(kvm->memslots, slots);
3152 synchronize_srcu_expedited(&kvm->srcu);
3153 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3157 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3158 vfree(dirty_bitmap);
3161 vfree(dirty_bitmap);
3164 if (clear_user(log->dirty_bitmap, n))
3170 mutex_unlock(&kvm->slots_lock);
3174 long kvm_arch_vm_ioctl(struct file *filp,
3175 unsigned int ioctl, unsigned long arg)
3177 struct kvm *kvm = filp->private_data;
3178 void __user *argp = (void __user *)arg;
3181 * This union makes it completely explicit to gcc-3.x
3182 * that these two variables' stack usage should be
3183 * combined, not added together.
3186 struct kvm_pit_state ps;
3187 struct kvm_pit_state2 ps2;
3188 struct kvm_pit_config pit_config;
3192 case KVM_SET_TSS_ADDR:
3193 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3197 case KVM_SET_IDENTITY_MAP_ADDR: {
3201 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3203 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3208 case KVM_SET_NR_MMU_PAGES:
3209 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3213 case KVM_GET_NR_MMU_PAGES:
3214 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3216 case KVM_CREATE_IRQCHIP: {
3217 struct kvm_pic *vpic;
3219 mutex_lock(&kvm->lock);
3222 goto create_irqchip_unlock;
3224 vpic = kvm_create_pic(kvm);
3226 r = kvm_ioapic_init(kvm);
3228 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3231 goto create_irqchip_unlock;
3234 goto create_irqchip_unlock;
3236 kvm->arch.vpic = vpic;
3238 r = kvm_setup_default_irq_routing(kvm);
3240 mutex_lock(&kvm->irq_lock);
3241 kvm_ioapic_destroy(kvm);
3242 kvm_destroy_pic(kvm);
3243 mutex_unlock(&kvm->irq_lock);
3245 create_irqchip_unlock:
3246 mutex_unlock(&kvm->lock);
3249 case KVM_CREATE_PIT:
3250 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3252 case KVM_CREATE_PIT2:
3254 if (copy_from_user(&u.pit_config, argp,
3255 sizeof(struct kvm_pit_config)))
3258 mutex_lock(&kvm->slots_lock);
3261 goto create_pit_unlock;
3263 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3267 mutex_unlock(&kvm->slots_lock);
3269 case KVM_IRQ_LINE_STATUS:
3270 case KVM_IRQ_LINE: {
3271 struct kvm_irq_level irq_event;
3274 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3277 if (irqchip_in_kernel(kvm)) {
3279 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3280 irq_event.irq, irq_event.level);
3281 if (ioctl == KVM_IRQ_LINE_STATUS) {
3283 irq_event.status = status;
3284 if (copy_to_user(argp, &irq_event,
3292 case KVM_GET_IRQCHIP: {
3293 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3294 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3300 if (copy_from_user(chip, argp, sizeof *chip))
3301 goto get_irqchip_out;
3303 if (!irqchip_in_kernel(kvm))
3304 goto get_irqchip_out;
3305 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3307 goto get_irqchip_out;
3309 if (copy_to_user(argp, chip, sizeof *chip))
3310 goto get_irqchip_out;
3318 case KVM_SET_IRQCHIP: {
3319 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3320 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3326 if (copy_from_user(chip, argp, sizeof *chip))
3327 goto set_irqchip_out;
3329 if (!irqchip_in_kernel(kvm))
3330 goto set_irqchip_out;
3331 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3333 goto set_irqchip_out;
3343 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3346 if (!kvm->arch.vpit)
3348 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3352 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3359 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3362 if (!kvm->arch.vpit)
3364 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3370 case KVM_GET_PIT2: {
3372 if (!kvm->arch.vpit)
3374 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3378 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3383 case KVM_SET_PIT2: {
3385 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3388 if (!kvm->arch.vpit)
3390 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3396 case KVM_REINJECT_CONTROL: {
3397 struct kvm_reinject_control control;
3399 if (copy_from_user(&control, argp, sizeof(control)))
3401 r = kvm_vm_ioctl_reinject(kvm, &control);
3407 case KVM_XEN_HVM_CONFIG: {
3409 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3410 sizeof(struct kvm_xen_hvm_config)))
3413 if (kvm->arch.xen_hvm_config.flags)
3418 case KVM_SET_CLOCK: {
3419 struct kvm_clock_data user_ns;
3424 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3432 now_ns = get_kernel_ns();
3433 delta = user_ns.clock - now_ns;
3434 kvm->arch.kvmclock_offset = delta;
3437 case KVM_GET_CLOCK: {
3438 struct kvm_clock_data user_ns;
3441 now_ns = get_kernel_ns();
3442 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3446 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3459 static void kvm_init_msr_list(void)
3464 /* skip the first msrs in the list. KVM-specific */
3465 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3466 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3469 msrs_to_save[j] = msrs_to_save[i];
3472 num_msrs_to_save = j;
3475 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3478 if (vcpu->arch.apic &&
3479 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3482 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
3485 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3487 if (vcpu->arch.apic &&
3488 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3491 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
3494 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3495 struct kvm_segment *var, int seg)
3497 kvm_x86_ops->set_segment(vcpu, var, seg);
3500 void kvm_get_segment(struct kvm_vcpu *vcpu,
3501 struct kvm_segment *var, int seg)
3503 kvm_x86_ops->get_segment(vcpu, var, seg);
3506 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3511 static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3516 BUG_ON(!mmu_is_nested(vcpu));
3518 /* NPT walks are always user-walks */
3519 access |= PFERR_USER_MASK;
3520 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3521 if (t_gpa == UNMAPPED_GVA)
3522 vcpu->arch.fault.nested = true;
3527 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3529 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3530 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
3533 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3535 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3536 access |= PFERR_FETCH_MASK;
3537 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
3540 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3542 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3543 access |= PFERR_WRITE_MASK;
3544 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
3547 /* uses this to access any guest's mapped memory without checking CPL */
3548 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3550 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
3553 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3554 struct kvm_vcpu *vcpu, u32 access,
3558 int r = X86EMUL_CONTINUE;
3561 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3563 unsigned offset = addr & (PAGE_SIZE-1);
3564 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3567 if (gpa == UNMAPPED_GVA) {
3568 r = X86EMUL_PROPAGATE_FAULT;
3571 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3573 r = X86EMUL_IO_NEEDED;
3585 /* used for instruction fetching */
3586 static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3587 struct kvm_vcpu *vcpu, u32 *error)
3589 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3590 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3591 access | PFERR_FETCH_MASK, error);
3594 static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3595 struct kvm_vcpu *vcpu, u32 *error)
3597 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3598 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3602 static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3603 struct kvm_vcpu *vcpu, u32 *error)
3605 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3608 static int kvm_write_guest_virt_system(gva_t addr, void *val,
3610 struct kvm_vcpu *vcpu,
3614 int r = X86EMUL_CONTINUE;
3617 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3620 unsigned offset = addr & (PAGE_SIZE-1);
3621 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3624 if (gpa == UNMAPPED_GVA) {
3625 r = X86EMUL_PROPAGATE_FAULT;
3628 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3630 r = X86EMUL_IO_NEEDED;
3642 static int emulator_read_emulated(unsigned long addr,
3645 unsigned int *error_code,
3646 struct kvm_vcpu *vcpu)
3650 if (vcpu->mmio_read_completed) {
3651 memcpy(val, vcpu->mmio_data, bytes);
3652 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3653 vcpu->mmio_phys_addr, *(u64 *)val);
3654 vcpu->mmio_read_completed = 0;
3655 return X86EMUL_CONTINUE;
3658 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
3660 if (gpa == UNMAPPED_GVA)
3661 return X86EMUL_PROPAGATE_FAULT;
3663 /* For APIC access vmexit */
3664 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3667 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
3668 == X86EMUL_CONTINUE)
3669 return X86EMUL_CONTINUE;
3673 * Is this MMIO handled locally?
3675 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3676 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
3677 return X86EMUL_CONTINUE;
3680 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3682 vcpu->mmio_needed = 1;
3683 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3684 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3685 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3686 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
3688 return X86EMUL_IO_NEEDED;
3691 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3692 const void *val, int bytes)
3696 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3699 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
3703 static int emulator_write_emulated_onepage(unsigned long addr,
3706 unsigned int *error_code,
3707 struct kvm_vcpu *vcpu)
3711 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
3713 if (gpa == UNMAPPED_GVA)
3714 return X86EMUL_PROPAGATE_FAULT;
3716 /* For APIC access vmexit */
3717 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3720 if (emulator_write_phys(vcpu, gpa, val, bytes))
3721 return X86EMUL_CONTINUE;
3724 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3726 * Is this MMIO handled locally?
3728 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
3729 return X86EMUL_CONTINUE;
3731 vcpu->mmio_needed = 1;
3732 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3733 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3734 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3735 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3736 memcpy(vcpu->run->mmio.data, val, bytes);
3738 return X86EMUL_CONTINUE;
3741 int emulator_write_emulated(unsigned long addr,
3744 unsigned int *error_code,
3745 struct kvm_vcpu *vcpu)
3747 /* Crossing a page boundary? */
3748 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3751 now = -addr & ~PAGE_MASK;
3752 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3754 if (rc != X86EMUL_CONTINUE)
3760 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3764 #define CMPXCHG_TYPE(t, ptr, old, new) \
3765 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3767 #ifdef CONFIG_X86_64
3768 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3770 # define CMPXCHG64(ptr, old, new) \
3771 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3774 static int emulator_cmpxchg_emulated(unsigned long addr,
3778 unsigned int *error_code,
3779 struct kvm_vcpu *vcpu)
3786 /* guests cmpxchg8b have to be emulated atomically */
3787 if (bytes > 8 || (bytes & (bytes - 1)))
3790 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3792 if (gpa == UNMAPPED_GVA ||
3793 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3796 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3799 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3800 if (is_error_page(page)) {
3801 kvm_release_page_clean(page);
3805 kaddr = kmap_atomic(page, KM_USER0);
3806 kaddr += offset_in_page(gpa);
3809 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3812 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3815 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3818 exchanged = CMPXCHG64(kaddr, old, new);
3823 kunmap_atomic(kaddr, KM_USER0);
3824 kvm_release_page_dirty(page);
3827 return X86EMUL_CMPXCHG_FAILED;
3829 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3831 return X86EMUL_CONTINUE;
3834 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3836 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
3839 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3841 /* TODO: String I/O for in kernel device */
3844 if (vcpu->arch.pio.in)
3845 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3846 vcpu->arch.pio.size, pd);
3848 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3849 vcpu->arch.pio.port, vcpu->arch.pio.size,
3855 static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3856 unsigned int count, struct kvm_vcpu *vcpu)
3858 if (vcpu->arch.pio.count)
3861 trace_kvm_pio(0, port, size, 1);
3863 vcpu->arch.pio.port = port;
3864 vcpu->arch.pio.in = 1;
3865 vcpu->arch.pio.count = count;
3866 vcpu->arch.pio.size = size;
3868 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3870 memcpy(val, vcpu->arch.pio_data, size * count);
3871 vcpu->arch.pio.count = 0;
3875 vcpu->run->exit_reason = KVM_EXIT_IO;
3876 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3877 vcpu->run->io.size = size;
3878 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3879 vcpu->run->io.count = count;
3880 vcpu->run->io.port = port;
3885 static int emulator_pio_out_emulated(int size, unsigned short port,
3886 const void *val, unsigned int count,
3887 struct kvm_vcpu *vcpu)
3889 trace_kvm_pio(1, port, size, 1);
3891 vcpu->arch.pio.port = port;
3892 vcpu->arch.pio.in = 0;
3893 vcpu->arch.pio.count = count;
3894 vcpu->arch.pio.size = size;
3896 memcpy(vcpu->arch.pio_data, val, size * count);
3898 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3899 vcpu->arch.pio.count = 0;
3903 vcpu->run->exit_reason = KVM_EXIT_IO;
3904 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3905 vcpu->run->io.size = size;
3906 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3907 vcpu->run->io.count = count;
3908 vcpu->run->io.port = port;
3913 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3915 return kvm_x86_ops->get_segment_base(vcpu, seg);
3918 int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3920 kvm_mmu_invlpg(vcpu, address);
3921 return X86EMUL_CONTINUE;
3924 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3926 if (!need_emulate_wbinvd(vcpu))
3927 return X86EMUL_CONTINUE;
3929 if (kvm_x86_ops->has_wbinvd_exit()) {
3930 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3931 wbinvd_ipi, NULL, 1);
3932 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3935 return X86EMUL_CONTINUE;
3937 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3939 int emulate_clts(struct kvm_vcpu *vcpu)
3941 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3942 kvm_x86_ops->fpu_activate(vcpu);
3943 return X86EMUL_CONTINUE;
3946 int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
3948 return _kvm_get_dr(vcpu, dr, dest);
3951 int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
3954 return __kvm_set_dr(vcpu, dr, value);
3957 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3959 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3962 static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
3964 unsigned long value;
3968 value = kvm_read_cr0(vcpu);
3971 value = vcpu->arch.cr2;
3974 value = vcpu->arch.cr3;
3977 value = kvm_read_cr4(vcpu);
3980 value = kvm_get_cr8(vcpu);
3983 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3990 static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
3996 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
3999 vcpu->arch.cr2 = val;
4002 res = kvm_set_cr3(vcpu, val);
4005 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4008 res = __kvm_set_cr8(vcpu, val & 0xfUL);
4011 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4018 static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4020 return kvm_x86_ops->get_cpl(vcpu);
4023 static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4025 kvm_x86_ops->get_gdt(vcpu, dt);
4028 static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4030 kvm_x86_ops->get_idt(vcpu, dt);
4033 static unsigned long emulator_get_cached_segment_base(int seg,
4034 struct kvm_vcpu *vcpu)
4036 return get_segment_base(vcpu, seg);
4039 static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4040 struct kvm_vcpu *vcpu)
4042 struct kvm_segment var;
4044 kvm_get_segment(vcpu, &var, seg);
4051 set_desc_limit(desc, var.limit);
4052 set_desc_base(desc, (unsigned long)var.base);
4053 desc->type = var.type;
4055 desc->dpl = var.dpl;
4056 desc->p = var.present;
4057 desc->avl = var.avl;
4065 static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4066 struct kvm_vcpu *vcpu)
4068 struct kvm_segment var;
4070 /* needed to preserve selector */
4071 kvm_get_segment(vcpu, &var, seg);
4073 var.base = get_desc_base(desc);
4074 var.limit = get_desc_limit(desc);
4076 var.limit = (var.limit << 12) | 0xfff;
4077 var.type = desc->type;
4078 var.present = desc->p;
4079 var.dpl = desc->dpl;
4084 var.avl = desc->avl;
4085 var.present = desc->p;
4086 var.unusable = !var.present;
4089 kvm_set_segment(vcpu, &var, seg);
4093 static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4095 struct kvm_segment kvm_seg;
4097 kvm_get_segment(vcpu, &kvm_seg, seg);
4098 return kvm_seg.selector;
4101 static void emulator_set_segment_selector(u16 sel, int seg,
4102 struct kvm_vcpu *vcpu)
4104 struct kvm_segment kvm_seg;
4106 kvm_get_segment(vcpu, &kvm_seg, seg);
4107 kvm_seg.selector = sel;
4108 kvm_set_segment(vcpu, &kvm_seg, seg);
4111 static struct x86_emulate_ops emulate_ops = {
4112 .read_std = kvm_read_guest_virt_system,
4113 .write_std = kvm_write_guest_virt_system,
4114 .fetch = kvm_fetch_guest_virt,
4115 .read_emulated = emulator_read_emulated,
4116 .write_emulated = emulator_write_emulated,
4117 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4118 .pio_in_emulated = emulator_pio_in_emulated,
4119 .pio_out_emulated = emulator_pio_out_emulated,
4120 .get_cached_descriptor = emulator_get_cached_descriptor,
4121 .set_cached_descriptor = emulator_set_cached_descriptor,
4122 .get_segment_selector = emulator_get_segment_selector,
4123 .set_segment_selector = emulator_set_segment_selector,
4124 .get_cached_segment_base = emulator_get_cached_segment_base,
4125 .get_gdt = emulator_get_gdt,
4126 .get_idt = emulator_get_idt,
4127 .get_cr = emulator_get_cr,
4128 .set_cr = emulator_set_cr,
4129 .cpl = emulator_get_cpl,
4130 .get_dr = emulator_get_dr,
4131 .set_dr = emulator_set_dr,
4132 .set_msr = kvm_set_msr,
4133 .get_msr = kvm_get_msr,
4136 static void cache_all_regs(struct kvm_vcpu *vcpu)
4138 kvm_register_read(vcpu, VCPU_REGS_RAX);
4139 kvm_register_read(vcpu, VCPU_REGS_RSP);
4140 kvm_register_read(vcpu, VCPU_REGS_RIP);
4141 vcpu->arch.regs_dirty = ~0;
4144 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4146 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4148 * an sti; sti; sequence only disable interrupts for the first
4149 * instruction. So, if the last instruction, be it emulated or
4150 * not, left the system with the INT_STI flag enabled, it
4151 * means that the last instruction is an sti. We should not
4152 * leave the flag on in this case. The same goes for mov ss
4154 if (!(int_shadow & mask))
4155 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4158 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4160 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4161 if (ctxt->exception == PF_VECTOR)
4162 kvm_propagate_fault(vcpu);
4163 else if (ctxt->error_code_valid)
4164 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4166 kvm_queue_exception(vcpu, ctxt->exception);
4169 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4171 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4174 cache_all_regs(vcpu);
4176 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4178 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4179 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4180 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4181 vcpu->arch.emulate_ctxt.mode =
4182 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4183 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4184 ? X86EMUL_MODE_VM86 : cs_l
4185 ? X86EMUL_MODE_PROT64 : cs_db
4186 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4187 memset(c, 0, sizeof(struct decode_cache));
4188 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4191 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4193 ++vcpu->stat.insn_emulation_fail;
4194 trace_kvm_emulate_insn_failed(vcpu);
4195 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4196 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4197 vcpu->run->internal.ndata = 0;
4198 kvm_queue_exception(vcpu, UD_VECTOR);
4199 return EMULATE_FAIL;
4202 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4210 * if emulation was due to access to shadowed page table
4211 * and it failed try to unshadow page and re-entetr the
4212 * guest to let CPU execute the instruction.
4214 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4217 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4219 if (gpa == UNMAPPED_GVA)
4220 return true; /* let cpu generate fault */
4222 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4228 int emulate_instruction(struct kvm_vcpu *vcpu,
4234 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4236 kvm_clear_exception_queue(vcpu);
4237 vcpu->arch.mmio_fault_cr2 = cr2;
4239 * TODO: fix emulate.c to use guest_read/write_register
4240 * instead of direct ->regs accesses, can save hundred cycles
4241 * on Intel for instructions that don't read/change RSP, for
4244 cache_all_regs(vcpu);
4246 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4247 init_emulate_ctxt(vcpu);
4248 vcpu->arch.emulate_ctxt.interruptibility = 0;
4249 vcpu->arch.emulate_ctxt.exception = -1;
4250 vcpu->arch.emulate_ctxt.perm_ok = false;
4252 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
4253 if (r == X86EMUL_PROPAGATE_FAULT)
4256 trace_kvm_emulate_insn_start(vcpu);
4258 /* Only allow emulation of specific instructions on #UD
4259 * (namely VMMCALL, sysenter, sysexit, syscall)*/
4260 if (emulation_type & EMULTYPE_TRAP_UD) {
4262 return EMULATE_FAIL;
4264 case 0x01: /* VMMCALL */
4265 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4266 return EMULATE_FAIL;
4268 case 0x34: /* sysenter */
4269 case 0x35: /* sysexit */
4270 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4271 return EMULATE_FAIL;
4273 case 0x05: /* syscall */
4274 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4275 return EMULATE_FAIL;
4278 return EMULATE_FAIL;
4281 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4282 return EMULATE_FAIL;
4285 ++vcpu->stat.insn_emulation;
4287 if (reexecute_instruction(vcpu, cr2))
4288 return EMULATE_DONE;
4289 if (emulation_type & EMULTYPE_SKIP)
4290 return EMULATE_FAIL;
4291 return handle_emulation_failure(vcpu);
4295 if (emulation_type & EMULTYPE_SKIP) {
4296 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4297 return EMULATE_DONE;
4300 /* this is needed for vmware backdor interface to work since it
4301 changes registers values during IO operation */
4302 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4305 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
4307 if (r == EMULATION_FAILED) {
4308 if (reexecute_instruction(vcpu, cr2))
4309 return EMULATE_DONE;
4311 return handle_emulation_failure(vcpu);
4315 if (vcpu->arch.emulate_ctxt.exception >= 0) {
4316 inject_emulated_exception(vcpu);
4318 } else if (vcpu->arch.pio.count) {
4319 if (!vcpu->arch.pio.in)
4320 vcpu->arch.pio.count = 0;
4321 r = EMULATE_DO_MMIO;
4322 } else if (vcpu->mmio_needed) {
4323 if (vcpu->mmio_is_write)
4324 vcpu->mmio_needed = 0;
4325 r = EMULATE_DO_MMIO;
4326 } else if (r == EMULATION_RESTART)
4331 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4332 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4333 kvm_make_request(KVM_REQ_EVENT, vcpu);
4334 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4335 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4339 EXPORT_SYMBOL_GPL(emulate_instruction);
4341 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4343 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4344 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4345 /* do not return to emulator after return from userspace */
4346 vcpu->arch.pio.count = 0;
4349 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4351 static void tsc_bad(void *info)
4353 __get_cpu_var(cpu_tsc_khz) = 0;
4356 static void tsc_khz_changed(void *data)
4358 struct cpufreq_freqs *freq = data;
4359 unsigned long khz = 0;
4363 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4364 khz = cpufreq_quick_get(raw_smp_processor_id());
4367 __get_cpu_var(cpu_tsc_khz) = khz;
4370 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4373 struct cpufreq_freqs *freq = data;
4375 struct kvm_vcpu *vcpu;
4376 int i, send_ipi = 0;
4379 * We allow guests to temporarily run on slowing clocks,
4380 * provided we notify them after, or to run on accelerating
4381 * clocks, provided we notify them before. Thus time never
4384 * However, we have a problem. We can't atomically update
4385 * the frequency of a given CPU from this function; it is
4386 * merely a notifier, which can be called from any CPU.
4387 * Changing the TSC frequency at arbitrary points in time
4388 * requires a recomputation of local variables related to
4389 * the TSC for each VCPU. We must flag these local variables
4390 * to be updated and be sure the update takes place with the
4391 * new frequency before any guests proceed.
4393 * Unfortunately, the combination of hotplug CPU and frequency
4394 * change creates an intractable locking scenario; the order
4395 * of when these callouts happen is undefined with respect to
4396 * CPU hotplug, and they can race with each other. As such,
4397 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4398 * undefined; you can actually have a CPU frequency change take
4399 * place in between the computation of X and the setting of the
4400 * variable. To protect against this problem, all updates of
4401 * the per_cpu tsc_khz variable are done in an interrupt
4402 * protected IPI, and all callers wishing to update the value
4403 * must wait for a synchronous IPI to complete (which is trivial
4404 * if the caller is on the CPU already). This establishes the
4405 * necessary total order on variable updates.
4407 * Note that because a guest time update may take place
4408 * anytime after the setting of the VCPU's request bit, the
4409 * correct TSC value must be set before the request. However,
4410 * to ensure the update actually makes it to any guest which
4411 * starts running in hardware virtualization between the set
4412 * and the acquisition of the spinlock, we must also ping the
4413 * CPU after setting the request bit.
4417 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4419 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4422 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4424 spin_lock(&kvm_lock);
4425 list_for_each_entry(kvm, &vm_list, vm_list) {
4426 kvm_for_each_vcpu(i, vcpu, kvm) {
4427 if (vcpu->cpu != freq->cpu)
4429 if (!kvm_request_guest_time_update(vcpu))
4431 if (vcpu->cpu != smp_processor_id())
4435 spin_unlock(&kvm_lock);
4437 if (freq->old < freq->new && send_ipi) {
4439 * We upscale the frequency. Must make the guest
4440 * doesn't see old kvmclock values while running with
4441 * the new frequency, otherwise we risk the guest sees
4442 * time go backwards.
4444 * In case we update the frequency for another cpu
4445 * (which might be in guest context) send an interrupt
4446 * to kick the cpu out of guest context. Next time
4447 * guest context is entered kvmclock will be updated,
4448 * so the guest will not see stale values.
4450 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4455 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4456 .notifier_call = kvmclock_cpufreq_notifier
4459 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4460 unsigned long action, void *hcpu)
4462 unsigned int cpu = (unsigned long)hcpu;
4466 case CPU_DOWN_FAILED:
4467 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4469 case CPU_DOWN_PREPARE:
4470 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4476 static struct notifier_block kvmclock_cpu_notifier_block = {
4477 .notifier_call = kvmclock_cpu_notifier,
4478 .priority = -INT_MAX
4481 static void kvm_timer_init(void)
4485 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4486 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4487 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4488 CPUFREQ_TRANSITION_NOTIFIER);
4490 for_each_online_cpu(cpu)
4491 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4494 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4496 static int kvm_is_in_guest(void)
4498 return percpu_read(current_vcpu) != NULL;
4501 static int kvm_is_user_mode(void)
4505 if (percpu_read(current_vcpu))
4506 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
4508 return user_mode != 0;
4511 static unsigned long kvm_get_guest_ip(void)
4513 unsigned long ip = 0;
4515 if (percpu_read(current_vcpu))
4516 ip = kvm_rip_read(percpu_read(current_vcpu));
4521 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4522 .is_in_guest = kvm_is_in_guest,
4523 .is_user_mode = kvm_is_user_mode,
4524 .get_guest_ip = kvm_get_guest_ip,
4527 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4529 percpu_write(current_vcpu, vcpu);
4531 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4533 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4535 percpu_write(current_vcpu, NULL);
4537 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4539 int kvm_arch_init(void *opaque)
4542 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4545 printk(KERN_ERR "kvm: already loaded the other module\n");
4550 if (!ops->cpu_has_kvm_support()) {
4551 printk(KERN_ERR "kvm: no hardware support\n");
4555 if (ops->disabled_by_bios()) {
4556 printk(KERN_ERR "kvm: disabled by bios\n");
4561 r = kvm_mmu_module_init();
4565 kvm_init_msr_list();
4568 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
4569 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4570 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4571 PT_DIRTY_MASK, PT64_NX_MASK, 0);
4575 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4578 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4586 void kvm_arch_exit(void)
4588 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4590 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4591 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4592 CPUFREQ_TRANSITION_NOTIFIER);
4593 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4595 kvm_mmu_module_exit();
4598 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4600 ++vcpu->stat.halt_exits;
4601 if (irqchip_in_kernel(vcpu->kvm)) {
4602 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4605 vcpu->run->exit_reason = KVM_EXIT_HLT;
4609 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4611 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4614 if (is_long_mode(vcpu))
4617 return a0 | ((gpa_t)a1 << 32);
4620 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4622 u64 param, ingpa, outgpa, ret;
4623 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4624 bool fast, longmode;
4628 * hypercall generates UD from non zero cpl and real mode
4631 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4632 kvm_queue_exception(vcpu, UD_VECTOR);
4636 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4637 longmode = is_long_mode(vcpu) && cs_l == 1;
4640 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4641 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4642 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4643 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4644 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4645 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4647 #ifdef CONFIG_X86_64
4649 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4650 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4651 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4655 code = param & 0xffff;
4656 fast = (param >> 16) & 0x1;
4657 rep_cnt = (param >> 32) & 0xfff;
4658 rep_idx = (param >> 48) & 0xfff;
4660 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4663 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4664 kvm_vcpu_on_spin(vcpu);
4667 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4671 ret = res | (((u64)rep_done & 0xfff) << 32);
4673 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4675 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4676 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4682 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4684 unsigned long nr, a0, a1, a2, a3, ret;
4687 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4688 return kvm_hv_hypercall(vcpu);
4690 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4691 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4692 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4693 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4694 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
4696 trace_kvm_hypercall(nr, a0, a1, a2, a3);
4698 if (!is_long_mode(vcpu)) {
4706 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4712 case KVM_HC_VAPIC_POLL_IRQ:
4716 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4723 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4724 ++vcpu->stat.hypercalls;
4727 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4729 int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4731 char instruction[3];
4732 unsigned long rip = kvm_rip_read(vcpu);
4735 * Blow out the MMU to ensure that no other VCPU has an active mapping
4736 * to ensure that the updated hypercall appears atomically across all
4739 kvm_mmu_zap_all(vcpu->kvm);
4741 kvm_x86_ops->patch_hypercall(vcpu, instruction);
4743 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
4746 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4748 struct desc_ptr dt = { limit, base };
4750 kvm_x86_ops->set_gdt(vcpu, &dt);
4753 void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4755 struct desc_ptr dt = { limit, base };
4757 kvm_x86_ops->set_idt(vcpu, &dt);
4760 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4762 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4763 int j, nent = vcpu->arch.cpuid_nent;
4765 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4766 /* when no next entry is found, the current entry[i] is reselected */
4767 for (j = i + 1; ; j = (j + 1) % nent) {
4768 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
4769 if (ej->function == e->function) {
4770 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4774 return 0; /* silence gcc, even though control never reaches here */
4777 /* find an entry with matching function, matching index (if needed), and that
4778 * should be read next (if it's stateful) */
4779 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4780 u32 function, u32 index)
4782 if (e->function != function)
4784 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4786 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
4787 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
4792 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4793 u32 function, u32 index)
4796 struct kvm_cpuid_entry2 *best = NULL;
4798 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
4799 struct kvm_cpuid_entry2 *e;
4801 e = &vcpu->arch.cpuid_entries[i];
4802 if (is_matching_cpuid_entry(e, function, index)) {
4803 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4804 move_to_next_stateful_cpuid_entry(vcpu, i);
4809 * Both basic or both extended?
4811 if (((e->function ^ function) & 0x80000000) == 0)
4812 if (!best || e->function > best->function)
4817 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
4819 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4821 struct kvm_cpuid_entry2 *best;
4823 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4824 if (!best || best->eax < 0x80000008)
4826 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4828 return best->eax & 0xff;
4833 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4835 u32 function, index;
4836 struct kvm_cpuid_entry2 *best;
4838 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4839 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4840 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4841 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4842 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4843 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4844 best = kvm_find_cpuid_entry(vcpu, function, index);
4846 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4847 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4848 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4849 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
4851 kvm_x86_ops->skip_emulated_instruction(vcpu);
4852 trace_kvm_cpuid(function,
4853 kvm_register_read(vcpu, VCPU_REGS_RAX),
4854 kvm_register_read(vcpu, VCPU_REGS_RBX),
4855 kvm_register_read(vcpu, VCPU_REGS_RCX),
4856 kvm_register_read(vcpu, VCPU_REGS_RDX));
4858 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
4861 * Check if userspace requested an interrupt window, and that the
4862 * interrupt window is open.
4864 * No need to exit to userspace if we already have an interrupt queued.
4866 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
4868 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
4869 vcpu->run->request_interrupt_window &&
4870 kvm_arch_interrupt_allowed(vcpu));
4873 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
4875 struct kvm_run *kvm_run = vcpu->run;
4877 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
4878 kvm_run->cr8 = kvm_get_cr8(vcpu);
4879 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4880 if (irqchip_in_kernel(vcpu->kvm))
4881 kvm_run->ready_for_interrupt_injection = 1;
4883 kvm_run->ready_for_interrupt_injection =
4884 kvm_arch_interrupt_allowed(vcpu) &&
4885 !kvm_cpu_has_interrupt(vcpu) &&
4886 !kvm_event_needs_reinjection(vcpu);
4889 static void vapic_enter(struct kvm_vcpu *vcpu)
4891 struct kvm_lapic *apic = vcpu->arch.apic;
4894 if (!apic || !apic->vapic_addr)
4897 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4899 vcpu->arch.apic->vapic_page = page;
4902 static void vapic_exit(struct kvm_vcpu *vcpu)
4904 struct kvm_lapic *apic = vcpu->arch.apic;
4907 if (!apic || !apic->vapic_addr)
4910 idx = srcu_read_lock(&vcpu->kvm->srcu);
4911 kvm_release_page_dirty(apic->vapic_page);
4912 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4913 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4916 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4920 if (!kvm_x86_ops->update_cr8_intercept)
4923 if (!vcpu->arch.apic)
4926 if (!vcpu->arch.apic->vapic_addr)
4927 max_irr = kvm_lapic_find_highest_irr(vcpu);
4934 tpr = kvm_lapic_get_cr8(vcpu);
4936 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4939 static void inject_pending_event(struct kvm_vcpu *vcpu)
4941 /* try to reinject previous events if any */
4942 if (vcpu->arch.exception.pending) {
4943 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4944 vcpu->arch.exception.has_error_code,
4945 vcpu->arch.exception.error_code);
4946 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4947 vcpu->arch.exception.has_error_code,
4948 vcpu->arch.exception.error_code,
4949 vcpu->arch.exception.reinject);
4953 if (vcpu->arch.nmi_injected) {
4954 kvm_x86_ops->set_nmi(vcpu);
4958 if (vcpu->arch.interrupt.pending) {
4959 kvm_x86_ops->set_irq(vcpu);
4963 /* try to inject new event if pending */
4964 if (vcpu->arch.nmi_pending) {
4965 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4966 vcpu->arch.nmi_pending = false;
4967 vcpu->arch.nmi_injected = true;
4968 kvm_x86_ops->set_nmi(vcpu);
4970 } else if (kvm_cpu_has_interrupt(vcpu)) {
4971 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
4972 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4974 kvm_x86_ops->set_irq(vcpu);
4979 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4981 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4982 !vcpu->guest_xcr0_loaded) {
4983 /* kvm_set_xcr() also depends on this */
4984 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4985 vcpu->guest_xcr0_loaded = 1;
4989 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4991 if (vcpu->guest_xcr0_loaded) {
4992 if (vcpu->arch.xcr0 != host_xcr0)
4993 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4994 vcpu->guest_xcr0_loaded = 0;
4998 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5001 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5002 vcpu->run->request_interrupt_window;
5004 if (vcpu->requests) {
5005 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5006 kvm_mmu_unload(vcpu);
5007 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5008 __kvm_migrate_timers(vcpu);
5009 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
5010 r = kvm_write_guest_time(vcpu);
5014 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5015 kvm_mmu_sync_roots(vcpu);
5016 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5017 kvm_x86_ops->tlb_flush(vcpu);
5018 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5019 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5023 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5024 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5028 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5029 vcpu->fpu_active = 0;
5030 kvm_x86_ops->fpu_deactivate(vcpu);
5034 r = kvm_mmu_reload(vcpu);
5038 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5039 inject_pending_event(vcpu);
5041 /* enable NMI/IRQ window open exits if needed */
5042 if (vcpu->arch.nmi_pending)
5043 kvm_x86_ops->enable_nmi_window(vcpu);
5044 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5045 kvm_x86_ops->enable_irq_window(vcpu);
5047 if (kvm_lapic_enabled(vcpu)) {
5048 update_cr8_intercept(vcpu);
5049 kvm_lapic_sync_to_vapic(vcpu);
5055 kvm_x86_ops->prepare_guest_switch(vcpu);
5056 if (vcpu->fpu_active)
5057 kvm_load_guest_fpu(vcpu);
5058 kvm_load_guest_xcr0(vcpu);
5060 atomic_set(&vcpu->guest_mode, 1);
5063 local_irq_disable();
5065 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5066 || need_resched() || signal_pending(current)) {
5067 atomic_set(&vcpu->guest_mode, 0);
5071 kvm_x86_ops->cancel_injection(vcpu);
5076 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5080 if (unlikely(vcpu->arch.switch_db_regs)) {
5082 set_debugreg(vcpu->arch.eff_db[0], 0);
5083 set_debugreg(vcpu->arch.eff_db[1], 1);
5084 set_debugreg(vcpu->arch.eff_db[2], 2);
5085 set_debugreg(vcpu->arch.eff_db[3], 3);
5088 trace_kvm_entry(vcpu->vcpu_id);
5089 kvm_x86_ops->run(vcpu);
5092 * If the guest has used debug registers, at least dr7
5093 * will be disabled while returning to the host.
5094 * If we don't have active breakpoints in the host, we don't
5095 * care about the messed up debug address registers. But if
5096 * we have some of them active, restore the old state.
5098 if (hw_breakpoint_active())
5099 hw_breakpoint_restore();
5101 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5103 atomic_set(&vcpu->guest_mode, 0);
5110 * We must have an instruction between local_irq_enable() and
5111 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5112 * the interrupt shadow. The stat.exits increment will do nicely.
5113 * But we need to prevent reordering, hence this barrier():
5121 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5124 * Profile KVM exit RIPs:
5126 if (unlikely(prof_on == KVM_PROFILING)) {
5127 unsigned long rip = kvm_rip_read(vcpu);
5128 profile_hit(KVM_PROFILING, (void *)rip);
5132 kvm_lapic_sync_from_vapic(vcpu);
5134 r = kvm_x86_ops->handle_exit(vcpu);
5140 static int __vcpu_run(struct kvm_vcpu *vcpu)
5143 struct kvm *kvm = vcpu->kvm;
5145 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5146 pr_debug("vcpu %d received sipi with vector # %x\n",
5147 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5148 kvm_lapic_reset(vcpu);
5149 r = kvm_arch_vcpu_reset(vcpu);
5152 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5155 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5160 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
5161 r = vcpu_enter_guest(vcpu);
5163 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5164 kvm_vcpu_block(vcpu);
5165 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5166 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5168 switch(vcpu->arch.mp_state) {
5169 case KVM_MP_STATE_HALTED:
5170 vcpu->arch.mp_state =
5171 KVM_MP_STATE_RUNNABLE;
5172 case KVM_MP_STATE_RUNNABLE:
5174 case KVM_MP_STATE_SIPI_RECEIVED:
5185 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5186 if (kvm_cpu_has_pending_timer(vcpu))
5187 kvm_inject_pending_timer_irqs(vcpu);
5189 if (dm_request_for_irq_injection(vcpu)) {
5191 vcpu->run->exit_reason = KVM_EXIT_INTR;
5192 ++vcpu->stat.request_irq_exits;
5194 if (signal_pending(current)) {
5196 vcpu->run->exit_reason = KVM_EXIT_INTR;
5197 ++vcpu->stat.signal_exits;
5199 if (need_resched()) {
5200 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5202 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5206 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5213 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5218 if (vcpu->sigset_active)
5219 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5221 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5222 kvm_vcpu_block(vcpu);
5223 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5228 /* re-sync apic's tpr */
5229 if (!irqchip_in_kernel(vcpu->kvm))
5230 kvm_set_cr8(vcpu, kvm_run->cr8);
5232 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
5233 if (vcpu->mmio_needed) {
5234 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5235 vcpu->mmio_read_completed = 1;
5236 vcpu->mmio_needed = 0;
5238 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5239 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
5240 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5241 if (r != EMULATE_DONE) {
5246 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5247 kvm_register_write(vcpu, VCPU_REGS_RAX,
5248 kvm_run->hypercall.ret);
5250 r = __vcpu_run(vcpu);
5253 post_kvm_run_save(vcpu);
5254 if (vcpu->sigset_active)
5255 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5260 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5262 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5263 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5264 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5265 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5266 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5267 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5268 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5269 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5270 #ifdef CONFIG_X86_64
5271 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5272 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5273 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5274 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5275 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5276 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5277 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5278 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5281 regs->rip = kvm_rip_read(vcpu);
5282 regs->rflags = kvm_get_rflags(vcpu);
5287 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5289 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5290 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5291 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5292 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5293 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5294 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5295 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5296 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5297 #ifdef CONFIG_X86_64
5298 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5299 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5300 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5301 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5302 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5303 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5304 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5305 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5308 kvm_rip_write(vcpu, regs->rip);
5309 kvm_set_rflags(vcpu, regs->rflags);
5311 vcpu->arch.exception.pending = false;
5313 kvm_make_request(KVM_REQ_EVENT, vcpu);
5318 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5320 struct kvm_segment cs;
5322 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5326 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5328 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5329 struct kvm_sregs *sregs)
5333 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5334 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5335 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5336 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5337 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5338 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5340 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5341 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5343 kvm_x86_ops->get_idt(vcpu, &dt);
5344 sregs->idt.limit = dt.size;
5345 sregs->idt.base = dt.address;
5346 kvm_x86_ops->get_gdt(vcpu, &dt);
5347 sregs->gdt.limit = dt.size;
5348 sregs->gdt.base = dt.address;
5350 sregs->cr0 = kvm_read_cr0(vcpu);
5351 sregs->cr2 = vcpu->arch.cr2;
5352 sregs->cr3 = vcpu->arch.cr3;
5353 sregs->cr4 = kvm_read_cr4(vcpu);
5354 sregs->cr8 = kvm_get_cr8(vcpu);
5355 sregs->efer = vcpu->arch.efer;
5356 sregs->apic_base = kvm_get_apic_base(vcpu);
5358 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5360 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5361 set_bit(vcpu->arch.interrupt.nr,
5362 (unsigned long *)sregs->interrupt_bitmap);
5367 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5368 struct kvm_mp_state *mp_state)
5370 mp_state->mp_state = vcpu->arch.mp_state;
5374 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5375 struct kvm_mp_state *mp_state)
5377 vcpu->arch.mp_state = mp_state->mp_state;
5378 kvm_make_request(KVM_REQ_EVENT, vcpu);
5382 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5383 bool has_error_code, u32 error_code)
5385 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
5388 init_emulate_ctxt(vcpu);
5390 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
5391 tss_selector, reason, has_error_code,
5395 return EMULATE_FAIL;
5397 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
5398 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
5399 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5400 kvm_make_request(KVM_REQ_EVENT, vcpu);
5401 return EMULATE_DONE;
5403 EXPORT_SYMBOL_GPL(kvm_task_switch);
5405 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5406 struct kvm_sregs *sregs)
5408 int mmu_reset_needed = 0;
5409 int pending_vec, max_bits;
5412 dt.size = sregs->idt.limit;
5413 dt.address = sregs->idt.base;
5414 kvm_x86_ops->set_idt(vcpu, &dt);
5415 dt.size = sregs->gdt.limit;
5416 dt.address = sregs->gdt.base;
5417 kvm_x86_ops->set_gdt(vcpu, &dt);
5419 vcpu->arch.cr2 = sregs->cr2;
5420 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
5421 vcpu->arch.cr3 = sregs->cr3;
5423 kvm_set_cr8(vcpu, sregs->cr8);
5425 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5426 kvm_x86_ops->set_efer(vcpu, sregs->efer);
5427 kvm_set_apic_base(vcpu, sregs->apic_base);
5429 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5430 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5431 vcpu->arch.cr0 = sregs->cr0;
5433 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5434 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5435 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5436 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
5437 mmu_reset_needed = 1;
5440 if (mmu_reset_needed)
5441 kvm_mmu_reset_context(vcpu);
5443 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5444 pending_vec = find_first_bit(
5445 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5446 if (pending_vec < max_bits) {
5447 kvm_queue_interrupt(vcpu, pending_vec, false);
5448 pr_debug("Set back pending irq %d\n", pending_vec);
5449 if (irqchip_in_kernel(vcpu->kvm))
5450 kvm_pic_clear_isr_ack(vcpu->kvm);
5453 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5454 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5455 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5456 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5457 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5458 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5460 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5461 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5463 update_cr8_intercept(vcpu);
5465 /* Older userspace won't unhalt the vcpu on reset. */
5466 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5467 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5469 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5471 kvm_make_request(KVM_REQ_EVENT, vcpu);
5476 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5477 struct kvm_guest_debug *dbg)
5479 unsigned long rflags;
5482 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5484 if (vcpu->arch.exception.pending)
5486 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5487 kvm_queue_exception(vcpu, DB_VECTOR);
5489 kvm_queue_exception(vcpu, BP_VECTOR);
5493 * Read rflags as long as potentially injected trace flags are still
5496 rflags = kvm_get_rflags(vcpu);
5498 vcpu->guest_debug = dbg->control;
5499 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5500 vcpu->guest_debug = 0;
5502 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5503 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5504 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5505 vcpu->arch.switch_db_regs =
5506 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5508 for (i = 0; i < KVM_NR_DB_REGS; i++)
5509 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5510 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5513 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5514 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5515 get_segment_base(vcpu, VCPU_SREG_CS);
5518 * Trigger an rflags update that will inject or remove the trace
5521 kvm_set_rflags(vcpu, rflags);
5523 kvm_x86_ops->set_guest_debug(vcpu, dbg);
5533 * Translate a guest virtual address to a guest physical address.
5535 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5536 struct kvm_translation *tr)
5538 unsigned long vaddr = tr->linear_address;
5542 idx = srcu_read_lock(&vcpu->kvm->srcu);
5543 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5544 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5545 tr->physical_address = gpa;
5546 tr->valid = gpa != UNMAPPED_GVA;
5553 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5555 struct i387_fxsave_struct *fxsave =
5556 &vcpu->arch.guest_fpu.state->fxsave;
5558 memcpy(fpu->fpr, fxsave->st_space, 128);
5559 fpu->fcw = fxsave->cwd;
5560 fpu->fsw = fxsave->swd;
5561 fpu->ftwx = fxsave->twd;
5562 fpu->last_opcode = fxsave->fop;
5563 fpu->last_ip = fxsave->rip;
5564 fpu->last_dp = fxsave->rdp;
5565 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5570 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5572 struct i387_fxsave_struct *fxsave =
5573 &vcpu->arch.guest_fpu.state->fxsave;
5575 memcpy(fxsave->st_space, fpu->fpr, 128);
5576 fxsave->cwd = fpu->fcw;
5577 fxsave->swd = fpu->fsw;
5578 fxsave->twd = fpu->ftwx;
5579 fxsave->fop = fpu->last_opcode;
5580 fxsave->rip = fpu->last_ip;
5581 fxsave->rdp = fpu->last_dp;
5582 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5587 int fx_init(struct kvm_vcpu *vcpu)
5591 err = fpu_alloc(&vcpu->arch.guest_fpu);
5595 fpu_finit(&vcpu->arch.guest_fpu);
5598 * Ensure guest xcr0 is valid for loading
5600 vcpu->arch.xcr0 = XSTATE_FP;
5602 vcpu->arch.cr0 |= X86_CR0_ET;
5606 EXPORT_SYMBOL_GPL(fx_init);
5608 static void fx_free(struct kvm_vcpu *vcpu)
5610 fpu_free(&vcpu->arch.guest_fpu);
5613 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5615 if (vcpu->guest_fpu_loaded)
5619 * Restore all possible states in the guest,
5620 * and assume host would use all available bits.
5621 * Guest xcr0 would be loaded later.
5623 kvm_put_guest_xcr0(vcpu);
5624 vcpu->guest_fpu_loaded = 1;
5625 unlazy_fpu(current);
5626 fpu_restore_checking(&vcpu->arch.guest_fpu);
5630 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5632 kvm_put_guest_xcr0(vcpu);
5634 if (!vcpu->guest_fpu_loaded)
5637 vcpu->guest_fpu_loaded = 0;
5638 fpu_save_init(&vcpu->arch.guest_fpu);
5639 ++vcpu->stat.fpu_reload;
5640 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5644 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5646 if (vcpu->arch.time_page) {
5647 kvm_release_page_dirty(vcpu->arch.time_page);
5648 vcpu->arch.time_page = NULL;
5651 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5653 kvm_x86_ops->vcpu_free(vcpu);
5656 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5659 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5660 printk_once(KERN_WARNING
5661 "kvm: SMP vm created on host with unstable TSC; "
5662 "guest TSC will not be reliable\n");
5663 return kvm_x86_ops->vcpu_create(kvm, id);
5666 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5670 vcpu->arch.mtrr_state.have_fixed = 1;
5672 r = kvm_arch_vcpu_reset(vcpu);
5674 r = kvm_mmu_setup(vcpu);
5681 kvm_x86_ops->vcpu_free(vcpu);
5685 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
5688 kvm_mmu_unload(vcpu);
5692 kvm_x86_ops->vcpu_free(vcpu);
5695 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5697 vcpu->arch.nmi_pending = false;
5698 vcpu->arch.nmi_injected = false;
5700 vcpu->arch.switch_db_regs = 0;
5701 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5702 vcpu->arch.dr6 = DR6_FIXED_1;
5703 vcpu->arch.dr7 = DR7_FIXED_1;
5705 kvm_make_request(KVM_REQ_EVENT, vcpu);
5707 return kvm_x86_ops->vcpu_reset(vcpu);
5710 int kvm_arch_hardware_enable(void *garbage)
5713 struct kvm_vcpu *vcpu;
5716 kvm_shared_msr_cpu_online();
5717 list_for_each_entry(kvm, &vm_list, vm_list)
5718 kvm_for_each_vcpu(i, vcpu, kvm)
5719 if (vcpu->cpu == smp_processor_id())
5720 kvm_request_guest_time_update(vcpu);
5721 return kvm_x86_ops->hardware_enable(garbage);
5724 void kvm_arch_hardware_disable(void *garbage)
5726 kvm_x86_ops->hardware_disable(garbage);
5727 drop_user_return_notifiers(garbage);
5730 int kvm_arch_hardware_setup(void)
5732 return kvm_x86_ops->hardware_setup();
5735 void kvm_arch_hardware_unsetup(void)
5737 kvm_x86_ops->hardware_unsetup();
5740 void kvm_arch_check_processor_compat(void *rtn)
5742 kvm_x86_ops->check_processor_compatibility(rtn);
5745 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5751 BUG_ON(vcpu->kvm == NULL);
5754 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
5755 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
5756 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
5757 vcpu->arch.mmu.translate_gpa = translate_gpa;
5758 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5759 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
5760 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5762 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
5764 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5769 vcpu->arch.pio_data = page_address(page);
5771 r = kvm_mmu_create(vcpu);
5773 goto fail_free_pio_data;
5775 if (irqchip_in_kernel(kvm)) {
5776 r = kvm_create_lapic(vcpu);
5778 goto fail_mmu_destroy;
5781 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5783 if (!vcpu->arch.mce_banks) {
5785 goto fail_free_lapic;
5787 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5789 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5790 goto fail_free_mce_banks;
5793 fail_free_mce_banks:
5794 kfree(vcpu->arch.mce_banks);
5796 kvm_free_lapic(vcpu);
5798 kvm_mmu_destroy(vcpu);
5800 free_page((unsigned long)vcpu->arch.pio_data);
5805 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5809 kfree(vcpu->arch.mce_banks);
5810 kvm_free_lapic(vcpu);
5811 idx = srcu_read_lock(&vcpu->kvm->srcu);
5812 kvm_mmu_destroy(vcpu);
5813 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5814 free_page((unsigned long)vcpu->arch.pio_data);
5817 struct kvm *kvm_arch_create_vm(void)
5819 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5822 return ERR_PTR(-ENOMEM);
5824 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
5825 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
5827 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5828 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5830 spin_lock_init(&kvm->arch.tsc_write_lock);
5835 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5838 kvm_mmu_unload(vcpu);
5842 static void kvm_free_vcpus(struct kvm *kvm)
5845 struct kvm_vcpu *vcpu;
5848 * Unpin any mmu pages first.
5850 kvm_for_each_vcpu(i, vcpu, kvm)
5851 kvm_unload_vcpu_mmu(vcpu);
5852 kvm_for_each_vcpu(i, vcpu, kvm)
5853 kvm_arch_vcpu_free(vcpu);
5855 mutex_lock(&kvm->lock);
5856 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5857 kvm->vcpus[i] = NULL;
5859 atomic_set(&kvm->online_vcpus, 0);
5860 mutex_unlock(&kvm->lock);
5863 void kvm_arch_sync_events(struct kvm *kvm)
5865 kvm_free_all_assigned_devices(kvm);
5869 void kvm_arch_destroy_vm(struct kvm *kvm)
5871 kvm_iommu_unmap_guest(kvm);
5872 kfree(kvm->arch.vpic);
5873 kfree(kvm->arch.vioapic);
5874 kvm_free_vcpus(kvm);
5875 kvm_free_physmem(kvm);
5876 if (kvm->arch.apic_access_page)
5877 put_page(kvm->arch.apic_access_page);
5878 if (kvm->arch.ept_identity_pagetable)
5879 put_page(kvm->arch.ept_identity_pagetable);
5880 cleanup_srcu_struct(&kvm->srcu);
5884 int kvm_arch_prepare_memory_region(struct kvm *kvm,
5885 struct kvm_memory_slot *memslot,
5886 struct kvm_memory_slot old,
5887 struct kvm_userspace_memory_region *mem,
5890 int npages = memslot->npages;
5891 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5893 /* Prevent internal slot pages from being moved by fork()/COW. */
5894 if (memslot->id >= KVM_MEMORY_SLOTS)
5895 map_flags = MAP_SHARED | MAP_ANONYMOUS;
5897 /*To keep backward compatibility with older userspace,
5898 *x86 needs to hanlde !user_alloc case.
5901 if (npages && !old.rmap) {
5902 unsigned long userspace_addr;
5904 down_write(¤t->mm->mmap_sem);
5905 userspace_addr = do_mmap(NULL, 0,
5907 PROT_READ | PROT_WRITE,
5910 up_write(¤t->mm->mmap_sem);
5912 if (IS_ERR((void *)userspace_addr))
5913 return PTR_ERR((void *)userspace_addr);
5915 memslot->userspace_addr = userspace_addr;
5923 void kvm_arch_commit_memory_region(struct kvm *kvm,
5924 struct kvm_userspace_memory_region *mem,
5925 struct kvm_memory_slot old,
5929 int npages = mem->memory_size >> PAGE_SHIFT;
5931 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5934 down_write(¤t->mm->mmap_sem);
5935 ret = do_munmap(current->mm, old.userspace_addr,
5936 old.npages * PAGE_SIZE);
5937 up_write(¤t->mm->mmap_sem);
5940 "kvm_vm_ioctl_set_memory_region: "
5941 "failed to munmap memory\n");
5944 spin_lock(&kvm->mmu_lock);
5945 if (!kvm->arch.n_requested_mmu_pages) {
5946 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5947 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5950 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
5951 spin_unlock(&kvm->mmu_lock);
5954 void kvm_arch_flush_shadow(struct kvm *kvm)
5956 kvm_mmu_zap_all(kvm);
5957 kvm_reload_remote_mmus(kvm);
5960 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5962 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
5963 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5964 || vcpu->arch.nmi_pending ||
5965 (kvm_arch_interrupt_allowed(vcpu) &&
5966 kvm_cpu_has_interrupt(vcpu));
5969 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5972 int cpu = vcpu->cpu;
5974 if (waitqueue_active(&vcpu->wq)) {
5975 wake_up_interruptible(&vcpu->wq);
5976 ++vcpu->stat.halt_wakeup;
5980 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5981 if (atomic_xchg(&vcpu->guest_mode, 0))
5982 smp_send_reschedule(cpu);
5986 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5988 return kvm_x86_ops->interrupt_allowed(vcpu);
5991 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5993 unsigned long current_rip = kvm_rip_read(vcpu) +
5994 get_segment_base(vcpu, VCPU_SREG_CS);
5996 return current_rip == linear_rip;
5998 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6000 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6002 unsigned long rflags;
6004 rflags = kvm_x86_ops->get_rflags(vcpu);
6005 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6006 rflags &= ~X86_EFLAGS_TF;
6009 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6011 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6013 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6014 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6015 rflags |= X86_EFLAGS_TF;
6016 kvm_x86_ops->set_rflags(vcpu, rflags);
6017 kvm_make_request(KVM_REQ_EVENT, vcpu);
6019 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6021 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6022 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6023 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6024 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6025 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6026 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6027 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6028 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6029 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6030 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6031 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6032 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);