arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affilates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 static int __read_mostly bypass_guest_pf = 1;
  51 module_param(bypass_guest_pf, bool, S_IRUGO);
  52
  53 static int __read_mostly enable_vpid = 1;
  54 module_param_named(vpid, enable_vpid, bool, 0444);
  55
  56 static int __read_mostly flexpriority_enabled = 1;
  57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_ept = 1;
  60 module_param_named(ept, enable_ept, bool, S_IRUGO);
  61
  62 static int __read_mostly enable_unrestricted_guest = 1;
  63 module_param_named(unrestricted_guest,
  64                         enable_unrestricted_guest, bool, S_IRUGO);
  65
  66 static int __read_mostly emulate_invalid_guest_state = 0;
  67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  68
  69 static int __read_mostly vmm_exclusive = 1;
  70 module_param(vmm_exclusive, bool, S_IRUGO);
  71
  72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  73         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  74 #define KVM_GUEST_CR0_MASK                                              \
  75         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  77         (X86_CR0_WP | X86_CR0_NE)
  78 #define KVM_VM_CR0_ALWAYS_ON                                            \
  79         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  80 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  81         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  82          | X86_CR4_OSXMMEXCPT)
  83
  84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  86
  87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  88
  89 /*
  90  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  91  * ple_gap:    upper bound on the amount of time between two successive
  92  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  93  *             According to test, this time is usually small than 41 cycles.
  94  * ple_window: upper bound on the amount of time a guest is allowed to execute
  95  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  96  *             less than 2^12 cycles
  97  * Time is measured based on a counter that runs at the same rate as the TSC,
  98  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  99  */
 100 #define KVM_VMX_DEFAULT_PLE_GAP    41
 101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 102 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 103 module_param(ple_gap, int, S_IRUGO);
 104
 105 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 106 module_param(ple_window, int, S_IRUGO);
 107
 108 #define NR_AUTOLOAD_MSRS 1
 109
 110 struct vmcs {
 111         u32 revision_id;
 112         u32 abort;
 113         char data[0];
 114 };
 115
 116 struct shared_msr_entry {
 117         unsigned index;
 118         u64 data;
 119         u64 mask;
 120 };
 121
 122 struct vcpu_vmx {
 123         struct kvm_vcpu       vcpu;
 124         struct list_head      local_vcpus_link;
 125         unsigned long         host_rsp;
 126         int                   launched;
 127         u8                    fail;
 128         u32                   idt_vectoring_info;
 129         struct shared_msr_entry *guest_msrs;
 130         int                   nmsrs;
 131         int                   save_nmsrs;
 132 #ifdef CONFIG_X86_64
 133         u64                   msr_host_kernel_gs_base;
 134         u64                   msr_guest_kernel_gs_base;
 135 #endif
 136         struct vmcs          *vmcs;
 137         struct msr_autoload {
 138                 unsigned nr;
 139                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 140                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 141         } msr_autoload;
 142         struct {
 143                 int           loaded;
 144                 u16           fs_sel, gs_sel, ldt_sel;
 145                 int           gs_ldt_reload_needed;
 146                 int           fs_reload_needed;
 147         } host_state;
 148         struct {
 149                 int vm86_active;
 150                 ulong save_rflags;
 151                 struct kvm_save_segment {
 152                         u16 selector;
 153                         unsigned long base;
 154                         u32 limit;
 155                         u32 ar;
 156                 } tr, es, ds, fs, gs;
 157                 struct {
 158                         bool pending;
 159                         u8 vector;
 160                         unsigned rip;
 161                 } irq;
 162         } rmode;
 163         int vpid;
 164         bool emulation_required;
 165
 166         /* Support for vnmi-less CPUs */
 167         int soft_vnmi_blocked;
 168         ktime_t entry_time;
 169         s64 vnmi_blocked_time;
 170         u32 exit_reason;
 171
 172         bool rdtscp_enabled;
 173 };
 174
 175 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 176 {
 177         return container_of(vcpu, struct vcpu_vmx, vcpu);
 178 }
 179
 180 static int init_rmode(struct kvm *kvm);
 181 static u64 construct_eptp(unsigned long root_hpa);
 182 static void kvm_cpu_vmxon(u64 addr);
 183 static void kvm_cpu_vmxoff(void);
 184
 185 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 186 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 187 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 188 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 189
 190 static unsigned long *vmx_io_bitmap_a;
 191 static unsigned long *vmx_io_bitmap_b;
 192 static unsigned long *vmx_msr_bitmap_legacy;
 193 static unsigned long *vmx_msr_bitmap_longmode;
 194
 195 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 196 static DEFINE_SPINLOCK(vmx_vpid_lock);
 197
 198 static struct vmcs_config {
 199         int size;
 200         int order;
 201         u32 revision_id;
 202         u32 pin_based_exec_ctrl;
 203         u32 cpu_based_exec_ctrl;
 204         u32 cpu_based_2nd_exec_ctrl;
 205         u32 vmexit_ctrl;
 206         u32 vmentry_ctrl;
 207 } vmcs_config;
 208
 209 static struct vmx_capability {
 210         u32 ept;
 211         u32 vpid;
 212 } vmx_capability;
 213
 214 #define VMX_SEGMENT_FIELD(seg)                                  \
 215         [VCPU_SREG_##seg] = {                                   \
 216                 .selector = GUEST_##seg##_SELECTOR,             \
 217                 .base = GUEST_##seg##_BASE,                     \
 218                 .limit = GUEST_##seg##_LIMIT,                   \
 219                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 220         }
 221
 222 static struct kvm_vmx_segment_field {
 223         unsigned selector;
 224         unsigned base;
 225         unsigned limit;
 226         unsigned ar_bytes;
 227 } kvm_vmx_segment_fields[] = {
 228         VMX_SEGMENT_FIELD(CS),
 229         VMX_SEGMENT_FIELD(DS),
 230         VMX_SEGMENT_FIELD(ES),
 231         VMX_SEGMENT_FIELD(FS),
 232         VMX_SEGMENT_FIELD(GS),
 233         VMX_SEGMENT_FIELD(SS),
 234         VMX_SEGMENT_FIELD(TR),
 235         VMX_SEGMENT_FIELD(LDTR),
 236 };
 237
 238 static u64 host_efer;
 239
 240 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 241
 242 /*
 243  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 244  * away by decrementing the array size.
 245  */
 246 static const u32 vmx_msr_index[] = {
 247 #ifdef CONFIG_X86_64
 248         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 249 #endif
 250         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 251 };
 252 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 253
 254 static inline bool is_page_fault(u32 intr_info)
 255 {
 256         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 257                              INTR_INFO_VALID_MASK)) ==
 258                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 259 }
 260
 261 static inline bool is_no_device(u32 intr_info)
 262 {
 263         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 264                              INTR_INFO_VALID_MASK)) ==
 265                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 266 }
 267
 268 static inline bool is_invalid_opcode(u32 intr_info)
 269 {
 270         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 271                              INTR_INFO_VALID_MASK)) ==
 272                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 273 }
 274
 275 static inline bool is_external_interrupt(u32 intr_info)
 276 {
 277         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 278                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 279 }
 280
 281 static inline bool is_machine_check(u32 intr_info)
 282 {
 283         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 284                              INTR_INFO_VALID_MASK)) ==
 285                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 286 }
 287
 288 static inline bool cpu_has_vmx_msr_bitmap(void)
 289 {
 290         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 291 }
 292
 293 static inline bool cpu_has_vmx_tpr_shadow(void)
 294 {
 295         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 296 }
 297
 298 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 299 {
 300         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 301 }
 302
 303 static inline bool cpu_has_secondary_exec_ctrls(void)
 304 {
 305         return vmcs_config.cpu_based_exec_ctrl &
 306                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 307 }
 308
 309 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 310 {
 311         return vmcs_config.cpu_based_2nd_exec_ctrl &
 312                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 313 }
 314
 315 static inline bool cpu_has_vmx_flexpriority(void)
 316 {
 317         return cpu_has_vmx_tpr_shadow() &&
 318                 cpu_has_vmx_virtualize_apic_accesses();
 319 }
 320
 321 static inline bool cpu_has_vmx_ept_execute_only(void)
 322 {
 323         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 324 }
 325
 326 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 327 {
 328         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 329 }
 330
 331 static inline bool cpu_has_vmx_eptp_writeback(void)
 332 {
 333         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 334 }
 335
 336 static inline bool cpu_has_vmx_ept_2m_page(void)
 337 {
 338         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 339 }
 340
 341 static inline bool cpu_has_vmx_ept_1g_page(void)
 342 {
 343         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 344 }
 345
 346 static inline bool cpu_has_vmx_ept_4levels(void)
 347 {
 348         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 349 }
 350
 351 static inline bool cpu_has_vmx_invept_individual_addr(void)
 352 {
 353         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 354 }
 355
 356 static inline bool cpu_has_vmx_invept_context(void)
 357 {
 358         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 359 }
 360
 361 static inline bool cpu_has_vmx_invept_global(void)
 362 {
 363         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 364 }
 365
 366 static inline bool cpu_has_vmx_invvpid_single(void)
 367 {
 368         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 369 }
 370
 371 static inline bool cpu_has_vmx_invvpid_global(void)
 372 {
 373         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 374 }
 375
 376 static inline bool cpu_has_vmx_ept(void)
 377 {
 378         return vmcs_config.cpu_based_2nd_exec_ctrl &
 379                 SECONDARY_EXEC_ENABLE_EPT;
 380 }
 381
 382 static inline bool cpu_has_vmx_unrestricted_guest(void)
 383 {
 384         return vmcs_config.cpu_based_2nd_exec_ctrl &
 385                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 386 }
 387
 388 static inline bool cpu_has_vmx_ple(void)
 389 {
 390         return vmcs_config.cpu_based_2nd_exec_ctrl &
 391                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 392 }
 393
 394 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 395 {
 396         return flexpriority_enabled && irqchip_in_kernel(kvm);
 397 }
 398
 399 static inline bool cpu_has_vmx_vpid(void)
 400 {
 401         return vmcs_config.cpu_based_2nd_exec_ctrl &
 402                 SECONDARY_EXEC_ENABLE_VPID;
 403 }
 404
 405 static inline bool cpu_has_vmx_rdtscp(void)
 406 {
 407         return vmcs_config.cpu_based_2nd_exec_ctrl &
 408                 SECONDARY_EXEC_RDTSCP;
 409 }
 410
 411 static inline bool cpu_has_virtual_nmis(void)
 412 {
 413         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 414 }
 415
 416 static inline bool cpu_has_vmx_wbinvd_exit(void)
 417 {
 418         return vmcs_config.cpu_based_2nd_exec_ctrl &
 419                 SECONDARY_EXEC_WBINVD_EXITING;
 420 }
 421
 422 static inline bool report_flexpriority(void)
 423 {
 424         return flexpriority_enabled;
 425 }
 426
 427 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 428 {
 429         int i;
 430
 431         for (i = 0; i < vmx->nmsrs; ++i)
 432                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 433                         return i;
 434         return -1;
 435 }
 436
 437 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 438 {
 439     struct {
 440         u64 vpid : 16;
 441         u64 rsvd : 48;
 442         u64 gva;
 443     } operand = { vpid, 0, gva };
 444
 445     asm volatile (__ex(ASM_VMX_INVVPID)
 446                   /* CF==1 or ZF==1 --> rc = -1 */
 447                   "; ja 1f ; ud2 ; 1:"
 448                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 449 }
 450
 451 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 452 {
 453         struct {
 454                 u64 eptp, gpa;
 455         } operand = {eptp, gpa};
 456
 457         asm volatile (__ex(ASM_VMX_INVEPT)
 458                         /* CF==1 or ZF==1 --> rc = -1 */
 459                         "; ja 1f ; ud2 ; 1:\n"
 460                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 461 }
 462
 463 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 464 {
 465         int i;
 466
 467         i = __find_msr_index(vmx, msr);
 468         if (i >= 0)
 469                 return &vmx->guest_msrs[i];
 470         return NULL;
 471 }
 472
 473 static void vmcs_clear(struct vmcs *vmcs)
 474 {
 475         u64 phys_addr = __pa(vmcs);
 476         u8 error;
 477
 478         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 479                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 480                       : "cc", "memory");
 481         if (error)
 482                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 483                        vmcs, phys_addr);
 484 }
 485
 486 static void vmcs_load(struct vmcs *vmcs)
 487 {
 488         u64 phys_addr = __pa(vmcs);
 489         u8 error;
 490
 491         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 492                         : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 493                         : "cc", "memory");
 494         if (error)
 495                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 496                        vmcs, phys_addr);
 497 }
 498
 499 static void __vcpu_clear(void *arg)
 500 {
 501         struct vcpu_vmx *vmx = arg;
 502         int cpu = raw_smp_processor_id();
 503
 504         if (vmx->vcpu.cpu == cpu)
 505                 vmcs_clear(vmx->vmcs);
 506         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 507                 per_cpu(current_vmcs, cpu) = NULL;
 508         list_del(&vmx->local_vcpus_link);
 509         vmx->vcpu.cpu = -1;
 510         vmx->launched = 0;
 511 }
 512
 513 static void vcpu_clear(struct vcpu_vmx *vmx)
 514 {
 515         if (vmx->vcpu.cpu == -1)
 516                 return;
 517         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 518 }
 519
 520 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 521 {
 522         if (vmx->vpid == 0)
 523                 return;
 524
 525         if (cpu_has_vmx_invvpid_single())
 526                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 527 }
 528
 529 static inline void vpid_sync_vcpu_global(void)
 530 {
 531         if (cpu_has_vmx_invvpid_global())
 532                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 533 }
 534
 535 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 536 {
 537         if (cpu_has_vmx_invvpid_single())
 538                 vpid_sync_vcpu_single(vmx);
 539         else
 540                 vpid_sync_vcpu_global();
 541 }
 542
 543 static inline void ept_sync_global(void)
 544 {
 545         if (cpu_has_vmx_invept_global())
 546                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 547 }
 548
 549 static inline void ept_sync_context(u64 eptp)
 550 {
 551         if (enable_ept) {
 552                 if (cpu_has_vmx_invept_context())
 553                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 554                 else
 555                         ept_sync_global();
 556         }
 557 }
 558
 559 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 560 {
 561         if (enable_ept) {
 562                 if (cpu_has_vmx_invept_individual_addr())
 563                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 564                                         eptp, gpa);
 565                 else
 566                         ept_sync_context(eptp);
 567         }
 568 }
 569
 570 static unsigned long vmcs_readl(unsigned long field)
 571 {
 572         unsigned long value;
 573
 574         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 575                       : "=a"(value) : "d"(field) : "cc");
 576         return value;
 577 }
 578
 579 static u16 vmcs_read16(unsigned long field)
 580 {
 581         return vmcs_readl(field);
 582 }
 583
 584 static u32 vmcs_read32(unsigned long field)
 585 {
 586         return vmcs_readl(field);
 587 }
 588
 589 static u64 vmcs_read64(unsigned long field)
 590 {
 591 #ifdef CONFIG_X86_64
 592         return vmcs_readl(field);
 593 #else
 594         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 595 #endif
 596 }
 597
 598 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 599 {
 600         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 601                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 602         dump_stack();
 603 }
 604
 605 static void vmcs_writel(unsigned long field, unsigned long value)
 606 {
 607         u8 error;
 608
 609         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 610                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 611         if (unlikely(error))
 612                 vmwrite_error(field, value);
 613 }
 614
 615 static void vmcs_write16(unsigned long field, u16 value)
 616 {
 617         vmcs_writel(field, value);
 618 }
 619
 620 static void vmcs_write32(unsigned long field, u32 value)
 621 {
 622         vmcs_writel(field, value);
 623 }
 624
 625 static void vmcs_write64(unsigned long field, u64 value)
 626 {
 627         vmcs_writel(field, value);
 628 #ifndef CONFIG_X86_64
 629         asm volatile ("");
 630         vmcs_writel(field+1, value >> 32);
 631 #endif
 632 }
 633
 634 static void vmcs_clear_bits(unsigned long field, u32 mask)
 635 {
 636         vmcs_writel(field, vmcs_readl(field) & ~mask);
 637 }
 638
 639 static void vmcs_set_bits(unsigned long field, u32 mask)
 640 {
 641         vmcs_writel(field, vmcs_readl(field) | mask);
 642 }
 643
 644 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 645 {
 646         u32 eb;
 647
 648         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 649              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 650         if ((vcpu->guest_debug &
 651              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 652             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 653                 eb |= 1u << BP_VECTOR;
 654         if (to_vmx(vcpu)->rmode.vm86_active)
 655                 eb = ~0;
 656         if (enable_ept)
 657                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 658         if (vcpu->fpu_active)
 659                 eb &= ~(1u << NM_VECTOR);
 660         vmcs_write32(EXCEPTION_BITMAP, eb);
 661 }
 662
 663 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 664 {
 665         unsigned i;
 666         struct msr_autoload *m = &vmx->msr_autoload;
 667
 668         for (i = 0; i < m->nr; ++i)
 669                 if (m->guest[i].index == msr)
 670                         break;
 671
 672         if (i == m->nr)
 673                 return;
 674         --m->nr;
 675         m->guest[i] = m->guest[m->nr];
 676         m->host[i] = m->host[m->nr];
 677         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 678         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 679 }
 680
 681 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 682                                   u64 guest_val, u64 host_val)
 683 {
 684         unsigned i;
 685         struct msr_autoload *m = &vmx->msr_autoload;
 686
 687         for (i = 0; i < m->nr; ++i)
 688                 if (m->guest[i].index == msr)
 689                         break;
 690
 691         if (i == m->nr) {
 692                 ++m->nr;
 693                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 694                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 695         }
 696
 697         m->guest[i].index = msr;
 698         m->guest[i].value = guest_val;
 699         m->host[i].index = msr;
 700         m->host[i].value = host_val;
 701 }
 702
 703 static void reload_tss(void)
 704 {
 705         /*
 706          * VT restores TR but not its size.  Useless.
 707          */
 708         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 709         struct desc_struct *descs;
 710
 711         descs = (void *)gdt->address;
 712         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 713         load_TR_desc();
 714 }
 715
 716 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 717 {
 718         u64 guest_efer;
 719         u64 ignore_bits;
 720
 721         guest_efer = vmx->vcpu.arch.efer;
 722
 723         /*
 724          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 725          * outside long mode
 726          */
 727         ignore_bits = EFER_NX | EFER_SCE;
 728 #ifdef CONFIG_X86_64
 729         ignore_bits |= EFER_LMA | EFER_LME;
 730         /* SCE is meaningful only in long mode on Intel */
 731         if (guest_efer & EFER_LMA)
 732                 ignore_bits &= ~(u64)EFER_SCE;
 733 #endif
 734         guest_efer &= ~ignore_bits;
 735         guest_efer |= host_efer & ignore_bits;
 736         vmx->guest_msrs[efer_offset].data = guest_efer;
 737         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 738
 739         clear_atomic_switch_msr(vmx, MSR_EFER);
 740         /* On ept, can't emulate nx, and must switch nx atomically */
 741         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 742                 guest_efer = vmx->vcpu.arch.efer;
 743                 if (!(guest_efer & EFER_LMA))
 744                         guest_efer &= ~EFER_LME;
 745                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 746                 return false;
 747         }
 748
 749         return true;
 750 }
 751
 752 static unsigned long segment_base(u16 selector)
 753 {
 754         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 755         struct desc_struct *d;
 756         unsigned long table_base;
 757         unsigned long v;
 758
 759         if (!(selector & ~3))
 760                 return 0;
 761
 762         table_base = gdt->address;
 763
 764         if (selector & 4) {           /* from ldt */
 765                 u16 ldt_selector = kvm_read_ldt();
 766
 767                 if (!(ldt_selector & ~3))
 768                         return 0;
 769
 770                 table_base = segment_base(ldt_selector);
 771         }
 772         d = (struct desc_struct *)(table_base + (selector & ~7));
 773         v = get_desc_base(d);
 774 #ifdef CONFIG_X86_64
 775        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 776                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 777 #endif
 778         return v;
 779 }
 780
 781 static inline unsigned long kvm_read_tr_base(void)
 782 {
 783         u16 tr;
 784         asm("str %0" : "=g"(tr));
 785         return segment_base(tr);
 786 }
 787
 788 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 789 {
 790         struct vcpu_vmx *vmx = to_vmx(vcpu);
 791         int i;
 792
 793         if (vmx->host_state.loaded)
 794                 return;
 795
 796         vmx->host_state.loaded = 1;
 797         /*
 798          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 799          * allow segment selectors with cpl > 0 or ti == 1.
 800          */
 801         vmx->host_state.ldt_sel = kvm_read_ldt();
 802         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 803         savesegment(fs, vmx->host_state.fs_sel);
 804         if (!(vmx->host_state.fs_sel & 7)) {
 805                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 806                 vmx->host_state.fs_reload_needed = 0;
 807         } else {
 808                 vmcs_write16(HOST_FS_SELECTOR, 0);
 809                 vmx->host_state.fs_reload_needed = 1;
 810         }
 811         savesegment(gs, vmx->host_state.gs_sel);
 812         if (!(vmx->host_state.gs_sel & 7))
 813                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 814         else {
 815                 vmcs_write16(HOST_GS_SELECTOR, 0);
 816                 vmx->host_state.gs_ldt_reload_needed = 1;
 817         }
 818
 819 #ifdef CONFIG_X86_64
 820         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 821         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 822 #else
 823         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 824         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 825 #endif
 826
 827 #ifdef CONFIG_X86_64
 828         if (is_long_mode(&vmx->vcpu)) {
 829                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 830                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 831         }
 832 #endif
 833         for (i = 0; i < vmx->save_nmsrs; ++i)
 834                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 835                                    vmx->guest_msrs[i].data,
 836                                    vmx->guest_msrs[i].mask);
 837 }
 838
 839 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 840 {
 841         if (!vmx->host_state.loaded)
 842                 return;
 843
 844         ++vmx->vcpu.stat.host_state_reload;
 845         vmx->host_state.loaded = 0;
 846         if (vmx->host_state.fs_reload_needed)
 847                 loadsegment(fs, vmx->host_state.fs_sel);
 848         if (vmx->host_state.gs_ldt_reload_needed) {
 849                 kvm_load_ldt(vmx->host_state.ldt_sel);
 850 #ifdef CONFIG_X86_64
 851                 load_gs_index(vmx->host_state.gs_sel);
 852                 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
 853 #else
 854                 loadsegment(gs, vmx->host_state.gs_sel);
 855 #endif
 856         }
 857         reload_tss();
 858 #ifdef CONFIG_X86_64
 859         if (is_long_mode(&vmx->vcpu)) {
 860                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 861                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 862         }
 863 #endif
 864         if (current_thread_info()->status & TS_USEDFPU)
 865                 clts();
 866         load_gdt(&__get_cpu_var(host_gdt));
 867 }
 868
 869 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 870 {
 871         preempt_disable();
 872         __vmx_load_host_state(vmx);
 873         preempt_enable();
 874 }
 875
 876 /*
 877  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 878  * vcpu mutex is already taken.
 879  */
 880 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 881 {
 882         struct vcpu_vmx *vmx = to_vmx(vcpu);
 883         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 884
 885         if (!vmm_exclusive)
 886                 kvm_cpu_vmxon(phys_addr);
 887         else if (vcpu->cpu != cpu)
 888                 vcpu_clear(vmx);
 889
 890         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 891                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 892                 vmcs_load(vmx->vmcs);
 893         }
 894
 895         if (vcpu->cpu != cpu) {
 896                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 897                 unsigned long sysenter_esp;
 898
 899                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 900                 local_irq_disable();
 901                 list_add(&vmx->local_vcpus_link,
 902                          &per_cpu(vcpus_on_cpu, cpu));
 903                 local_irq_enable();
 904
 905                 /*
 906                  * Linux uses per-cpu TSS and GDT, so set these when switching
 907                  * processors.
 908                  */
 909                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 910                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
 911
 912                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 913                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 914         }
 915 }
 916
 917 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 918 {
 919         __vmx_load_host_state(to_vmx(vcpu));
 920         if (!vmm_exclusive) {
 921                 __vcpu_clear(to_vmx(vcpu));
 922                 kvm_cpu_vmxoff();
 923         }
 924 }
 925
 926 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 927 {
 928         ulong cr0;
 929
 930         if (vcpu->fpu_active)
 931                 return;
 932         vcpu->fpu_active = 1;
 933         cr0 = vmcs_readl(GUEST_CR0);
 934         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 935         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 936         vmcs_writel(GUEST_CR0, cr0);
 937         update_exception_bitmap(vcpu);
 938         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 939         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 940 }
 941
 942 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 943
 944 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 945 {
 946         vmx_decache_cr0_guest_bits(vcpu);
 947         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 948         update_exception_bitmap(vcpu);
 949         vcpu->arch.cr0_guest_owned_bits = 0;
 950         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 951         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 952 }
 953
 954 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 955 {
 956         unsigned long rflags, save_rflags;
 957
 958         rflags = vmcs_readl(GUEST_RFLAGS);
 959         if (to_vmx(vcpu)->rmode.vm86_active) {
 960                 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 961                 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 962                 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 963         }
 964         return rflags;
 965 }
 966
 967 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 968 {
 969         if (to_vmx(vcpu)->rmode.vm86_active) {
 970                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 971                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 972         }
 973         vmcs_writel(GUEST_RFLAGS, rflags);
 974 }
 975
 976 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 977 {
 978         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 979         int ret = 0;
 980
 981         if (interruptibility & GUEST_INTR_STATE_STI)
 982                 ret |= KVM_X86_SHADOW_INT_STI;
 983         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 984                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
 985
 986         return ret & mask;
 987 }
 988
 989 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 990 {
 991         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 992         u32 interruptibility = interruptibility_old;
 993
 994         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 995
 996         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
 997                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 998         else if (mask & KVM_X86_SHADOW_INT_STI)
 999                 interruptibility |= GUEST_INTR_STATE_STI;
1000
1001         if ((interruptibility != interruptibility_old))
1002                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1003 }
1004
1005 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1006 {
1007         unsigned long rip;
1008
1009         rip = kvm_rip_read(vcpu);
1010         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1011         kvm_rip_write(vcpu, rip);
1012
1013         /* skipping an emulated instruction also counts */
1014         vmx_set_interrupt_shadow(vcpu, 0);
1015 }
1016
1017 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1018                                 bool has_error_code, u32 error_code,
1019                                 bool reinject)
1020 {
1021         struct vcpu_vmx *vmx = to_vmx(vcpu);
1022         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1023
1024         if (has_error_code) {
1025                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1026                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1027         }
1028
1029         if (vmx->rmode.vm86_active) {
1030                 vmx->rmode.irq.pending = true;
1031                 vmx->rmode.irq.vector = nr;
1032                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
1033                 if (kvm_exception_is_soft(nr))
1034                         vmx->rmode.irq.rip +=
1035                                 vmx->vcpu.arch.event_exit_inst_len;
1036                 intr_info |= INTR_TYPE_SOFT_INTR;
1037                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1038                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1039                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1040                 return;
1041         }
1042
1043         if (kvm_exception_is_soft(nr)) {
1044                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1045                              vmx->vcpu.arch.event_exit_inst_len);
1046                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1047         } else
1048                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1049
1050         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1051 }
1052
1053 static bool vmx_rdtscp_supported(void)
1054 {
1055         return cpu_has_vmx_rdtscp();
1056 }
1057
1058 /*
1059  * Swap MSR entry in host/guest MSR entry array.
1060  */
1061 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1062 {
1063         struct shared_msr_entry tmp;
1064
1065         tmp = vmx->guest_msrs[to];
1066         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1067         vmx->guest_msrs[from] = tmp;
1068 }
1069
1070 /*
1071  * Set up the vmcs to automatically save and restore system
1072  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1073  * mode, as fiddling with msrs is very expensive.
1074  */
1075 static void setup_msrs(struct vcpu_vmx *vmx)
1076 {
1077         int save_nmsrs, index;
1078         unsigned long *msr_bitmap;
1079
1080         vmx_load_host_state(vmx);
1081         save_nmsrs = 0;
1082 #ifdef CONFIG_X86_64
1083         if (is_long_mode(&vmx->vcpu)) {
1084                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1085                 if (index >= 0)
1086                         move_msr_up(vmx, index, save_nmsrs++);
1087                 index = __find_msr_index(vmx, MSR_LSTAR);
1088                 if (index >= 0)
1089                         move_msr_up(vmx, index, save_nmsrs++);
1090                 index = __find_msr_index(vmx, MSR_CSTAR);
1091                 if (index >= 0)
1092                         move_msr_up(vmx, index, save_nmsrs++);
1093                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1094                 if (index >= 0 && vmx->rdtscp_enabled)
1095                         move_msr_up(vmx, index, save_nmsrs++);
1096                 /*
1097                  * MSR_STAR is only needed on long mode guests, and only
1098                  * if efer.sce is enabled.
1099                  */
1100                 index = __find_msr_index(vmx, MSR_STAR);
1101                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1102                         move_msr_up(vmx, index, save_nmsrs++);
1103         }
1104 #endif
1105         index = __find_msr_index(vmx, MSR_EFER);
1106         if (index >= 0 && update_transition_efer(vmx, index))
1107                 move_msr_up(vmx, index, save_nmsrs++);
1108
1109         vmx->save_nmsrs = save_nmsrs;
1110
1111         if (cpu_has_vmx_msr_bitmap()) {
1112                 if (is_long_mode(&vmx->vcpu))
1113                         msr_bitmap = vmx_msr_bitmap_longmode;
1114                 else
1115                         msr_bitmap = vmx_msr_bitmap_legacy;
1116
1117                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1118         }
1119 }
1120
1121 /*
1122  * reads and returns guest's timestamp counter "register"
1123  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1124  */
1125 static u64 guest_read_tsc(void)
1126 {
1127         u64 host_tsc, tsc_offset;
1128
1129         rdtscll(host_tsc);
1130         tsc_offset = vmcs_read64(TSC_OFFSET);
1131         return host_tsc + tsc_offset;
1132 }
1133
1134 /*
1135  * writes 'offset' into guest's timestamp counter offset register
1136  */
1137 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1138 {
1139         vmcs_write64(TSC_OFFSET, offset);
1140 }
1141
1142 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1143 {
1144         u64 offset = vmcs_read64(TSC_OFFSET);
1145         vmcs_write64(TSC_OFFSET, offset + adjustment);
1146 }
1147
1148 /*
1149  * Reads an msr value (of 'msr_index') into 'pdata'.
1150  * Returns 0 on success, non-0 otherwise.
1151  * Assumes vcpu_load() was already called.
1152  */
1153 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1154 {
1155         u64 data;
1156         struct shared_msr_entry *msr;
1157
1158         if (!pdata) {
1159                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1160                 return -EINVAL;
1161         }
1162
1163         switch (msr_index) {
1164 #ifdef CONFIG_X86_64
1165         case MSR_FS_BASE:
1166                 data = vmcs_readl(GUEST_FS_BASE);
1167                 break;
1168         case MSR_GS_BASE:
1169                 data = vmcs_readl(GUEST_GS_BASE);
1170                 break;
1171         case MSR_KERNEL_GS_BASE:
1172                 vmx_load_host_state(to_vmx(vcpu));
1173                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1174                 break;
1175 #endif
1176         case MSR_EFER:
1177                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1178         case MSR_IA32_TSC:
1179                 data = guest_read_tsc();
1180                 break;
1181         case MSR_IA32_SYSENTER_CS:
1182                 data = vmcs_read32(GUEST_SYSENTER_CS);
1183                 break;
1184         case MSR_IA32_SYSENTER_EIP:
1185                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1186                 break;
1187         case MSR_IA32_SYSENTER_ESP:
1188                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1189                 break;
1190         case MSR_TSC_AUX:
1191                 if (!to_vmx(vcpu)->rdtscp_enabled)
1192                         return 1;
1193                 /* Otherwise falls through */
1194         default:
1195                 vmx_load_host_state(to_vmx(vcpu));
1196                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1197                 if (msr) {
1198                         vmx_load_host_state(to_vmx(vcpu));
1199                         data = msr->data;
1200                         break;
1201                 }
1202                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1203         }
1204
1205         *pdata = data;
1206         return 0;
1207 }
1208
1209 /*
1210  * Writes msr value into into the appropriate "register".
1211  * Returns 0 on success, non-0 otherwise.
1212  * Assumes vcpu_load() was already called.
1213  */
1214 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1215 {
1216         struct vcpu_vmx *vmx = to_vmx(vcpu);
1217         struct shared_msr_entry *msr;
1218         int ret = 0;
1219
1220         switch (msr_index) {
1221         case MSR_EFER:
1222                 vmx_load_host_state(vmx);
1223                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1224                 break;
1225 #ifdef CONFIG_X86_64
1226         case MSR_FS_BASE:
1227                 vmcs_writel(GUEST_FS_BASE, data);
1228                 break;
1229         case MSR_GS_BASE:
1230                 vmcs_writel(GUEST_GS_BASE, data);
1231                 break;
1232         case MSR_KERNEL_GS_BASE:
1233                 vmx_load_host_state(vmx);
1234                 vmx->msr_guest_kernel_gs_base = data;
1235                 break;
1236 #endif
1237         case MSR_IA32_SYSENTER_CS:
1238                 vmcs_write32(GUEST_SYSENTER_CS, data);
1239                 break;
1240         case MSR_IA32_SYSENTER_EIP:
1241                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1242                 break;
1243         case MSR_IA32_SYSENTER_ESP:
1244                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1245                 break;
1246         case MSR_IA32_TSC:
1247                 kvm_write_tsc(vcpu, data);
1248                 break;
1249         case MSR_IA32_CR_PAT:
1250                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1251                         vmcs_write64(GUEST_IA32_PAT, data);
1252                         vcpu->arch.pat = data;
1253                         break;
1254                 }
1255                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1256                 break;
1257         case MSR_TSC_AUX:
1258                 if (!vmx->rdtscp_enabled)
1259                         return 1;
1260                 /* Check reserved bit, higher 32 bits should be zero */
1261                 if ((data >> 32) != 0)
1262                         return 1;
1263                 /* Otherwise falls through */
1264         default:
1265                 msr = find_msr_entry(vmx, msr_index);
1266                 if (msr) {
1267                         vmx_load_host_state(vmx);
1268                         msr->data = data;
1269                         break;
1270                 }
1271                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1272         }
1273
1274         return ret;
1275 }
1276
1277 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1278 {
1279         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1280         switch (reg) {
1281         case VCPU_REGS_RSP:
1282                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1283                 break;
1284         case VCPU_REGS_RIP:
1285                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1286                 break;
1287         case VCPU_EXREG_PDPTR:
1288                 if (enable_ept)
1289                         ept_save_pdptrs(vcpu);
1290                 break;
1291         default:
1292                 break;
1293         }
1294 }
1295
1296 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1297 {
1298         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1299                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1300         else
1301                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1302
1303         update_exception_bitmap(vcpu);
1304 }
1305
1306 static __init int cpu_has_kvm_support(void)
1307 {
1308         return cpu_has_vmx();
1309 }
1310
1311 static __init int vmx_disabled_by_bios(void)
1312 {
1313         u64 msr;
1314
1315         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1316         if (msr & FEATURE_CONTROL_LOCKED) {
1317                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1318                         && tboot_enabled())
1319                         return 1;
1320                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1321                         && !tboot_enabled())
1322                         return 1;
1323         }
1324
1325         return 0;
1326         /* locked but not enabled */
1327 }
1328
1329 static void kvm_cpu_vmxon(u64 addr)
1330 {
1331         asm volatile (ASM_VMX_VMXON_RAX
1332                         : : "a"(&addr), "m"(addr)
1333                         : "memory", "cc");
1334 }
1335
1336 static int hardware_enable(void *garbage)
1337 {
1338         int cpu = raw_smp_processor_id();
1339         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1340         u64 old, test_bits;
1341
1342         if (read_cr4() & X86_CR4_VMXE)
1343                 return -EBUSY;
1344
1345         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1346         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1347
1348         test_bits = FEATURE_CONTROL_LOCKED;
1349         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1350         if (tboot_enabled())
1351                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1352
1353         if ((old & test_bits) != test_bits) {
1354                 /* enable and lock */
1355                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1356         }
1357         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1358
1359         if (vmm_exclusive) {
1360                 kvm_cpu_vmxon(phys_addr);
1361                 ept_sync_global();
1362         }
1363
1364         store_gdt(&__get_cpu_var(host_gdt));
1365
1366         return 0;
1367 }
1368
1369 static void vmclear_local_vcpus(void)
1370 {
1371         int cpu = raw_smp_processor_id();
1372         struct vcpu_vmx *vmx, *n;
1373
1374         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1375                                  local_vcpus_link)
1376                 __vcpu_clear(vmx);
1377 }
1378
1379
1380 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1381  * tricks.
1382  */
1383 static void kvm_cpu_vmxoff(void)
1384 {
1385         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1386 }
1387
1388 static void hardware_disable(void *garbage)
1389 {
1390         if (vmm_exclusive) {
1391                 vmclear_local_vcpus();
1392                 kvm_cpu_vmxoff();
1393         }
1394         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1395 }
1396
1397 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1398                                       u32 msr, u32 *result)
1399 {
1400         u32 vmx_msr_low, vmx_msr_high;
1401         u32 ctl = ctl_min | ctl_opt;
1402
1403         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1404
1405         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1406         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1407
1408         /* Ensure minimum (required) set of control bits are supported. */
1409         if (ctl_min & ~ctl)
1410                 return -EIO;
1411
1412         *result = ctl;
1413         return 0;
1414 }
1415
1416 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1417 {
1418         u32 vmx_msr_low, vmx_msr_high;
1419         u32 min, opt, min2, opt2;
1420         u32 _pin_based_exec_control = 0;
1421         u32 _cpu_based_exec_control = 0;
1422         u32 _cpu_based_2nd_exec_control = 0;
1423         u32 _vmexit_control = 0;
1424         u32 _vmentry_control = 0;
1425
1426         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1427         opt = PIN_BASED_VIRTUAL_NMIS;
1428         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1429                                 &_pin_based_exec_control) < 0)
1430                 return -EIO;
1431
1432         min = CPU_BASED_HLT_EXITING |
1433 #ifdef CONFIG_X86_64
1434               CPU_BASED_CR8_LOAD_EXITING |
1435               CPU_BASED_CR8_STORE_EXITING |
1436 #endif
1437               CPU_BASED_CR3_LOAD_EXITING |
1438               CPU_BASED_CR3_STORE_EXITING |
1439               CPU_BASED_USE_IO_BITMAPS |
1440               CPU_BASED_MOV_DR_EXITING |
1441               CPU_BASED_USE_TSC_OFFSETING |
1442               CPU_BASED_MWAIT_EXITING |
1443               CPU_BASED_MONITOR_EXITING |
1444               CPU_BASED_INVLPG_EXITING;
1445         opt = CPU_BASED_TPR_SHADOW |
1446               CPU_BASED_USE_MSR_BITMAPS |
1447               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1448         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1449                                 &_cpu_based_exec_control) < 0)
1450                 return -EIO;
1451 #ifdef CONFIG_X86_64
1452         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1453                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1454                                            ~CPU_BASED_CR8_STORE_EXITING;
1455 #endif
1456         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1457                 min2 = 0;
1458                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1459                         SECONDARY_EXEC_WBINVD_EXITING |
1460                         SECONDARY_EXEC_ENABLE_VPID |
1461                         SECONDARY_EXEC_ENABLE_EPT |
1462                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1463                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1464                         SECONDARY_EXEC_RDTSCP;
1465                 if (adjust_vmx_controls(min2, opt2,
1466                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1467                                         &_cpu_based_2nd_exec_control) < 0)
1468                         return -EIO;
1469         }
1470 #ifndef CONFIG_X86_64
1471         if (!(_cpu_based_2nd_exec_control &
1472                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1473                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1474 #endif
1475         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1476                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1477                    enabled */
1478                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1479                                              CPU_BASED_CR3_STORE_EXITING |
1480                                              CPU_BASED_INVLPG_EXITING);
1481                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1482                       vmx_capability.ept, vmx_capability.vpid);
1483         }
1484
1485         min = 0;
1486 #ifdef CONFIG_X86_64
1487         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1488 #endif
1489         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1490         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1491                                 &_vmexit_control) < 0)
1492                 return -EIO;
1493
1494         min = 0;
1495         opt = VM_ENTRY_LOAD_IA32_PAT;
1496         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1497                                 &_vmentry_control) < 0)
1498                 return -EIO;
1499
1500         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1501
1502         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1503         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1504                 return -EIO;
1505
1506 #ifdef CONFIG_X86_64
1507         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1508         if (vmx_msr_high & (1u<<16))
1509                 return -EIO;
1510 #endif
1511
1512         /* Require Write-Back (WB) memory type for VMCS accesses. */
1513         if (((vmx_msr_high >> 18) & 15) != 6)
1514                 return -EIO;
1515
1516         vmcs_conf->size = vmx_msr_high & 0x1fff;
1517         vmcs_conf->order = get_order(vmcs_config.size);
1518         vmcs_conf->revision_id = vmx_msr_low;
1519
1520         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1521         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1522         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1523         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1524         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1525
1526         return 0;
1527 }
1528
1529 static struct vmcs *alloc_vmcs_cpu(int cpu)
1530 {
1531         int node = cpu_to_node(cpu);
1532         struct page *pages;
1533         struct vmcs *vmcs;
1534
1535         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1536         if (!pages)
1537                 return NULL;
1538         vmcs = page_address(pages);
1539         memset(vmcs, 0, vmcs_config.size);
1540         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1541         return vmcs;
1542 }
1543
1544 static struct vmcs *alloc_vmcs(void)
1545 {
1546         return alloc_vmcs_cpu(raw_smp_processor_id());
1547 }
1548
1549 static void free_vmcs(struct vmcs *vmcs)
1550 {
1551         free_pages((unsigned long)vmcs, vmcs_config.order);
1552 }
1553
1554 static void free_kvm_area(void)
1555 {
1556         int cpu;
1557
1558         for_each_possible_cpu(cpu) {
1559                 free_vmcs(per_cpu(vmxarea, cpu));
1560                 per_cpu(vmxarea, cpu) = NULL;
1561         }
1562 }
1563
1564 static __init int alloc_kvm_area(void)
1565 {
1566         int cpu;
1567
1568         for_each_possible_cpu(cpu) {
1569                 struct vmcs *vmcs;
1570
1571                 vmcs = alloc_vmcs_cpu(cpu);
1572                 if (!vmcs) {
1573                         free_kvm_area();
1574                         return -ENOMEM;
1575                 }
1576
1577                 per_cpu(vmxarea, cpu) = vmcs;
1578         }
1579         return 0;
1580 }
1581
1582 static __init int hardware_setup(void)
1583 {
1584         if (setup_vmcs_config(&vmcs_config) < 0)
1585                 return -EIO;
1586
1587         if (boot_cpu_has(X86_FEATURE_NX))
1588                 kvm_enable_efer_bits(EFER_NX);
1589
1590         if (!cpu_has_vmx_vpid())
1591                 enable_vpid = 0;
1592
1593         if (!cpu_has_vmx_ept() ||
1594             !cpu_has_vmx_ept_4levels()) {
1595                 enable_ept = 0;
1596                 enable_unrestricted_guest = 0;
1597         }
1598
1599         if (!cpu_has_vmx_unrestricted_guest())
1600                 enable_unrestricted_guest = 0;
1601
1602         if (!cpu_has_vmx_flexpriority())
1603                 flexpriority_enabled = 0;
1604
1605         if (!cpu_has_vmx_tpr_shadow())
1606                 kvm_x86_ops->update_cr8_intercept = NULL;
1607
1608         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1609                 kvm_disable_largepages();
1610
1611         if (!cpu_has_vmx_ple())
1612                 ple_gap = 0;
1613
1614         return alloc_kvm_area();
1615 }
1616
1617 static __exit void hardware_unsetup(void)
1618 {
1619         free_kvm_area();
1620 }
1621
1622 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1623 {
1624         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1625
1626         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1627                 vmcs_write16(sf->selector, save->selector);
1628                 vmcs_writel(sf->base, save->base);
1629                 vmcs_write32(sf->limit, save->limit);
1630                 vmcs_write32(sf->ar_bytes, save->ar);
1631         } else {
1632                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1633                         << AR_DPL_SHIFT;
1634                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1635         }
1636 }
1637
1638 static void enter_pmode(struct kvm_vcpu *vcpu)
1639 {
1640         unsigned long flags;
1641         struct vcpu_vmx *vmx = to_vmx(vcpu);
1642
1643         vmx->emulation_required = 1;
1644         vmx->rmode.vm86_active = 0;
1645
1646         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1647         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1648         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1649
1650         flags = vmcs_readl(GUEST_RFLAGS);
1651         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1652         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1653         vmcs_writel(GUEST_RFLAGS, flags);
1654
1655         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1656                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1657
1658         update_exception_bitmap(vcpu);
1659
1660         if (emulate_invalid_guest_state)
1661                 return;
1662
1663         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1664         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1665         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1666         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1667
1668         vmcs_write16(GUEST_SS_SELECTOR, 0);
1669         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1670
1671         vmcs_write16(GUEST_CS_SELECTOR,
1672                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1673         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1674 }
1675
1676 static gva_t rmode_tss_base(struct kvm *kvm)
1677 {
1678         if (!kvm->arch.tss_addr) {
1679                 struct kvm_memslots *slots;
1680                 gfn_t base_gfn;
1681
1682                 slots = kvm_memslots(kvm);
1683                 base_gfn = slots->memslots[0].base_gfn +
1684                                  kvm->memslots->memslots[0].npages - 3;
1685                 return base_gfn << PAGE_SHIFT;
1686         }
1687         return kvm->arch.tss_addr;
1688 }
1689
1690 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1691 {
1692         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1693
1694         save->selector = vmcs_read16(sf->selector);
1695         save->base = vmcs_readl(sf->base);
1696         save->limit = vmcs_read32(sf->limit);
1697         save->ar = vmcs_read32(sf->ar_bytes);
1698         vmcs_write16(sf->selector, save->base >> 4);
1699         vmcs_write32(sf->base, save->base & 0xfffff);
1700         vmcs_write32(sf->limit, 0xffff);
1701         vmcs_write32(sf->ar_bytes, 0xf3);
1702 }
1703
1704 static void enter_rmode(struct kvm_vcpu *vcpu)
1705 {
1706         unsigned long flags;
1707         struct vcpu_vmx *vmx = to_vmx(vcpu);
1708
1709         if (enable_unrestricted_guest)
1710                 return;
1711
1712         vmx->emulation_required = 1;
1713         vmx->rmode.vm86_active = 1;
1714
1715         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1716         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1717
1718         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1719         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1720
1721         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1722         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1723
1724         flags = vmcs_readl(GUEST_RFLAGS);
1725         vmx->rmode.save_rflags = flags;
1726
1727         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1728
1729         vmcs_writel(GUEST_RFLAGS, flags);
1730         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1731         update_exception_bitmap(vcpu);
1732
1733         if (emulate_invalid_guest_state)
1734                 goto continue_rmode;
1735
1736         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1737         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1738         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1739
1740         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1741         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1742         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1743                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1744         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1745
1746         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1747         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1748         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1749         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1750
1751 continue_rmode:
1752         kvm_mmu_reset_context(vcpu);
1753         init_rmode(vcpu->kvm);
1754 }
1755
1756 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1757 {
1758         struct vcpu_vmx *vmx = to_vmx(vcpu);
1759         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1760
1761         if (!msr)
1762                 return;
1763
1764         /*
1765          * Force kernel_gs_base reloading before EFER changes, as control
1766          * of this msr depends on is_long_mode().
1767          */
1768         vmx_load_host_state(to_vmx(vcpu));
1769         vcpu->arch.efer = efer;
1770         if (efer & EFER_LMA) {
1771                 vmcs_write32(VM_ENTRY_CONTROLS,
1772                              vmcs_read32(VM_ENTRY_CONTROLS) |
1773                              VM_ENTRY_IA32E_MODE);
1774                 msr->data = efer;
1775         } else {
1776                 vmcs_write32(VM_ENTRY_CONTROLS,
1777                              vmcs_read32(VM_ENTRY_CONTROLS) &
1778                              ~VM_ENTRY_IA32E_MODE);
1779
1780                 msr->data = efer & ~EFER_LME;
1781         }
1782         setup_msrs(vmx);
1783 }
1784
1785 #ifdef CONFIG_X86_64
1786
1787 static void enter_lmode(struct kvm_vcpu *vcpu)
1788 {
1789         u32 guest_tr_ar;
1790
1791         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1792         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1793                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1794                        __func__);
1795                 vmcs_write32(GUEST_TR_AR_BYTES,
1796                              (guest_tr_ar & ~AR_TYPE_MASK)
1797                              | AR_TYPE_BUSY_64_TSS);
1798         }
1799         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1800 }
1801
1802 static void exit_lmode(struct kvm_vcpu *vcpu)
1803 {
1804         vmcs_write32(VM_ENTRY_CONTROLS,
1805                      vmcs_read32(VM_ENTRY_CONTROLS)
1806                      & ~VM_ENTRY_IA32E_MODE);
1807         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1808 }
1809
1810 #endif
1811
1812 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1813 {
1814         vpid_sync_context(to_vmx(vcpu));
1815         if (enable_ept) {
1816                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1817                         return;
1818                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1819         }
1820 }
1821
1822 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1823 {
1824         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1825
1826         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1827         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1828 }
1829
1830 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1831 {
1832         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1833
1834         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1835         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1836 }
1837
1838 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1839 {
1840         if (!test_bit(VCPU_EXREG_PDPTR,
1841                       (unsigned long *)&vcpu->arch.regs_dirty))
1842                 return;
1843
1844         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1845                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1846                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1847                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1848                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1849         }
1850 }
1851
1852 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1853 {
1854         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1855                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1856                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1857                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1858                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1859         }
1860
1861         __set_bit(VCPU_EXREG_PDPTR,
1862                   (unsigned long *)&vcpu->arch.regs_avail);
1863         __set_bit(VCPU_EXREG_PDPTR,
1864                   (unsigned long *)&vcpu->arch.regs_dirty);
1865 }
1866
1867 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1868
1869 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1870                                         unsigned long cr0,
1871                                         struct kvm_vcpu *vcpu)
1872 {
1873         if (!(cr0 & X86_CR0_PG)) {
1874                 /* From paging/starting to nonpaging */
1875                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1876                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1877                              (CPU_BASED_CR3_LOAD_EXITING |
1878                               CPU_BASED_CR3_STORE_EXITING));
1879                 vcpu->arch.cr0 = cr0;
1880                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1881         } else if (!is_paging(vcpu)) {
1882                 /* From nonpaging to paging */
1883                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1884                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1885                              ~(CPU_BASED_CR3_LOAD_EXITING |
1886                                CPU_BASED_CR3_STORE_EXITING));
1887                 vcpu->arch.cr0 = cr0;
1888                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1889         }
1890
1891         if (!(cr0 & X86_CR0_WP))
1892                 *hw_cr0 &= ~X86_CR0_WP;
1893 }
1894
1895 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1896 {
1897         struct vcpu_vmx *vmx = to_vmx(vcpu);
1898         unsigned long hw_cr0;
1899
1900         if (enable_unrestricted_guest)
1901                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1902                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1903         else
1904                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1905
1906         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1907                 enter_pmode(vcpu);
1908
1909         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1910                 enter_rmode(vcpu);
1911
1912 #ifdef CONFIG_X86_64
1913         if (vcpu->arch.efer & EFER_LME) {
1914                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1915                         enter_lmode(vcpu);
1916                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1917                         exit_lmode(vcpu);
1918         }
1919 #endif
1920
1921         if (enable_ept)
1922                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1923
1924         if (!vcpu->fpu_active)
1925                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1926
1927         vmcs_writel(CR0_READ_SHADOW, cr0);
1928         vmcs_writel(GUEST_CR0, hw_cr0);
1929         vcpu->arch.cr0 = cr0;
1930 }
1931
1932 static u64 construct_eptp(unsigned long root_hpa)
1933 {
1934         u64 eptp;
1935
1936         /* TODO write the value reading from MSR */
1937         eptp = VMX_EPT_DEFAULT_MT |
1938                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1939         eptp |= (root_hpa & PAGE_MASK);
1940
1941         return eptp;
1942 }
1943
1944 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1945 {
1946         unsigned long guest_cr3;
1947         u64 eptp;
1948
1949         guest_cr3 = cr3;
1950         if (enable_ept) {
1951                 eptp = construct_eptp(cr3);
1952                 vmcs_write64(EPT_POINTER, eptp);
1953                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1954                         vcpu->kvm->arch.ept_identity_map_addr;
1955                 ept_load_pdptrs(vcpu);
1956         }
1957
1958         vmx_flush_tlb(vcpu);
1959         vmcs_writel(GUEST_CR3, guest_cr3);
1960 }
1961
1962 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1963 {
1964         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1965                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1966
1967         vcpu->arch.cr4 = cr4;
1968         if (enable_ept) {
1969                 if (!is_paging(vcpu)) {
1970                         hw_cr4 &= ~X86_CR4_PAE;
1971                         hw_cr4 |= X86_CR4_PSE;
1972                 } else if (!(cr4 & X86_CR4_PAE)) {
1973                         hw_cr4 &= ~X86_CR4_PAE;
1974                 }
1975         }
1976
1977         vmcs_writel(CR4_READ_SHADOW, cr4);
1978         vmcs_writel(GUEST_CR4, hw_cr4);
1979 }
1980
1981 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1982 {
1983         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1984
1985         return vmcs_readl(sf->base);
1986 }
1987
1988 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1989                             struct kvm_segment *var, int seg)
1990 {
1991         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1992         u32 ar;
1993
1994         var->base = vmcs_readl(sf->base);
1995         var->limit = vmcs_read32(sf->limit);
1996         var->selector = vmcs_read16(sf->selector);
1997         ar = vmcs_read32(sf->ar_bytes);
1998         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1999                 ar = 0;
2000         var->type = ar & 15;
2001         var->s = (ar >> 4) & 1;
2002         var->dpl = (ar >> 5) & 3;
2003         var->present = (ar >> 7) & 1;
2004         var->avl = (ar >> 12) & 1;
2005         var->l = (ar >> 13) & 1;
2006         var->db = (ar >> 14) & 1;
2007         var->g = (ar >> 15) & 1;
2008         var->unusable = (ar >> 16) & 1;
2009 }
2010
2011 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2012 {
2013         if (!is_protmode(vcpu))
2014                 return 0;
2015
2016         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2017                 return 3;
2018
2019         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2020 }
2021
2022 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2023 {
2024         u32 ar;
2025
2026         if (var->unusable)
2027                 ar = 1 << 16;
2028         else {
2029                 ar = var->type & 15;
2030                 ar |= (var->s & 1) << 4;
2031                 ar |= (var->dpl & 3) << 5;
2032                 ar |= (var->present & 1) << 7;
2033                 ar |= (var->avl & 1) << 12;
2034                 ar |= (var->l & 1) << 13;
2035                 ar |= (var->db & 1) << 14;
2036                 ar |= (var->g & 1) << 15;
2037         }
2038         if (ar == 0) /* a 0 value means unusable */
2039                 ar = AR_UNUSABLE_MASK;
2040
2041         return ar;
2042 }
2043
2044 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2045                             struct kvm_segment *var, int seg)
2046 {
2047         struct vcpu_vmx *vmx = to_vmx(vcpu);
2048         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2049         u32 ar;
2050
2051         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2052                 vmx->rmode.tr.selector = var->selector;
2053                 vmx->rmode.tr.base = var->base;
2054                 vmx->rmode.tr.limit = var->limit;
2055                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2056                 return;
2057         }
2058         vmcs_writel(sf->base, var->base);
2059         vmcs_write32(sf->limit, var->limit);
2060         vmcs_write16(sf->selector, var->selector);
2061         if (vmx->rmode.vm86_active && var->s) {
2062                 /*
2063                  * Hack real-mode segments into vm86 compatibility.
2064                  */
2065                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2066                         vmcs_writel(sf->base, 0xf0000);
2067                 ar = 0xf3;
2068         } else
2069                 ar = vmx_segment_access_rights(var);
2070
2071         /*
2072          *   Fix the "Accessed" bit in AR field of segment registers for older
2073          * qemu binaries.
2074          *   IA32 arch specifies that at the time of processor reset the
2075          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2076          * is setting it to 0 in the usedland code. This causes invalid guest
2077          * state vmexit when "unrestricted guest" mode is turned on.
2078          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2079          * tree. Newer qemu binaries with that qemu fix would not need this
2080          * kvm hack.
2081          */
2082         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2083                 ar |= 0x1; /* Accessed */
2084
2085         vmcs_write32(sf->ar_bytes, ar);
2086 }
2087
2088 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2089 {
2090         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2091
2092         *db = (ar >> 14) & 1;
2093         *l = (ar >> 13) & 1;
2094 }
2095
2096 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2097 {
2098         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2099         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2100 }
2101
2102 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2103 {
2104         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2105         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2106 }
2107
2108 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2109 {
2110         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2111         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2112 }
2113
2114 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2115 {
2116         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2117         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2118 }
2119
2120 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2121 {
2122         struct kvm_segment var;
2123         u32 ar;
2124
2125         vmx_get_segment(vcpu, &var, seg);
2126         ar = vmx_segment_access_rights(&var);
2127
2128         if (var.base != (var.selector << 4))
2129                 return false;
2130         if (var.limit != 0xffff)
2131                 return false;
2132         if (ar != 0xf3)
2133                 return false;
2134
2135         return true;
2136 }
2137
2138 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2139 {
2140         struct kvm_segment cs;
2141         unsigned int cs_rpl;
2142
2143         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2144         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2145
2146         if (cs.unusable)
2147                 return false;
2148         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2149                 return false;
2150         if (!cs.s)
2151                 return false;
2152         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2153                 if (cs.dpl > cs_rpl)
2154                         return false;
2155         } else {
2156                 if (cs.dpl != cs_rpl)
2157                         return false;
2158         }
2159         if (!cs.present)
2160                 return false;
2161
2162         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2163         return true;
2164 }
2165
2166 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2167 {
2168         struct kvm_segment ss;
2169         unsigned int ss_rpl;
2170
2171         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2172         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2173
2174         if (ss.unusable)
2175                 return true;
2176         if (ss.type != 3 && ss.type != 7)
2177                 return false;
2178         if (!ss.s)
2179                 return false;
2180         if (ss.dpl != ss_rpl) /* DPL != RPL */
2181                 return false;
2182         if (!ss.present)
2183                 return false;
2184
2185         return true;
2186 }
2187
2188 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2189 {
2190         struct kvm_segment var;
2191         unsigned int rpl;
2192
2193         vmx_get_segment(vcpu, &var, seg);
2194         rpl = var.selector & SELECTOR_RPL_MASK;
2195
2196         if (var.unusable)
2197                 return true;
2198         if (!var.s)
2199                 return false;
2200         if (!var.present)
2201                 return false;
2202         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2203                 if (var.dpl < rpl) /* DPL < RPL */
2204                         return false;
2205         }
2206
2207         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2208          * rights flags
2209          */
2210         return true;
2211 }
2212
2213 static bool tr_valid(struct kvm_vcpu *vcpu)
2214 {
2215         struct kvm_segment tr;
2216
2217         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2218
2219         if (tr.unusable)
2220                 return false;
2221         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2222                 return false;
2223         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2224                 return false;
2225         if (!tr.present)
2226                 return false;
2227
2228         return true;
2229 }
2230
2231 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2232 {
2233         struct kvm_segment ldtr;
2234
2235         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2236
2237         if (ldtr.unusable)
2238                 return true;
2239         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2240                 return false;
2241         if (ldtr.type != 2)
2242                 return false;
2243         if (!ldtr.present)
2244                 return false;
2245
2246         return true;
2247 }
2248
2249 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2250 {
2251         struct kvm_segment cs, ss;
2252
2253         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2254         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2255
2256         return ((cs.selector & SELECTOR_RPL_MASK) ==
2257                  (ss.selector & SELECTOR_RPL_MASK));
2258 }
2259
2260 /*
2261  * Check if guest state is valid. Returns true if valid, false if
2262  * not.
2263  * We assume that registers are always usable
2264  */
2265 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2266 {
2267         /* real mode guest state checks */
2268         if (!is_protmode(vcpu)) {
2269                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2270                         return false;
2271                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2272                         return false;
2273                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2274                         return false;
2275                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2276                         return false;
2277                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2278                         return false;
2279                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2280                         return false;
2281         } else {
2282         /* protected mode guest state checks */
2283                 if (!cs_ss_rpl_check(vcpu))
2284                         return false;
2285                 if (!code_segment_valid(vcpu))
2286                         return false;
2287                 if (!stack_segment_valid(vcpu))
2288                         return false;
2289                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2290                         return false;
2291                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2292                         return false;
2293                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2294                         return false;
2295                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2296                         return false;
2297                 if (!tr_valid(vcpu))
2298                         return false;
2299                 if (!ldtr_valid(vcpu))
2300                         return false;
2301         }
2302         /* TODO:
2303          * - Add checks on RIP
2304          * - Add checks on RFLAGS
2305          */
2306
2307         return true;
2308 }
2309
2310 static int init_rmode_tss(struct kvm *kvm)
2311 {
2312         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2313         u16 data = 0;
2314         int ret = 0;
2315         int r;
2316
2317         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2318         if (r < 0)
2319                 goto out;
2320         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2321         r = kvm_write_guest_page(kvm, fn++, &data,
2322                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2323         if (r < 0)
2324                 goto out;
2325         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2326         if (r < 0)
2327                 goto out;
2328         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2329         if (r < 0)
2330                 goto out;
2331         data = ~0;
2332         r = kvm_write_guest_page(kvm, fn, &data,
2333                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2334                                  sizeof(u8));
2335         if (r < 0)
2336                 goto out;
2337
2338         ret = 1;
2339 out:
2340         return ret;
2341 }
2342
2343 static int init_rmode_identity_map(struct kvm *kvm)
2344 {
2345         int i, r, ret;
2346         pfn_t identity_map_pfn;
2347         u32 tmp;
2348
2349         if (!enable_ept)
2350                 return 1;
2351         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2352                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2353                         "haven't been allocated!\n");
2354                 return 0;
2355         }
2356         if (likely(kvm->arch.ept_identity_pagetable_done))
2357                 return 1;
2358         ret = 0;
2359         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2360         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2361         if (r < 0)
2362                 goto out;
2363         /* Set up identity-mapping pagetable for EPT in real mode */
2364         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2365                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2366                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2367                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2368                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2369                 if (r < 0)
2370                         goto out;
2371         }
2372         kvm->arch.ept_identity_pagetable_done = true;
2373         ret = 1;
2374 out:
2375         return ret;
2376 }
2377
2378 static void seg_setup(int seg)
2379 {
2380         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2381         unsigned int ar;
2382
2383         vmcs_write16(sf->selector, 0);
2384         vmcs_writel(sf->base, 0);
2385         vmcs_write32(sf->limit, 0xffff);
2386         if (enable_unrestricted_guest) {
2387                 ar = 0x93;
2388                 if (seg == VCPU_SREG_CS)
2389                         ar |= 0x08; /* code segment */
2390         } else
2391                 ar = 0xf3;
2392
2393         vmcs_write32(sf->ar_bytes, ar);
2394 }
2395
2396 static int alloc_apic_access_page(struct kvm *kvm)
2397 {
2398         struct kvm_userspace_memory_region kvm_userspace_mem;
2399         int r = 0;
2400
2401         mutex_lock(&kvm->slots_lock);
2402         if (kvm->arch.apic_access_page)
2403                 goto out;
2404         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2405         kvm_userspace_mem.flags = 0;
2406         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2407         kvm_userspace_mem.memory_size = PAGE_SIZE;
2408         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2409         if (r)
2410                 goto out;
2411
2412         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2413 out:
2414         mutex_unlock(&kvm->slots_lock);
2415         return r;
2416 }
2417
2418 static int alloc_identity_pagetable(struct kvm *kvm)
2419 {
2420         struct kvm_userspace_memory_region kvm_userspace_mem;
2421         int r = 0;
2422
2423         mutex_lock(&kvm->slots_lock);
2424         if (kvm->arch.ept_identity_pagetable)
2425                 goto out;
2426         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2427         kvm_userspace_mem.flags = 0;
2428         kvm_userspace_mem.guest_phys_addr =
2429                 kvm->arch.ept_identity_map_addr;
2430         kvm_userspace_mem.memory_size = PAGE_SIZE;
2431         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2432         if (r)
2433                 goto out;
2434
2435         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2436                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2437 out:
2438         mutex_unlock(&kvm->slots_lock);
2439         return r;
2440 }
2441
2442 static void allocate_vpid(struct vcpu_vmx *vmx)
2443 {
2444         int vpid;
2445
2446         vmx->vpid = 0;
2447         if (!enable_vpid)
2448                 return;
2449         spin_lock(&vmx_vpid_lock);
2450         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2451         if (vpid < VMX_NR_VPIDS) {
2452                 vmx->vpid = vpid;
2453                 __set_bit(vpid, vmx_vpid_bitmap);
2454         }
2455         spin_unlock(&vmx_vpid_lock);
2456 }
2457
2458 static void free_vpid(struct vcpu_vmx *vmx)
2459 {
2460         if (!enable_vpid)
2461                 return;
2462         spin_lock(&vmx_vpid_lock);
2463         if (vmx->vpid != 0)
2464                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2465         spin_unlock(&vmx_vpid_lock);
2466 }
2467
2468 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2469 {
2470         int f = sizeof(unsigned long);
2471
2472         if (!cpu_has_vmx_msr_bitmap())
2473                 return;
2474
2475         /*
2476          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2477          * have the write-low and read-high bitmap offsets the wrong way round.
2478          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2479          */
2480         if (msr <= 0x1fff) {
2481                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2482                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2483         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2484                 msr &= 0x1fff;
2485                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2486                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2487         }
2488 }
2489
2490 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2491 {
2492         if (!longmode_only)
2493                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2494         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2495 }
2496
2497 /*
2498  * Sets up the vmcs for emulated real mode.
2499  */
2500 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2501 {
2502         u32 host_sysenter_cs, msr_low, msr_high;
2503         u32 junk;
2504         u64 host_pat;
2505         unsigned long a;
2506         struct desc_ptr dt;
2507         int i;
2508         unsigned long kvm_vmx_return;
2509         u32 exec_control;
2510
2511         /* I/O */
2512         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2513         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2514
2515         if (cpu_has_vmx_msr_bitmap())
2516                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2517
2518         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2519
2520         /* Control */
2521         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2522                 vmcs_config.pin_based_exec_ctrl);
2523
2524         exec_control = vmcs_config.cpu_based_exec_ctrl;
2525         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2526                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2527 #ifdef CONFIG_X86_64
2528                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2529                                 CPU_BASED_CR8_LOAD_EXITING;
2530 #endif
2531         }
2532         if (!enable_ept)
2533                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2534                                 CPU_BASED_CR3_LOAD_EXITING  |
2535                                 CPU_BASED_INVLPG_EXITING;
2536         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2537
2538         if (cpu_has_secondary_exec_ctrls()) {
2539                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2540                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2541                         exec_control &=
2542                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2543                 if (vmx->vpid == 0)
2544                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2545                 if (!enable_ept) {
2546                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2547                         enable_unrestricted_guest = 0;
2548                 }
2549                 if (!enable_unrestricted_guest)
2550                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2551                 if (!ple_gap)
2552                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2553                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2554         }
2555
2556         if (ple_gap) {
2557                 vmcs_write32(PLE_GAP, ple_gap);
2558                 vmcs_write32(PLE_WINDOW, ple_window);
2559         }
2560
2561         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2562         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2563         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2564
2565         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2566         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2567         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2568
2569         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2570         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2571         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2572         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
2573         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
2574         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2575 #ifdef CONFIG_X86_64
2576         rdmsrl(MSR_FS_BASE, a);
2577         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2578         rdmsrl(MSR_GS_BASE, a);
2579         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2580 #else
2581         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2582         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2583 #endif
2584
2585         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2586
2587         native_store_idt(&dt);
2588         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2589
2590         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2591         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2592         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2593         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2594         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2595         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2596         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2597
2598         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2599         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2600         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2601         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2602         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2603         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2604
2605         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2606                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2607                 host_pat = msr_low | ((u64) msr_high << 32);
2608                 vmcs_write64(HOST_IA32_PAT, host_pat);
2609         }
2610         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2611                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2612                 host_pat = msr_low | ((u64) msr_high << 32);
2613                 /* Write the default value follow host pat */
2614                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2615                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2616                 vmx->vcpu.arch.pat = host_pat;
2617         }
2618
2619         for (i = 0; i < NR_VMX_MSR; ++i) {
2620                 u32 index = vmx_msr_index[i];
2621                 u32 data_low, data_high;
2622                 int j = vmx->nmsrs;
2623
2624                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2625                         continue;
2626                 if (wrmsr_safe(index, data_low, data_high) < 0)
2627                         continue;
2628                 vmx->guest_msrs[j].index = i;
2629                 vmx->guest_msrs[j].data = 0;
2630                 vmx->guest_msrs[j].mask = -1ull;
2631                 ++vmx->nmsrs;
2632         }
2633
2634         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2635
2636         /* 22.2.1, 20.8.1 */
2637         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2638
2639         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2640         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2641         if (enable_ept)
2642                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2643         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2644
2645         kvm_write_tsc(&vmx->vcpu, 0);
2646
2647         return 0;
2648 }
2649
2650 static int init_rmode(struct kvm *kvm)
2651 {
2652         int idx, ret = 0;
2653
2654         idx = srcu_read_lock(&kvm->srcu);
2655         if (!init_rmode_tss(kvm))
2656                 goto exit;
2657         if (!init_rmode_identity_map(kvm))
2658                 goto exit;
2659
2660         ret = 1;
2661 exit:
2662         srcu_read_unlock(&kvm->srcu, idx);
2663         return ret;
2664 }
2665
2666 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2667 {
2668         struct vcpu_vmx *vmx = to_vmx(vcpu);
2669         u64 msr;
2670         int ret;
2671
2672         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2673         if (!init_rmode(vmx->vcpu.kvm)) {
2674                 ret = -ENOMEM;
2675                 goto out;
2676         }
2677
2678         vmx->rmode.vm86_active = 0;
2679
2680         vmx->soft_vnmi_blocked = 0;
2681
2682         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2683         kvm_set_cr8(&vmx->vcpu, 0);
2684         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2685         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2686                 msr |= MSR_IA32_APICBASE_BSP;
2687         kvm_set_apic_base(&vmx->vcpu, msr);
2688
2689         ret = fx_init(&vmx->vcpu);
2690         if (ret != 0)
2691                 goto out;
2692
2693         seg_setup(VCPU_SREG_CS);
2694         /*
2695          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2696          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2697          */
2698         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2699                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2700                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2701         } else {
2702                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2703                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2704         }
2705
2706         seg_setup(VCPU_SREG_DS);
2707         seg_setup(VCPU_SREG_ES);
2708         seg_setup(VCPU_SREG_FS);
2709         seg_setup(VCPU_SREG_GS);
2710         seg_setup(VCPU_SREG_SS);
2711
2712         vmcs_write16(GUEST_TR_SELECTOR, 0);
2713         vmcs_writel(GUEST_TR_BASE, 0);
2714         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2715         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2716
2717         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2718         vmcs_writel(GUEST_LDTR_BASE, 0);
2719         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2720         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2721
2722         vmcs_write32(GUEST_SYSENTER_CS, 0);
2723         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2724         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2725
2726         vmcs_writel(GUEST_RFLAGS, 0x02);
2727         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2728                 kvm_rip_write(vcpu, 0xfff0);
2729         else
2730                 kvm_rip_write(vcpu, 0);
2731         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2732
2733         vmcs_writel(GUEST_DR7, 0x400);
2734
2735         vmcs_writel(GUEST_GDTR_BASE, 0);
2736         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2737
2738         vmcs_writel(GUEST_IDTR_BASE, 0);
2739         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2740
2741         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2742         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2743         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2744
2745         /* Special registers */
2746         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2747
2748         setup_msrs(vmx);
2749
2750         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2751
2752         if (cpu_has_vmx_tpr_shadow()) {
2753                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2754                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2755                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2756                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2757                 vmcs_write32(TPR_THRESHOLD, 0);
2758         }
2759
2760         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2761                 vmcs_write64(APIC_ACCESS_ADDR,
2762                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2763
2764         if (vmx->vpid != 0)
2765                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2766
2767         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2768         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2769         vmx_set_cr4(&vmx->vcpu, 0);
2770         vmx_set_efer(&vmx->vcpu, 0);
2771         vmx_fpu_activate(&vmx->vcpu);
2772         update_exception_bitmap(&vmx->vcpu);
2773
2774         vpid_sync_context(vmx);
2775
2776         ret = 0;
2777
2778         /* HACK: Don't enable emulation on guest boot/reset */
2779         vmx->emulation_required = 0;
2780
2781 out:
2782         return ret;
2783 }
2784
2785 static void enable_irq_window(struct kvm_vcpu *vcpu)
2786 {
2787         u32 cpu_based_vm_exec_control;
2788
2789         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2790         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2791         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2792 }
2793
2794 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2795 {
2796         u32 cpu_based_vm_exec_control;
2797
2798         if (!cpu_has_virtual_nmis()) {
2799                 enable_irq_window(vcpu);
2800                 return;
2801         }
2802
2803         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2804         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2805         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2806 }
2807
2808 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2809 {
2810         struct vcpu_vmx *vmx = to_vmx(vcpu);
2811         uint32_t intr;
2812         int irq = vcpu->arch.interrupt.nr;
2813
2814         trace_kvm_inj_virq(irq);
2815
2816         ++vcpu->stat.irq_injections;
2817         if (vmx->rmode.vm86_active) {
2818                 vmx->rmode.irq.pending = true;
2819                 vmx->rmode.irq.vector = irq;
2820                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2821                 if (vcpu->arch.interrupt.soft)
2822                         vmx->rmode.irq.rip +=
2823                                 vmx->vcpu.arch.event_exit_inst_len;
2824                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2825                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2826                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2827                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2828                 return;
2829         }
2830         intr = irq | INTR_INFO_VALID_MASK;
2831         if (vcpu->arch.interrupt.soft) {
2832                 intr |= INTR_TYPE_SOFT_INTR;
2833                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2834                              vmx->vcpu.arch.event_exit_inst_len);
2835         } else
2836                 intr |= INTR_TYPE_EXT_INTR;
2837         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2838 }
2839
2840 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2841 {
2842         struct vcpu_vmx *vmx = to_vmx(vcpu);
2843
2844         if (!cpu_has_virtual_nmis()) {
2845                 /*
2846                  * Tracking the NMI-blocked state in software is built upon
2847                  * finding the next open IRQ window. This, in turn, depends on
2848                  * well-behaving guests: They have to keep IRQs disabled at
2849                  * least as long as the NMI handler runs. Otherwise we may
2850                  * cause NMI nesting, maybe breaking the guest. But as this is
2851                  * highly unlikely, we can live with the residual risk.
2852                  */
2853                 vmx->soft_vnmi_blocked = 1;
2854                 vmx->vnmi_blocked_time = 0;
2855         }
2856
2857         ++vcpu->stat.nmi_injections;
2858         if (vmx->rmode.vm86_active) {
2859                 vmx->rmode.irq.pending = true;
2860                 vmx->rmode.irq.vector = NMI_VECTOR;
2861                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2862                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2863                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2864                              INTR_INFO_VALID_MASK);
2865                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2866                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2867                 return;
2868         }
2869         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2870                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2871 }
2872
2873 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2874 {
2875         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2876                 return 0;
2877
2878         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2879                         (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2880 }
2881
2882 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2883 {
2884         if (!cpu_has_virtual_nmis())
2885                 return to_vmx(vcpu)->soft_vnmi_blocked;
2886         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2887 }
2888
2889 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2890 {
2891         struct vcpu_vmx *vmx = to_vmx(vcpu);
2892
2893         if (!cpu_has_virtual_nmis()) {
2894                 if (vmx->soft_vnmi_blocked != masked) {
2895                         vmx->soft_vnmi_blocked = masked;
2896                         vmx->vnmi_blocked_time = 0;
2897                 }
2898         } else {
2899                 if (masked)
2900                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2901                                       GUEST_INTR_STATE_NMI);
2902                 else
2903                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2904                                         GUEST_INTR_STATE_NMI);
2905         }
2906 }
2907
2908 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2909 {
2910         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2911                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2912                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2913 }
2914
2915 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2916 {
2917         int ret;
2918         struct kvm_userspace_memory_region tss_mem = {
2919                 .slot = TSS_PRIVATE_MEMSLOT,
2920                 .guest_phys_addr = addr,
2921                 .memory_size = PAGE_SIZE * 3,
2922                 .flags = 0,
2923         };
2924
2925         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2926         if (ret)
2927                 return ret;
2928         kvm->arch.tss_addr = addr;
2929         return 0;
2930 }
2931
2932 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2933                                   int vec, u32 err_code)
2934 {
2935         /*
2936          * Instruction with address size override prefix opcode 0x67
2937          * Cause the #SS fault with 0 error code in VM86 mode.
2938          */
2939         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2940                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2941                         return 1;
2942         /*
2943          * Forward all other exceptions that are valid in real mode.
2944          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2945          *        the required debugging infrastructure rework.
2946          */
2947         switch (vec) {
2948         case DB_VECTOR:
2949                 if (vcpu->guest_debug &
2950                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2951                         return 0;
2952                 kvm_queue_exception(vcpu, vec);
2953                 return 1;
2954         case BP_VECTOR:
2955                 /*
2956                  * Update instruction length as we may reinject the exception
2957                  * from user space while in guest debugging mode.
2958                  */
2959                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2960                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2961                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2962                         return 0;
2963                 /* fall through */
2964         case DE_VECTOR:
2965         case OF_VECTOR:
2966         case BR_VECTOR:
2967         case UD_VECTOR:
2968         case DF_VECTOR:
2969         case SS_VECTOR:
2970         case GP_VECTOR:
2971         case MF_VECTOR:
2972                 kvm_queue_exception(vcpu, vec);
2973                 return 1;
2974         }
2975         return 0;
2976 }
2977
2978 /*
2979  * Trigger machine check on the host. We assume all the MSRs are already set up
2980  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2981  * We pass a fake environment to the machine check handler because we want
2982  * the guest to be always treated like user space, no matter what context
2983  * it used internally.
2984  */
2985 static void kvm_machine_check(void)
2986 {
2987 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2988         struct pt_regs regs = {
2989                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2990                 .flags = X86_EFLAGS_IF,
2991         };
2992
2993         do_machine_check(&regs, 0);
2994 #endif
2995 }
2996
2997 static int handle_machine_check(struct kvm_vcpu *vcpu)
2998 {
2999         /* already handled by vcpu_run */
3000         return 1;
3001 }
3002
3003 static int handle_exception(struct kvm_vcpu *vcpu)
3004 {
3005         struct vcpu_vmx *vmx = to_vmx(vcpu);
3006         struct kvm_run *kvm_run = vcpu->run;
3007         u32 intr_info, ex_no, error_code;
3008         unsigned long cr2, rip, dr6;
3009         u32 vect_info;
3010         enum emulation_result er;
3011
3012         vect_info = vmx->idt_vectoring_info;
3013         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3014
3015         if (is_machine_check(intr_info))
3016                 return handle_machine_check(vcpu);
3017
3018         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3019             !is_page_fault(intr_info)) {
3020                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3021                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3022                 vcpu->run->internal.ndata = 2;
3023                 vcpu->run->internal.data[0] = vect_info;
3024                 vcpu->run->internal.data[1] = intr_info;
3025                 return 0;
3026         }
3027
3028         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3029                 return 1;  /* already handled by vmx_vcpu_run() */
3030
3031         if (is_no_device(intr_info)) {
3032                 vmx_fpu_activate(vcpu);
3033                 return 1;
3034         }
3035
3036         if (is_invalid_opcode(intr_info)) {
3037                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3038                 if (er != EMULATE_DONE)
3039                         kvm_queue_exception(vcpu, UD_VECTOR);
3040                 return 1;
3041         }
3042
3043         error_code = 0;
3044         rip = kvm_rip_read(vcpu);
3045         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3046                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3047         if (is_page_fault(intr_info)) {
3048                 /* EPT won't cause page fault directly */
3049                 if (enable_ept)
3050                         BUG();
3051                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3052                 trace_kvm_page_fault(cr2, error_code);
3053
3054                 if (kvm_event_needs_reinjection(vcpu))
3055                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3056                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3057         }
3058
3059         if (vmx->rmode.vm86_active &&
3060             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3061                                                                 error_code)) {
3062                 if (vcpu->arch.halt_request) {
3063                         vcpu->arch.halt_request = 0;
3064                         return kvm_emulate_halt(vcpu);
3065                 }
3066                 return 1;
3067         }
3068
3069         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3070         switch (ex_no) {
3071         case DB_VECTOR:
3072                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3073                 if (!(vcpu->guest_debug &
3074                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3075                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3076                         kvm_queue_exception(vcpu, DB_VECTOR);
3077                         return 1;
3078                 }
3079                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3080                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3081                 /* fall through */
3082         case BP_VECTOR:
3083                 /*
3084                  * Update instruction length as we may reinject #BP from
3085                  * user space while in guest debugging mode. Reading it for
3086                  * #DB as well causes no harm, it is not used in that case.
3087                  */
3088                 vmx->vcpu.arch.event_exit_inst_len =
3089                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3090                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3091                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3092                 kvm_run->debug.arch.exception = ex_no;
3093                 break;
3094         default:
3095                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3096                 kvm_run->ex.exception = ex_no;
3097                 kvm_run->ex.error_code = error_code;
3098                 break;
3099         }
3100         return 0;
3101 }
3102
3103 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3104 {
3105         ++vcpu->stat.irq_exits;
3106         return 1;
3107 }
3108
3109 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3110 {
3111         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3112         return 0;
3113 }
3114
3115 static int handle_io(struct kvm_vcpu *vcpu)
3116 {
3117         unsigned long exit_qualification;
3118         int size, in, string;
3119         unsigned port;
3120
3121         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3122         string = (exit_qualification & 16) != 0;
3123         in = (exit_qualification & 8) != 0;
3124
3125         ++vcpu->stat.io_exits;
3126
3127         if (string || in)
3128                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3129
3130         port = exit_qualification >> 16;
3131         size = (exit_qualification & 7) + 1;
3132         skip_emulated_instruction(vcpu);
3133
3134         return kvm_fast_pio_out(vcpu, size, port);
3135 }
3136
3137 static void
3138 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3139 {
3140         /*
3141          * Patch in the VMCALL instruction:
3142          */
3143         hypercall[0] = 0x0f;
3144         hypercall[1] = 0x01;
3145         hypercall[2] = 0xc1;
3146 }
3147
3148 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3149 {
3150         if (err)
3151                 kvm_inject_gp(vcpu, 0);
3152         else
3153                 skip_emulated_instruction(vcpu);
3154 }
3155
3156 static int handle_cr(struct kvm_vcpu *vcpu)
3157 {
3158         unsigned long exit_qualification, val;
3159         int cr;
3160         int reg;
3161         int err;
3162
3163         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3164         cr = exit_qualification & 15;
3165         reg = (exit_qualification >> 8) & 15;
3166         switch ((exit_qualification >> 4) & 3) {
3167         case 0: /* mov to cr */
3168                 val = kvm_register_read(vcpu, reg);
3169                 trace_kvm_cr_write(cr, val);
3170                 switch (cr) {
3171                 case 0:
3172                         err = kvm_set_cr0(vcpu, val);
3173                         complete_insn_gp(vcpu, err);
3174                         return 1;
3175                 case 3:
3176                         err = kvm_set_cr3(vcpu, val);
3177                         complete_insn_gp(vcpu, err);
3178                         return 1;
3179                 case 4:
3180                         err = kvm_set_cr4(vcpu, val);
3181                         complete_insn_gp(vcpu, err);
3182                         return 1;
3183                 case 8: {
3184                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3185                                 u8 cr8 = kvm_register_read(vcpu, reg);
3186                                 kvm_set_cr8(vcpu, cr8);
3187                                 skip_emulated_instruction(vcpu);
3188                                 if (irqchip_in_kernel(vcpu->kvm))
3189                                         return 1;
3190                                 if (cr8_prev <= cr8)
3191                                         return 1;
3192                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3193                                 return 0;
3194                         }
3195                 };
3196                 break;
3197         case 2: /* clts */
3198                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3199                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3200                 skip_emulated_instruction(vcpu);
3201                 vmx_fpu_activate(vcpu);
3202                 return 1;
3203         case 1: /*mov from cr*/
3204                 switch (cr) {
3205                 case 3:
3206                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3207                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3208                         skip_emulated_instruction(vcpu);
3209                         return 1;
3210                 case 8:
3211                         val = kvm_get_cr8(vcpu);
3212                         kvm_register_write(vcpu, reg, val);
3213                         trace_kvm_cr_read(cr, val);
3214                         skip_emulated_instruction(vcpu);
3215                         return 1;
3216                 }
3217                 break;
3218         case 3: /* lmsw */
3219                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3220                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3221                 kvm_lmsw(vcpu, val);
3222
3223                 skip_emulated_instruction(vcpu);
3224                 return 1;
3225         default:
3226                 break;
3227         }
3228         vcpu->run->exit_reason = 0;
3229         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3230                (int)(exit_qualification >> 4) & 3, cr);
3231         return 0;
3232 }
3233
3234 static int handle_dr(struct kvm_vcpu *vcpu)
3235 {
3236         unsigned long exit_qualification;
3237         int dr, reg;
3238
3239         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3240         if (!kvm_require_cpl(vcpu, 0))
3241                 return 1;
3242         dr = vmcs_readl(GUEST_DR7);
3243         if (dr & DR7_GD) {
3244                 /*
3245                  * As the vm-exit takes precedence over the debug trap, we
3246                  * need to emulate the latter, either for the host or the
3247                  * guest debugging itself.
3248                  */
3249                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3250                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3251                         vcpu->run->debug.arch.dr7 = dr;
3252                         vcpu->run->debug.arch.pc =
3253                                 vmcs_readl(GUEST_CS_BASE) +
3254                                 vmcs_readl(GUEST_RIP);
3255                         vcpu->run->debug.arch.exception = DB_VECTOR;
3256                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3257                         return 0;
3258                 } else {
3259                         vcpu->arch.dr7 &= ~DR7_GD;
3260                         vcpu->arch.dr6 |= DR6_BD;
3261                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3262                         kvm_queue_exception(vcpu, DB_VECTOR);
3263                         return 1;
3264                 }
3265         }
3266
3267         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3268         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3269         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3270         if (exit_qualification & TYPE_MOV_FROM_DR) {
3271                 unsigned long val;
3272                 if (!kvm_get_dr(vcpu, dr, &val))
3273                         kvm_register_write(vcpu, reg, val);
3274         } else
3275                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3276         skip_emulated_instruction(vcpu);
3277         return 1;
3278 }
3279
3280 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3281 {
3282         vmcs_writel(GUEST_DR7, val);
3283 }
3284
3285 static int handle_cpuid(struct kvm_vcpu *vcpu)
3286 {
3287         kvm_emulate_cpuid(vcpu);
3288         return 1;
3289 }
3290
3291 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3292 {
3293         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3294         u64 data;
3295
3296         if (vmx_get_msr(vcpu, ecx, &data)) {
3297                 trace_kvm_msr_read_ex(ecx);
3298                 kvm_inject_gp(vcpu, 0);
3299                 return 1;
3300         }
3301
3302         trace_kvm_msr_read(ecx, data);
3303
3304         /* FIXME: handling of bits 32:63 of rax, rdx */
3305         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3306         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3307         skip_emulated_instruction(vcpu);
3308         return 1;
3309 }
3310
3311 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3312 {
3313         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3314         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3315                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3316
3317         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3318                 trace_kvm_msr_write_ex(ecx, data);
3319                 kvm_inject_gp(vcpu, 0);
3320                 return 1;
3321         }
3322
3323         trace_kvm_msr_write(ecx, data);
3324         skip_emulated_instruction(vcpu);
3325         return 1;
3326 }
3327
3328 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3329 {
3330         return 1;
3331 }
3332
3333 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3334 {
3335         u32 cpu_based_vm_exec_control;
3336
3337         /* clear pending irq */
3338         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3339         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3340         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3341
3342         ++vcpu->stat.irq_window_exits;
3343
3344         /*
3345          * If the user space waits to inject interrupts, exit as soon as
3346          * possible
3347          */
3348         if (!irqchip_in_kernel(vcpu->kvm) &&
3349             vcpu->run->request_interrupt_window &&
3350             !kvm_cpu_has_interrupt(vcpu)) {
3351                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3352                 return 0;
3353         }
3354         return 1;
3355 }
3356
3357 static int handle_halt(struct kvm_vcpu *vcpu)
3358 {
3359         skip_emulated_instruction(vcpu);
3360         return kvm_emulate_halt(vcpu);
3361 }
3362
3363 static int handle_vmcall(struct kvm_vcpu *vcpu)
3364 {
3365         skip_emulated_instruction(vcpu);
3366         kvm_emulate_hypercall(vcpu);
3367         return 1;
3368 }
3369
3370 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3371 {
3372         kvm_queue_exception(vcpu, UD_VECTOR);
3373         return 1;
3374 }
3375
3376 static int handle_invlpg(struct kvm_vcpu *vcpu)
3377 {
3378         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3379
3380         kvm_mmu_invlpg(vcpu, exit_qualification);
3381         skip_emulated_instruction(vcpu);
3382         return 1;
3383 }
3384
3385 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3386 {
3387         skip_emulated_instruction(vcpu);
3388         kvm_emulate_wbinvd(vcpu);
3389         return 1;
3390 }
3391
3392 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3393 {
3394         u64 new_bv = kvm_read_edx_eax(vcpu);
3395         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3396
3397         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3398                 skip_emulated_instruction(vcpu);
3399         return 1;
3400 }
3401
3402 static int handle_apic_access(struct kvm_vcpu *vcpu)
3403 {
3404         return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3405 }
3406
3407 static int handle_task_switch(struct kvm_vcpu *vcpu)
3408 {
3409         struct vcpu_vmx *vmx = to_vmx(vcpu);
3410         unsigned long exit_qualification;
3411         bool has_error_code = false;
3412         u32 error_code = 0;
3413         u16 tss_selector;
3414         int reason, type, idt_v;
3415
3416         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3417         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3418
3419         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3420
3421         reason = (u32)exit_qualification >> 30;
3422         if (reason == TASK_SWITCH_GATE && idt_v) {
3423                 switch (type) {
3424                 case INTR_TYPE_NMI_INTR:
3425                         vcpu->arch.nmi_injected = false;
3426                         if (cpu_has_virtual_nmis())
3427                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3428                                               GUEST_INTR_STATE_NMI);
3429                         break;
3430                 case INTR_TYPE_EXT_INTR:
3431                 case INTR_TYPE_SOFT_INTR:
3432                         kvm_clear_interrupt_queue(vcpu);
3433                         break;
3434                 case INTR_TYPE_HARD_EXCEPTION:
3435                         if (vmx->idt_vectoring_info &
3436                             VECTORING_INFO_DELIVER_CODE_MASK) {
3437                                 has_error_code = true;
3438                                 error_code =
3439                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3440                         }
3441                         /* fall through */
3442                 case INTR_TYPE_SOFT_EXCEPTION:
3443                         kvm_clear_exception_queue(vcpu);
3444                         break;
3445                 default:
3446                         break;
3447                 }
3448         }
3449         tss_selector = exit_qualification;
3450
3451         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3452                        type != INTR_TYPE_EXT_INTR &&
3453                        type != INTR_TYPE_NMI_INTR))
3454                 skip_emulated_instruction(vcpu);
3455
3456         if (kvm_task_switch(vcpu, tss_selector, reason,
3457                                 has_error_code, error_code) == EMULATE_FAIL) {
3458                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3459                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3460                 vcpu->run->internal.ndata = 0;
3461                 return 0;
3462         }
3463
3464         /* clear all local breakpoint enable flags */
3465         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3466
3467         /*
3468          * TODO: What about debug traps on tss switch?
3469          *       Are we supposed to inject them and update dr6?
3470          */
3471
3472         return 1;
3473 }
3474
3475 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3476 {
3477         unsigned long exit_qualification;
3478         gpa_t gpa;
3479         int gla_validity;
3480
3481         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3482
3483         if (exit_qualification & (1 << 6)) {
3484                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3485                 return -EINVAL;
3486         }
3487
3488         gla_validity = (exit_qualification >> 7) & 0x3;
3489         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3490                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3491                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3492                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3493                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3494                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3495                         (long unsigned int)exit_qualification);
3496                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3497                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3498                 return 0;
3499         }
3500
3501         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3502         trace_kvm_page_fault(gpa, exit_qualification);
3503         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3504 }
3505
3506 static u64 ept_rsvd_mask(u64 spte, int level)
3507 {
3508         int i;
3509         u64 mask = 0;
3510
3511         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3512                 mask |= (1ULL << i);
3513
3514         if (level > 2)
3515                 /* bits 7:3 reserved */
3516                 mask |= 0xf8;
3517         else if (level == 2) {
3518                 if (spte & (1ULL << 7))
3519                         /* 2MB ref, bits 20:12 reserved */
3520                         mask |= 0x1ff000;
3521                 else
3522                         /* bits 6:3 reserved */
3523                         mask |= 0x78;
3524         }
3525
3526         return mask;
3527 }
3528
3529 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3530                                        int level)
3531 {
3532         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3533
3534         /* 010b (write-only) */
3535         WARN_ON((spte & 0x7) == 0x2);
3536
3537         /* 110b (write/execute) */
3538         WARN_ON((spte & 0x7) == 0x6);
3539
3540         /* 100b (execute-only) and value not supported by logical processor */
3541         if (!cpu_has_vmx_ept_execute_only())
3542                 WARN_ON((spte & 0x7) == 0x4);
3543
3544         /* not 000b */
3545         if ((spte & 0x7)) {
3546                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3547
3548                 if (rsvd_bits != 0) {
3549                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3550                                          __func__, rsvd_bits);
3551                         WARN_ON(1);
3552                 }
3553
3554                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3555                         u64 ept_mem_type = (spte & 0x38) >> 3;
3556
3557                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3558                             ept_mem_type == 7) {
3559                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3560                                                 __func__, ept_mem_type);
3561                                 WARN_ON(1);
3562                         }
3563                 }
3564         }
3565 }
3566
3567 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3568 {
3569         u64 sptes[4];
3570         int nr_sptes, i;
3571         gpa_t gpa;
3572
3573         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3574
3575         printk(KERN_ERR "EPT: Misconfiguration.\n");
3576         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3577
3578         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3579
3580         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3581                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3582
3583         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3584         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3585
3586         return 0;
3587 }
3588
3589 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3590 {
3591         u32 cpu_based_vm_exec_control;
3592
3593         /* clear pending NMI */
3594         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3595         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3596         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3597         ++vcpu->stat.nmi_window_exits;
3598
3599         return 1;
3600 }
3601
3602 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3603 {
3604         struct vcpu_vmx *vmx = to_vmx(vcpu);
3605         enum emulation_result err = EMULATE_DONE;
3606         int ret = 1;
3607
3608         while (!guest_state_valid(vcpu)) {
3609                 err = emulate_instruction(vcpu, 0, 0, 0);
3610
3611                 if (err == EMULATE_DO_MMIO) {
3612                         ret = 0;
3613                         goto out;
3614                 }
3615
3616                 if (err != EMULATE_DONE)
3617                         return 0;
3618
3619                 if (signal_pending(current))
3620                         goto out;
3621                 if (need_resched())
3622                         schedule();
3623         }
3624
3625         vmx->emulation_required = 0;
3626 out:
3627         return ret;
3628 }
3629
3630 /*
3631  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3632  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3633  */
3634 static int handle_pause(struct kvm_vcpu *vcpu)
3635 {
3636         skip_emulated_instruction(vcpu);
3637         kvm_vcpu_on_spin(vcpu);
3638
3639         return 1;
3640 }
3641
3642 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3643 {
3644         kvm_queue_exception(vcpu, UD_VECTOR);
3645         return 1;
3646 }
3647
3648 /*
3649  * The exit handlers return 1 if the exit was handled fully and guest execution
3650  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3651  * to be done to userspace and return 0.
3652  */
3653 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3654         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3655         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3656         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3657         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3658         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3659         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3660         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3661         [EXIT_REASON_CPUID]                   = handle_cpuid,
3662         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3663         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3664         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3665         [EXIT_REASON_HLT]                     = handle_halt,
3666         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3667         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3668         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3669         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3670         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3671         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3672         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3673         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3674         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3675         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3676         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3677         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3678         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3679         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3680         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
3681         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3682         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3683         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3684         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3685         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3686         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3687         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3688 };
3689
3690 static const int kvm_vmx_max_exit_handlers =
3691         ARRAY_SIZE(kvm_vmx_exit_handlers);
3692
3693 /*
3694  * The guest has exited.  See if we can fix it or if we need userspace
3695  * assistance.
3696  */
3697 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3698 {
3699         struct vcpu_vmx *vmx = to_vmx(vcpu);
3700         u32 exit_reason = vmx->exit_reason;
3701         u32 vectoring_info = vmx->idt_vectoring_info;
3702
3703         trace_kvm_exit(exit_reason, vcpu);
3704
3705         /* If guest state is invalid, start emulating */
3706         if (vmx->emulation_required && emulate_invalid_guest_state)
3707                 return handle_invalid_guest_state(vcpu);
3708
3709         /* Access CR3 don't cause VMExit in paging mode, so we need
3710          * to sync with guest real CR3. */
3711         if (enable_ept && is_paging(vcpu))
3712                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3713
3714         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3715                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3716                 vcpu->run->fail_entry.hardware_entry_failure_reason
3717                         = exit_reason;
3718                 return 0;
3719         }
3720
3721         if (unlikely(vmx->fail)) {
3722                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3723                 vcpu->run->fail_entry.hardware_entry_failure_reason
3724                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3725                 return 0;
3726         }
3727
3728         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3729                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3730                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3731                         exit_reason != EXIT_REASON_TASK_SWITCH))
3732                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3733                        "(0x%x) and exit reason is 0x%x\n",
3734                        __func__, vectoring_info, exit_reason);
3735
3736         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3737                 if (vmx_interrupt_allowed(vcpu)) {
3738                         vmx->soft_vnmi_blocked = 0;
3739                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3740                            vcpu->arch.nmi_pending) {
3741                         /*
3742                          * This CPU don't support us in finding the end of an
3743                          * NMI-blocked window if the guest runs with IRQs
3744                          * disabled. So we pull the trigger after 1 s of
3745                          * futile waiting, but inform the user about this.
3746                          */
3747                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3748                                "state on VCPU %d after 1 s timeout\n",
3749                                __func__, vcpu->vcpu_id);
3750                         vmx->soft_vnmi_blocked = 0;
3751                 }
3752         }
3753
3754         if (exit_reason < kvm_vmx_max_exit_handlers
3755             && kvm_vmx_exit_handlers[exit_reason])
3756                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3757         else {
3758                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3759                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3760         }
3761         return 0;
3762 }
3763
3764 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3765 {
3766         if (irr == -1 || tpr < irr) {
3767                 vmcs_write32(TPR_THRESHOLD, 0);
3768                 return;
3769         }
3770
3771         vmcs_write32(TPR_THRESHOLD, irr);
3772 }
3773
3774 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3775 {
3776         u32 exit_intr_info;
3777         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3778         bool unblock_nmi;
3779         u8 vector;
3780         int type;
3781         bool idtv_info_valid;
3782
3783         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3784
3785         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3786
3787         /* Handle machine checks before interrupts are enabled */
3788         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3789             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3790                 && is_machine_check(exit_intr_info)))
3791                 kvm_machine_check();
3792
3793         /* We need to handle NMIs before interrupts are enabled */
3794         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3795             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3796                 kvm_before_handle_nmi(&vmx->vcpu);
3797                 asm("int $2");
3798                 kvm_after_handle_nmi(&vmx->vcpu);
3799         }
3800
3801         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3802
3803         if (cpu_has_virtual_nmis()) {
3804                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3805                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3806                 /*
3807                  * SDM 3: 27.7.1.2 (September 2008)
3808                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3809                  * a guest IRET fault.
3810                  * SDM 3: 23.2.2 (September 2008)
3811                  * Bit 12 is undefined in any of the following cases:
3812                  *  If the VM exit sets the valid bit in the IDT-vectoring
3813                  *   information field.
3814                  *  If the VM exit is due to a double fault.
3815                  */
3816                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3817                     vector != DF_VECTOR && !idtv_info_valid)
3818                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3819                                       GUEST_INTR_STATE_NMI);
3820         } else if (unlikely(vmx->soft_vnmi_blocked))
3821                 vmx->vnmi_blocked_time +=
3822                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3823
3824         vmx->vcpu.arch.nmi_injected = false;
3825         kvm_clear_exception_queue(&vmx->vcpu);
3826         kvm_clear_interrupt_queue(&vmx->vcpu);
3827
3828         if (!idtv_info_valid)
3829                 return;
3830
3831         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3832         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3833
3834         switch (type) {
3835         case INTR_TYPE_NMI_INTR:
3836                 vmx->vcpu.arch.nmi_injected = true;
3837                 /*
3838                  * SDM 3: 27.7.1.2 (September 2008)
3839                  * Clear bit "block by NMI" before VM entry if a NMI
3840                  * delivery faulted.
3841                  */
3842                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3843                                 GUEST_INTR_STATE_NMI);
3844                 break;
3845         case INTR_TYPE_SOFT_EXCEPTION:
3846                 vmx->vcpu.arch.event_exit_inst_len =
3847                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3848                 /* fall through */
3849         case INTR_TYPE_HARD_EXCEPTION:
3850                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3851                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3852                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3853                 } else
3854                         kvm_queue_exception(&vmx->vcpu, vector);
3855                 break;
3856         case INTR_TYPE_SOFT_INTR:
3857                 vmx->vcpu.arch.event_exit_inst_len =
3858                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3859                 /* fall through */
3860         case INTR_TYPE_EXT_INTR:
3861                 kvm_queue_interrupt(&vmx->vcpu, vector,
3862                         type == INTR_TYPE_SOFT_INTR);
3863                 break;
3864         default:
3865                 break;
3866         }
3867 }
3868
3869 /*
3870  * Failure to inject an interrupt should give us the information
3871  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3872  * when fetching the interrupt redirection bitmap in the real-mode
3873  * tss, this doesn't happen.  So we do it ourselves.
3874  */
3875 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3876 {
3877         vmx->rmode.irq.pending = 0;
3878         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3879                 return;
3880         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3881         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3882                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3883                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3884                 return;
3885         }
3886         vmx->idt_vectoring_info =
3887                 VECTORING_INFO_VALID_MASK
3888                 | INTR_TYPE_EXT_INTR
3889                 | vmx->rmode.irq.vector;
3890 }
3891
3892 #ifdef CONFIG_X86_64
3893 #define R "r"
3894 #define Q "q"
3895 #else
3896 #define R "e"
3897 #define Q "l"
3898 #endif
3899
3900 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3901 {
3902         struct vcpu_vmx *vmx = to_vmx(vcpu);
3903
3904         /* Record the guest's net vcpu time for enforced NMI injections. */
3905         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3906                 vmx->entry_time = ktime_get();
3907
3908         /* Don't enter VMX if guest state is invalid, let the exit handler
3909            start emulation until we arrive back to a valid state */
3910         if (vmx->emulation_required && emulate_invalid_guest_state)
3911                 return;
3912
3913         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3914                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3915         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3916                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3917
3918         /* When single-stepping over STI and MOV SS, we must clear the
3919          * corresponding interruptibility bits in the guest state. Otherwise
3920          * vmentry fails as it then expects bit 14 (BS) in pending debug
3921          * exceptions being set, but that's not correct for the guest debugging
3922          * case. */
3923         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3924                 vmx_set_interrupt_shadow(vcpu, 0);
3925
3926         asm(
3927                 /* Store host registers */
3928                 "push %%"R"dx; push %%"R"bp;"
3929                 "push %%"R"cx \n\t"
3930                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3931                 "je 1f \n\t"
3932                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3933                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3934                 "1: \n\t"
3935                 /* Reload cr2 if changed */
3936                 "mov %c[cr2](%0), %%"R"ax \n\t"
3937                 "mov %%cr2, %%"R"dx \n\t"
3938                 "cmp %%"R"ax, %%"R"dx \n\t"
3939                 "je 2f \n\t"
3940                 "mov %%"R"ax, %%cr2 \n\t"
3941                 "2: \n\t"
3942                 /* Check if vmlaunch of vmresume is needed */
3943                 "cmpl $0, %c[launched](%0) \n\t"
3944                 /* Load guest registers.  Don't clobber flags. */
3945                 "mov %c[rax](%0), %%"R"ax \n\t"
3946                 "mov %c[rbx](%0), %%"R"bx \n\t"
3947                 "mov %c[rdx](%0), %%"R"dx \n\t"
3948                 "mov %c[rsi](%0), %%"R"si \n\t"
3949                 "mov %c[rdi](%0), %%"R"di \n\t"
3950                 "mov %c[rbp](%0), %%"R"bp \n\t"
3951 #ifdef CONFIG_X86_64
3952                 "mov %c[r8](%0),  %%r8  \n\t"
3953                 "mov %c[r9](%0),  %%r9  \n\t"
3954                 "mov %c[r10](%0), %%r10 \n\t"
3955                 "mov %c[r11](%0), %%r11 \n\t"
3956                 "mov %c[r12](%0), %%r12 \n\t"
3957                 "mov %c[r13](%0), %%r13 \n\t"
3958                 "mov %c[r14](%0), %%r14 \n\t"
3959                 "mov %c[r15](%0), %%r15 \n\t"
3960 #endif
3961                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3962
3963                 /* Enter guest mode */
3964                 "jne .Llaunched \n\t"
3965                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3966                 "jmp .Lkvm_vmx_return \n\t"
3967                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3968                 ".Lkvm_vmx_return: "
3969                 /* Save guest registers, load host registers, keep flags */
3970                 "xchg %0,     (%%"R"sp) \n\t"
3971                 "mov %%"R"ax, %c[rax](%0) \n\t"
3972                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3973                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3974                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3975                 "mov %%"R"si, %c[rsi](%0) \n\t"
3976                 "mov %%"R"di, %c[rdi](%0) \n\t"
3977                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3978 #ifdef CONFIG_X86_64
3979                 "mov %%r8,  %c[r8](%0) \n\t"
3980                 "mov %%r9,  %c[r9](%0) \n\t"
3981                 "mov %%r10, %c[r10](%0) \n\t"
3982                 "mov %%r11, %c[r11](%0) \n\t"
3983                 "mov %%r12, %c[r12](%0) \n\t"
3984                 "mov %%r13, %c[r13](%0) \n\t"
3985                 "mov %%r14, %c[r14](%0) \n\t"
3986                 "mov %%r15, %c[r15](%0) \n\t"
3987 #endif
3988                 "mov %%cr2, %%"R"ax   \n\t"
3989                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3990
3991                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3992                 "setbe %c[fail](%0) \n\t"
3993               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3994                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3995                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3996                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3997                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3998                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3999                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4000                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4001                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4002                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4003                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4004 #ifdef CONFIG_X86_64
4005                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4006                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4007                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4008                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4009                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4010                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4011                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4012                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4013 #endif
4014                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4015               : "cc", "memory"
4016                 , R"bx", R"di", R"si"
4017 #ifdef CONFIG_X86_64
4018                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4019 #endif
4020               );
4021
4022         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4023                                   | (1 << VCPU_EXREG_PDPTR));
4024         vcpu->arch.regs_dirty = 0;
4025
4026         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4027         if (vmx->rmode.irq.pending)
4028                 fixup_rmode_irq(vmx);
4029
4030         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4031         vmx->launched = 1;
4032
4033         vmx_complete_interrupts(vmx);
4034 }
4035
4036 #undef R
4037 #undef Q
4038
4039 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4040 {
4041         struct vcpu_vmx *vmx = to_vmx(vcpu);
4042
4043         if (vmx->vmcs) {
4044                 vcpu_clear(vmx);
4045                 free_vmcs(vmx->vmcs);
4046                 vmx->vmcs = NULL;
4047         }
4048 }
4049
4050 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4051 {
4052         struct vcpu_vmx *vmx = to_vmx(vcpu);
4053
4054         free_vpid(vmx);
4055         vmx_free_vmcs(vcpu);
4056         kfree(vmx->guest_msrs);
4057         kvm_vcpu_uninit(vcpu);
4058         kmem_cache_free(kvm_vcpu_cache, vmx);
4059 }
4060
4061 static inline void vmcs_init(struct vmcs *vmcs)
4062 {
4063         u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4064
4065         if (!vmm_exclusive)
4066                 kvm_cpu_vmxon(phys_addr);
4067
4068         vmcs_clear(vmcs);
4069
4070         if (!vmm_exclusive)
4071                 kvm_cpu_vmxoff();
4072 }
4073
4074 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4075 {
4076         int err;
4077         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4078         int cpu;
4079
4080         if (!vmx)
4081                 return ERR_PTR(-ENOMEM);
4082
4083         allocate_vpid(vmx);
4084
4085         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4086         if (err)
4087                 goto free_vcpu;
4088
4089         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4090         if (!vmx->guest_msrs) {
4091                 err = -ENOMEM;
4092                 goto uninit_vcpu;
4093         }
4094
4095         vmx->vmcs = alloc_vmcs();
4096         if (!vmx->vmcs)
4097                 goto free_msrs;
4098
4099         vmcs_init(vmx->vmcs);
4100
4101         cpu = get_cpu();
4102         vmx_vcpu_load(&vmx->vcpu, cpu);
4103         vmx->vcpu.cpu = cpu;
4104         err = vmx_vcpu_setup(vmx);
4105         vmx_vcpu_put(&vmx->vcpu);
4106         put_cpu();
4107         if (err)
4108                 goto free_vmcs;
4109         if (vm_need_virtualize_apic_accesses(kvm))
4110                 if (alloc_apic_access_page(kvm) != 0)
4111                         goto free_vmcs;
4112
4113         if (enable_ept) {
4114                 if (!kvm->arch.ept_identity_map_addr)
4115                         kvm->arch.ept_identity_map_addr =
4116                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4117                 if (alloc_identity_pagetable(kvm) != 0)
4118                         goto free_vmcs;
4119         }
4120
4121         return &vmx->vcpu;
4122
4123 free_vmcs:
4124         free_vmcs(vmx->vmcs);
4125 free_msrs:
4126         kfree(vmx->guest_msrs);
4127 uninit_vcpu:
4128         kvm_vcpu_uninit(&vmx->vcpu);
4129 free_vcpu:
4130         free_vpid(vmx);
4131         kmem_cache_free(kvm_vcpu_cache, vmx);
4132         return ERR_PTR(err);
4133 }
4134
4135 static void __init vmx_check_processor_compat(void *rtn)
4136 {
4137         struct vmcs_config vmcs_conf;
4138
4139         *(int *)rtn = 0;
4140         if (setup_vmcs_config(&vmcs_conf) < 0)
4141                 *(int *)rtn = -EIO;
4142         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4143                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4144                                 smp_processor_id());
4145                 *(int *)rtn = -EIO;
4146         }
4147 }
4148
4149 static int get_ept_level(void)
4150 {
4151         return VMX_EPT_DEFAULT_GAW + 1;
4152 }
4153
4154 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4155 {
4156         u64 ret;
4157
4158         /* For VT-d and EPT combination
4159          * 1. MMIO: always map as UC
4160          * 2. EPT with VT-d:
4161          *   a. VT-d without snooping control feature: can't guarantee the
4162          *      result, try to trust guest.
4163          *   b. VT-d with snooping control feature: snooping control feature of
4164          *      VT-d engine can guarantee the cache correctness. Just set it
4165          *      to WB to keep consistent with host. So the same as item 3.
4166          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4167          *    consistent with host MTRR
4168          */
4169         if (is_mmio)
4170                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4171         else if (vcpu->kvm->arch.iommu_domain &&
4172                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4173                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4174                       VMX_EPT_MT_EPTE_SHIFT;
4175         else
4176                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4177                         | VMX_EPT_IPAT_BIT;
4178
4179         return ret;
4180 }
4181
4182 #define _ER(x) { EXIT_REASON_##x, #x }
4183
4184 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4185         _ER(EXCEPTION_NMI),
4186         _ER(EXTERNAL_INTERRUPT),
4187         _ER(TRIPLE_FAULT),
4188         _ER(PENDING_INTERRUPT),
4189         _ER(NMI_WINDOW),
4190         _ER(TASK_SWITCH),
4191         _ER(CPUID),
4192         _ER(HLT),
4193         _ER(INVLPG),
4194         _ER(RDPMC),
4195         _ER(RDTSC),
4196         _ER(VMCALL),
4197         _ER(VMCLEAR),
4198         _ER(VMLAUNCH),
4199         _ER(VMPTRLD),
4200         _ER(VMPTRST),
4201         _ER(VMREAD),
4202         _ER(VMRESUME),
4203         _ER(VMWRITE),
4204         _ER(VMOFF),
4205         _ER(VMON),
4206         _ER(CR_ACCESS),
4207         _ER(DR_ACCESS),
4208         _ER(IO_INSTRUCTION),
4209         _ER(MSR_READ),
4210         _ER(MSR_WRITE),
4211         _ER(MWAIT_INSTRUCTION),
4212         _ER(MONITOR_INSTRUCTION),
4213         _ER(PAUSE_INSTRUCTION),
4214         _ER(MCE_DURING_VMENTRY),
4215         _ER(TPR_BELOW_THRESHOLD),
4216         _ER(APIC_ACCESS),
4217         _ER(EPT_VIOLATION),
4218         _ER(EPT_MISCONFIG),
4219         _ER(WBINVD),
4220         { -1, NULL }
4221 };
4222
4223 #undef _ER
4224
4225 static int vmx_get_lpage_level(void)
4226 {
4227         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4228                 return PT_DIRECTORY_LEVEL;
4229         else
4230                 /* For shadow and EPT supported 1GB page */
4231                 return PT_PDPE_LEVEL;
4232 }
4233
4234 static inline u32 bit(int bitno)
4235 {
4236         return 1 << (bitno & 31);
4237 }
4238
4239 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4240 {
4241         struct kvm_cpuid_entry2 *best;
4242         struct vcpu_vmx *vmx = to_vmx(vcpu);
4243         u32 exec_control;
4244
4245         vmx->rdtscp_enabled = false;
4246         if (vmx_rdtscp_supported()) {
4247                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4248                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4249                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4250                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4251                                 vmx->rdtscp_enabled = true;
4252                         else {
4253                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4254                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4255                                                 exec_control);
4256                         }
4257                 }
4258         }
4259 }
4260
4261 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4262 {
4263 }
4264
4265 static struct kvm_x86_ops vmx_x86_ops = {
4266         .cpu_has_kvm_support = cpu_has_kvm_support,
4267         .disabled_by_bios = vmx_disabled_by_bios,
4268         .hardware_setup = hardware_setup,
4269         .hardware_unsetup = hardware_unsetup,
4270         .check_processor_compatibility = vmx_check_processor_compat,
4271         .hardware_enable = hardware_enable,
4272         .hardware_disable = hardware_disable,
4273         .cpu_has_accelerated_tpr = report_flexpriority,
4274
4275         .vcpu_create = vmx_create_vcpu,
4276         .vcpu_free = vmx_free_vcpu,
4277         .vcpu_reset = vmx_vcpu_reset,
4278
4279         .prepare_guest_switch = vmx_save_host_state,
4280         .vcpu_load = vmx_vcpu_load,
4281         .vcpu_put = vmx_vcpu_put,
4282
4283         .set_guest_debug = set_guest_debug,
4284         .get_msr = vmx_get_msr,
4285         .set_msr = vmx_set_msr,
4286         .get_segment_base = vmx_get_segment_base,
4287         .get_segment = vmx_get_segment,
4288         .set_segment = vmx_set_segment,
4289         .get_cpl = vmx_get_cpl,
4290         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4291         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4292         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4293         .set_cr0 = vmx_set_cr0,
4294         .set_cr3 = vmx_set_cr3,
4295         .set_cr4 = vmx_set_cr4,
4296         .set_efer = vmx_set_efer,
4297         .get_idt = vmx_get_idt,
4298         .set_idt = vmx_set_idt,
4299         .get_gdt = vmx_get_gdt,
4300         .set_gdt = vmx_set_gdt,
4301         .set_dr7 = vmx_set_dr7,
4302         .cache_reg = vmx_cache_reg,
4303         .get_rflags = vmx_get_rflags,
4304         .set_rflags = vmx_set_rflags,
4305         .fpu_activate = vmx_fpu_activate,
4306         .fpu_deactivate = vmx_fpu_deactivate,
4307
4308         .tlb_flush = vmx_flush_tlb,
4309
4310         .run = vmx_vcpu_run,
4311         .handle_exit = vmx_handle_exit,
4312         .skip_emulated_instruction = skip_emulated_instruction,
4313         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4314         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4315         .patch_hypercall = vmx_patch_hypercall,
4316         .set_irq = vmx_inject_irq,
4317         .set_nmi = vmx_inject_nmi,
4318         .queue_exception = vmx_queue_exception,
4319         .interrupt_allowed = vmx_interrupt_allowed,
4320         .nmi_allowed = vmx_nmi_allowed,
4321         .get_nmi_mask = vmx_get_nmi_mask,
4322         .set_nmi_mask = vmx_set_nmi_mask,
4323         .enable_nmi_window = enable_nmi_window,
4324         .enable_irq_window = enable_irq_window,
4325         .update_cr8_intercept = update_cr8_intercept,
4326
4327         .set_tss_addr = vmx_set_tss_addr,
4328         .get_tdp_level = get_ept_level,
4329         .get_mt_mask = vmx_get_mt_mask,
4330
4331         .exit_reasons_str = vmx_exit_reasons_str,
4332         .get_lpage_level = vmx_get_lpage_level,
4333
4334         .cpuid_update = vmx_cpuid_update,
4335
4336         .rdtscp_supported = vmx_rdtscp_supported,
4337
4338         .set_supported_cpuid = vmx_set_supported_cpuid,
4339
4340         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4341
4342         .write_tsc_offset = vmx_write_tsc_offset,
4343         .adjust_tsc_offset = vmx_adjust_tsc_offset,
4344
4345         .set_tdp_cr3 = vmx_set_cr3,
4346 };
4347
4348 static int __init vmx_init(void)
4349 {
4350         int r, i;
4351
4352         rdmsrl_safe(MSR_EFER, &host_efer);
4353
4354         for (i = 0; i < NR_VMX_MSR; ++i)
4355                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4356
4357         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4358         if (!vmx_io_bitmap_a)
4359                 return -ENOMEM;
4360
4361         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4362         if (!vmx_io_bitmap_b) {
4363                 r = -ENOMEM;
4364                 goto out;
4365         }
4366
4367         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4368         if (!vmx_msr_bitmap_legacy) {
4369                 r = -ENOMEM;
4370                 goto out1;
4371         }
4372
4373         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4374         if (!vmx_msr_bitmap_longmode) {
4375                 r = -ENOMEM;
4376                 goto out2;
4377         }
4378
4379         /*
4380          * Allow direct access to the PC debug port (it is often used for I/O
4381          * delays, but the vmexits simply slow things down).
4382          */
4383         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4384         clear_bit(0x80, vmx_io_bitmap_a);
4385
4386         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4387
4388         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4389         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4390
4391         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4392
4393         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4394                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4395         if (r)
4396                 goto out3;
4397
4398         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4399         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4400         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4401         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4402         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4403         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4404
4405         if (enable_ept) {
4406                 bypass_guest_pf = 0;
4407                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4408                         VMX_EPT_WRITABLE_MASK);
4409                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4410                                 VMX_EPT_EXECUTABLE_MASK);
4411                 kvm_enable_tdp();
4412         } else
4413                 kvm_disable_tdp();
4414
4415         if (bypass_guest_pf)
4416                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4417
4418         return 0;
4419
4420 out3:
4421         free_page((unsigned long)vmx_msr_bitmap_longmode);
4422 out2:
4423         free_page((unsigned long)vmx_msr_bitmap_legacy);
4424 out1:
4425         free_page((unsigned long)vmx_io_bitmap_b);
4426 out:
4427         free_page((unsigned long)vmx_io_bitmap_a);
4428         return r;
4429 }
4430
4431 static void __exit vmx_exit(void)
4432 {
4433         free_page((unsigned long)vmx_msr_bitmap_legacy);
4434         free_page((unsigned long)vmx_msr_bitmap_longmode);
4435         free_page((unsigned long)vmx_io_bitmap_b);
4436         free_page((unsigned long)vmx_io_bitmap_a);
4437
4438         kvm_exit();
4439 }
4440
4441 module_init(vmx_init)
4442 module_exit(vmx_exit)