arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affilates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 static int __read_mostly bypass_guest_pf = 1;
  51 module_param(bypass_guest_pf, bool, S_IRUGO);
  52
  53 static int __read_mostly enable_vpid = 1;
  54 module_param_named(vpid, enable_vpid, bool, 0444);
  55
  56 static int __read_mostly flexpriority_enabled = 1;
  57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_ept = 1;
  60 module_param_named(ept, enable_ept, bool, S_IRUGO);
  61
  62 static int __read_mostly enable_unrestricted_guest = 1;
  63 module_param_named(unrestricted_guest,
  64                         enable_unrestricted_guest, bool, S_IRUGO);
  65
  66 static int __read_mostly emulate_invalid_guest_state = 0;
  67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  68
  69 static int __read_mostly vmm_exclusive = 1;
  70 module_param(vmm_exclusive, bool, S_IRUGO);
  71
  72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  73         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  74 #define KVM_GUEST_CR0_MASK                                              \
  75         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  77         (X86_CR0_WP | X86_CR0_NE)
  78 #define KVM_VM_CR0_ALWAYS_ON                                            \
  79         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  80 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  81         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  82          | X86_CR4_OSXMMEXCPT)
  83
  84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  86
  87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  88
  89 /*
  90  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  91  * ple_gap:    upper bound on the amount of time between two successive
  92  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  93  *             According to test, this time is usually small than 41 cycles.
  94  * ple_window: upper bound on the amount of time a guest is allowed to execute
  95  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  96  *             less than 2^12 cycles
  97  * Time is measured based on a counter that runs at the same rate as the TSC,
  98  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  99  */
 100 #define KVM_VMX_DEFAULT_PLE_GAP    41
 101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 102 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 103 module_param(ple_gap, int, S_IRUGO);
 104
 105 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 106 module_param(ple_window, int, S_IRUGO);
 107
 108 #define NR_AUTOLOAD_MSRS 1
 109
 110 struct vmcs {
 111         u32 revision_id;
 112         u32 abort;
 113         char data[0];
 114 };
 115
 116 struct shared_msr_entry {
 117         unsigned index;
 118         u64 data;
 119         u64 mask;
 120 };
 121
 122 struct vcpu_vmx {
 123         struct kvm_vcpu       vcpu;
 124         struct list_head      local_vcpus_link;
 125         unsigned long         host_rsp;
 126         int                   launched;
 127         u8                    fail;
 128         u32                   exit_intr_info;
 129         u32                   idt_vectoring_info;
 130         struct shared_msr_entry *guest_msrs;
 131         int                   nmsrs;
 132         int                   save_nmsrs;
 133 #ifdef CONFIG_X86_64
 134         u64                   msr_host_kernel_gs_base;
 135         u64                   msr_guest_kernel_gs_base;
 136 #endif
 137         struct vmcs          *vmcs;
 138         struct msr_autoload {
 139                 unsigned nr;
 140                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 141                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 142         } msr_autoload;
 143         struct {
 144                 int           loaded;
 145                 u16           fs_sel, gs_sel, ldt_sel;
 146                 int           gs_ldt_reload_needed;
 147                 int           fs_reload_needed;
 148         } host_state;
 149         struct {
 150                 int vm86_active;
 151                 ulong save_rflags;
 152                 struct kvm_save_segment {
 153                         u16 selector;
 154                         unsigned long base;
 155                         u32 limit;
 156                         u32 ar;
 157                 } tr, es, ds, fs, gs;
 158                 struct {
 159                         bool pending;
 160                         u8 vector;
 161                         unsigned rip;
 162                 } irq;
 163         } rmode;
 164         int vpid;
 165         bool emulation_required;
 166
 167         /* Support for vnmi-less CPUs */
 168         int soft_vnmi_blocked;
 169         ktime_t entry_time;
 170         s64 vnmi_blocked_time;
 171         u32 exit_reason;
 172
 173         bool rdtscp_enabled;
 174 };
 175
 176 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 177 {
 178         return container_of(vcpu, struct vcpu_vmx, vcpu);
 179 }
 180
 181 static int init_rmode(struct kvm *kvm);
 182 static u64 construct_eptp(unsigned long root_hpa);
 183 static void kvm_cpu_vmxon(u64 addr);
 184 static void kvm_cpu_vmxoff(void);
 185 static void fixup_rmode_irq(struct vcpu_vmx *vmx, u32 *idt_vectoring_info);
 186
 187 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 188 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 189 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 190 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 191
 192 static unsigned long *vmx_io_bitmap_a;
 193 static unsigned long *vmx_io_bitmap_b;
 194 static unsigned long *vmx_msr_bitmap_legacy;
 195 static unsigned long *vmx_msr_bitmap_longmode;
 196
 197 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 198 static DEFINE_SPINLOCK(vmx_vpid_lock);
 199
 200 static struct vmcs_config {
 201         int size;
 202         int order;
 203         u32 revision_id;
 204         u32 pin_based_exec_ctrl;
 205         u32 cpu_based_exec_ctrl;
 206         u32 cpu_based_2nd_exec_ctrl;
 207         u32 vmexit_ctrl;
 208         u32 vmentry_ctrl;
 209 } vmcs_config;
 210
 211 static struct vmx_capability {
 212         u32 ept;
 213         u32 vpid;
 214 } vmx_capability;
 215
 216 #define VMX_SEGMENT_FIELD(seg)                                  \
 217         [VCPU_SREG_##seg] = {                                   \
 218                 .selector = GUEST_##seg##_SELECTOR,             \
 219                 .base = GUEST_##seg##_BASE,                     \
 220                 .limit = GUEST_##seg##_LIMIT,                   \
 221                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 222         }
 223
 224 static struct kvm_vmx_segment_field {
 225         unsigned selector;
 226         unsigned base;
 227         unsigned limit;
 228         unsigned ar_bytes;
 229 } kvm_vmx_segment_fields[] = {
 230         VMX_SEGMENT_FIELD(CS),
 231         VMX_SEGMENT_FIELD(DS),
 232         VMX_SEGMENT_FIELD(ES),
 233         VMX_SEGMENT_FIELD(FS),
 234         VMX_SEGMENT_FIELD(GS),
 235         VMX_SEGMENT_FIELD(SS),
 236         VMX_SEGMENT_FIELD(TR),
 237         VMX_SEGMENT_FIELD(LDTR),
 238 };
 239
 240 static u64 host_efer;
 241
 242 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 243
 244 /*
 245  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 246  * away by decrementing the array size.
 247  */
 248 static const u32 vmx_msr_index[] = {
 249 #ifdef CONFIG_X86_64
 250         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 251 #endif
 252         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 253 };
 254 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 255
 256 static inline bool is_page_fault(u32 intr_info)
 257 {
 258         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 259                              INTR_INFO_VALID_MASK)) ==
 260                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 261 }
 262
 263 static inline bool is_no_device(u32 intr_info)
 264 {
 265         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 266                              INTR_INFO_VALID_MASK)) ==
 267                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 268 }
 269
 270 static inline bool is_invalid_opcode(u32 intr_info)
 271 {
 272         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 273                              INTR_INFO_VALID_MASK)) ==
 274                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 275 }
 276
 277 static inline bool is_external_interrupt(u32 intr_info)
 278 {
 279         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 280                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 281 }
 282
 283 static inline bool is_machine_check(u32 intr_info)
 284 {
 285         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 286                              INTR_INFO_VALID_MASK)) ==
 287                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 288 }
 289
 290 static inline bool cpu_has_vmx_msr_bitmap(void)
 291 {
 292         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 293 }
 294
 295 static inline bool cpu_has_vmx_tpr_shadow(void)
 296 {
 297         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 298 }
 299
 300 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 301 {
 302         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 303 }
 304
 305 static inline bool cpu_has_secondary_exec_ctrls(void)
 306 {
 307         return vmcs_config.cpu_based_exec_ctrl &
 308                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 309 }
 310
 311 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 312 {
 313         return vmcs_config.cpu_based_2nd_exec_ctrl &
 314                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 315 }
 316
 317 static inline bool cpu_has_vmx_flexpriority(void)
 318 {
 319         return cpu_has_vmx_tpr_shadow() &&
 320                 cpu_has_vmx_virtualize_apic_accesses();
 321 }
 322
 323 static inline bool cpu_has_vmx_ept_execute_only(void)
 324 {
 325         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 326 }
 327
 328 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 329 {
 330         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 331 }
 332
 333 static inline bool cpu_has_vmx_eptp_writeback(void)
 334 {
 335         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 336 }
 337
 338 static inline bool cpu_has_vmx_ept_2m_page(void)
 339 {
 340         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 341 }
 342
 343 static inline bool cpu_has_vmx_ept_1g_page(void)
 344 {
 345         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 346 }
 347
 348 static inline bool cpu_has_vmx_ept_4levels(void)
 349 {
 350         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 351 }
 352
 353 static inline bool cpu_has_vmx_invept_individual_addr(void)
 354 {
 355         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 356 }
 357
 358 static inline bool cpu_has_vmx_invept_context(void)
 359 {
 360         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 361 }
 362
 363 static inline bool cpu_has_vmx_invept_global(void)
 364 {
 365         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 366 }
 367
 368 static inline bool cpu_has_vmx_invvpid_single(void)
 369 {
 370         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 371 }
 372
 373 static inline bool cpu_has_vmx_invvpid_global(void)
 374 {
 375         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 376 }
 377
 378 static inline bool cpu_has_vmx_ept(void)
 379 {
 380         return vmcs_config.cpu_based_2nd_exec_ctrl &
 381                 SECONDARY_EXEC_ENABLE_EPT;
 382 }
 383
 384 static inline bool cpu_has_vmx_unrestricted_guest(void)
 385 {
 386         return vmcs_config.cpu_based_2nd_exec_ctrl &
 387                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 388 }
 389
 390 static inline bool cpu_has_vmx_ple(void)
 391 {
 392         return vmcs_config.cpu_based_2nd_exec_ctrl &
 393                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 394 }
 395
 396 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 397 {
 398         return flexpriority_enabled && irqchip_in_kernel(kvm);
 399 }
 400
 401 static inline bool cpu_has_vmx_vpid(void)
 402 {
 403         return vmcs_config.cpu_based_2nd_exec_ctrl &
 404                 SECONDARY_EXEC_ENABLE_VPID;
 405 }
 406
 407 static inline bool cpu_has_vmx_rdtscp(void)
 408 {
 409         return vmcs_config.cpu_based_2nd_exec_ctrl &
 410                 SECONDARY_EXEC_RDTSCP;
 411 }
 412
 413 static inline bool cpu_has_virtual_nmis(void)
 414 {
 415         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 416 }
 417
 418 static inline bool cpu_has_vmx_wbinvd_exit(void)
 419 {
 420         return vmcs_config.cpu_based_2nd_exec_ctrl &
 421                 SECONDARY_EXEC_WBINVD_EXITING;
 422 }
 423
 424 static inline bool report_flexpriority(void)
 425 {
 426         return flexpriority_enabled;
 427 }
 428
 429 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 430 {
 431         int i;
 432
 433         for (i = 0; i < vmx->nmsrs; ++i)
 434                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 435                         return i;
 436         return -1;
 437 }
 438
 439 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 440 {
 441     struct {
 442         u64 vpid : 16;
 443         u64 rsvd : 48;
 444         u64 gva;
 445     } operand = { vpid, 0, gva };
 446
 447     asm volatile (__ex(ASM_VMX_INVVPID)
 448                   /* CF==1 or ZF==1 --> rc = -1 */
 449                   "; ja 1f ; ud2 ; 1:"
 450                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 451 }
 452
 453 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 454 {
 455         struct {
 456                 u64 eptp, gpa;
 457         } operand = {eptp, gpa};
 458
 459         asm volatile (__ex(ASM_VMX_INVEPT)
 460                         /* CF==1 or ZF==1 --> rc = -1 */
 461                         "; ja 1f ; ud2 ; 1:\n"
 462                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 463 }
 464
 465 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 466 {
 467         int i;
 468
 469         i = __find_msr_index(vmx, msr);
 470         if (i >= 0)
 471                 return &vmx->guest_msrs[i];
 472         return NULL;
 473 }
 474
 475 static void vmcs_clear(struct vmcs *vmcs)
 476 {
 477         u64 phys_addr = __pa(vmcs);
 478         u8 error;
 479
 480         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 481                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 482                       : "cc", "memory");
 483         if (error)
 484                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 485                        vmcs, phys_addr);
 486 }
 487
 488 static void vmcs_load(struct vmcs *vmcs)
 489 {
 490         u64 phys_addr = __pa(vmcs);
 491         u8 error;
 492
 493         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 494                         : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 495                         : "cc", "memory");
 496         if (error)
 497                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 498                        vmcs, phys_addr);
 499 }
 500
 501 static void __vcpu_clear(void *arg)
 502 {
 503         struct vcpu_vmx *vmx = arg;
 504         int cpu = raw_smp_processor_id();
 505
 506         if (vmx->vcpu.cpu == cpu)
 507                 vmcs_clear(vmx->vmcs);
 508         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 509                 per_cpu(current_vmcs, cpu) = NULL;
 510         list_del(&vmx->local_vcpus_link);
 511         vmx->vcpu.cpu = -1;
 512         vmx->launched = 0;
 513 }
 514
 515 static void vcpu_clear(struct vcpu_vmx *vmx)
 516 {
 517         if (vmx->vcpu.cpu == -1)
 518                 return;
 519         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 520 }
 521
 522 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 523 {
 524         if (vmx->vpid == 0)
 525                 return;
 526
 527         if (cpu_has_vmx_invvpid_single())
 528                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 529 }
 530
 531 static inline void vpid_sync_vcpu_global(void)
 532 {
 533         if (cpu_has_vmx_invvpid_global())
 534                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 535 }
 536
 537 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 538 {
 539         if (cpu_has_vmx_invvpid_single())
 540                 vpid_sync_vcpu_single(vmx);
 541         else
 542                 vpid_sync_vcpu_global();
 543 }
 544
 545 static inline void ept_sync_global(void)
 546 {
 547         if (cpu_has_vmx_invept_global())
 548                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 549 }
 550
 551 static inline void ept_sync_context(u64 eptp)
 552 {
 553         if (enable_ept) {
 554                 if (cpu_has_vmx_invept_context())
 555                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 556                 else
 557                         ept_sync_global();
 558         }
 559 }
 560
 561 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 562 {
 563         if (enable_ept) {
 564                 if (cpu_has_vmx_invept_individual_addr())
 565                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 566                                         eptp, gpa);
 567                 else
 568                         ept_sync_context(eptp);
 569         }
 570 }
 571
 572 static unsigned long vmcs_readl(unsigned long field)
 573 {
 574         unsigned long value;
 575
 576         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 577                       : "=a"(value) : "d"(field) : "cc");
 578         return value;
 579 }
 580
 581 static u16 vmcs_read16(unsigned long field)
 582 {
 583         return vmcs_readl(field);
 584 }
 585
 586 static u32 vmcs_read32(unsigned long field)
 587 {
 588         return vmcs_readl(field);
 589 }
 590
 591 static u64 vmcs_read64(unsigned long field)
 592 {
 593 #ifdef CONFIG_X86_64
 594         return vmcs_readl(field);
 595 #else
 596         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 597 #endif
 598 }
 599
 600 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 601 {
 602         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 603                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 604         dump_stack();
 605 }
 606
 607 static void vmcs_writel(unsigned long field, unsigned long value)
 608 {
 609         u8 error;
 610
 611         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 612                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 613         if (unlikely(error))
 614                 vmwrite_error(field, value);
 615 }
 616
 617 static void vmcs_write16(unsigned long field, u16 value)
 618 {
 619         vmcs_writel(field, value);
 620 }
 621
 622 static void vmcs_write32(unsigned long field, u32 value)
 623 {
 624         vmcs_writel(field, value);
 625 }
 626
 627 static void vmcs_write64(unsigned long field, u64 value)
 628 {
 629         vmcs_writel(field, value);
 630 #ifndef CONFIG_X86_64
 631         asm volatile ("");
 632         vmcs_writel(field+1, value >> 32);
 633 #endif
 634 }
 635
 636 static void vmcs_clear_bits(unsigned long field, u32 mask)
 637 {
 638         vmcs_writel(field, vmcs_readl(field) & ~mask);
 639 }
 640
 641 static void vmcs_set_bits(unsigned long field, u32 mask)
 642 {
 643         vmcs_writel(field, vmcs_readl(field) | mask);
 644 }
 645
 646 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 647 {
 648         u32 eb;
 649
 650         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 651              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 652         if ((vcpu->guest_debug &
 653              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 654             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 655                 eb |= 1u << BP_VECTOR;
 656         if (to_vmx(vcpu)->rmode.vm86_active)
 657                 eb = ~0;
 658         if (enable_ept)
 659                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 660         if (vcpu->fpu_active)
 661                 eb &= ~(1u << NM_VECTOR);
 662         vmcs_write32(EXCEPTION_BITMAP, eb);
 663 }
 664
 665 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 666 {
 667         unsigned i;
 668         struct msr_autoload *m = &vmx->msr_autoload;
 669
 670         for (i = 0; i < m->nr; ++i)
 671                 if (m->guest[i].index == msr)
 672                         break;
 673
 674         if (i == m->nr)
 675                 return;
 676         --m->nr;
 677         m->guest[i] = m->guest[m->nr];
 678         m->host[i] = m->host[m->nr];
 679         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 680         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 681 }
 682
 683 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 684                                   u64 guest_val, u64 host_val)
 685 {
 686         unsigned i;
 687         struct msr_autoload *m = &vmx->msr_autoload;
 688
 689         for (i = 0; i < m->nr; ++i)
 690                 if (m->guest[i].index == msr)
 691                         break;
 692
 693         if (i == m->nr) {
 694                 ++m->nr;
 695                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 696                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 697         }
 698
 699         m->guest[i].index = msr;
 700         m->guest[i].value = guest_val;
 701         m->host[i].index = msr;
 702         m->host[i].value = host_val;
 703 }
 704
 705 static void reload_tss(void)
 706 {
 707         /*
 708          * VT restores TR but not its size.  Useless.
 709          */
 710         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 711         struct desc_struct *descs;
 712
 713         descs = (void *)gdt->address;
 714         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 715         load_TR_desc();
 716 }
 717
 718 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 719 {
 720         u64 guest_efer;
 721         u64 ignore_bits;
 722
 723         guest_efer = vmx->vcpu.arch.efer;
 724
 725         /*
 726          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 727          * outside long mode
 728          */
 729         ignore_bits = EFER_NX | EFER_SCE;
 730 #ifdef CONFIG_X86_64
 731         ignore_bits |= EFER_LMA | EFER_LME;
 732         /* SCE is meaningful only in long mode on Intel */
 733         if (guest_efer & EFER_LMA)
 734                 ignore_bits &= ~(u64)EFER_SCE;
 735 #endif
 736         guest_efer &= ~ignore_bits;
 737         guest_efer |= host_efer & ignore_bits;
 738         vmx->guest_msrs[efer_offset].data = guest_efer;
 739         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 740
 741         clear_atomic_switch_msr(vmx, MSR_EFER);
 742         /* On ept, can't emulate nx, and must switch nx atomically */
 743         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 744                 guest_efer = vmx->vcpu.arch.efer;
 745                 if (!(guest_efer & EFER_LMA))
 746                         guest_efer &= ~EFER_LME;
 747                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 748                 return false;
 749         }
 750
 751         return true;
 752 }
 753
 754 static unsigned long segment_base(u16 selector)
 755 {
 756         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 757         struct desc_struct *d;
 758         unsigned long table_base;
 759         unsigned long v;
 760
 761         if (!(selector & ~3))
 762                 return 0;
 763
 764         table_base = gdt->address;
 765
 766         if (selector & 4) {           /* from ldt */
 767                 u16 ldt_selector = kvm_read_ldt();
 768
 769                 if (!(ldt_selector & ~3))
 770                         return 0;
 771
 772                 table_base = segment_base(ldt_selector);
 773         }
 774         d = (struct desc_struct *)(table_base + (selector & ~7));
 775         v = get_desc_base(d);
 776 #ifdef CONFIG_X86_64
 777        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 778                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 779 #endif
 780         return v;
 781 }
 782
 783 static inline unsigned long kvm_read_tr_base(void)
 784 {
 785         u16 tr;
 786         asm("str %0" : "=g"(tr));
 787         return segment_base(tr);
 788 }
 789
 790 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 791 {
 792         struct vcpu_vmx *vmx = to_vmx(vcpu);
 793         int i;
 794
 795         if (vmx->host_state.loaded)
 796                 return;
 797
 798         vmx->host_state.loaded = 1;
 799         /*
 800          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 801          * allow segment selectors with cpl > 0 or ti == 1.
 802          */
 803         vmx->host_state.ldt_sel = kvm_read_ldt();
 804         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 805         savesegment(fs, vmx->host_state.fs_sel);
 806         if (!(vmx->host_state.fs_sel & 7)) {
 807                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 808                 vmx->host_state.fs_reload_needed = 0;
 809         } else {
 810                 vmcs_write16(HOST_FS_SELECTOR, 0);
 811                 vmx->host_state.fs_reload_needed = 1;
 812         }
 813         savesegment(gs, vmx->host_state.gs_sel);
 814         if (!(vmx->host_state.gs_sel & 7))
 815                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 816         else {
 817                 vmcs_write16(HOST_GS_SELECTOR, 0);
 818                 vmx->host_state.gs_ldt_reload_needed = 1;
 819         }
 820
 821 #ifdef CONFIG_X86_64
 822         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 823         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 824 #else
 825         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 826         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 827 #endif
 828
 829 #ifdef CONFIG_X86_64
 830         if (is_long_mode(&vmx->vcpu)) {
 831                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 832                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 833         }
 834 #endif
 835         for (i = 0; i < vmx->save_nmsrs; ++i)
 836                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 837                                    vmx->guest_msrs[i].data,
 838                                    vmx->guest_msrs[i].mask);
 839 }
 840
 841 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 842 {
 843         if (!vmx->host_state.loaded)
 844                 return;
 845
 846         ++vmx->vcpu.stat.host_state_reload;
 847         vmx->host_state.loaded = 0;
 848         if (vmx->host_state.fs_reload_needed)
 849                 loadsegment(fs, vmx->host_state.fs_sel);
 850         if (vmx->host_state.gs_ldt_reload_needed) {
 851                 kvm_load_ldt(vmx->host_state.ldt_sel);
 852 #ifdef CONFIG_X86_64
 853                 load_gs_index(vmx->host_state.gs_sel);
 854                 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
 855 #else
 856                 loadsegment(gs, vmx->host_state.gs_sel);
 857 #endif
 858         }
 859         reload_tss();
 860 #ifdef CONFIG_X86_64
 861         if (is_long_mode(&vmx->vcpu)) {
 862                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 863                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 864         }
 865 #endif
 866         if (current_thread_info()->status & TS_USEDFPU)
 867                 clts();
 868         load_gdt(&__get_cpu_var(host_gdt));
 869 }
 870
 871 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 872 {
 873         preempt_disable();
 874         __vmx_load_host_state(vmx);
 875         preempt_enable();
 876 }
 877
 878 /*
 879  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 880  * vcpu mutex is already taken.
 881  */
 882 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 883 {
 884         struct vcpu_vmx *vmx = to_vmx(vcpu);
 885         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 886
 887         if (!vmm_exclusive)
 888                 kvm_cpu_vmxon(phys_addr);
 889         else if (vcpu->cpu != cpu)
 890                 vcpu_clear(vmx);
 891
 892         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 893                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 894                 vmcs_load(vmx->vmcs);
 895         }
 896
 897         if (vcpu->cpu != cpu) {
 898                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 899                 unsigned long sysenter_esp;
 900
 901                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 902                 local_irq_disable();
 903                 list_add(&vmx->local_vcpus_link,
 904                          &per_cpu(vcpus_on_cpu, cpu));
 905                 local_irq_enable();
 906
 907                 /*
 908                  * Linux uses per-cpu TSS and GDT, so set these when switching
 909                  * processors.
 910                  */
 911                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 912                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
 913
 914                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 915                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 916         }
 917 }
 918
 919 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 920 {
 921         __vmx_load_host_state(to_vmx(vcpu));
 922         if (!vmm_exclusive) {
 923                 __vcpu_clear(to_vmx(vcpu));
 924                 kvm_cpu_vmxoff();
 925         }
 926 }
 927
 928 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 929 {
 930         ulong cr0;
 931
 932         if (vcpu->fpu_active)
 933                 return;
 934         vcpu->fpu_active = 1;
 935         cr0 = vmcs_readl(GUEST_CR0);
 936         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 937         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 938         vmcs_writel(GUEST_CR0, cr0);
 939         update_exception_bitmap(vcpu);
 940         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 941         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 942 }
 943
 944 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 945
 946 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 947 {
 948         vmx_decache_cr0_guest_bits(vcpu);
 949         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 950         update_exception_bitmap(vcpu);
 951         vcpu->arch.cr0_guest_owned_bits = 0;
 952         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 953         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 954 }
 955
 956 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 957 {
 958         unsigned long rflags, save_rflags;
 959
 960         rflags = vmcs_readl(GUEST_RFLAGS);
 961         if (to_vmx(vcpu)->rmode.vm86_active) {
 962                 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 963                 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 964                 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 965         }
 966         return rflags;
 967 }
 968
 969 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 970 {
 971         if (to_vmx(vcpu)->rmode.vm86_active) {
 972                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 973                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 974         }
 975         vmcs_writel(GUEST_RFLAGS, rflags);
 976 }
 977
 978 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 979 {
 980         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 981         int ret = 0;
 982
 983         if (interruptibility & GUEST_INTR_STATE_STI)
 984                 ret |= KVM_X86_SHADOW_INT_STI;
 985         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 986                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
 987
 988         return ret & mask;
 989 }
 990
 991 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 992 {
 993         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 994         u32 interruptibility = interruptibility_old;
 995
 996         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 997
 998         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
 999                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1000         else if (mask & KVM_X86_SHADOW_INT_STI)
1001                 interruptibility |= GUEST_INTR_STATE_STI;
1002
1003         if ((interruptibility != interruptibility_old))
1004                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1005 }
1006
1007 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1008 {
1009         unsigned long rip;
1010
1011         rip = kvm_rip_read(vcpu);
1012         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1013         kvm_rip_write(vcpu, rip);
1014
1015         /* skipping an emulated instruction also counts */
1016         vmx_set_interrupt_shadow(vcpu, 0);
1017 }
1018
1019 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1020                                 bool has_error_code, u32 error_code,
1021                                 bool reinject)
1022 {
1023         struct vcpu_vmx *vmx = to_vmx(vcpu);
1024         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1025
1026         if (has_error_code) {
1027                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1028                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1029         }
1030
1031         if (vmx->rmode.vm86_active) {
1032                 vmx->rmode.irq.pending = true;
1033                 vmx->rmode.irq.vector = nr;
1034                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
1035                 if (kvm_exception_is_soft(nr))
1036                         vmx->rmode.irq.rip +=
1037                                 vmx->vcpu.arch.event_exit_inst_len;
1038                 intr_info |= INTR_TYPE_SOFT_INTR;
1039                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1040                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1041                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1042                 return;
1043         }
1044
1045         if (kvm_exception_is_soft(nr)) {
1046                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1047                              vmx->vcpu.arch.event_exit_inst_len);
1048                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1049         } else
1050                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1051
1052         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1053 }
1054
1055 static bool vmx_rdtscp_supported(void)
1056 {
1057         return cpu_has_vmx_rdtscp();
1058 }
1059
1060 /*
1061  * Swap MSR entry in host/guest MSR entry array.
1062  */
1063 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1064 {
1065         struct shared_msr_entry tmp;
1066
1067         tmp = vmx->guest_msrs[to];
1068         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1069         vmx->guest_msrs[from] = tmp;
1070 }
1071
1072 /*
1073  * Set up the vmcs to automatically save and restore system
1074  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1075  * mode, as fiddling with msrs is very expensive.
1076  */
1077 static void setup_msrs(struct vcpu_vmx *vmx)
1078 {
1079         int save_nmsrs, index;
1080         unsigned long *msr_bitmap;
1081
1082         vmx_load_host_state(vmx);
1083         save_nmsrs = 0;
1084 #ifdef CONFIG_X86_64
1085         if (is_long_mode(&vmx->vcpu)) {
1086                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1087                 if (index >= 0)
1088                         move_msr_up(vmx, index, save_nmsrs++);
1089                 index = __find_msr_index(vmx, MSR_LSTAR);
1090                 if (index >= 0)
1091                         move_msr_up(vmx, index, save_nmsrs++);
1092                 index = __find_msr_index(vmx, MSR_CSTAR);
1093                 if (index >= 0)
1094                         move_msr_up(vmx, index, save_nmsrs++);
1095                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1096                 if (index >= 0 && vmx->rdtscp_enabled)
1097                         move_msr_up(vmx, index, save_nmsrs++);
1098                 /*
1099                  * MSR_STAR is only needed on long mode guests, and only
1100                  * if efer.sce is enabled.
1101                  */
1102                 index = __find_msr_index(vmx, MSR_STAR);
1103                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1104                         move_msr_up(vmx, index, save_nmsrs++);
1105         }
1106 #endif
1107         index = __find_msr_index(vmx, MSR_EFER);
1108         if (index >= 0 && update_transition_efer(vmx, index))
1109                 move_msr_up(vmx, index, save_nmsrs++);
1110
1111         vmx->save_nmsrs = save_nmsrs;
1112
1113         if (cpu_has_vmx_msr_bitmap()) {
1114                 if (is_long_mode(&vmx->vcpu))
1115                         msr_bitmap = vmx_msr_bitmap_longmode;
1116                 else
1117                         msr_bitmap = vmx_msr_bitmap_legacy;
1118
1119                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1120         }
1121 }
1122
1123 /*
1124  * reads and returns guest's timestamp counter "register"
1125  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1126  */
1127 static u64 guest_read_tsc(void)
1128 {
1129         u64 host_tsc, tsc_offset;
1130
1131         rdtscll(host_tsc);
1132         tsc_offset = vmcs_read64(TSC_OFFSET);
1133         return host_tsc + tsc_offset;
1134 }
1135
1136 /*
1137  * writes 'offset' into guest's timestamp counter offset register
1138  */
1139 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1140 {
1141         vmcs_write64(TSC_OFFSET, offset);
1142 }
1143
1144 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1145 {
1146         u64 offset = vmcs_read64(TSC_OFFSET);
1147         vmcs_write64(TSC_OFFSET, offset + adjustment);
1148 }
1149
1150 /*
1151  * Reads an msr value (of 'msr_index') into 'pdata'.
1152  * Returns 0 on success, non-0 otherwise.
1153  * Assumes vcpu_load() was already called.
1154  */
1155 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1156 {
1157         u64 data;
1158         struct shared_msr_entry *msr;
1159
1160         if (!pdata) {
1161                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1162                 return -EINVAL;
1163         }
1164
1165         switch (msr_index) {
1166 #ifdef CONFIG_X86_64
1167         case MSR_FS_BASE:
1168                 data = vmcs_readl(GUEST_FS_BASE);
1169                 break;
1170         case MSR_GS_BASE:
1171                 data = vmcs_readl(GUEST_GS_BASE);
1172                 break;
1173         case MSR_KERNEL_GS_BASE:
1174                 vmx_load_host_state(to_vmx(vcpu));
1175                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1176                 break;
1177 #endif
1178         case MSR_EFER:
1179                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1180         case MSR_IA32_TSC:
1181                 data = guest_read_tsc();
1182                 break;
1183         case MSR_IA32_SYSENTER_CS:
1184                 data = vmcs_read32(GUEST_SYSENTER_CS);
1185                 break;
1186         case MSR_IA32_SYSENTER_EIP:
1187                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1188                 break;
1189         case MSR_IA32_SYSENTER_ESP:
1190                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1191                 break;
1192         case MSR_TSC_AUX:
1193                 if (!to_vmx(vcpu)->rdtscp_enabled)
1194                         return 1;
1195                 /* Otherwise falls through */
1196         default:
1197                 vmx_load_host_state(to_vmx(vcpu));
1198                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1199                 if (msr) {
1200                         vmx_load_host_state(to_vmx(vcpu));
1201                         data = msr->data;
1202                         break;
1203                 }
1204                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1205         }
1206
1207         *pdata = data;
1208         return 0;
1209 }
1210
1211 /*
1212  * Writes msr value into into the appropriate "register".
1213  * Returns 0 on success, non-0 otherwise.
1214  * Assumes vcpu_load() was already called.
1215  */
1216 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1217 {
1218         struct vcpu_vmx *vmx = to_vmx(vcpu);
1219         struct shared_msr_entry *msr;
1220         int ret = 0;
1221
1222         switch (msr_index) {
1223         case MSR_EFER:
1224                 vmx_load_host_state(vmx);
1225                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1226                 break;
1227 #ifdef CONFIG_X86_64
1228         case MSR_FS_BASE:
1229                 vmcs_writel(GUEST_FS_BASE, data);
1230                 break;
1231         case MSR_GS_BASE:
1232                 vmcs_writel(GUEST_GS_BASE, data);
1233                 break;
1234         case MSR_KERNEL_GS_BASE:
1235                 vmx_load_host_state(vmx);
1236                 vmx->msr_guest_kernel_gs_base = data;
1237                 break;
1238 #endif
1239         case MSR_IA32_SYSENTER_CS:
1240                 vmcs_write32(GUEST_SYSENTER_CS, data);
1241                 break;
1242         case MSR_IA32_SYSENTER_EIP:
1243                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1244                 break;
1245         case MSR_IA32_SYSENTER_ESP:
1246                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1247                 break;
1248         case MSR_IA32_TSC:
1249                 kvm_write_tsc(vcpu, data);
1250                 break;
1251         case MSR_IA32_CR_PAT:
1252                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1253                         vmcs_write64(GUEST_IA32_PAT, data);
1254                         vcpu->arch.pat = data;
1255                         break;
1256                 }
1257                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1258                 break;
1259         case MSR_TSC_AUX:
1260                 if (!vmx->rdtscp_enabled)
1261                         return 1;
1262                 /* Check reserved bit, higher 32 bits should be zero */
1263                 if ((data >> 32) != 0)
1264                         return 1;
1265                 /* Otherwise falls through */
1266         default:
1267                 msr = find_msr_entry(vmx, msr_index);
1268                 if (msr) {
1269                         vmx_load_host_state(vmx);
1270                         msr->data = data;
1271                         break;
1272                 }
1273                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1274         }
1275
1276         return ret;
1277 }
1278
1279 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1280 {
1281         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1282         switch (reg) {
1283         case VCPU_REGS_RSP:
1284                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1285                 break;
1286         case VCPU_REGS_RIP:
1287                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1288                 break;
1289         case VCPU_EXREG_PDPTR:
1290                 if (enable_ept)
1291                         ept_save_pdptrs(vcpu);
1292                 break;
1293         default:
1294                 break;
1295         }
1296 }
1297
1298 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1299 {
1300         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1301                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1302         else
1303                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1304
1305         update_exception_bitmap(vcpu);
1306 }
1307
1308 static __init int cpu_has_kvm_support(void)
1309 {
1310         return cpu_has_vmx();
1311 }
1312
1313 static __init int vmx_disabled_by_bios(void)
1314 {
1315         u64 msr;
1316
1317         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1318         if (msr & FEATURE_CONTROL_LOCKED) {
1319                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1320                         && tboot_enabled())
1321                         return 1;
1322                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1323                         && !tboot_enabled())
1324                         return 1;
1325         }
1326
1327         return 0;
1328         /* locked but not enabled */
1329 }
1330
1331 static void kvm_cpu_vmxon(u64 addr)
1332 {
1333         asm volatile (ASM_VMX_VMXON_RAX
1334                         : : "a"(&addr), "m"(addr)
1335                         : "memory", "cc");
1336 }
1337
1338 static int hardware_enable(void *garbage)
1339 {
1340         int cpu = raw_smp_processor_id();
1341         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1342         u64 old, test_bits;
1343
1344         if (read_cr4() & X86_CR4_VMXE)
1345                 return -EBUSY;
1346
1347         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1348         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1349
1350         test_bits = FEATURE_CONTROL_LOCKED;
1351         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1352         if (tboot_enabled())
1353                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1354
1355         if ((old & test_bits) != test_bits) {
1356                 /* enable and lock */
1357                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1358         }
1359         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1360
1361         if (vmm_exclusive) {
1362                 kvm_cpu_vmxon(phys_addr);
1363                 ept_sync_global();
1364         }
1365
1366         store_gdt(&__get_cpu_var(host_gdt));
1367
1368         return 0;
1369 }
1370
1371 static void vmclear_local_vcpus(void)
1372 {
1373         int cpu = raw_smp_processor_id();
1374         struct vcpu_vmx *vmx, *n;
1375
1376         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1377                                  local_vcpus_link)
1378                 __vcpu_clear(vmx);
1379 }
1380
1381
1382 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1383  * tricks.
1384  */
1385 static void kvm_cpu_vmxoff(void)
1386 {
1387         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1388 }
1389
1390 static void hardware_disable(void *garbage)
1391 {
1392         if (vmm_exclusive) {
1393                 vmclear_local_vcpus();
1394                 kvm_cpu_vmxoff();
1395         }
1396         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1397 }
1398
1399 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1400                                       u32 msr, u32 *result)
1401 {
1402         u32 vmx_msr_low, vmx_msr_high;
1403         u32 ctl = ctl_min | ctl_opt;
1404
1405         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1406
1407         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1408         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1409
1410         /* Ensure minimum (required) set of control bits are supported. */
1411         if (ctl_min & ~ctl)
1412                 return -EIO;
1413
1414         *result = ctl;
1415         return 0;
1416 }
1417
1418 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1419 {
1420         u32 vmx_msr_low, vmx_msr_high;
1421         u32 min, opt, min2, opt2;
1422         u32 _pin_based_exec_control = 0;
1423         u32 _cpu_based_exec_control = 0;
1424         u32 _cpu_based_2nd_exec_control = 0;
1425         u32 _vmexit_control = 0;
1426         u32 _vmentry_control = 0;
1427
1428         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1429         opt = PIN_BASED_VIRTUAL_NMIS;
1430         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1431                                 &_pin_based_exec_control) < 0)
1432                 return -EIO;
1433
1434         min = CPU_BASED_HLT_EXITING |
1435 #ifdef CONFIG_X86_64
1436               CPU_BASED_CR8_LOAD_EXITING |
1437               CPU_BASED_CR8_STORE_EXITING |
1438 #endif
1439               CPU_BASED_CR3_LOAD_EXITING |
1440               CPU_BASED_CR3_STORE_EXITING |
1441               CPU_BASED_USE_IO_BITMAPS |
1442               CPU_BASED_MOV_DR_EXITING |
1443               CPU_BASED_USE_TSC_OFFSETING |
1444               CPU_BASED_MWAIT_EXITING |
1445               CPU_BASED_MONITOR_EXITING |
1446               CPU_BASED_INVLPG_EXITING;
1447         opt = CPU_BASED_TPR_SHADOW |
1448               CPU_BASED_USE_MSR_BITMAPS |
1449               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1450         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1451                                 &_cpu_based_exec_control) < 0)
1452                 return -EIO;
1453 #ifdef CONFIG_X86_64
1454         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1455                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1456                                            ~CPU_BASED_CR8_STORE_EXITING;
1457 #endif
1458         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1459                 min2 = 0;
1460                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1461                         SECONDARY_EXEC_WBINVD_EXITING |
1462                         SECONDARY_EXEC_ENABLE_VPID |
1463                         SECONDARY_EXEC_ENABLE_EPT |
1464                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1465                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1466                         SECONDARY_EXEC_RDTSCP;
1467                 if (adjust_vmx_controls(min2, opt2,
1468                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1469                                         &_cpu_based_2nd_exec_control) < 0)
1470                         return -EIO;
1471         }
1472 #ifndef CONFIG_X86_64
1473         if (!(_cpu_based_2nd_exec_control &
1474                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1475                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1476 #endif
1477         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1478                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1479                    enabled */
1480                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1481                                              CPU_BASED_CR3_STORE_EXITING |
1482                                              CPU_BASED_INVLPG_EXITING);
1483                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1484                       vmx_capability.ept, vmx_capability.vpid);
1485         }
1486
1487         min = 0;
1488 #ifdef CONFIG_X86_64
1489         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1490 #endif
1491         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1492         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1493                                 &_vmexit_control) < 0)
1494                 return -EIO;
1495
1496         min = 0;
1497         opt = VM_ENTRY_LOAD_IA32_PAT;
1498         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1499                                 &_vmentry_control) < 0)
1500                 return -EIO;
1501
1502         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1503
1504         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1505         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1506                 return -EIO;
1507
1508 #ifdef CONFIG_X86_64
1509         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1510         if (vmx_msr_high & (1u<<16))
1511                 return -EIO;
1512 #endif
1513
1514         /* Require Write-Back (WB) memory type for VMCS accesses. */
1515         if (((vmx_msr_high >> 18) & 15) != 6)
1516                 return -EIO;
1517
1518         vmcs_conf->size = vmx_msr_high & 0x1fff;
1519         vmcs_conf->order = get_order(vmcs_config.size);
1520         vmcs_conf->revision_id = vmx_msr_low;
1521
1522         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1523         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1524         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1525         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1526         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1527
1528         return 0;
1529 }
1530
1531 static struct vmcs *alloc_vmcs_cpu(int cpu)
1532 {
1533         int node = cpu_to_node(cpu);
1534         struct page *pages;
1535         struct vmcs *vmcs;
1536
1537         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1538         if (!pages)
1539                 return NULL;
1540         vmcs = page_address(pages);
1541         memset(vmcs, 0, vmcs_config.size);
1542         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1543         return vmcs;
1544 }
1545
1546 static struct vmcs *alloc_vmcs(void)
1547 {
1548         return alloc_vmcs_cpu(raw_smp_processor_id());
1549 }
1550
1551 static void free_vmcs(struct vmcs *vmcs)
1552 {
1553         free_pages((unsigned long)vmcs, vmcs_config.order);
1554 }
1555
1556 static void free_kvm_area(void)
1557 {
1558         int cpu;
1559
1560         for_each_possible_cpu(cpu) {
1561                 free_vmcs(per_cpu(vmxarea, cpu));
1562                 per_cpu(vmxarea, cpu) = NULL;
1563         }
1564 }
1565
1566 static __init int alloc_kvm_area(void)
1567 {
1568         int cpu;
1569
1570         for_each_possible_cpu(cpu) {
1571                 struct vmcs *vmcs;
1572
1573                 vmcs = alloc_vmcs_cpu(cpu);
1574                 if (!vmcs) {
1575                         free_kvm_area();
1576                         return -ENOMEM;
1577                 }
1578
1579                 per_cpu(vmxarea, cpu) = vmcs;
1580         }
1581         return 0;
1582 }
1583
1584 static __init int hardware_setup(void)
1585 {
1586         if (setup_vmcs_config(&vmcs_config) < 0)
1587                 return -EIO;
1588
1589         if (boot_cpu_has(X86_FEATURE_NX))
1590                 kvm_enable_efer_bits(EFER_NX);
1591
1592         if (!cpu_has_vmx_vpid())
1593                 enable_vpid = 0;
1594
1595         if (!cpu_has_vmx_ept() ||
1596             !cpu_has_vmx_ept_4levels()) {
1597                 enable_ept = 0;
1598                 enable_unrestricted_guest = 0;
1599         }
1600
1601         if (!cpu_has_vmx_unrestricted_guest())
1602                 enable_unrestricted_guest = 0;
1603
1604         if (!cpu_has_vmx_flexpriority())
1605                 flexpriority_enabled = 0;
1606
1607         if (!cpu_has_vmx_tpr_shadow())
1608                 kvm_x86_ops->update_cr8_intercept = NULL;
1609
1610         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1611                 kvm_disable_largepages();
1612
1613         if (!cpu_has_vmx_ple())
1614                 ple_gap = 0;
1615
1616         return alloc_kvm_area();
1617 }
1618
1619 static __exit void hardware_unsetup(void)
1620 {
1621         free_kvm_area();
1622 }
1623
1624 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1625 {
1626         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1627
1628         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1629                 vmcs_write16(sf->selector, save->selector);
1630                 vmcs_writel(sf->base, save->base);
1631                 vmcs_write32(sf->limit, save->limit);
1632                 vmcs_write32(sf->ar_bytes, save->ar);
1633         } else {
1634                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1635                         << AR_DPL_SHIFT;
1636                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1637         }
1638 }
1639
1640 static void enter_pmode(struct kvm_vcpu *vcpu)
1641 {
1642         unsigned long flags;
1643         struct vcpu_vmx *vmx = to_vmx(vcpu);
1644
1645         vmx->emulation_required = 1;
1646         vmx->rmode.vm86_active = 0;
1647
1648         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1649         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1650         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1651
1652         flags = vmcs_readl(GUEST_RFLAGS);
1653         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1654         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1655         vmcs_writel(GUEST_RFLAGS, flags);
1656
1657         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1658                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1659
1660         update_exception_bitmap(vcpu);
1661
1662         if (emulate_invalid_guest_state)
1663                 return;
1664
1665         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1666         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1667         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1668         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1669
1670         vmcs_write16(GUEST_SS_SELECTOR, 0);
1671         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1672
1673         vmcs_write16(GUEST_CS_SELECTOR,
1674                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1675         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1676 }
1677
1678 static gva_t rmode_tss_base(struct kvm *kvm)
1679 {
1680         if (!kvm->arch.tss_addr) {
1681                 struct kvm_memslots *slots;
1682                 gfn_t base_gfn;
1683
1684                 slots = kvm_memslots(kvm);
1685                 base_gfn = slots->memslots[0].base_gfn +
1686                                  kvm->memslots->memslots[0].npages - 3;
1687                 return base_gfn << PAGE_SHIFT;
1688         }
1689         return kvm->arch.tss_addr;
1690 }
1691
1692 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1693 {
1694         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1695
1696         save->selector = vmcs_read16(sf->selector);
1697         save->base = vmcs_readl(sf->base);
1698         save->limit = vmcs_read32(sf->limit);
1699         save->ar = vmcs_read32(sf->ar_bytes);
1700         vmcs_write16(sf->selector, save->base >> 4);
1701         vmcs_write32(sf->base, save->base & 0xfffff);
1702         vmcs_write32(sf->limit, 0xffff);
1703         vmcs_write32(sf->ar_bytes, 0xf3);
1704 }
1705
1706 static void enter_rmode(struct kvm_vcpu *vcpu)
1707 {
1708         unsigned long flags;
1709         struct vcpu_vmx *vmx = to_vmx(vcpu);
1710
1711         if (enable_unrestricted_guest)
1712                 return;
1713
1714         vmx->emulation_required = 1;
1715         vmx->rmode.vm86_active = 1;
1716
1717         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1718         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1719
1720         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1721         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1722
1723         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1724         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1725
1726         flags = vmcs_readl(GUEST_RFLAGS);
1727         vmx->rmode.save_rflags = flags;
1728
1729         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1730
1731         vmcs_writel(GUEST_RFLAGS, flags);
1732         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1733         update_exception_bitmap(vcpu);
1734
1735         if (emulate_invalid_guest_state)
1736                 goto continue_rmode;
1737
1738         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1739         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1740         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1741
1742         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1743         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1744         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1745                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1746         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1747
1748         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1749         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1750         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1751         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1752
1753 continue_rmode:
1754         kvm_mmu_reset_context(vcpu);
1755         init_rmode(vcpu->kvm);
1756 }
1757
1758 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1759 {
1760         struct vcpu_vmx *vmx = to_vmx(vcpu);
1761         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1762
1763         if (!msr)
1764                 return;
1765
1766         /*
1767          * Force kernel_gs_base reloading before EFER changes, as control
1768          * of this msr depends on is_long_mode().
1769          */
1770         vmx_load_host_state(to_vmx(vcpu));
1771         vcpu->arch.efer = efer;
1772         if (efer & EFER_LMA) {
1773                 vmcs_write32(VM_ENTRY_CONTROLS,
1774                              vmcs_read32(VM_ENTRY_CONTROLS) |
1775                              VM_ENTRY_IA32E_MODE);
1776                 msr->data = efer;
1777         } else {
1778                 vmcs_write32(VM_ENTRY_CONTROLS,
1779                              vmcs_read32(VM_ENTRY_CONTROLS) &
1780                              ~VM_ENTRY_IA32E_MODE);
1781
1782                 msr->data = efer & ~EFER_LME;
1783         }
1784         setup_msrs(vmx);
1785 }
1786
1787 #ifdef CONFIG_X86_64
1788
1789 static void enter_lmode(struct kvm_vcpu *vcpu)
1790 {
1791         u32 guest_tr_ar;
1792
1793         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1794         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1795                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1796                        __func__);
1797                 vmcs_write32(GUEST_TR_AR_BYTES,
1798                              (guest_tr_ar & ~AR_TYPE_MASK)
1799                              | AR_TYPE_BUSY_64_TSS);
1800         }
1801         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1802 }
1803
1804 static void exit_lmode(struct kvm_vcpu *vcpu)
1805 {
1806         vmcs_write32(VM_ENTRY_CONTROLS,
1807                      vmcs_read32(VM_ENTRY_CONTROLS)
1808                      & ~VM_ENTRY_IA32E_MODE);
1809         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1810 }
1811
1812 #endif
1813
1814 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1815 {
1816         vpid_sync_context(to_vmx(vcpu));
1817         if (enable_ept) {
1818                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1819                         return;
1820                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1821         }
1822 }
1823
1824 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1825 {
1826         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1827
1828         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1829         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1830 }
1831
1832 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1833 {
1834         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1835
1836         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1837         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1838 }
1839
1840 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1841 {
1842         if (!test_bit(VCPU_EXREG_PDPTR,
1843                       (unsigned long *)&vcpu->arch.regs_dirty))
1844                 return;
1845
1846         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1847                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1848                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1849                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1850                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1851         }
1852 }
1853
1854 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1855 {
1856         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1857                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1858                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1859                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1860                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1861         }
1862
1863         __set_bit(VCPU_EXREG_PDPTR,
1864                   (unsigned long *)&vcpu->arch.regs_avail);
1865         __set_bit(VCPU_EXREG_PDPTR,
1866                   (unsigned long *)&vcpu->arch.regs_dirty);
1867 }
1868
1869 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1870
1871 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1872                                         unsigned long cr0,
1873                                         struct kvm_vcpu *vcpu)
1874 {
1875         if (!(cr0 & X86_CR0_PG)) {
1876                 /* From paging/starting to nonpaging */
1877                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1878                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1879                              (CPU_BASED_CR3_LOAD_EXITING |
1880                               CPU_BASED_CR3_STORE_EXITING));
1881                 vcpu->arch.cr0 = cr0;
1882                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1883         } else if (!is_paging(vcpu)) {
1884                 /* From nonpaging to paging */
1885                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1886                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1887                              ~(CPU_BASED_CR3_LOAD_EXITING |
1888                                CPU_BASED_CR3_STORE_EXITING));
1889                 vcpu->arch.cr0 = cr0;
1890                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1891         }
1892
1893         if (!(cr0 & X86_CR0_WP))
1894                 *hw_cr0 &= ~X86_CR0_WP;
1895 }
1896
1897 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1898 {
1899         struct vcpu_vmx *vmx = to_vmx(vcpu);
1900         unsigned long hw_cr0;
1901
1902         if (enable_unrestricted_guest)
1903                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1904                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1905         else
1906                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1907
1908         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1909                 enter_pmode(vcpu);
1910
1911         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1912                 enter_rmode(vcpu);
1913
1914 #ifdef CONFIG_X86_64
1915         if (vcpu->arch.efer & EFER_LME) {
1916                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1917                         enter_lmode(vcpu);
1918                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1919                         exit_lmode(vcpu);
1920         }
1921 #endif
1922
1923         if (enable_ept)
1924                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1925
1926         if (!vcpu->fpu_active)
1927                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1928
1929         vmcs_writel(CR0_READ_SHADOW, cr0);
1930         vmcs_writel(GUEST_CR0, hw_cr0);
1931         vcpu->arch.cr0 = cr0;
1932 }
1933
1934 static u64 construct_eptp(unsigned long root_hpa)
1935 {
1936         u64 eptp;
1937
1938         /* TODO write the value reading from MSR */
1939         eptp = VMX_EPT_DEFAULT_MT |
1940                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1941         eptp |= (root_hpa & PAGE_MASK);
1942
1943         return eptp;
1944 }
1945
1946 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1947 {
1948         unsigned long guest_cr3;
1949         u64 eptp;
1950
1951         guest_cr3 = cr3;
1952         if (enable_ept) {
1953                 eptp = construct_eptp(cr3);
1954                 vmcs_write64(EPT_POINTER, eptp);
1955                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1956                         vcpu->kvm->arch.ept_identity_map_addr;
1957                 ept_load_pdptrs(vcpu);
1958         }
1959
1960         vmx_flush_tlb(vcpu);
1961         vmcs_writel(GUEST_CR3, guest_cr3);
1962 }
1963
1964 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1965 {
1966         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1967                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1968
1969         vcpu->arch.cr4 = cr4;
1970         if (enable_ept) {
1971                 if (!is_paging(vcpu)) {
1972                         hw_cr4 &= ~X86_CR4_PAE;
1973                         hw_cr4 |= X86_CR4_PSE;
1974                 } else if (!(cr4 & X86_CR4_PAE)) {
1975                         hw_cr4 &= ~X86_CR4_PAE;
1976                 }
1977         }
1978
1979         vmcs_writel(CR4_READ_SHADOW, cr4);
1980         vmcs_writel(GUEST_CR4, hw_cr4);
1981 }
1982
1983 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1984 {
1985         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1986
1987         return vmcs_readl(sf->base);
1988 }
1989
1990 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1991                             struct kvm_segment *var, int seg)
1992 {
1993         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1994         u32 ar;
1995
1996         var->base = vmcs_readl(sf->base);
1997         var->limit = vmcs_read32(sf->limit);
1998         var->selector = vmcs_read16(sf->selector);
1999         ar = vmcs_read32(sf->ar_bytes);
2000         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2001                 ar = 0;
2002         var->type = ar & 15;
2003         var->s = (ar >> 4) & 1;
2004         var->dpl = (ar >> 5) & 3;
2005         var->present = (ar >> 7) & 1;
2006         var->avl = (ar >> 12) & 1;
2007         var->l = (ar >> 13) & 1;
2008         var->db = (ar >> 14) & 1;
2009         var->g = (ar >> 15) & 1;
2010         var->unusable = (ar >> 16) & 1;
2011 }
2012
2013 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2014 {
2015         if (!is_protmode(vcpu))
2016                 return 0;
2017
2018         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2019                 return 3;
2020
2021         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2022 }
2023
2024 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2025 {
2026         u32 ar;
2027
2028         if (var->unusable)
2029                 ar = 1 << 16;
2030         else {
2031                 ar = var->type & 15;
2032                 ar |= (var->s & 1) << 4;
2033                 ar |= (var->dpl & 3) << 5;
2034                 ar |= (var->present & 1) << 7;
2035                 ar |= (var->avl & 1) << 12;
2036                 ar |= (var->l & 1) << 13;
2037                 ar |= (var->db & 1) << 14;
2038                 ar |= (var->g & 1) << 15;
2039         }
2040         if (ar == 0) /* a 0 value means unusable */
2041                 ar = AR_UNUSABLE_MASK;
2042
2043         return ar;
2044 }
2045
2046 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2047                             struct kvm_segment *var, int seg)
2048 {
2049         struct vcpu_vmx *vmx = to_vmx(vcpu);
2050         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2051         u32 ar;
2052
2053         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2054                 vmx->rmode.tr.selector = var->selector;
2055                 vmx->rmode.tr.base = var->base;
2056                 vmx->rmode.tr.limit = var->limit;
2057                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2058                 return;
2059         }
2060         vmcs_writel(sf->base, var->base);
2061         vmcs_write32(sf->limit, var->limit);
2062         vmcs_write16(sf->selector, var->selector);
2063         if (vmx->rmode.vm86_active && var->s) {
2064                 /*
2065                  * Hack real-mode segments into vm86 compatibility.
2066                  */
2067                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2068                         vmcs_writel(sf->base, 0xf0000);
2069                 ar = 0xf3;
2070         } else
2071                 ar = vmx_segment_access_rights(var);
2072
2073         /*
2074          *   Fix the "Accessed" bit in AR field of segment registers for older
2075          * qemu binaries.
2076          *   IA32 arch specifies that at the time of processor reset the
2077          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2078          * is setting it to 0 in the usedland code. This causes invalid guest
2079          * state vmexit when "unrestricted guest" mode is turned on.
2080          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2081          * tree. Newer qemu binaries with that qemu fix would not need this
2082          * kvm hack.
2083          */
2084         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2085                 ar |= 0x1; /* Accessed */
2086
2087         vmcs_write32(sf->ar_bytes, ar);
2088 }
2089
2090 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2091 {
2092         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2093
2094         *db = (ar >> 14) & 1;
2095         *l = (ar >> 13) & 1;
2096 }
2097
2098 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2099 {
2100         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2101         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2102 }
2103
2104 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2105 {
2106         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2107         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2108 }
2109
2110 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2111 {
2112         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2113         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2114 }
2115
2116 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2117 {
2118         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2119         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2120 }
2121
2122 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2123 {
2124         struct kvm_segment var;
2125         u32 ar;
2126
2127         vmx_get_segment(vcpu, &var, seg);
2128         ar = vmx_segment_access_rights(&var);
2129
2130         if (var.base != (var.selector << 4))
2131                 return false;
2132         if (var.limit != 0xffff)
2133                 return false;
2134         if (ar != 0xf3)
2135                 return false;
2136
2137         return true;
2138 }
2139
2140 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2141 {
2142         struct kvm_segment cs;
2143         unsigned int cs_rpl;
2144
2145         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2146         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2147
2148         if (cs.unusable)
2149                 return false;
2150         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2151                 return false;
2152         if (!cs.s)
2153                 return false;
2154         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2155                 if (cs.dpl > cs_rpl)
2156                         return false;
2157         } else {
2158                 if (cs.dpl != cs_rpl)
2159                         return false;
2160         }
2161         if (!cs.present)
2162                 return false;
2163
2164         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2165         return true;
2166 }
2167
2168 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2169 {
2170         struct kvm_segment ss;
2171         unsigned int ss_rpl;
2172
2173         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2174         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2175
2176         if (ss.unusable)
2177                 return true;
2178         if (ss.type != 3 && ss.type != 7)
2179                 return false;
2180         if (!ss.s)
2181                 return false;
2182         if (ss.dpl != ss_rpl) /* DPL != RPL */
2183                 return false;
2184         if (!ss.present)
2185                 return false;
2186
2187         return true;
2188 }
2189
2190 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2191 {
2192         struct kvm_segment var;
2193         unsigned int rpl;
2194
2195         vmx_get_segment(vcpu, &var, seg);
2196         rpl = var.selector & SELECTOR_RPL_MASK;
2197
2198         if (var.unusable)
2199                 return true;
2200         if (!var.s)
2201                 return false;
2202         if (!var.present)
2203                 return false;
2204         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2205                 if (var.dpl < rpl) /* DPL < RPL */
2206                         return false;
2207         }
2208
2209         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2210          * rights flags
2211          */
2212         return true;
2213 }
2214
2215 static bool tr_valid(struct kvm_vcpu *vcpu)
2216 {
2217         struct kvm_segment tr;
2218
2219         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2220
2221         if (tr.unusable)
2222                 return false;
2223         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2224                 return false;
2225         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2226                 return false;
2227         if (!tr.present)
2228                 return false;
2229
2230         return true;
2231 }
2232
2233 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2234 {
2235         struct kvm_segment ldtr;
2236
2237         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2238
2239         if (ldtr.unusable)
2240                 return true;
2241         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2242                 return false;
2243         if (ldtr.type != 2)
2244                 return false;
2245         if (!ldtr.present)
2246                 return false;
2247
2248         return true;
2249 }
2250
2251 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2252 {
2253         struct kvm_segment cs, ss;
2254
2255         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2256         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2257
2258         return ((cs.selector & SELECTOR_RPL_MASK) ==
2259                  (ss.selector & SELECTOR_RPL_MASK));
2260 }
2261
2262 /*
2263  * Check if guest state is valid. Returns true if valid, false if
2264  * not.
2265  * We assume that registers are always usable
2266  */
2267 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2268 {
2269         /* real mode guest state checks */
2270         if (!is_protmode(vcpu)) {
2271                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2272                         return false;
2273                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2274                         return false;
2275                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2276                         return false;
2277                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2278                         return false;
2279                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2280                         return false;
2281                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2282                         return false;
2283         } else {
2284         /* protected mode guest state checks */
2285                 if (!cs_ss_rpl_check(vcpu))
2286                         return false;
2287                 if (!code_segment_valid(vcpu))
2288                         return false;
2289                 if (!stack_segment_valid(vcpu))
2290                         return false;
2291                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2292                         return false;
2293                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2294                         return false;
2295                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2296                         return false;
2297                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2298                         return false;
2299                 if (!tr_valid(vcpu))
2300                         return false;
2301                 if (!ldtr_valid(vcpu))
2302                         return false;
2303         }
2304         /* TODO:
2305          * - Add checks on RIP
2306          * - Add checks on RFLAGS
2307          */
2308
2309         return true;
2310 }
2311
2312 static int init_rmode_tss(struct kvm *kvm)
2313 {
2314         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2315         u16 data = 0;
2316         int ret = 0;
2317         int r;
2318
2319         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2320         if (r < 0)
2321                 goto out;
2322         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2323         r = kvm_write_guest_page(kvm, fn++, &data,
2324                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2325         if (r < 0)
2326                 goto out;
2327         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2328         if (r < 0)
2329                 goto out;
2330         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2331         if (r < 0)
2332                 goto out;
2333         data = ~0;
2334         r = kvm_write_guest_page(kvm, fn, &data,
2335                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2336                                  sizeof(u8));
2337         if (r < 0)
2338                 goto out;
2339
2340         ret = 1;
2341 out:
2342         return ret;
2343 }
2344
2345 static int init_rmode_identity_map(struct kvm *kvm)
2346 {
2347         int i, r, ret;
2348         pfn_t identity_map_pfn;
2349         u32 tmp;
2350
2351         if (!enable_ept)
2352                 return 1;
2353         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2354                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2355                         "haven't been allocated!\n");
2356                 return 0;
2357         }
2358         if (likely(kvm->arch.ept_identity_pagetable_done))
2359                 return 1;
2360         ret = 0;
2361         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2362         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2363         if (r < 0)
2364                 goto out;
2365         /* Set up identity-mapping pagetable for EPT in real mode */
2366         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2367                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2368                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2369                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2370                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2371                 if (r < 0)
2372                         goto out;
2373         }
2374         kvm->arch.ept_identity_pagetable_done = true;
2375         ret = 1;
2376 out:
2377         return ret;
2378 }
2379
2380 static void seg_setup(int seg)
2381 {
2382         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2383         unsigned int ar;
2384
2385         vmcs_write16(sf->selector, 0);
2386         vmcs_writel(sf->base, 0);
2387         vmcs_write32(sf->limit, 0xffff);
2388         if (enable_unrestricted_guest) {
2389                 ar = 0x93;
2390                 if (seg == VCPU_SREG_CS)
2391                         ar |= 0x08; /* code segment */
2392         } else
2393                 ar = 0xf3;
2394
2395         vmcs_write32(sf->ar_bytes, ar);
2396 }
2397
2398 static int alloc_apic_access_page(struct kvm *kvm)
2399 {
2400         struct kvm_userspace_memory_region kvm_userspace_mem;
2401         int r = 0;
2402
2403         mutex_lock(&kvm->slots_lock);
2404         if (kvm->arch.apic_access_page)
2405                 goto out;
2406         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2407         kvm_userspace_mem.flags = 0;
2408         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2409         kvm_userspace_mem.memory_size = PAGE_SIZE;
2410         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2411         if (r)
2412                 goto out;
2413
2414         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2415 out:
2416         mutex_unlock(&kvm->slots_lock);
2417         return r;
2418 }
2419
2420 static int alloc_identity_pagetable(struct kvm *kvm)
2421 {
2422         struct kvm_userspace_memory_region kvm_userspace_mem;
2423         int r = 0;
2424
2425         mutex_lock(&kvm->slots_lock);
2426         if (kvm->arch.ept_identity_pagetable)
2427                 goto out;
2428         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2429         kvm_userspace_mem.flags = 0;
2430         kvm_userspace_mem.guest_phys_addr =
2431                 kvm->arch.ept_identity_map_addr;
2432         kvm_userspace_mem.memory_size = PAGE_SIZE;
2433         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2434         if (r)
2435                 goto out;
2436
2437         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2438                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2439 out:
2440         mutex_unlock(&kvm->slots_lock);
2441         return r;
2442 }
2443
2444 static void allocate_vpid(struct vcpu_vmx *vmx)
2445 {
2446         int vpid;
2447
2448         vmx->vpid = 0;
2449         if (!enable_vpid)
2450                 return;
2451         spin_lock(&vmx_vpid_lock);
2452         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2453         if (vpid < VMX_NR_VPIDS) {
2454                 vmx->vpid = vpid;
2455                 __set_bit(vpid, vmx_vpid_bitmap);
2456         }
2457         spin_unlock(&vmx_vpid_lock);
2458 }
2459
2460 static void free_vpid(struct vcpu_vmx *vmx)
2461 {
2462         if (!enable_vpid)
2463                 return;
2464         spin_lock(&vmx_vpid_lock);
2465         if (vmx->vpid != 0)
2466                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2467         spin_unlock(&vmx_vpid_lock);
2468 }
2469
2470 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2471 {
2472         int f = sizeof(unsigned long);
2473
2474         if (!cpu_has_vmx_msr_bitmap())
2475                 return;
2476
2477         /*
2478          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2479          * have the write-low and read-high bitmap offsets the wrong way round.
2480          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2481          */
2482         if (msr <= 0x1fff) {
2483                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2484                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2485         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2486                 msr &= 0x1fff;
2487                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2488                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2489         }
2490 }
2491
2492 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2493 {
2494         if (!longmode_only)
2495                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2496         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2497 }
2498
2499 /*
2500  * Sets up the vmcs for emulated real mode.
2501  */
2502 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2503 {
2504         u32 host_sysenter_cs, msr_low, msr_high;
2505         u32 junk;
2506         u64 host_pat;
2507         unsigned long a;
2508         struct desc_ptr dt;
2509         int i;
2510         unsigned long kvm_vmx_return;
2511         u32 exec_control;
2512
2513         /* I/O */
2514         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2515         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2516
2517         if (cpu_has_vmx_msr_bitmap())
2518                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2519
2520         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2521
2522         /* Control */
2523         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2524                 vmcs_config.pin_based_exec_ctrl);
2525
2526         exec_control = vmcs_config.cpu_based_exec_ctrl;
2527         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2528                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2529 #ifdef CONFIG_X86_64
2530                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2531                                 CPU_BASED_CR8_LOAD_EXITING;
2532 #endif
2533         }
2534         if (!enable_ept)
2535                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2536                                 CPU_BASED_CR3_LOAD_EXITING  |
2537                                 CPU_BASED_INVLPG_EXITING;
2538         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2539
2540         if (cpu_has_secondary_exec_ctrls()) {
2541                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2542                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2543                         exec_control &=
2544                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2545                 if (vmx->vpid == 0)
2546                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2547                 if (!enable_ept) {
2548                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2549                         enable_unrestricted_guest = 0;
2550                 }
2551                 if (!enable_unrestricted_guest)
2552                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2553                 if (!ple_gap)
2554                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2555                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2556         }
2557
2558         if (ple_gap) {
2559                 vmcs_write32(PLE_GAP, ple_gap);
2560                 vmcs_write32(PLE_WINDOW, ple_window);
2561         }
2562
2563         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2564         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2565         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2566
2567         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2568         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2569         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2570
2571         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2572         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2573         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2574         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
2575         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
2576         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2577 #ifdef CONFIG_X86_64
2578         rdmsrl(MSR_FS_BASE, a);
2579         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2580         rdmsrl(MSR_GS_BASE, a);
2581         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2582 #else
2583         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2584         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2585 #endif
2586
2587         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2588
2589         native_store_idt(&dt);
2590         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2591
2592         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2593         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2594         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2595         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2596         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2597         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2598         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2599
2600         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2601         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2602         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2603         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2604         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2605         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2606
2607         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2608                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2609                 host_pat = msr_low | ((u64) msr_high << 32);
2610                 vmcs_write64(HOST_IA32_PAT, host_pat);
2611         }
2612         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2613                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2614                 host_pat = msr_low | ((u64) msr_high << 32);
2615                 /* Write the default value follow host pat */
2616                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2617                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2618                 vmx->vcpu.arch.pat = host_pat;
2619         }
2620
2621         for (i = 0; i < NR_VMX_MSR; ++i) {
2622                 u32 index = vmx_msr_index[i];
2623                 u32 data_low, data_high;
2624                 int j = vmx->nmsrs;
2625
2626                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2627                         continue;
2628                 if (wrmsr_safe(index, data_low, data_high) < 0)
2629                         continue;
2630                 vmx->guest_msrs[j].index = i;
2631                 vmx->guest_msrs[j].data = 0;
2632                 vmx->guest_msrs[j].mask = -1ull;
2633                 ++vmx->nmsrs;
2634         }
2635
2636         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2637
2638         /* 22.2.1, 20.8.1 */
2639         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2640
2641         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2642         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2643         if (enable_ept)
2644                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2645         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2646
2647         kvm_write_tsc(&vmx->vcpu, 0);
2648
2649         return 0;
2650 }
2651
2652 static int init_rmode(struct kvm *kvm)
2653 {
2654         int idx, ret = 0;
2655
2656         idx = srcu_read_lock(&kvm->srcu);
2657         if (!init_rmode_tss(kvm))
2658                 goto exit;
2659         if (!init_rmode_identity_map(kvm))
2660                 goto exit;
2661
2662         ret = 1;
2663 exit:
2664         srcu_read_unlock(&kvm->srcu, idx);
2665         return ret;
2666 }
2667
2668 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2669 {
2670         struct vcpu_vmx *vmx = to_vmx(vcpu);
2671         u64 msr;
2672         int ret;
2673
2674         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2675         if (!init_rmode(vmx->vcpu.kvm)) {
2676                 ret = -ENOMEM;
2677                 goto out;
2678         }
2679
2680         vmx->rmode.vm86_active = 0;
2681
2682         vmx->soft_vnmi_blocked = 0;
2683
2684         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2685         kvm_set_cr8(&vmx->vcpu, 0);
2686         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2687         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2688                 msr |= MSR_IA32_APICBASE_BSP;
2689         kvm_set_apic_base(&vmx->vcpu, msr);
2690
2691         ret = fx_init(&vmx->vcpu);
2692         if (ret != 0)
2693                 goto out;
2694
2695         seg_setup(VCPU_SREG_CS);
2696         /*
2697          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2698          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2699          */
2700         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2701                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2702                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2703         } else {
2704                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2705                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2706         }
2707
2708         seg_setup(VCPU_SREG_DS);
2709         seg_setup(VCPU_SREG_ES);
2710         seg_setup(VCPU_SREG_FS);
2711         seg_setup(VCPU_SREG_GS);
2712         seg_setup(VCPU_SREG_SS);
2713
2714         vmcs_write16(GUEST_TR_SELECTOR, 0);
2715         vmcs_writel(GUEST_TR_BASE, 0);
2716         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2717         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2718
2719         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2720         vmcs_writel(GUEST_LDTR_BASE, 0);
2721         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2722         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2723
2724         vmcs_write32(GUEST_SYSENTER_CS, 0);
2725         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2726         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2727
2728         vmcs_writel(GUEST_RFLAGS, 0x02);
2729         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2730                 kvm_rip_write(vcpu, 0xfff0);
2731         else
2732                 kvm_rip_write(vcpu, 0);
2733         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2734
2735         vmcs_writel(GUEST_DR7, 0x400);
2736
2737         vmcs_writel(GUEST_GDTR_BASE, 0);
2738         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2739
2740         vmcs_writel(GUEST_IDTR_BASE, 0);
2741         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2742
2743         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2744         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2745         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2746
2747         /* Special registers */
2748         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2749
2750         setup_msrs(vmx);
2751
2752         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2753
2754         if (cpu_has_vmx_tpr_shadow()) {
2755                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2756                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2757                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2758                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2759                 vmcs_write32(TPR_THRESHOLD, 0);
2760         }
2761
2762         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2763                 vmcs_write64(APIC_ACCESS_ADDR,
2764                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2765
2766         if (vmx->vpid != 0)
2767                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2768
2769         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2770         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2771         vmx_set_cr4(&vmx->vcpu, 0);
2772         vmx_set_efer(&vmx->vcpu, 0);
2773         vmx_fpu_activate(&vmx->vcpu);
2774         update_exception_bitmap(&vmx->vcpu);
2775
2776         vpid_sync_context(vmx);
2777
2778         ret = 0;
2779
2780         /* HACK: Don't enable emulation on guest boot/reset */
2781         vmx->emulation_required = 0;
2782
2783 out:
2784         return ret;
2785 }
2786
2787 static void enable_irq_window(struct kvm_vcpu *vcpu)
2788 {
2789         u32 cpu_based_vm_exec_control;
2790
2791         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2792         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2793         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2794 }
2795
2796 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2797 {
2798         u32 cpu_based_vm_exec_control;
2799
2800         if (!cpu_has_virtual_nmis()) {
2801                 enable_irq_window(vcpu);
2802                 return;
2803         }
2804
2805         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2806         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2807         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2808 }
2809
2810 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2811 {
2812         struct vcpu_vmx *vmx = to_vmx(vcpu);
2813         uint32_t intr;
2814         int irq = vcpu->arch.interrupt.nr;
2815
2816         trace_kvm_inj_virq(irq);
2817
2818         ++vcpu->stat.irq_injections;
2819         if (vmx->rmode.vm86_active) {
2820                 vmx->rmode.irq.pending = true;
2821                 vmx->rmode.irq.vector = irq;
2822                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2823                 if (vcpu->arch.interrupt.soft)
2824                         vmx->rmode.irq.rip +=
2825                                 vmx->vcpu.arch.event_exit_inst_len;
2826                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2827                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2828                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2829                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2830                 return;
2831         }
2832         intr = irq | INTR_INFO_VALID_MASK;
2833         if (vcpu->arch.interrupt.soft) {
2834                 intr |= INTR_TYPE_SOFT_INTR;
2835                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2836                              vmx->vcpu.arch.event_exit_inst_len);
2837         } else
2838                 intr |= INTR_TYPE_EXT_INTR;
2839         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2840 }
2841
2842 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2843 {
2844         struct vcpu_vmx *vmx = to_vmx(vcpu);
2845
2846         if (!cpu_has_virtual_nmis()) {
2847                 /*
2848                  * Tracking the NMI-blocked state in software is built upon
2849                  * finding the next open IRQ window. This, in turn, depends on
2850                  * well-behaving guests: They have to keep IRQs disabled at
2851                  * least as long as the NMI handler runs. Otherwise we may
2852                  * cause NMI nesting, maybe breaking the guest. But as this is
2853                  * highly unlikely, we can live with the residual risk.
2854                  */
2855                 vmx->soft_vnmi_blocked = 1;
2856                 vmx->vnmi_blocked_time = 0;
2857         }
2858
2859         ++vcpu->stat.nmi_injections;
2860         if (vmx->rmode.vm86_active) {
2861                 vmx->rmode.irq.pending = true;
2862                 vmx->rmode.irq.vector = NMI_VECTOR;
2863                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2864                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2865                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2866                              INTR_INFO_VALID_MASK);
2867                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2868                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2869                 return;
2870         }
2871         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2872                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2873 }
2874
2875 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2876 {
2877         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2878                 return 0;
2879
2880         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2881                         (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2882 }
2883
2884 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2885 {
2886         if (!cpu_has_virtual_nmis())
2887                 return to_vmx(vcpu)->soft_vnmi_blocked;
2888         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2889 }
2890
2891 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2892 {
2893         struct vcpu_vmx *vmx = to_vmx(vcpu);
2894
2895         if (!cpu_has_virtual_nmis()) {
2896                 if (vmx->soft_vnmi_blocked != masked) {
2897                         vmx->soft_vnmi_blocked = masked;
2898                         vmx->vnmi_blocked_time = 0;
2899                 }
2900         } else {
2901                 if (masked)
2902                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2903                                       GUEST_INTR_STATE_NMI);
2904                 else
2905                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2906                                         GUEST_INTR_STATE_NMI);
2907         }
2908 }
2909
2910 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2911 {
2912         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2913                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2914                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2915 }
2916
2917 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2918 {
2919         int ret;
2920         struct kvm_userspace_memory_region tss_mem = {
2921                 .slot = TSS_PRIVATE_MEMSLOT,
2922                 .guest_phys_addr = addr,
2923                 .memory_size = PAGE_SIZE * 3,
2924                 .flags = 0,
2925         };
2926
2927         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2928         if (ret)
2929                 return ret;
2930         kvm->arch.tss_addr = addr;
2931         return 0;
2932 }
2933
2934 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2935                                   int vec, u32 err_code)
2936 {
2937         /*
2938          * Instruction with address size override prefix opcode 0x67
2939          * Cause the #SS fault with 0 error code in VM86 mode.
2940          */
2941         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2942                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2943                         return 1;
2944         /*
2945          * Forward all other exceptions that are valid in real mode.
2946          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2947          *        the required debugging infrastructure rework.
2948          */
2949         switch (vec) {
2950         case DB_VECTOR:
2951                 if (vcpu->guest_debug &
2952                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2953                         return 0;
2954                 kvm_queue_exception(vcpu, vec);
2955                 return 1;
2956         case BP_VECTOR:
2957                 /*
2958                  * Update instruction length as we may reinject the exception
2959                  * from user space while in guest debugging mode.
2960                  */
2961                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2962                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2963                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2964                         return 0;
2965                 /* fall through */
2966         case DE_VECTOR:
2967         case OF_VECTOR:
2968         case BR_VECTOR:
2969         case UD_VECTOR:
2970         case DF_VECTOR:
2971         case SS_VECTOR:
2972         case GP_VECTOR:
2973         case MF_VECTOR:
2974                 kvm_queue_exception(vcpu, vec);
2975                 return 1;
2976         }
2977         return 0;
2978 }
2979
2980 /*
2981  * Trigger machine check on the host. We assume all the MSRs are already set up
2982  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2983  * We pass a fake environment to the machine check handler because we want
2984  * the guest to be always treated like user space, no matter what context
2985  * it used internally.
2986  */
2987 static void kvm_machine_check(void)
2988 {
2989 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2990         struct pt_regs regs = {
2991                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2992                 .flags = X86_EFLAGS_IF,
2993         };
2994
2995         do_machine_check(&regs, 0);
2996 #endif
2997 }
2998
2999 static int handle_machine_check(struct kvm_vcpu *vcpu)
3000 {
3001         /* already handled by vcpu_run */
3002         return 1;
3003 }
3004
3005 static int handle_exception(struct kvm_vcpu *vcpu)
3006 {
3007         struct vcpu_vmx *vmx = to_vmx(vcpu);
3008         struct kvm_run *kvm_run = vcpu->run;
3009         u32 intr_info, ex_no, error_code;
3010         unsigned long cr2, rip, dr6;
3011         u32 vect_info;
3012         enum emulation_result er;
3013
3014         vect_info = vmx->idt_vectoring_info;
3015         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3016
3017         if (is_machine_check(intr_info))
3018                 return handle_machine_check(vcpu);
3019
3020         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3021             !is_page_fault(intr_info)) {
3022                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3023                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3024                 vcpu->run->internal.ndata = 2;
3025                 vcpu->run->internal.data[0] = vect_info;
3026                 vcpu->run->internal.data[1] = intr_info;
3027                 return 0;
3028         }
3029
3030         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3031                 return 1;  /* already handled by vmx_vcpu_run() */
3032
3033         if (is_no_device(intr_info)) {
3034                 vmx_fpu_activate(vcpu);
3035                 return 1;
3036         }
3037
3038         if (is_invalid_opcode(intr_info)) {
3039                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3040                 if (er != EMULATE_DONE)
3041                         kvm_queue_exception(vcpu, UD_VECTOR);
3042                 return 1;
3043         }
3044
3045         error_code = 0;
3046         rip = kvm_rip_read(vcpu);
3047         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3048                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3049         if (is_page_fault(intr_info)) {
3050                 /* EPT won't cause page fault directly */
3051                 if (enable_ept)
3052                         BUG();
3053                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3054                 trace_kvm_page_fault(cr2, error_code);
3055
3056                 if (kvm_event_needs_reinjection(vcpu))
3057                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3058                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3059         }
3060
3061         if (vmx->rmode.vm86_active &&
3062             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3063                                                                 error_code)) {
3064                 if (vcpu->arch.halt_request) {
3065                         vcpu->arch.halt_request = 0;
3066                         return kvm_emulate_halt(vcpu);
3067                 }
3068                 return 1;
3069         }
3070
3071         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3072         switch (ex_no) {
3073         case DB_VECTOR:
3074                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3075                 if (!(vcpu->guest_debug &
3076                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3077                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3078                         kvm_queue_exception(vcpu, DB_VECTOR);
3079                         return 1;
3080                 }
3081                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3082                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3083                 /* fall through */
3084         case BP_VECTOR:
3085                 /*
3086                  * Update instruction length as we may reinject #BP from
3087                  * user space while in guest debugging mode. Reading it for
3088                  * #DB as well causes no harm, it is not used in that case.
3089                  */
3090                 vmx->vcpu.arch.event_exit_inst_len =
3091                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3092                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3093                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3094                 kvm_run->debug.arch.exception = ex_no;
3095                 break;
3096         default:
3097                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3098                 kvm_run->ex.exception = ex_no;
3099                 kvm_run->ex.error_code = error_code;
3100                 break;
3101         }
3102         return 0;
3103 }
3104
3105 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3106 {
3107         ++vcpu->stat.irq_exits;
3108         return 1;
3109 }
3110
3111 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3112 {
3113         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3114         return 0;
3115 }
3116
3117 static int handle_io(struct kvm_vcpu *vcpu)
3118 {
3119         unsigned long exit_qualification;
3120         int size, in, string;
3121         unsigned port;
3122
3123         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3124         string = (exit_qualification & 16) != 0;
3125         in = (exit_qualification & 8) != 0;
3126
3127         ++vcpu->stat.io_exits;
3128
3129         if (string || in)
3130                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3131
3132         port = exit_qualification >> 16;
3133         size = (exit_qualification & 7) + 1;
3134         skip_emulated_instruction(vcpu);
3135
3136         return kvm_fast_pio_out(vcpu, size, port);
3137 }
3138
3139 static void
3140 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3141 {
3142         /*
3143          * Patch in the VMCALL instruction:
3144          */
3145         hypercall[0] = 0x0f;
3146         hypercall[1] = 0x01;
3147         hypercall[2] = 0xc1;
3148 }
3149
3150 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3151 {
3152         if (err)
3153                 kvm_inject_gp(vcpu, 0);
3154         else
3155                 skip_emulated_instruction(vcpu);
3156 }
3157
3158 static int handle_cr(struct kvm_vcpu *vcpu)
3159 {
3160         unsigned long exit_qualification, val;
3161         int cr;
3162         int reg;
3163         int err;
3164
3165         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3166         cr = exit_qualification & 15;
3167         reg = (exit_qualification >> 8) & 15;
3168         switch ((exit_qualification >> 4) & 3) {
3169         case 0: /* mov to cr */
3170                 val = kvm_register_read(vcpu, reg);
3171                 trace_kvm_cr_write(cr, val);
3172                 switch (cr) {
3173                 case 0:
3174                         err = kvm_set_cr0(vcpu, val);
3175                         complete_insn_gp(vcpu, err);
3176                         return 1;
3177                 case 3:
3178                         err = kvm_set_cr3(vcpu, val);
3179                         complete_insn_gp(vcpu, err);
3180                         return 1;
3181                 case 4:
3182                         err = kvm_set_cr4(vcpu, val);
3183                         complete_insn_gp(vcpu, err);
3184                         return 1;
3185                 case 8: {
3186                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3187                                 u8 cr8 = kvm_register_read(vcpu, reg);
3188                                 kvm_set_cr8(vcpu, cr8);
3189                                 skip_emulated_instruction(vcpu);
3190                                 if (irqchip_in_kernel(vcpu->kvm))
3191                                         return 1;
3192                                 if (cr8_prev <= cr8)
3193                                         return 1;
3194                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3195                                 return 0;
3196                         }
3197                 };
3198                 break;
3199         case 2: /* clts */
3200                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3201                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3202                 skip_emulated_instruction(vcpu);
3203                 vmx_fpu_activate(vcpu);
3204                 return 1;
3205         case 1: /*mov from cr*/
3206                 switch (cr) {
3207                 case 3:
3208                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3209                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3210                         skip_emulated_instruction(vcpu);
3211                         return 1;
3212                 case 8:
3213                         val = kvm_get_cr8(vcpu);
3214                         kvm_register_write(vcpu, reg, val);
3215                         trace_kvm_cr_read(cr, val);
3216                         skip_emulated_instruction(vcpu);
3217                         return 1;
3218                 }
3219                 break;
3220         case 3: /* lmsw */
3221                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3222                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3223                 kvm_lmsw(vcpu, val);
3224
3225                 skip_emulated_instruction(vcpu);
3226                 return 1;
3227         default:
3228                 break;
3229         }
3230         vcpu->run->exit_reason = 0;
3231         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3232                (int)(exit_qualification >> 4) & 3, cr);
3233         return 0;
3234 }
3235
3236 static int handle_dr(struct kvm_vcpu *vcpu)
3237 {
3238         unsigned long exit_qualification;
3239         int dr, reg;
3240
3241         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3242         if (!kvm_require_cpl(vcpu, 0))
3243                 return 1;
3244         dr = vmcs_readl(GUEST_DR7);
3245         if (dr & DR7_GD) {
3246                 /*
3247                  * As the vm-exit takes precedence over the debug trap, we
3248                  * need to emulate the latter, either for the host or the
3249                  * guest debugging itself.
3250                  */
3251                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3252                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3253                         vcpu->run->debug.arch.dr7 = dr;
3254                         vcpu->run->debug.arch.pc =
3255                                 vmcs_readl(GUEST_CS_BASE) +
3256                                 vmcs_readl(GUEST_RIP);
3257                         vcpu->run->debug.arch.exception = DB_VECTOR;
3258                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3259                         return 0;
3260                 } else {
3261                         vcpu->arch.dr7 &= ~DR7_GD;
3262                         vcpu->arch.dr6 |= DR6_BD;
3263                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3264                         kvm_queue_exception(vcpu, DB_VECTOR);
3265                         return 1;
3266                 }
3267         }
3268
3269         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3270         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3271         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3272         if (exit_qualification & TYPE_MOV_FROM_DR) {
3273                 unsigned long val;
3274                 if (!kvm_get_dr(vcpu, dr, &val))
3275                         kvm_register_write(vcpu, reg, val);
3276         } else
3277                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3278         skip_emulated_instruction(vcpu);
3279         return 1;
3280 }
3281
3282 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3283 {
3284         vmcs_writel(GUEST_DR7, val);
3285 }
3286
3287 static int handle_cpuid(struct kvm_vcpu *vcpu)
3288 {
3289         kvm_emulate_cpuid(vcpu);
3290         return 1;
3291 }
3292
3293 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3294 {
3295         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3296         u64 data;
3297
3298         if (vmx_get_msr(vcpu, ecx, &data)) {
3299                 trace_kvm_msr_read_ex(ecx);
3300                 kvm_inject_gp(vcpu, 0);
3301                 return 1;
3302         }
3303
3304         trace_kvm_msr_read(ecx, data);
3305
3306         /* FIXME: handling of bits 32:63 of rax, rdx */
3307         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3308         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3309         skip_emulated_instruction(vcpu);
3310         return 1;
3311 }
3312
3313 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3314 {
3315         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3316         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3317                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3318
3319         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3320                 trace_kvm_msr_write_ex(ecx, data);
3321                 kvm_inject_gp(vcpu, 0);
3322                 return 1;
3323         }
3324
3325         trace_kvm_msr_write(ecx, data);
3326         skip_emulated_instruction(vcpu);
3327         return 1;
3328 }
3329
3330 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3331 {
3332         kvm_make_request(KVM_REQ_EVENT, vcpu);
3333         return 1;
3334 }
3335
3336 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3337 {
3338         u32 cpu_based_vm_exec_control;
3339
3340         /* clear pending irq */
3341         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3342         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3343         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3344
3345         kvm_make_request(KVM_REQ_EVENT, vcpu);
3346
3347         ++vcpu->stat.irq_window_exits;
3348
3349         /*
3350          * If the user space waits to inject interrupts, exit as soon as
3351          * possible
3352          */
3353         if (!irqchip_in_kernel(vcpu->kvm) &&
3354             vcpu->run->request_interrupt_window &&
3355             !kvm_cpu_has_interrupt(vcpu)) {
3356                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3357                 return 0;
3358         }
3359         return 1;
3360 }
3361
3362 static int handle_halt(struct kvm_vcpu *vcpu)
3363 {
3364         skip_emulated_instruction(vcpu);
3365         return kvm_emulate_halt(vcpu);
3366 }
3367
3368 static int handle_vmcall(struct kvm_vcpu *vcpu)
3369 {
3370         skip_emulated_instruction(vcpu);
3371         kvm_emulate_hypercall(vcpu);
3372         return 1;
3373 }
3374
3375 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3376 {
3377         kvm_queue_exception(vcpu, UD_VECTOR);
3378         return 1;
3379 }
3380
3381 static int handle_invlpg(struct kvm_vcpu *vcpu)
3382 {
3383         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3384
3385         kvm_mmu_invlpg(vcpu, exit_qualification);
3386         skip_emulated_instruction(vcpu);
3387         return 1;
3388 }
3389
3390 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3391 {
3392         skip_emulated_instruction(vcpu);
3393         kvm_emulate_wbinvd(vcpu);
3394         return 1;
3395 }
3396
3397 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3398 {
3399         u64 new_bv = kvm_read_edx_eax(vcpu);
3400         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3401
3402         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3403                 skip_emulated_instruction(vcpu);
3404         return 1;
3405 }
3406
3407 static int handle_apic_access(struct kvm_vcpu *vcpu)
3408 {
3409         return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3410 }
3411
3412 static int handle_task_switch(struct kvm_vcpu *vcpu)
3413 {
3414         struct vcpu_vmx *vmx = to_vmx(vcpu);
3415         unsigned long exit_qualification;
3416         bool has_error_code = false;
3417         u32 error_code = 0;
3418         u16 tss_selector;
3419         int reason, type, idt_v;
3420
3421         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3422         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3423
3424         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3425
3426         reason = (u32)exit_qualification >> 30;
3427         if (reason == TASK_SWITCH_GATE && idt_v) {
3428                 switch (type) {
3429                 case INTR_TYPE_NMI_INTR:
3430                         vcpu->arch.nmi_injected = false;
3431                         if (cpu_has_virtual_nmis())
3432                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3433                                               GUEST_INTR_STATE_NMI);
3434                         break;
3435                 case INTR_TYPE_EXT_INTR:
3436                 case INTR_TYPE_SOFT_INTR:
3437                         kvm_clear_interrupt_queue(vcpu);
3438                         break;
3439                 case INTR_TYPE_HARD_EXCEPTION:
3440                         if (vmx->idt_vectoring_info &
3441                             VECTORING_INFO_DELIVER_CODE_MASK) {
3442                                 has_error_code = true;
3443                                 error_code =
3444                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3445                         }
3446                         /* fall through */
3447                 case INTR_TYPE_SOFT_EXCEPTION:
3448                         kvm_clear_exception_queue(vcpu);
3449                         break;
3450                 default:
3451                         break;
3452                 }
3453         }
3454         tss_selector = exit_qualification;
3455
3456         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3457                        type != INTR_TYPE_EXT_INTR &&
3458                        type != INTR_TYPE_NMI_INTR))
3459                 skip_emulated_instruction(vcpu);
3460
3461         if (kvm_task_switch(vcpu, tss_selector, reason,
3462                                 has_error_code, error_code) == EMULATE_FAIL) {
3463                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3464                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3465                 vcpu->run->internal.ndata = 0;
3466                 return 0;
3467         }
3468
3469         /* clear all local breakpoint enable flags */
3470         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3471
3472         /*
3473          * TODO: What about debug traps on tss switch?
3474          *       Are we supposed to inject them and update dr6?
3475          */
3476
3477         return 1;
3478 }
3479
3480 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3481 {
3482         unsigned long exit_qualification;
3483         gpa_t gpa;
3484         int gla_validity;
3485
3486         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3487
3488         if (exit_qualification & (1 << 6)) {
3489                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3490                 return -EINVAL;
3491         }
3492
3493         gla_validity = (exit_qualification >> 7) & 0x3;
3494         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3495                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3496                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3497                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3498                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3499                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3500                         (long unsigned int)exit_qualification);
3501                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3502                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3503                 return 0;
3504         }
3505
3506         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3507         trace_kvm_page_fault(gpa, exit_qualification);
3508         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3509 }
3510
3511 static u64 ept_rsvd_mask(u64 spte, int level)
3512 {
3513         int i;
3514         u64 mask = 0;
3515
3516         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3517                 mask |= (1ULL << i);
3518
3519         if (level > 2)
3520                 /* bits 7:3 reserved */
3521                 mask |= 0xf8;
3522         else if (level == 2) {
3523                 if (spte & (1ULL << 7))
3524                         /* 2MB ref, bits 20:12 reserved */
3525                         mask |= 0x1ff000;
3526                 else
3527                         /* bits 6:3 reserved */
3528                         mask |= 0x78;
3529         }
3530
3531         return mask;
3532 }
3533
3534 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3535                                        int level)
3536 {
3537         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3538
3539         /* 010b (write-only) */
3540         WARN_ON((spte & 0x7) == 0x2);
3541
3542         /* 110b (write/execute) */
3543         WARN_ON((spte & 0x7) == 0x6);
3544
3545         /* 100b (execute-only) and value not supported by logical processor */
3546         if (!cpu_has_vmx_ept_execute_only())
3547                 WARN_ON((spte & 0x7) == 0x4);
3548
3549         /* not 000b */
3550         if ((spte & 0x7)) {
3551                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3552
3553                 if (rsvd_bits != 0) {
3554                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3555                                          __func__, rsvd_bits);
3556                         WARN_ON(1);
3557                 }
3558
3559                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3560                         u64 ept_mem_type = (spte & 0x38) >> 3;
3561
3562                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3563                             ept_mem_type == 7) {
3564                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3565                                                 __func__, ept_mem_type);
3566                                 WARN_ON(1);
3567                         }
3568                 }
3569         }
3570 }
3571
3572 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3573 {
3574         u64 sptes[4];
3575         int nr_sptes, i;
3576         gpa_t gpa;
3577
3578         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3579
3580         printk(KERN_ERR "EPT: Misconfiguration.\n");
3581         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3582
3583         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3584
3585         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3586                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3587
3588         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3589         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3590
3591         return 0;
3592 }
3593
3594 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3595 {
3596         u32 cpu_based_vm_exec_control;
3597
3598         /* clear pending NMI */
3599         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3600         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3601         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3602         ++vcpu->stat.nmi_window_exits;
3603         kvm_make_request(KVM_REQ_EVENT, vcpu);
3604
3605         return 1;
3606 }
3607
3608 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3609 {
3610         struct vcpu_vmx *vmx = to_vmx(vcpu);
3611         enum emulation_result err = EMULATE_DONE;
3612         int ret = 1;
3613
3614         while (!guest_state_valid(vcpu)) {
3615                 err = emulate_instruction(vcpu, 0, 0, 0);
3616
3617                 if (err == EMULATE_DO_MMIO) {
3618                         ret = 0;
3619                         goto out;
3620                 }
3621
3622                 if (err != EMULATE_DONE)
3623                         return 0;
3624
3625                 if (signal_pending(current))
3626                         goto out;
3627                 if (need_resched())
3628                         schedule();
3629         }
3630
3631         vmx->emulation_required = 0;
3632 out:
3633         return ret;
3634 }
3635
3636 /*
3637  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3638  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3639  */
3640 static int handle_pause(struct kvm_vcpu *vcpu)
3641 {
3642         skip_emulated_instruction(vcpu);
3643         kvm_vcpu_on_spin(vcpu);
3644
3645         return 1;
3646 }
3647
3648 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3649 {
3650         kvm_queue_exception(vcpu, UD_VECTOR);
3651         return 1;
3652 }
3653
3654 /*
3655  * The exit handlers return 1 if the exit was handled fully and guest execution
3656  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3657  * to be done to userspace and return 0.
3658  */
3659 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3660         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3661         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3662         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3663         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3664         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3665         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3666         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3667         [EXIT_REASON_CPUID]                   = handle_cpuid,
3668         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3669         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3670         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3671         [EXIT_REASON_HLT]                     = handle_halt,
3672         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3673         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3674         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3675         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3676         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3677         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3678         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3679         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3680         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3681         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3682         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3683         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3684         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3685         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3686         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
3687         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3688         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3689         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3690         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3691         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3692         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3693         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3694 };
3695
3696 static const int kvm_vmx_max_exit_handlers =
3697         ARRAY_SIZE(kvm_vmx_exit_handlers);
3698
3699 /*
3700  * The guest has exited.  See if we can fix it or if we need userspace
3701  * assistance.
3702  */
3703 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3704 {
3705         struct vcpu_vmx *vmx = to_vmx(vcpu);
3706         u32 exit_reason = vmx->exit_reason;
3707         u32 vectoring_info = vmx->idt_vectoring_info;
3708
3709         trace_kvm_exit(exit_reason, vcpu);
3710
3711         /* If guest state is invalid, start emulating */
3712         if (vmx->emulation_required && emulate_invalid_guest_state)
3713                 return handle_invalid_guest_state(vcpu);
3714
3715         /* Access CR3 don't cause VMExit in paging mode, so we need
3716          * to sync with guest real CR3. */
3717         if (enable_ept && is_paging(vcpu))
3718                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3719
3720         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3721                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3722                 vcpu->run->fail_entry.hardware_entry_failure_reason
3723                         = exit_reason;
3724                 return 0;
3725         }
3726
3727         if (unlikely(vmx->fail)) {
3728                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3729                 vcpu->run->fail_entry.hardware_entry_failure_reason
3730                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3731                 return 0;
3732         }
3733
3734         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3735                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3736                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3737                         exit_reason != EXIT_REASON_TASK_SWITCH))
3738                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3739                        "(0x%x) and exit reason is 0x%x\n",
3740                        __func__, vectoring_info, exit_reason);
3741
3742         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3743                 if (vmx_interrupt_allowed(vcpu)) {
3744                         vmx->soft_vnmi_blocked = 0;
3745                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3746                            vcpu->arch.nmi_pending) {
3747                         /*
3748                          * This CPU don't support us in finding the end of an
3749                          * NMI-blocked window if the guest runs with IRQs
3750                          * disabled. So we pull the trigger after 1 s of
3751                          * futile waiting, but inform the user about this.
3752                          */
3753                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3754                                "state on VCPU %d after 1 s timeout\n",
3755                                __func__, vcpu->vcpu_id);
3756                         vmx->soft_vnmi_blocked = 0;
3757                 }
3758         }
3759
3760         if (exit_reason < kvm_vmx_max_exit_handlers
3761             && kvm_vmx_exit_handlers[exit_reason])
3762                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3763         else {
3764                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3765                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3766         }
3767         return 0;
3768 }
3769
3770 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3771 {
3772         if (irr == -1 || tpr < irr) {
3773                 vmcs_write32(TPR_THRESHOLD, 0);
3774                 return;
3775         }
3776
3777         vmcs_write32(TPR_THRESHOLD, irr);
3778 }
3779
3780 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3781 {
3782         u32 exit_intr_info = vmx->exit_intr_info;
3783
3784         /* Handle machine checks before interrupts are enabled */
3785         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3786             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3787                 && is_machine_check(exit_intr_info)))
3788                 kvm_machine_check();
3789
3790         /* We need to handle NMIs before interrupts are enabled */
3791         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3792             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3793                 kvm_before_handle_nmi(&vmx->vcpu);
3794                 asm("int $2");
3795                 kvm_after_handle_nmi(&vmx->vcpu);
3796         }
3797 }
3798
3799 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3800 {
3801         u32 exit_intr_info = vmx->exit_intr_info;
3802         bool unblock_nmi;
3803         u8 vector;
3804         bool idtv_info_valid;
3805
3806         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3807
3808         if (cpu_has_virtual_nmis()) {
3809                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3810                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3811                 /*
3812                  * SDM 3: 27.7.1.2 (September 2008)
3813                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3814                  * a guest IRET fault.
3815                  * SDM 3: 23.2.2 (September 2008)
3816                  * Bit 12 is undefined in any of the following cases:
3817                  *  If the VM exit sets the valid bit in the IDT-vectoring
3818                  *   information field.
3819                  *  If the VM exit is due to a double fault.
3820                  */
3821                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3822                     vector != DF_VECTOR && !idtv_info_valid)
3823                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3824                                       GUEST_INTR_STATE_NMI);
3825         } else if (unlikely(vmx->soft_vnmi_blocked))
3826                 vmx->vnmi_blocked_time +=
3827                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3828 }
3829
3830 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3831                                       u32 idt_vectoring_info,
3832                                       int instr_len_field,
3833                                       int error_code_field)
3834 {
3835         u8 vector;
3836         int type;
3837         bool idtv_info_valid;
3838
3839         if (vmx->rmode.irq.pending)
3840                 fixup_rmode_irq(vmx, &idt_vectoring_info);
3841
3842         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3843
3844         vmx->vcpu.arch.nmi_injected = false;
3845         kvm_clear_exception_queue(&vmx->vcpu);
3846         kvm_clear_interrupt_queue(&vmx->vcpu);
3847
3848         if (!idtv_info_valid)
3849                 return;
3850
3851         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3852
3853         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3854         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3855
3856         switch (type) {
3857         case INTR_TYPE_NMI_INTR:
3858                 vmx->vcpu.arch.nmi_injected = true;
3859                 /*
3860                  * SDM 3: 27.7.1.2 (September 2008)
3861                  * Clear bit "block by NMI" before VM entry if a NMI
3862                  * delivery faulted.
3863                  */
3864                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3865                                 GUEST_INTR_STATE_NMI);
3866                 break;
3867         case INTR_TYPE_SOFT_EXCEPTION:
3868                 vmx->vcpu.arch.event_exit_inst_len =
3869                         vmcs_read32(instr_len_field);
3870                 /* fall through */
3871         case INTR_TYPE_HARD_EXCEPTION:
3872                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3873                         u32 err = vmcs_read32(error_code_field);
3874                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3875                 } else
3876                         kvm_queue_exception(&vmx->vcpu, vector);
3877                 break;
3878         case INTR_TYPE_SOFT_INTR:
3879                 vmx->vcpu.arch.event_exit_inst_len =
3880                         vmcs_read32(instr_len_field);
3881                 /* fall through */
3882         case INTR_TYPE_EXT_INTR:
3883                 kvm_queue_interrupt(&vmx->vcpu, vector,
3884                         type == INTR_TYPE_SOFT_INTR);
3885                 break;
3886         default:
3887                 break;
3888         }
3889 }
3890
3891 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3892 {
3893         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3894                                   VM_EXIT_INSTRUCTION_LEN,
3895                                   IDT_VECTORING_ERROR_CODE);
3896 }
3897
3898 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3899 {
3900         __vmx_complete_interrupts(to_vmx(vcpu),
3901                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3902                                   VM_ENTRY_INSTRUCTION_LEN,
3903                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
3904
3905         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3906 }
3907
3908 /*
3909  * Failure to inject an interrupt should give us the information
3910  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3911  * when fetching the interrupt redirection bitmap in the real-mode
3912  * tss, this doesn't happen.  So we do it ourselves.
3913  */
3914 static void fixup_rmode_irq(struct vcpu_vmx *vmx, u32 *idt_vectoring_info)
3915 {
3916         vmx->rmode.irq.pending = 0;
3917         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3918                 return;
3919         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3920         if (*idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3921                 *idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3922                 *idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3923                 return;
3924         }
3925         *idt_vectoring_info =
3926                 VECTORING_INFO_VALID_MASK
3927                 | INTR_TYPE_EXT_INTR
3928                 | vmx->rmode.irq.vector;
3929 }
3930
3931 #ifdef CONFIG_X86_64
3932 #define R "r"
3933 #define Q "q"
3934 #else
3935 #define R "e"
3936 #define Q "l"
3937 #endif
3938
3939 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3940 {
3941         struct vcpu_vmx *vmx = to_vmx(vcpu);
3942
3943         /* Record the guest's net vcpu time for enforced NMI injections. */
3944         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3945                 vmx->entry_time = ktime_get();
3946
3947         /* Don't enter VMX if guest state is invalid, let the exit handler
3948            start emulation until we arrive back to a valid state */
3949         if (vmx->emulation_required && emulate_invalid_guest_state)
3950                 return;
3951
3952         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3953                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3954         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3955                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3956
3957         /* When single-stepping over STI and MOV SS, we must clear the
3958          * corresponding interruptibility bits in the guest state. Otherwise
3959          * vmentry fails as it then expects bit 14 (BS) in pending debug
3960          * exceptions being set, but that's not correct for the guest debugging
3961          * case. */
3962         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3963                 vmx_set_interrupt_shadow(vcpu, 0);
3964
3965         asm(
3966                 /* Store host registers */
3967                 "push %%"R"dx; push %%"R"bp;"
3968                 "push %%"R"cx \n\t"
3969                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3970                 "je 1f \n\t"
3971                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3972                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3973                 "1: \n\t"
3974                 /* Reload cr2 if changed */
3975                 "mov %c[cr2](%0), %%"R"ax \n\t"
3976                 "mov %%cr2, %%"R"dx \n\t"
3977                 "cmp %%"R"ax, %%"R"dx \n\t"
3978                 "je 2f \n\t"
3979                 "mov %%"R"ax, %%cr2 \n\t"
3980                 "2: \n\t"
3981                 /* Check if vmlaunch of vmresume is needed */
3982                 "cmpl $0, %c[launched](%0) \n\t"
3983                 /* Load guest registers.  Don't clobber flags. */
3984                 "mov %c[rax](%0), %%"R"ax \n\t"
3985                 "mov %c[rbx](%0), %%"R"bx \n\t"
3986                 "mov %c[rdx](%0), %%"R"dx \n\t"
3987                 "mov %c[rsi](%0), %%"R"si \n\t"
3988                 "mov %c[rdi](%0), %%"R"di \n\t"
3989                 "mov %c[rbp](%0), %%"R"bp \n\t"
3990 #ifdef CONFIG_X86_64
3991                 "mov %c[r8](%0),  %%r8  \n\t"
3992                 "mov %c[r9](%0),  %%r9  \n\t"
3993                 "mov %c[r10](%0), %%r10 \n\t"
3994                 "mov %c[r11](%0), %%r11 \n\t"
3995                 "mov %c[r12](%0), %%r12 \n\t"
3996                 "mov %c[r13](%0), %%r13 \n\t"
3997                 "mov %c[r14](%0), %%r14 \n\t"
3998                 "mov %c[r15](%0), %%r15 \n\t"
3999 #endif
4000                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4001
4002                 /* Enter guest mode */
4003                 "jne .Llaunched \n\t"
4004                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4005                 "jmp .Lkvm_vmx_return \n\t"
4006                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4007                 ".Lkvm_vmx_return: "
4008                 /* Save guest registers, load host registers, keep flags */
4009                 "xchg %0,     (%%"R"sp) \n\t"
4010                 "mov %%"R"ax, %c[rax](%0) \n\t"
4011                 "mov %%"R"bx, %c[rbx](%0) \n\t"
4012                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
4013                 "mov %%"R"dx, %c[rdx](%0) \n\t"
4014                 "mov %%"R"si, %c[rsi](%0) \n\t"
4015                 "mov %%"R"di, %c[rdi](%0) \n\t"
4016                 "mov %%"R"bp, %c[rbp](%0) \n\t"
4017 #ifdef CONFIG_X86_64
4018                 "mov %%r8,  %c[r8](%0) \n\t"
4019                 "mov %%r9,  %c[r9](%0) \n\t"
4020                 "mov %%r10, %c[r10](%0) \n\t"
4021                 "mov %%r11, %c[r11](%0) \n\t"
4022                 "mov %%r12, %c[r12](%0) \n\t"
4023                 "mov %%r13, %c[r13](%0) \n\t"
4024                 "mov %%r14, %c[r14](%0) \n\t"
4025                 "mov %%r15, %c[r15](%0) \n\t"
4026 #endif
4027                 "mov %%cr2, %%"R"ax   \n\t"
4028                 "mov %%"R"ax, %c[cr2](%0) \n\t"
4029
4030                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
4031                 "setbe %c[fail](%0) \n\t"
4032               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4033                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4034                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4035                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4036                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4037                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4038                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4039                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4040                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4041                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4042                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4043 #ifdef CONFIG_X86_64
4044                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4045                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4046                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4047                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4048                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4049                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4050                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4051                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4052 #endif
4053                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4054               : "cc", "memory"
4055                 , R"bx", R"di", R"si"
4056 #ifdef CONFIG_X86_64
4057                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4058 #endif
4059               );
4060
4061         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4062                                   | (1 << VCPU_EXREG_PDPTR));
4063         vcpu->arch.regs_dirty = 0;
4064
4065         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4066
4067         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4068         vmx->launched = 1;
4069
4070         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4071         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4072
4073         vmx_complete_atomic_exit(vmx);
4074         vmx_recover_nmi_blocking(vmx);
4075         vmx_complete_interrupts(vmx);
4076 }
4077
4078 #undef R
4079 #undef Q
4080
4081 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4082 {
4083         struct vcpu_vmx *vmx = to_vmx(vcpu);
4084
4085         if (vmx->vmcs) {
4086                 vcpu_clear(vmx);
4087                 free_vmcs(vmx->vmcs);
4088                 vmx->vmcs = NULL;
4089         }
4090 }
4091
4092 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4093 {
4094         struct vcpu_vmx *vmx = to_vmx(vcpu);
4095
4096         free_vpid(vmx);
4097         vmx_free_vmcs(vcpu);
4098         kfree(vmx->guest_msrs);
4099         kvm_vcpu_uninit(vcpu);
4100         kmem_cache_free(kvm_vcpu_cache, vmx);
4101 }
4102
4103 static inline void vmcs_init(struct vmcs *vmcs)
4104 {
4105         u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4106
4107         if (!vmm_exclusive)
4108                 kvm_cpu_vmxon(phys_addr);
4109
4110         vmcs_clear(vmcs);
4111
4112         if (!vmm_exclusive)
4113                 kvm_cpu_vmxoff();
4114 }
4115
4116 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4117 {
4118         int err;
4119         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4120         int cpu;
4121
4122         if (!vmx)
4123                 return ERR_PTR(-ENOMEM);
4124
4125         allocate_vpid(vmx);
4126
4127         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4128         if (err)
4129                 goto free_vcpu;
4130
4131         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4132         if (!vmx->guest_msrs) {
4133                 err = -ENOMEM;
4134                 goto uninit_vcpu;
4135         }
4136
4137         vmx->vmcs = alloc_vmcs();
4138         if (!vmx->vmcs)
4139                 goto free_msrs;
4140
4141         vmcs_init(vmx->vmcs);
4142
4143         cpu = get_cpu();
4144         vmx_vcpu_load(&vmx->vcpu, cpu);
4145         vmx->vcpu.cpu = cpu;
4146         err = vmx_vcpu_setup(vmx);
4147         vmx_vcpu_put(&vmx->vcpu);
4148         put_cpu();
4149         if (err)
4150                 goto free_vmcs;
4151         if (vm_need_virtualize_apic_accesses(kvm))
4152                 if (alloc_apic_access_page(kvm) != 0)
4153                         goto free_vmcs;
4154
4155         if (enable_ept) {
4156                 if (!kvm->arch.ept_identity_map_addr)
4157                         kvm->arch.ept_identity_map_addr =
4158                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4159                 if (alloc_identity_pagetable(kvm) != 0)
4160                         goto free_vmcs;
4161         }
4162
4163         return &vmx->vcpu;
4164
4165 free_vmcs:
4166         free_vmcs(vmx->vmcs);
4167 free_msrs:
4168         kfree(vmx->guest_msrs);
4169 uninit_vcpu:
4170         kvm_vcpu_uninit(&vmx->vcpu);
4171 free_vcpu:
4172         free_vpid(vmx);
4173         kmem_cache_free(kvm_vcpu_cache, vmx);
4174         return ERR_PTR(err);
4175 }
4176
4177 static void __init vmx_check_processor_compat(void *rtn)
4178 {
4179         struct vmcs_config vmcs_conf;
4180
4181         *(int *)rtn = 0;
4182         if (setup_vmcs_config(&vmcs_conf) < 0)
4183                 *(int *)rtn = -EIO;
4184         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4185                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4186                                 smp_processor_id());
4187                 *(int *)rtn = -EIO;
4188         }
4189 }
4190
4191 static int get_ept_level(void)
4192 {
4193         return VMX_EPT_DEFAULT_GAW + 1;
4194 }
4195
4196 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4197 {
4198         u64 ret;
4199
4200         /* For VT-d and EPT combination
4201          * 1. MMIO: always map as UC
4202          * 2. EPT with VT-d:
4203          *   a. VT-d without snooping control feature: can't guarantee the
4204          *      result, try to trust guest.
4205          *   b. VT-d with snooping control feature: snooping control feature of
4206          *      VT-d engine can guarantee the cache correctness. Just set it
4207          *      to WB to keep consistent with host. So the same as item 3.
4208          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4209          *    consistent with host MTRR
4210          */
4211         if (is_mmio)
4212                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4213         else if (vcpu->kvm->arch.iommu_domain &&
4214                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4215                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4216                       VMX_EPT_MT_EPTE_SHIFT;
4217         else
4218                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4219                         | VMX_EPT_IPAT_BIT;
4220
4221         return ret;
4222 }
4223
4224 #define _ER(x) { EXIT_REASON_##x, #x }
4225
4226 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4227         _ER(EXCEPTION_NMI),
4228         _ER(EXTERNAL_INTERRUPT),
4229         _ER(TRIPLE_FAULT),
4230         _ER(PENDING_INTERRUPT),
4231         _ER(NMI_WINDOW),
4232         _ER(TASK_SWITCH),
4233         _ER(CPUID),
4234         _ER(HLT),
4235         _ER(INVLPG),
4236         _ER(RDPMC),
4237         _ER(RDTSC),
4238         _ER(VMCALL),
4239         _ER(VMCLEAR),
4240         _ER(VMLAUNCH),
4241         _ER(VMPTRLD),
4242         _ER(VMPTRST),
4243         _ER(VMREAD),
4244         _ER(VMRESUME),
4245         _ER(VMWRITE),
4246         _ER(VMOFF),
4247         _ER(VMON),
4248         _ER(CR_ACCESS),
4249         _ER(DR_ACCESS),
4250         _ER(IO_INSTRUCTION),
4251         _ER(MSR_READ),
4252         _ER(MSR_WRITE),
4253         _ER(MWAIT_INSTRUCTION),
4254         _ER(MONITOR_INSTRUCTION),
4255         _ER(PAUSE_INSTRUCTION),
4256         _ER(MCE_DURING_VMENTRY),
4257         _ER(TPR_BELOW_THRESHOLD),
4258         _ER(APIC_ACCESS),
4259         _ER(EPT_VIOLATION),
4260         _ER(EPT_MISCONFIG),
4261         _ER(WBINVD),
4262         { -1, NULL }
4263 };
4264
4265 #undef _ER
4266
4267 static int vmx_get_lpage_level(void)
4268 {
4269         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4270                 return PT_DIRECTORY_LEVEL;
4271         else
4272                 /* For shadow and EPT supported 1GB page */
4273                 return PT_PDPE_LEVEL;
4274 }
4275
4276 static inline u32 bit(int bitno)
4277 {
4278         return 1 << (bitno & 31);
4279 }
4280
4281 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4282 {
4283         struct kvm_cpuid_entry2 *best;
4284         struct vcpu_vmx *vmx = to_vmx(vcpu);
4285         u32 exec_control;
4286
4287         vmx->rdtscp_enabled = false;
4288         if (vmx_rdtscp_supported()) {
4289                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4290                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4291                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4292                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4293                                 vmx->rdtscp_enabled = true;
4294                         else {
4295                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4296                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4297                                                 exec_control);
4298                         }
4299                 }
4300         }
4301 }
4302
4303 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4304 {
4305 }
4306
4307 static struct kvm_x86_ops vmx_x86_ops = {
4308         .cpu_has_kvm_support = cpu_has_kvm_support,
4309         .disabled_by_bios = vmx_disabled_by_bios,
4310         .hardware_setup = hardware_setup,
4311         .hardware_unsetup = hardware_unsetup,
4312         .check_processor_compatibility = vmx_check_processor_compat,
4313         .hardware_enable = hardware_enable,
4314         .hardware_disable = hardware_disable,
4315         .cpu_has_accelerated_tpr = report_flexpriority,
4316
4317         .vcpu_create = vmx_create_vcpu,
4318         .vcpu_free = vmx_free_vcpu,
4319         .vcpu_reset = vmx_vcpu_reset,
4320
4321         .prepare_guest_switch = vmx_save_host_state,
4322         .vcpu_load = vmx_vcpu_load,
4323         .vcpu_put = vmx_vcpu_put,
4324
4325         .set_guest_debug = set_guest_debug,
4326         .get_msr = vmx_get_msr,
4327         .set_msr = vmx_set_msr,
4328         .get_segment_base = vmx_get_segment_base,
4329         .get_segment = vmx_get_segment,
4330         .set_segment = vmx_set_segment,
4331         .get_cpl = vmx_get_cpl,
4332         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4333         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4334         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4335         .set_cr0 = vmx_set_cr0,
4336         .set_cr3 = vmx_set_cr3,
4337         .set_cr4 = vmx_set_cr4,
4338         .set_efer = vmx_set_efer,
4339         .get_idt = vmx_get_idt,
4340         .set_idt = vmx_set_idt,
4341         .get_gdt = vmx_get_gdt,
4342         .set_gdt = vmx_set_gdt,
4343         .set_dr7 = vmx_set_dr7,
4344         .cache_reg = vmx_cache_reg,
4345         .get_rflags = vmx_get_rflags,
4346         .set_rflags = vmx_set_rflags,
4347         .fpu_activate = vmx_fpu_activate,
4348         .fpu_deactivate = vmx_fpu_deactivate,
4349
4350         .tlb_flush = vmx_flush_tlb,
4351
4352         .run = vmx_vcpu_run,
4353         .handle_exit = vmx_handle_exit,
4354         .skip_emulated_instruction = skip_emulated_instruction,
4355         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4356         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4357         .patch_hypercall = vmx_patch_hypercall,
4358         .set_irq = vmx_inject_irq,
4359         .set_nmi = vmx_inject_nmi,
4360         .queue_exception = vmx_queue_exception,
4361         .cancel_injection = vmx_cancel_injection,
4362         .interrupt_allowed = vmx_interrupt_allowed,
4363         .nmi_allowed = vmx_nmi_allowed,
4364         .get_nmi_mask = vmx_get_nmi_mask,
4365         .set_nmi_mask = vmx_set_nmi_mask,
4366         .enable_nmi_window = enable_nmi_window,
4367         .enable_irq_window = enable_irq_window,
4368         .update_cr8_intercept = update_cr8_intercept,
4369
4370         .set_tss_addr = vmx_set_tss_addr,
4371         .get_tdp_level = get_ept_level,
4372         .get_mt_mask = vmx_get_mt_mask,
4373
4374         .exit_reasons_str = vmx_exit_reasons_str,
4375         .get_lpage_level = vmx_get_lpage_level,
4376
4377         .cpuid_update = vmx_cpuid_update,
4378
4379         .rdtscp_supported = vmx_rdtscp_supported,
4380
4381         .set_supported_cpuid = vmx_set_supported_cpuid,
4382
4383         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4384
4385         .write_tsc_offset = vmx_write_tsc_offset,
4386         .adjust_tsc_offset = vmx_adjust_tsc_offset,
4387
4388         .set_tdp_cr3 = vmx_set_cr3,
4389 };
4390
4391 static int __init vmx_init(void)
4392 {
4393         int r, i;
4394
4395         rdmsrl_safe(MSR_EFER, &host_efer);
4396
4397         for (i = 0; i < NR_VMX_MSR; ++i)
4398                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4399
4400         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4401         if (!vmx_io_bitmap_a)
4402                 return -ENOMEM;
4403
4404         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4405         if (!vmx_io_bitmap_b) {
4406                 r = -ENOMEM;
4407                 goto out;
4408         }
4409
4410         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4411         if (!vmx_msr_bitmap_legacy) {
4412                 r = -ENOMEM;
4413                 goto out1;
4414         }
4415
4416         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4417         if (!vmx_msr_bitmap_longmode) {
4418                 r = -ENOMEM;
4419                 goto out2;
4420         }
4421
4422         /*
4423          * Allow direct access to the PC debug port (it is often used for I/O
4424          * delays, but the vmexits simply slow things down).
4425          */
4426         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4427         clear_bit(0x80, vmx_io_bitmap_a);
4428
4429         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4430
4431         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4432         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4433
4434         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4435
4436         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4437                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4438         if (r)
4439                 goto out3;
4440
4441         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4442         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4443         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4444         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4445         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4446         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4447
4448         if (enable_ept) {
4449                 bypass_guest_pf = 0;
4450                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4451                         VMX_EPT_WRITABLE_MASK);
4452                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4453                                 VMX_EPT_EXECUTABLE_MASK);
4454                 kvm_enable_tdp();
4455         } else
4456                 kvm_disable_tdp();
4457
4458         if (bypass_guest_pf)
4459                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4460
4461         return 0;
4462
4463 out3:
4464         free_page((unsigned long)vmx_msr_bitmap_longmode);
4465 out2:
4466         free_page((unsigned long)vmx_msr_bitmap_legacy);
4467 out1:
4468         free_page((unsigned long)vmx_io_bitmap_b);
4469 out:
4470         free_page((unsigned long)vmx_io_bitmap_a);
4471         return r;
4472 }
4473
4474 static void __exit vmx_exit(void)
4475 {
4476         free_page((unsigned long)vmx_msr_bitmap_legacy);
4477         free_page((unsigned long)vmx_msr_bitmap_longmode);
4478         free_page((unsigned long)vmx_io_bitmap_b);
4479         free_page((unsigned long)vmx_io_bitmap_a);
4480
4481         kvm_exit();
4482 }
4483
4484 module_init(vmx_init)
4485 module_exit(vmx_exit)