2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
52 static int __read_mostly bypass_guest_pf = 1;
53 module_param(bypass_guest_pf, bool, S_IRUGO);
55 static int __read_mostly enable_vpid = 1;
56 module_param_named(vpid, enable_vpid, bool, 0444);
58 static int __read_mostly flexpriority_enabled = 1;
59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
61 static int __read_mostly enable_ept = 1;
62 module_param_named(ept, enable_ept, bool, S_IRUGO);
64 static int __read_mostly enable_unrestricted_guest = 1;
65 module_param_named(unrestricted_guest,
66 enable_unrestricted_guest, bool, S_IRUGO);
68 static int __read_mostly emulate_invalid_guest_state = 0;
69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
71 static int __read_mostly vmm_exclusive = 1;
72 module_param(vmm_exclusive, bool, S_IRUGO);
74 static int __read_mostly yield_on_hlt = 1;
75 module_param(yield_on_hlt, bool, S_IRUGO);
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
82 static int __read_mostly nested = 0;
83 module_param(nested, bool, S_IRUGO);
85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87 #define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
90 (X86_CR0_WP | X86_CR0_NE)
91 #define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
93 #define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
106 * According to test, this time is usually smaller than 128 cycles.
107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
113 #define KVM_VMX_DEFAULT_PLE_GAP 128
114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116 module_param(ple_gap, int, S_IRUGO);
118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119 module_param(ple_window, int, S_IRUGO);
121 #define NR_AUTOLOAD_MSRS 1
122 #define VMCS02_POOL_SIZE 1
131 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133 * loaded on this CPU (so we can clear them if the CPU goes down).
139 struct list_head loaded_vmcss_on_cpu_link;
142 struct shared_msr_entry {
149 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154 * More than one of these structures may exist, if L1 runs multiple L2 guests.
155 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156 * underlying hardware which will be used to run L2.
157 * This structure is packed to ensure that its layout is identical across
158 * machines (necessary for live migration).
159 * If there are changes in this struct, VMCS12_REVISION must be changed.
161 typedef u64 natural_width;
162 struct __packed vmcs12 {
163 /* According to the Intel spec, a VMCS region must start with the
164 * following two fields. Then follow implementation-specific data.
169 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170 u32 padding[7]; /* room for future expansion */
175 u64 vm_exit_msr_store_addr;
176 u64 vm_exit_msr_load_addr;
177 u64 vm_entry_msr_load_addr;
179 u64 virtual_apic_page_addr;
180 u64 apic_access_addr;
182 u64 guest_physical_address;
183 u64 vmcs_link_pointer;
184 u64 guest_ia32_debugctl;
187 u64 guest_ia32_perf_global_ctrl;
194 u64 host_ia32_perf_global_ctrl;
195 u64 padding64[8]; /* room for future expansion */
197 * To allow migration of L1 (complete with its L2 guests) between
198 * machines of different natural widths (32 or 64 bit), we cannot have
199 * unsigned long fields with no explict size. We use u64 (aliased
200 * natural_width) instead. Luckily, x86 is little-endian.
202 natural_width cr0_guest_host_mask;
203 natural_width cr4_guest_host_mask;
204 natural_width cr0_read_shadow;
205 natural_width cr4_read_shadow;
206 natural_width cr3_target_value0;
207 natural_width cr3_target_value1;
208 natural_width cr3_target_value2;
209 natural_width cr3_target_value3;
210 natural_width exit_qualification;
211 natural_width guest_linear_address;
212 natural_width guest_cr0;
213 natural_width guest_cr3;
214 natural_width guest_cr4;
215 natural_width guest_es_base;
216 natural_width guest_cs_base;
217 natural_width guest_ss_base;
218 natural_width guest_ds_base;
219 natural_width guest_fs_base;
220 natural_width guest_gs_base;
221 natural_width guest_ldtr_base;
222 natural_width guest_tr_base;
223 natural_width guest_gdtr_base;
224 natural_width guest_idtr_base;
225 natural_width guest_dr7;
226 natural_width guest_rsp;
227 natural_width guest_rip;
228 natural_width guest_rflags;
229 natural_width guest_pending_dbg_exceptions;
230 natural_width guest_sysenter_esp;
231 natural_width guest_sysenter_eip;
232 natural_width host_cr0;
233 natural_width host_cr3;
234 natural_width host_cr4;
235 natural_width host_fs_base;
236 natural_width host_gs_base;
237 natural_width host_tr_base;
238 natural_width host_gdtr_base;
239 natural_width host_idtr_base;
240 natural_width host_ia32_sysenter_esp;
241 natural_width host_ia32_sysenter_eip;
242 natural_width host_rsp;
243 natural_width host_rip;
244 natural_width paddingl[8]; /* room for future expansion */
245 u32 pin_based_vm_exec_control;
246 u32 cpu_based_vm_exec_control;
247 u32 exception_bitmap;
248 u32 page_fault_error_code_mask;
249 u32 page_fault_error_code_match;
250 u32 cr3_target_count;
251 u32 vm_exit_controls;
252 u32 vm_exit_msr_store_count;
253 u32 vm_exit_msr_load_count;
254 u32 vm_entry_controls;
255 u32 vm_entry_msr_load_count;
256 u32 vm_entry_intr_info_field;
257 u32 vm_entry_exception_error_code;
258 u32 vm_entry_instruction_len;
260 u32 secondary_vm_exec_control;
261 u32 vm_instruction_error;
263 u32 vm_exit_intr_info;
264 u32 vm_exit_intr_error_code;
265 u32 idt_vectoring_info_field;
266 u32 idt_vectoring_error_code;
267 u32 vm_exit_instruction_len;
268 u32 vmx_instruction_info;
275 u32 guest_ldtr_limit;
277 u32 guest_gdtr_limit;
278 u32 guest_idtr_limit;
279 u32 guest_es_ar_bytes;
280 u32 guest_cs_ar_bytes;
281 u32 guest_ss_ar_bytes;
282 u32 guest_ds_ar_bytes;
283 u32 guest_fs_ar_bytes;
284 u32 guest_gs_ar_bytes;
285 u32 guest_ldtr_ar_bytes;
286 u32 guest_tr_ar_bytes;
287 u32 guest_interruptibility_info;
288 u32 guest_activity_state;
289 u32 guest_sysenter_cs;
290 u32 host_ia32_sysenter_cs;
291 u32 padding32[8]; /* room for future expansion */
292 u16 virtual_processor_id;
293 u16 guest_es_selector;
294 u16 guest_cs_selector;
295 u16 guest_ss_selector;
296 u16 guest_ds_selector;
297 u16 guest_fs_selector;
298 u16 guest_gs_selector;
299 u16 guest_ldtr_selector;
300 u16 guest_tr_selector;
301 u16 host_es_selector;
302 u16 host_cs_selector;
303 u16 host_ss_selector;
304 u16 host_ds_selector;
305 u16 host_fs_selector;
306 u16 host_gs_selector;
307 u16 host_tr_selector;
311 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
315 #define VMCS12_REVISION 0x11e57ed0
318 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320 * current implementation, 4K are reserved to avoid future complications.
322 #define VMCS12_SIZE 0x1000
324 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
326 struct list_head list;
328 struct loaded_vmcs vmcs02;
332 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
336 /* Has the level1 guest done vmxon? */
339 /* The guest-physical address of the current VMCS L1 keeps for L2 */
341 /* The host-usable pointer to the above */
342 struct page *current_vmcs12_page;
343 struct vmcs12 *current_vmcs12;
345 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346 struct list_head vmcs02_pool;
348 u64 vmcs01_tsc_offset;
349 /* L2 must run next, and mustn't decide to exit to L1. */
350 bool nested_run_pending;
352 * Guest pages referred to in vmcs02 with host-physical pointers, so
353 * we must keep them pinned while L2 runs.
355 struct page *apic_access_page;
359 struct kvm_vcpu vcpu;
360 unsigned long host_rsp;
363 bool nmi_known_unmasked;
365 u32 idt_vectoring_info;
367 struct shared_msr_entry *guest_msrs;
371 u64 msr_host_kernel_gs_base;
372 u64 msr_guest_kernel_gs_base;
375 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
376 * non-nested (L1) guest, it always points to vmcs01. For a nested
377 * guest (L2), it points to a different VMCS.
379 struct loaded_vmcs vmcs01;
380 struct loaded_vmcs *loaded_vmcs;
381 bool __launched; /* temporary, used in vmx_vcpu_run */
382 struct msr_autoload {
384 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
385 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
389 u16 fs_sel, gs_sel, ldt_sel;
390 int gs_ldt_reload_needed;
391 int fs_reload_needed;
396 struct kvm_save_segment {
401 } tr, es, ds, fs, gs;
404 u32 bitmask; /* 4 bits per segment (1 bit per field) */
405 struct kvm_save_segment seg[8];
408 bool emulation_required;
410 /* Support for vnmi-less CPUs */
411 int soft_vnmi_blocked;
413 s64 vnmi_blocked_time;
418 /* Support for a guest hypervisor (nested VMX) */
419 struct nested_vmx nested;
422 enum segment_cache_field {
431 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
433 return container_of(vcpu, struct vcpu_vmx, vcpu);
436 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
437 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
438 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
439 [number##_HIGH] = VMCS12_OFFSET(name)+4
441 static unsigned short vmcs_field_to_offset_table[] = {
442 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
443 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
444 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
445 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
446 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
447 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
448 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
449 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
450 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
451 FIELD(HOST_ES_SELECTOR, host_es_selector),
452 FIELD(HOST_CS_SELECTOR, host_cs_selector),
453 FIELD(HOST_SS_SELECTOR, host_ss_selector),
454 FIELD(HOST_DS_SELECTOR, host_ds_selector),
455 FIELD(HOST_FS_SELECTOR, host_fs_selector),
456 FIELD(HOST_GS_SELECTOR, host_gs_selector),
457 FIELD(HOST_TR_SELECTOR, host_tr_selector),
458 FIELD64(IO_BITMAP_A, io_bitmap_a),
459 FIELD64(IO_BITMAP_B, io_bitmap_b),
460 FIELD64(MSR_BITMAP, msr_bitmap),
461 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
462 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
463 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
464 FIELD64(TSC_OFFSET, tsc_offset),
465 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
466 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
467 FIELD64(EPT_POINTER, ept_pointer),
468 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
469 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
470 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
471 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
472 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
473 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
474 FIELD64(GUEST_PDPTR0, guest_pdptr0),
475 FIELD64(GUEST_PDPTR1, guest_pdptr1),
476 FIELD64(GUEST_PDPTR2, guest_pdptr2),
477 FIELD64(GUEST_PDPTR3, guest_pdptr3),
478 FIELD64(HOST_IA32_PAT, host_ia32_pat),
479 FIELD64(HOST_IA32_EFER, host_ia32_efer),
480 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
481 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
482 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
483 FIELD(EXCEPTION_BITMAP, exception_bitmap),
484 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
485 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
486 FIELD(CR3_TARGET_COUNT, cr3_target_count),
487 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
488 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
489 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
490 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
491 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
492 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
493 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
494 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
495 FIELD(TPR_THRESHOLD, tpr_threshold),
496 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
497 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
498 FIELD(VM_EXIT_REASON, vm_exit_reason),
499 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
500 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
501 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
502 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
503 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
504 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
505 FIELD(GUEST_ES_LIMIT, guest_es_limit),
506 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
507 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
508 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
509 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
510 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
511 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
512 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
513 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
514 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
515 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
516 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
517 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
518 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
519 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
520 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
521 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
522 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
523 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
524 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
525 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
526 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
527 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
528 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
529 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
530 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
531 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
532 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
533 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
534 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
535 FIELD(EXIT_QUALIFICATION, exit_qualification),
536 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
537 FIELD(GUEST_CR0, guest_cr0),
538 FIELD(GUEST_CR3, guest_cr3),
539 FIELD(GUEST_CR4, guest_cr4),
540 FIELD(GUEST_ES_BASE, guest_es_base),
541 FIELD(GUEST_CS_BASE, guest_cs_base),
542 FIELD(GUEST_SS_BASE, guest_ss_base),
543 FIELD(GUEST_DS_BASE, guest_ds_base),
544 FIELD(GUEST_FS_BASE, guest_fs_base),
545 FIELD(GUEST_GS_BASE, guest_gs_base),
546 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
547 FIELD(GUEST_TR_BASE, guest_tr_base),
548 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
549 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
550 FIELD(GUEST_DR7, guest_dr7),
551 FIELD(GUEST_RSP, guest_rsp),
552 FIELD(GUEST_RIP, guest_rip),
553 FIELD(GUEST_RFLAGS, guest_rflags),
554 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
555 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
556 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
557 FIELD(HOST_CR0, host_cr0),
558 FIELD(HOST_CR3, host_cr3),
559 FIELD(HOST_CR4, host_cr4),
560 FIELD(HOST_FS_BASE, host_fs_base),
561 FIELD(HOST_GS_BASE, host_gs_base),
562 FIELD(HOST_TR_BASE, host_tr_base),
563 FIELD(HOST_GDTR_BASE, host_gdtr_base),
564 FIELD(HOST_IDTR_BASE, host_idtr_base),
565 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
566 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
567 FIELD(HOST_RSP, host_rsp),
568 FIELD(HOST_RIP, host_rip),
570 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
572 static inline short vmcs_field_to_offset(unsigned long field)
574 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
576 return vmcs_field_to_offset_table[field];
579 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
581 return to_vmx(vcpu)->nested.current_vmcs12;
584 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
586 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
587 if (is_error_page(page)) {
588 kvm_release_page_clean(page);
594 static void nested_release_page(struct page *page)
596 kvm_release_page_dirty(page);
599 static void nested_release_page_clean(struct page *page)
601 kvm_release_page_clean(page);
604 static u64 construct_eptp(unsigned long root_hpa);
605 static void kvm_cpu_vmxon(u64 addr);
606 static void kvm_cpu_vmxoff(void);
607 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
608 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
610 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
611 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
613 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
614 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
616 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
617 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
619 static unsigned long *vmx_io_bitmap_a;
620 static unsigned long *vmx_io_bitmap_b;
621 static unsigned long *vmx_msr_bitmap_legacy;
622 static unsigned long *vmx_msr_bitmap_longmode;
624 static bool cpu_has_load_ia32_efer;
626 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
627 static DEFINE_SPINLOCK(vmx_vpid_lock);
629 static struct vmcs_config {
633 u32 pin_based_exec_ctrl;
634 u32 cpu_based_exec_ctrl;
635 u32 cpu_based_2nd_exec_ctrl;
640 static struct vmx_capability {
645 #define VMX_SEGMENT_FIELD(seg) \
646 [VCPU_SREG_##seg] = { \
647 .selector = GUEST_##seg##_SELECTOR, \
648 .base = GUEST_##seg##_BASE, \
649 .limit = GUEST_##seg##_LIMIT, \
650 .ar_bytes = GUEST_##seg##_AR_BYTES, \
653 static struct kvm_vmx_segment_field {
658 } kvm_vmx_segment_fields[] = {
659 VMX_SEGMENT_FIELD(CS),
660 VMX_SEGMENT_FIELD(DS),
661 VMX_SEGMENT_FIELD(ES),
662 VMX_SEGMENT_FIELD(FS),
663 VMX_SEGMENT_FIELD(GS),
664 VMX_SEGMENT_FIELD(SS),
665 VMX_SEGMENT_FIELD(TR),
666 VMX_SEGMENT_FIELD(LDTR),
669 static u64 host_efer;
671 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
674 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
675 * away by decrementing the array size.
677 static const u32 vmx_msr_index[] = {
679 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
681 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
683 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
685 static inline bool is_page_fault(u32 intr_info)
687 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
688 INTR_INFO_VALID_MASK)) ==
689 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
692 static inline bool is_no_device(u32 intr_info)
694 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
695 INTR_INFO_VALID_MASK)) ==
696 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
699 static inline bool is_invalid_opcode(u32 intr_info)
701 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
702 INTR_INFO_VALID_MASK)) ==
703 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
706 static inline bool is_external_interrupt(u32 intr_info)
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
709 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
712 static inline bool is_machine_check(u32 intr_info)
714 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
715 INTR_INFO_VALID_MASK)) ==
716 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
719 static inline bool cpu_has_vmx_msr_bitmap(void)
721 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
724 static inline bool cpu_has_vmx_tpr_shadow(void)
726 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
729 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
731 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
734 static inline bool cpu_has_secondary_exec_ctrls(void)
736 return vmcs_config.cpu_based_exec_ctrl &
737 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
740 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
742 return vmcs_config.cpu_based_2nd_exec_ctrl &
743 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
746 static inline bool cpu_has_vmx_flexpriority(void)
748 return cpu_has_vmx_tpr_shadow() &&
749 cpu_has_vmx_virtualize_apic_accesses();
752 static inline bool cpu_has_vmx_ept_execute_only(void)
754 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
757 static inline bool cpu_has_vmx_eptp_uncacheable(void)
759 return vmx_capability.ept & VMX_EPTP_UC_BIT;
762 static inline bool cpu_has_vmx_eptp_writeback(void)
764 return vmx_capability.ept & VMX_EPTP_WB_BIT;
767 static inline bool cpu_has_vmx_ept_2m_page(void)
769 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
772 static inline bool cpu_has_vmx_ept_1g_page(void)
774 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
777 static inline bool cpu_has_vmx_ept_4levels(void)
779 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
782 static inline bool cpu_has_vmx_invept_individual_addr(void)
784 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
787 static inline bool cpu_has_vmx_invept_context(void)
789 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
792 static inline bool cpu_has_vmx_invept_global(void)
794 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
797 static inline bool cpu_has_vmx_invvpid_single(void)
799 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
802 static inline bool cpu_has_vmx_invvpid_global(void)
804 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
807 static inline bool cpu_has_vmx_ept(void)
809 return vmcs_config.cpu_based_2nd_exec_ctrl &
810 SECONDARY_EXEC_ENABLE_EPT;
813 static inline bool cpu_has_vmx_unrestricted_guest(void)
815 return vmcs_config.cpu_based_2nd_exec_ctrl &
816 SECONDARY_EXEC_UNRESTRICTED_GUEST;
819 static inline bool cpu_has_vmx_ple(void)
821 return vmcs_config.cpu_based_2nd_exec_ctrl &
822 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
825 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
827 return flexpriority_enabled && irqchip_in_kernel(kvm);
830 static inline bool cpu_has_vmx_vpid(void)
832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_VPID;
836 static inline bool cpu_has_vmx_rdtscp(void)
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_RDTSCP;
842 static inline bool cpu_has_virtual_nmis(void)
844 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
847 static inline bool cpu_has_vmx_wbinvd_exit(void)
849 return vmcs_config.cpu_based_2nd_exec_ctrl &
850 SECONDARY_EXEC_WBINVD_EXITING;
853 static inline bool report_flexpriority(void)
855 return flexpriority_enabled;
858 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
860 return vmcs12->cpu_based_vm_exec_control & bit;
863 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
865 return (vmcs12->cpu_based_vm_exec_control &
866 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
867 (vmcs12->secondary_vm_exec_control & bit);
870 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
871 struct kvm_vcpu *vcpu)
873 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
876 static inline bool is_exception(u32 intr_info)
878 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
879 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
882 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
883 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
884 struct vmcs12 *vmcs12,
885 u32 reason, unsigned long qualification);
887 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
891 for (i = 0; i < vmx->nmsrs; ++i)
892 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
897 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
903 } operand = { vpid, 0, gva };
905 asm volatile (__ex(ASM_VMX_INVVPID)
906 /* CF==1 or ZF==1 --> rc = -1 */
908 : : "a"(&operand), "c"(ext) : "cc", "memory");
911 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
915 } operand = {eptp, gpa};
917 asm volatile (__ex(ASM_VMX_INVEPT)
918 /* CF==1 or ZF==1 --> rc = -1 */
919 "; ja 1f ; ud2 ; 1:\n"
920 : : "a" (&operand), "c" (ext) : "cc", "memory");
923 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
927 i = __find_msr_index(vmx, msr);
929 return &vmx->guest_msrs[i];
933 static void vmcs_clear(struct vmcs *vmcs)
935 u64 phys_addr = __pa(vmcs);
938 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
939 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
942 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
946 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
948 vmcs_clear(loaded_vmcs->vmcs);
949 loaded_vmcs->cpu = -1;
950 loaded_vmcs->launched = 0;
953 static void vmcs_load(struct vmcs *vmcs)
955 u64 phys_addr = __pa(vmcs);
958 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
959 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
962 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
966 static void __loaded_vmcs_clear(void *arg)
968 struct loaded_vmcs *loaded_vmcs = arg;
969 int cpu = raw_smp_processor_id();
971 if (loaded_vmcs->cpu != cpu)
972 return; /* vcpu migration can race with cpu offline */
973 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
974 per_cpu(current_vmcs, cpu) = NULL;
975 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
976 loaded_vmcs_init(loaded_vmcs);
979 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
981 if (loaded_vmcs->cpu != -1)
982 smp_call_function_single(
983 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
986 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
991 if (cpu_has_vmx_invvpid_single())
992 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
995 static inline void vpid_sync_vcpu_global(void)
997 if (cpu_has_vmx_invvpid_global())
998 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1001 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1003 if (cpu_has_vmx_invvpid_single())
1004 vpid_sync_vcpu_single(vmx);
1006 vpid_sync_vcpu_global();
1009 static inline void ept_sync_global(void)
1011 if (cpu_has_vmx_invept_global())
1012 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1015 static inline void ept_sync_context(u64 eptp)
1018 if (cpu_has_vmx_invept_context())
1019 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1025 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1028 if (cpu_has_vmx_invept_individual_addr())
1029 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1032 ept_sync_context(eptp);
1036 static __always_inline unsigned long vmcs_readl(unsigned long field)
1038 unsigned long value;
1040 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041 : "=a"(value) : "d"(field) : "cc");
1045 static __always_inline u16 vmcs_read16(unsigned long field)
1047 return vmcs_readl(field);
1050 static __always_inline u32 vmcs_read32(unsigned long field)
1052 return vmcs_readl(field);
1055 static __always_inline u64 vmcs_read64(unsigned long field)
1057 #ifdef CONFIG_X86_64
1058 return vmcs_readl(field);
1060 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1064 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1066 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1071 static void vmcs_writel(unsigned long field, unsigned long value)
1075 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1076 : "=q"(error) : "a"(value), "d"(field) : "cc");
1077 if (unlikely(error))
1078 vmwrite_error(field, value);
1081 static void vmcs_write16(unsigned long field, u16 value)
1083 vmcs_writel(field, value);
1086 static void vmcs_write32(unsigned long field, u32 value)
1088 vmcs_writel(field, value);
1091 static void vmcs_write64(unsigned long field, u64 value)
1093 vmcs_writel(field, value);
1094 #ifndef CONFIG_X86_64
1096 vmcs_writel(field+1, value >> 32);
1100 static void vmcs_clear_bits(unsigned long field, u32 mask)
1102 vmcs_writel(field, vmcs_readl(field) & ~mask);
1105 static void vmcs_set_bits(unsigned long field, u32 mask)
1107 vmcs_writel(field, vmcs_readl(field) | mask);
1110 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1112 vmx->segment_cache.bitmask = 0;
1115 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1119 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1121 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123 vmx->segment_cache.bitmask = 0;
1125 ret = vmx->segment_cache.bitmask & mask;
1126 vmx->segment_cache.bitmask |= mask;
1130 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1132 u16 *p = &vmx->segment_cache.seg[seg].selector;
1134 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1139 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1141 ulong *p = &vmx->segment_cache.seg[seg].base;
1143 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1148 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1150 u32 *p = &vmx->segment_cache.seg[seg].limit;
1152 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1157 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1159 u32 *p = &vmx->segment_cache.seg[seg].ar;
1161 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1166 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1170 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172 if ((vcpu->guest_debug &
1173 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175 eb |= 1u << BP_VECTOR;
1176 if (to_vmx(vcpu)->rmode.vm86_active)
1179 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1180 if (vcpu->fpu_active)
1181 eb &= ~(1u << NM_VECTOR);
1182 vmcs_write32(EXCEPTION_BITMAP, eb);
1185 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1188 struct msr_autoload *m = &vmx->msr_autoload;
1190 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1191 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1192 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1196 for (i = 0; i < m->nr; ++i)
1197 if (m->guest[i].index == msr)
1203 m->guest[i] = m->guest[m->nr];
1204 m->host[i] = m->host[m->nr];
1205 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1206 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1209 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1210 u64 guest_val, u64 host_val)
1213 struct msr_autoload *m = &vmx->msr_autoload;
1215 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1216 vmcs_write64(GUEST_IA32_EFER, guest_val);
1217 vmcs_write64(HOST_IA32_EFER, host_val);
1218 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1219 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1223 for (i = 0; i < m->nr; ++i)
1224 if (m->guest[i].index == msr)
1229 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1230 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1233 m->guest[i].index = msr;
1234 m->guest[i].value = guest_val;
1235 m->host[i].index = msr;
1236 m->host[i].value = host_val;
1239 static void reload_tss(void)
1242 * VT restores TR but not its size. Useless.
1244 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1245 struct desc_struct *descs;
1247 descs = (void *)gdt->address;
1248 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1252 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1257 guest_efer = vmx->vcpu.arch.efer;
1260 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1263 ignore_bits = EFER_NX | EFER_SCE;
1264 #ifdef CONFIG_X86_64
1265 ignore_bits |= EFER_LMA | EFER_LME;
1266 /* SCE is meaningful only in long mode on Intel */
1267 if (guest_efer & EFER_LMA)
1268 ignore_bits &= ~(u64)EFER_SCE;
1270 guest_efer &= ~ignore_bits;
1271 guest_efer |= host_efer & ignore_bits;
1272 vmx->guest_msrs[efer_offset].data = guest_efer;
1273 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1275 clear_atomic_switch_msr(vmx, MSR_EFER);
1276 /* On ept, can't emulate nx, and must switch nx atomically */
1277 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1278 guest_efer = vmx->vcpu.arch.efer;
1279 if (!(guest_efer & EFER_LMA))
1280 guest_efer &= ~EFER_LME;
1281 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1288 static unsigned long segment_base(u16 selector)
1290 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1291 struct desc_struct *d;
1292 unsigned long table_base;
1295 if (!(selector & ~3))
1298 table_base = gdt->address;
1300 if (selector & 4) { /* from ldt */
1301 u16 ldt_selector = kvm_read_ldt();
1303 if (!(ldt_selector & ~3))
1306 table_base = segment_base(ldt_selector);
1308 d = (struct desc_struct *)(table_base + (selector & ~7));
1309 v = get_desc_base(d);
1310 #ifdef CONFIG_X86_64
1311 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1312 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1317 static inline unsigned long kvm_read_tr_base(void)
1320 asm("str %0" : "=g"(tr));
1321 return segment_base(tr);
1324 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1326 struct vcpu_vmx *vmx = to_vmx(vcpu);
1329 if (vmx->host_state.loaded)
1332 vmx->host_state.loaded = 1;
1334 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1335 * allow segment selectors with cpl > 0 or ti == 1.
1337 vmx->host_state.ldt_sel = kvm_read_ldt();
1338 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1339 savesegment(fs, vmx->host_state.fs_sel);
1340 if (!(vmx->host_state.fs_sel & 7)) {
1341 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1342 vmx->host_state.fs_reload_needed = 0;
1344 vmcs_write16(HOST_FS_SELECTOR, 0);
1345 vmx->host_state.fs_reload_needed = 1;
1347 savesegment(gs, vmx->host_state.gs_sel);
1348 if (!(vmx->host_state.gs_sel & 7))
1349 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1351 vmcs_write16(HOST_GS_SELECTOR, 0);
1352 vmx->host_state.gs_ldt_reload_needed = 1;
1355 #ifdef CONFIG_X86_64
1356 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1357 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1359 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1360 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1363 #ifdef CONFIG_X86_64
1364 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1365 if (is_long_mode(&vmx->vcpu))
1366 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1368 for (i = 0; i < vmx->save_nmsrs; ++i)
1369 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1370 vmx->guest_msrs[i].data,
1371 vmx->guest_msrs[i].mask);
1374 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1376 if (!vmx->host_state.loaded)
1379 ++vmx->vcpu.stat.host_state_reload;
1380 vmx->host_state.loaded = 0;
1381 #ifdef CONFIG_X86_64
1382 if (is_long_mode(&vmx->vcpu))
1383 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1385 if (vmx->host_state.gs_ldt_reload_needed) {
1386 kvm_load_ldt(vmx->host_state.ldt_sel);
1387 #ifdef CONFIG_X86_64
1388 load_gs_index(vmx->host_state.gs_sel);
1390 loadsegment(gs, vmx->host_state.gs_sel);
1393 if (vmx->host_state.fs_reload_needed)
1394 loadsegment(fs, vmx->host_state.fs_sel);
1396 #ifdef CONFIG_X86_64
1397 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1399 if (current_thread_info()->status & TS_USEDFPU)
1401 load_gdt(&__get_cpu_var(host_gdt));
1404 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1407 __vmx_load_host_state(vmx);
1412 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1413 * vcpu mutex is already taken.
1415 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1417 struct vcpu_vmx *vmx = to_vmx(vcpu);
1418 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1421 kvm_cpu_vmxon(phys_addr);
1422 else if (vmx->loaded_vmcs->cpu != cpu)
1423 loaded_vmcs_clear(vmx->loaded_vmcs);
1425 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1426 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1427 vmcs_load(vmx->loaded_vmcs->vmcs);
1430 if (vmx->loaded_vmcs->cpu != cpu) {
1431 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1432 unsigned long sysenter_esp;
1434 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1435 local_irq_disable();
1436 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1437 &per_cpu(loaded_vmcss_on_cpu, cpu));
1441 * Linux uses per-cpu TSS and GDT, so set these when switching
1444 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1445 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1447 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1448 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1449 vmx->loaded_vmcs->cpu = cpu;
1453 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1455 __vmx_load_host_state(to_vmx(vcpu));
1456 if (!vmm_exclusive) {
1457 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1463 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1467 if (vcpu->fpu_active)
1469 vcpu->fpu_active = 1;
1470 cr0 = vmcs_readl(GUEST_CR0);
1471 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1472 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1473 vmcs_writel(GUEST_CR0, cr0);
1474 update_exception_bitmap(vcpu);
1475 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1476 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1479 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1482 * Return the cr0 value that a nested guest would read. This is a combination
1483 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1484 * its hypervisor (cr0_read_shadow).
1486 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1488 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1489 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1491 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1493 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1494 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1497 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1499 vmx_decache_cr0_guest_bits(vcpu);
1500 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1501 update_exception_bitmap(vcpu);
1502 vcpu->arch.cr0_guest_owned_bits = 0;
1503 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1504 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1507 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1509 unsigned long rflags, save_rflags;
1511 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1512 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1513 rflags = vmcs_readl(GUEST_RFLAGS);
1514 if (to_vmx(vcpu)->rmode.vm86_active) {
1515 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1516 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1517 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1519 to_vmx(vcpu)->rflags = rflags;
1521 return to_vmx(vcpu)->rflags;
1524 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1526 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1527 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1528 to_vmx(vcpu)->rflags = rflags;
1529 if (to_vmx(vcpu)->rmode.vm86_active) {
1530 to_vmx(vcpu)->rmode.save_rflags = rflags;
1531 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1533 vmcs_writel(GUEST_RFLAGS, rflags);
1536 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1538 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1541 if (interruptibility & GUEST_INTR_STATE_STI)
1542 ret |= KVM_X86_SHADOW_INT_STI;
1543 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1544 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1549 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1551 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1552 u32 interruptibility = interruptibility_old;
1554 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1556 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1557 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1558 else if (mask & KVM_X86_SHADOW_INT_STI)
1559 interruptibility |= GUEST_INTR_STATE_STI;
1561 if ((interruptibility != interruptibility_old))
1562 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1565 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1569 rip = kvm_rip_read(vcpu);
1570 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1571 kvm_rip_write(vcpu, rip);
1573 /* skipping an emulated instruction also counts */
1574 vmx_set_interrupt_shadow(vcpu, 0);
1577 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1579 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1580 * explicitly skip the instruction because if the HLT state is set, then
1581 * the instruction is already executing and RIP has already been
1583 if (!yield_on_hlt &&
1584 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1585 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1589 * KVM wants to inject page-faults which it got to the guest. This function
1590 * checks whether in a nested guest, we need to inject them to L1 or L2.
1591 * This function assumes it is called with the exit reason in vmcs02 being
1592 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1595 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1597 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1599 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1600 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1603 nested_vmx_vmexit(vcpu);
1607 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1608 bool has_error_code, u32 error_code,
1611 struct vcpu_vmx *vmx = to_vmx(vcpu);
1612 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1614 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1615 nested_pf_handled(vcpu))
1618 if (has_error_code) {
1619 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1620 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1623 if (vmx->rmode.vm86_active) {
1625 if (kvm_exception_is_soft(nr))
1626 inc_eip = vcpu->arch.event_exit_inst_len;
1627 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1628 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1632 if (kvm_exception_is_soft(nr)) {
1633 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1634 vmx->vcpu.arch.event_exit_inst_len);
1635 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1637 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1639 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1640 vmx_clear_hlt(vcpu);
1643 static bool vmx_rdtscp_supported(void)
1645 return cpu_has_vmx_rdtscp();
1649 * Swap MSR entry in host/guest MSR entry array.
1651 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1653 struct shared_msr_entry tmp;
1655 tmp = vmx->guest_msrs[to];
1656 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1657 vmx->guest_msrs[from] = tmp;
1661 * Set up the vmcs to automatically save and restore system
1662 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1663 * mode, as fiddling with msrs is very expensive.
1665 static void setup_msrs(struct vcpu_vmx *vmx)
1667 int save_nmsrs, index;
1668 unsigned long *msr_bitmap;
1670 vmx_load_host_state(vmx);
1672 #ifdef CONFIG_X86_64
1673 if (is_long_mode(&vmx->vcpu)) {
1674 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1676 move_msr_up(vmx, index, save_nmsrs++);
1677 index = __find_msr_index(vmx, MSR_LSTAR);
1679 move_msr_up(vmx, index, save_nmsrs++);
1680 index = __find_msr_index(vmx, MSR_CSTAR);
1682 move_msr_up(vmx, index, save_nmsrs++);
1683 index = __find_msr_index(vmx, MSR_TSC_AUX);
1684 if (index >= 0 && vmx->rdtscp_enabled)
1685 move_msr_up(vmx, index, save_nmsrs++);
1687 * MSR_STAR is only needed on long mode guests, and only
1688 * if efer.sce is enabled.
1690 index = __find_msr_index(vmx, MSR_STAR);
1691 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1692 move_msr_up(vmx, index, save_nmsrs++);
1695 index = __find_msr_index(vmx, MSR_EFER);
1696 if (index >= 0 && update_transition_efer(vmx, index))
1697 move_msr_up(vmx, index, save_nmsrs++);
1699 vmx->save_nmsrs = save_nmsrs;
1701 if (cpu_has_vmx_msr_bitmap()) {
1702 if (is_long_mode(&vmx->vcpu))
1703 msr_bitmap = vmx_msr_bitmap_longmode;
1705 msr_bitmap = vmx_msr_bitmap_legacy;
1707 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1712 * reads and returns guest's timestamp counter "register"
1713 * guest_tsc = host_tsc + tsc_offset -- 21.3
1715 static u64 guest_read_tsc(void)
1717 u64 host_tsc, tsc_offset;
1720 tsc_offset = vmcs_read64(TSC_OFFSET);
1721 return host_tsc + tsc_offset;
1725 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1726 * ioctl. In this case the call-back should update internal vmx state to make
1727 * the changes effective.
1729 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1731 /* Nothing to do here */
1735 * writes 'offset' into guest's timestamp counter offset register
1737 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1739 vmcs_write64(TSC_OFFSET, offset);
1742 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1744 u64 offset = vmcs_read64(TSC_OFFSET);
1745 vmcs_write64(TSC_OFFSET, offset + adjustment);
1748 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1750 return target_tsc - native_read_tsc();
1753 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1755 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1756 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1760 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1761 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1762 * all guests if the "nested" module option is off, and can also be disabled
1763 * for a single guest by disabling its VMX cpuid bit.
1765 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1767 return nested && guest_cpuid_has_vmx(vcpu);
1771 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1772 * returned for the various VMX controls MSRs when nested VMX is enabled.
1773 * The same values should also be used to verify that vmcs12 control fields are
1774 * valid during nested entry from L1 to L2.
1775 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1776 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1777 * bit in the high half is on if the corresponding bit in the control field
1778 * may be on. See also vmx_control_verify().
1779 * TODO: allow these variables to be modified (downgraded) by module options
1782 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1783 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1784 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1785 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1786 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1787 static __init void nested_vmx_setup_ctls_msrs(void)
1790 * Note that as a general rule, the high half of the MSRs (bits in
1791 * the control fields which may be 1) should be initialized by the
1792 * intersection of the underlying hardware's MSR (i.e., features which
1793 * can be supported) and the list of features we want to expose -
1794 * because they are known to be properly supported in our code.
1795 * Also, usually, the low half of the MSRs (bits which must be 1) can
1796 * be set to 0, meaning that L1 may turn off any of these bits. The
1797 * reason is that if one of these bits is necessary, it will appear
1798 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1799 * fields of vmcs01 and vmcs02, will turn these bits off - and
1800 * nested_vmx_exit_handled() will not pass related exits to L1.
1801 * These rules have exceptions below.
1804 /* pin-based controls */
1806 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1807 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1809 nested_vmx_pinbased_ctls_low = 0x16 ;
1810 nested_vmx_pinbased_ctls_high = 0x16 |
1811 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1812 PIN_BASED_VIRTUAL_NMIS;
1815 nested_vmx_exit_ctls_low = 0;
1816 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1817 #ifdef CONFIG_X86_64
1818 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1820 nested_vmx_exit_ctls_high = 0;
1823 /* entry controls */
1824 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1825 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1826 nested_vmx_entry_ctls_low = 0;
1827 nested_vmx_entry_ctls_high &=
1828 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1830 /* cpu-based controls */
1831 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1832 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1833 nested_vmx_procbased_ctls_low = 0;
1834 nested_vmx_procbased_ctls_high &=
1835 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1836 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1837 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1838 CPU_BASED_CR3_STORE_EXITING |
1839 #ifdef CONFIG_X86_64
1840 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1842 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1843 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1844 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1846 * We can allow some features even when not supported by the
1847 * hardware. For example, L1 can specify an MSR bitmap - and we
1848 * can use it to avoid exits to L1 - even when L0 runs L2
1849 * without MSR bitmaps.
1851 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1853 /* secondary cpu-based controls */
1854 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1855 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1856 nested_vmx_secondary_ctls_low = 0;
1857 nested_vmx_secondary_ctls_high &=
1858 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1861 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1864 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1866 return ((control & high) | low) == control;
1869 static inline u64 vmx_control_msr(u32 low, u32 high)
1871 return low | ((u64)high << 32);
1875 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1876 * also let it use VMX-specific MSRs.
1877 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1878 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1879 * like all other MSRs).
1881 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1883 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1884 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1886 * According to the spec, processors which do not support VMX
1887 * should throw a #GP(0) when VMX capability MSRs are read.
1889 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1893 switch (msr_index) {
1894 case MSR_IA32_FEATURE_CONTROL:
1897 case MSR_IA32_VMX_BASIC:
1899 * This MSR reports some information about VMX support. We
1900 * should return information about the VMX we emulate for the
1901 * guest, and the VMCS structure we give it - not about the
1902 * VMX support of the underlying hardware.
1904 *pdata = VMCS12_REVISION |
1905 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1906 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1908 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1909 case MSR_IA32_VMX_PINBASED_CTLS:
1910 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1911 nested_vmx_pinbased_ctls_high);
1913 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1914 case MSR_IA32_VMX_PROCBASED_CTLS:
1915 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1916 nested_vmx_procbased_ctls_high);
1918 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1919 case MSR_IA32_VMX_EXIT_CTLS:
1920 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1921 nested_vmx_exit_ctls_high);
1923 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1924 case MSR_IA32_VMX_ENTRY_CTLS:
1925 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1926 nested_vmx_entry_ctls_high);
1928 case MSR_IA32_VMX_MISC:
1932 * These MSRs specify bits which the guest must keep fixed (on or off)
1933 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1934 * We picked the standard core2 setting.
1936 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1937 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1938 case MSR_IA32_VMX_CR0_FIXED0:
1939 *pdata = VMXON_CR0_ALWAYSON;
1941 case MSR_IA32_VMX_CR0_FIXED1:
1944 case MSR_IA32_VMX_CR4_FIXED0:
1945 *pdata = VMXON_CR4_ALWAYSON;
1947 case MSR_IA32_VMX_CR4_FIXED1:
1950 case MSR_IA32_VMX_VMCS_ENUM:
1953 case MSR_IA32_VMX_PROCBASED_CTLS2:
1954 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1955 nested_vmx_secondary_ctls_high);
1957 case MSR_IA32_VMX_EPT_VPID_CAP:
1958 /* Currently, no nested ept or nested vpid */
1968 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1970 if (!nested_vmx_allowed(vcpu))
1973 if (msr_index == MSR_IA32_FEATURE_CONTROL)
1974 /* TODO: the right thing. */
1977 * No need to treat VMX capability MSRs specially: If we don't handle
1978 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1984 * Reads an msr value (of 'msr_index') into 'pdata'.
1985 * Returns 0 on success, non-0 otherwise.
1986 * Assumes vcpu_load() was already called.
1988 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1991 struct shared_msr_entry *msr;
1994 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1998 switch (msr_index) {
1999 #ifdef CONFIG_X86_64
2001 data = vmcs_readl(GUEST_FS_BASE);
2004 data = vmcs_readl(GUEST_GS_BASE);
2006 case MSR_KERNEL_GS_BASE:
2007 vmx_load_host_state(to_vmx(vcpu));
2008 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2012 return kvm_get_msr_common(vcpu, msr_index, pdata);
2014 data = guest_read_tsc();
2016 case MSR_IA32_SYSENTER_CS:
2017 data = vmcs_read32(GUEST_SYSENTER_CS);
2019 case MSR_IA32_SYSENTER_EIP:
2020 data = vmcs_readl(GUEST_SYSENTER_EIP);
2022 case MSR_IA32_SYSENTER_ESP:
2023 data = vmcs_readl(GUEST_SYSENTER_ESP);
2026 if (!to_vmx(vcpu)->rdtscp_enabled)
2028 /* Otherwise falls through */
2030 vmx_load_host_state(to_vmx(vcpu));
2031 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2033 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2035 vmx_load_host_state(to_vmx(vcpu));
2039 return kvm_get_msr_common(vcpu, msr_index, pdata);
2047 * Writes msr value into into the appropriate "register".
2048 * Returns 0 on success, non-0 otherwise.
2049 * Assumes vcpu_load() was already called.
2051 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2053 struct vcpu_vmx *vmx = to_vmx(vcpu);
2054 struct shared_msr_entry *msr;
2057 switch (msr_index) {
2059 vmx_load_host_state(vmx);
2060 ret = kvm_set_msr_common(vcpu, msr_index, data);
2062 #ifdef CONFIG_X86_64
2064 vmx_segment_cache_clear(vmx);
2065 vmcs_writel(GUEST_FS_BASE, data);
2068 vmx_segment_cache_clear(vmx);
2069 vmcs_writel(GUEST_GS_BASE, data);
2071 case MSR_KERNEL_GS_BASE:
2072 vmx_load_host_state(vmx);
2073 vmx->msr_guest_kernel_gs_base = data;
2076 case MSR_IA32_SYSENTER_CS:
2077 vmcs_write32(GUEST_SYSENTER_CS, data);
2079 case MSR_IA32_SYSENTER_EIP:
2080 vmcs_writel(GUEST_SYSENTER_EIP, data);
2082 case MSR_IA32_SYSENTER_ESP:
2083 vmcs_writel(GUEST_SYSENTER_ESP, data);
2086 kvm_write_tsc(vcpu, data);
2088 case MSR_IA32_CR_PAT:
2089 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2090 vmcs_write64(GUEST_IA32_PAT, data);
2091 vcpu->arch.pat = data;
2094 ret = kvm_set_msr_common(vcpu, msr_index, data);
2097 if (!vmx->rdtscp_enabled)
2099 /* Check reserved bit, higher 32 bits should be zero */
2100 if ((data >> 32) != 0)
2102 /* Otherwise falls through */
2104 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2106 msr = find_msr_entry(vmx, msr_index);
2108 vmx_load_host_state(vmx);
2112 ret = kvm_set_msr_common(vcpu, msr_index, data);
2118 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2120 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2123 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2126 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2128 case VCPU_EXREG_PDPTR:
2130 ept_save_pdptrs(vcpu);
2137 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2139 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2140 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2142 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2144 update_exception_bitmap(vcpu);
2147 static __init int cpu_has_kvm_support(void)
2149 return cpu_has_vmx();
2152 static __init int vmx_disabled_by_bios(void)
2156 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2157 if (msr & FEATURE_CONTROL_LOCKED) {
2158 /* launched w/ TXT and VMX disabled */
2159 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2162 /* launched w/o TXT and VMX only enabled w/ TXT */
2163 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2164 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2165 && !tboot_enabled()) {
2166 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2167 "activate TXT before enabling KVM\n");
2170 /* launched w/o TXT and VMX disabled */
2171 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2172 && !tboot_enabled())
2179 static void kvm_cpu_vmxon(u64 addr)
2181 asm volatile (ASM_VMX_VMXON_RAX
2182 : : "a"(&addr), "m"(addr)
2186 static int hardware_enable(void *garbage)
2188 int cpu = raw_smp_processor_id();
2189 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2192 if (read_cr4() & X86_CR4_VMXE)
2195 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2196 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2198 test_bits = FEATURE_CONTROL_LOCKED;
2199 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2200 if (tboot_enabled())
2201 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2203 if ((old & test_bits) != test_bits) {
2204 /* enable and lock */
2205 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2207 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2209 if (vmm_exclusive) {
2210 kvm_cpu_vmxon(phys_addr);
2214 store_gdt(&__get_cpu_var(host_gdt));
2219 static void vmclear_local_loaded_vmcss(void)
2221 int cpu = raw_smp_processor_id();
2222 struct loaded_vmcs *v, *n;
2224 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2225 loaded_vmcss_on_cpu_link)
2226 __loaded_vmcs_clear(v);
2230 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2233 static void kvm_cpu_vmxoff(void)
2235 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2238 static void hardware_disable(void *garbage)
2240 if (vmm_exclusive) {
2241 vmclear_local_loaded_vmcss();
2244 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2247 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2248 u32 msr, u32 *result)
2250 u32 vmx_msr_low, vmx_msr_high;
2251 u32 ctl = ctl_min | ctl_opt;
2253 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2255 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2256 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2258 /* Ensure minimum (required) set of control bits are supported. */
2266 static __init bool allow_1_setting(u32 msr, u32 ctl)
2268 u32 vmx_msr_low, vmx_msr_high;
2270 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2271 return vmx_msr_high & ctl;
2274 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2276 u32 vmx_msr_low, vmx_msr_high;
2277 u32 min, opt, min2, opt2;
2278 u32 _pin_based_exec_control = 0;
2279 u32 _cpu_based_exec_control = 0;
2280 u32 _cpu_based_2nd_exec_control = 0;
2281 u32 _vmexit_control = 0;
2282 u32 _vmentry_control = 0;
2284 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2285 opt = PIN_BASED_VIRTUAL_NMIS;
2286 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2287 &_pin_based_exec_control) < 0)
2291 #ifdef CONFIG_X86_64
2292 CPU_BASED_CR8_LOAD_EXITING |
2293 CPU_BASED_CR8_STORE_EXITING |
2295 CPU_BASED_CR3_LOAD_EXITING |
2296 CPU_BASED_CR3_STORE_EXITING |
2297 CPU_BASED_USE_IO_BITMAPS |
2298 CPU_BASED_MOV_DR_EXITING |
2299 CPU_BASED_USE_TSC_OFFSETING |
2300 CPU_BASED_MWAIT_EXITING |
2301 CPU_BASED_MONITOR_EXITING |
2302 CPU_BASED_INVLPG_EXITING;
2305 min |= CPU_BASED_HLT_EXITING;
2307 opt = CPU_BASED_TPR_SHADOW |
2308 CPU_BASED_USE_MSR_BITMAPS |
2309 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2310 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2311 &_cpu_based_exec_control) < 0)
2313 #ifdef CONFIG_X86_64
2314 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2315 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2316 ~CPU_BASED_CR8_STORE_EXITING;
2318 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2320 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2321 SECONDARY_EXEC_WBINVD_EXITING |
2322 SECONDARY_EXEC_ENABLE_VPID |
2323 SECONDARY_EXEC_ENABLE_EPT |
2324 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2325 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2326 SECONDARY_EXEC_RDTSCP;
2327 if (adjust_vmx_controls(min2, opt2,
2328 MSR_IA32_VMX_PROCBASED_CTLS2,
2329 &_cpu_based_2nd_exec_control) < 0)
2332 #ifndef CONFIG_X86_64
2333 if (!(_cpu_based_2nd_exec_control &
2334 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2335 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2337 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2338 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2340 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2341 CPU_BASED_CR3_STORE_EXITING |
2342 CPU_BASED_INVLPG_EXITING);
2343 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2344 vmx_capability.ept, vmx_capability.vpid);
2348 #ifdef CONFIG_X86_64
2349 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2351 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2352 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2353 &_vmexit_control) < 0)
2357 opt = VM_ENTRY_LOAD_IA32_PAT;
2358 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2359 &_vmentry_control) < 0)
2362 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2364 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2365 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2368 #ifdef CONFIG_X86_64
2369 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2370 if (vmx_msr_high & (1u<<16))
2374 /* Require Write-Back (WB) memory type for VMCS accesses. */
2375 if (((vmx_msr_high >> 18) & 15) != 6)
2378 vmcs_conf->size = vmx_msr_high & 0x1fff;
2379 vmcs_conf->order = get_order(vmcs_config.size);
2380 vmcs_conf->revision_id = vmx_msr_low;
2382 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2383 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2384 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2385 vmcs_conf->vmexit_ctrl = _vmexit_control;
2386 vmcs_conf->vmentry_ctrl = _vmentry_control;
2388 cpu_has_load_ia32_efer =
2389 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2390 VM_ENTRY_LOAD_IA32_EFER)
2391 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2392 VM_EXIT_LOAD_IA32_EFER);
2397 static struct vmcs *alloc_vmcs_cpu(int cpu)
2399 int node = cpu_to_node(cpu);
2403 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2406 vmcs = page_address(pages);
2407 memset(vmcs, 0, vmcs_config.size);
2408 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2412 static struct vmcs *alloc_vmcs(void)
2414 return alloc_vmcs_cpu(raw_smp_processor_id());
2417 static void free_vmcs(struct vmcs *vmcs)
2419 free_pages((unsigned long)vmcs, vmcs_config.order);
2423 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2425 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2427 if (!loaded_vmcs->vmcs)
2429 loaded_vmcs_clear(loaded_vmcs);
2430 free_vmcs(loaded_vmcs->vmcs);
2431 loaded_vmcs->vmcs = NULL;
2434 static void free_kvm_area(void)
2438 for_each_possible_cpu(cpu) {
2439 free_vmcs(per_cpu(vmxarea, cpu));
2440 per_cpu(vmxarea, cpu) = NULL;
2444 static __init int alloc_kvm_area(void)
2448 for_each_possible_cpu(cpu) {
2451 vmcs = alloc_vmcs_cpu(cpu);
2457 per_cpu(vmxarea, cpu) = vmcs;
2462 static __init int hardware_setup(void)
2464 if (setup_vmcs_config(&vmcs_config) < 0)
2467 if (boot_cpu_has(X86_FEATURE_NX))
2468 kvm_enable_efer_bits(EFER_NX);
2470 if (!cpu_has_vmx_vpid())
2473 if (!cpu_has_vmx_ept() ||
2474 !cpu_has_vmx_ept_4levels()) {
2476 enable_unrestricted_guest = 0;
2479 if (!cpu_has_vmx_unrestricted_guest())
2480 enable_unrestricted_guest = 0;
2482 if (!cpu_has_vmx_flexpriority())
2483 flexpriority_enabled = 0;
2485 if (!cpu_has_vmx_tpr_shadow())
2486 kvm_x86_ops->update_cr8_intercept = NULL;
2488 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2489 kvm_disable_largepages();
2491 if (!cpu_has_vmx_ple())
2495 nested_vmx_setup_ctls_msrs();
2497 return alloc_kvm_area();
2500 static __exit void hardware_unsetup(void)
2505 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2507 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2509 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2510 vmcs_write16(sf->selector, save->selector);
2511 vmcs_writel(sf->base, save->base);
2512 vmcs_write32(sf->limit, save->limit);
2513 vmcs_write32(sf->ar_bytes, save->ar);
2515 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2517 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2521 static void enter_pmode(struct kvm_vcpu *vcpu)
2523 unsigned long flags;
2524 struct vcpu_vmx *vmx = to_vmx(vcpu);
2526 vmx->emulation_required = 1;
2527 vmx->rmode.vm86_active = 0;
2529 vmx_segment_cache_clear(vmx);
2531 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2532 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2533 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2534 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2536 flags = vmcs_readl(GUEST_RFLAGS);
2537 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2538 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2539 vmcs_writel(GUEST_RFLAGS, flags);
2541 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2542 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2544 update_exception_bitmap(vcpu);
2546 if (emulate_invalid_guest_state)
2549 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2550 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2551 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2552 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2554 vmx_segment_cache_clear(vmx);
2556 vmcs_write16(GUEST_SS_SELECTOR, 0);
2557 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2559 vmcs_write16(GUEST_CS_SELECTOR,
2560 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2561 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2564 static gva_t rmode_tss_base(struct kvm *kvm)
2566 if (!kvm->arch.tss_addr) {
2567 struct kvm_memslots *slots;
2570 slots = kvm_memslots(kvm);
2571 base_gfn = slots->memslots[0].base_gfn +
2572 kvm->memslots->memslots[0].npages - 3;
2573 return base_gfn << PAGE_SHIFT;
2575 return kvm->arch.tss_addr;
2578 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2580 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2582 save->selector = vmcs_read16(sf->selector);
2583 save->base = vmcs_readl(sf->base);
2584 save->limit = vmcs_read32(sf->limit);
2585 save->ar = vmcs_read32(sf->ar_bytes);
2586 vmcs_write16(sf->selector, save->base >> 4);
2587 vmcs_write32(sf->base, save->base & 0xffff0);
2588 vmcs_write32(sf->limit, 0xffff);
2589 vmcs_write32(sf->ar_bytes, 0xf3);
2590 if (save->base & 0xf)
2591 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2592 " aligned when entering protected mode (seg=%d)",
2596 static void enter_rmode(struct kvm_vcpu *vcpu)
2598 unsigned long flags;
2599 struct vcpu_vmx *vmx = to_vmx(vcpu);
2601 if (enable_unrestricted_guest)
2604 vmx->emulation_required = 1;
2605 vmx->rmode.vm86_active = 1;
2608 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2609 * vcpu. Call it here with phys address pointing 16M below 4G.
2611 if (!vcpu->kvm->arch.tss_addr) {
2612 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2613 "called before entering vcpu\n");
2614 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2615 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2616 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2619 vmx_segment_cache_clear(vmx);
2621 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2622 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2623 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2625 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2626 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2628 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2629 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2631 flags = vmcs_readl(GUEST_RFLAGS);
2632 vmx->rmode.save_rflags = flags;
2634 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2636 vmcs_writel(GUEST_RFLAGS, flags);
2637 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2638 update_exception_bitmap(vcpu);
2640 if (emulate_invalid_guest_state)
2641 goto continue_rmode;
2643 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2644 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2645 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2647 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2648 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2649 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2650 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2651 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2653 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2654 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2655 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2656 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2659 kvm_mmu_reset_context(vcpu);
2662 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2664 struct vcpu_vmx *vmx = to_vmx(vcpu);
2665 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2671 * Force kernel_gs_base reloading before EFER changes, as control
2672 * of this msr depends on is_long_mode().
2674 vmx_load_host_state(to_vmx(vcpu));
2675 vcpu->arch.efer = efer;
2676 if (efer & EFER_LMA) {
2677 vmcs_write32(VM_ENTRY_CONTROLS,
2678 vmcs_read32(VM_ENTRY_CONTROLS) |
2679 VM_ENTRY_IA32E_MODE);
2682 vmcs_write32(VM_ENTRY_CONTROLS,
2683 vmcs_read32(VM_ENTRY_CONTROLS) &
2684 ~VM_ENTRY_IA32E_MODE);
2686 msr->data = efer & ~EFER_LME;
2691 #ifdef CONFIG_X86_64
2693 static void enter_lmode(struct kvm_vcpu *vcpu)
2697 vmx_segment_cache_clear(to_vmx(vcpu));
2699 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2700 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2701 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2703 vmcs_write32(GUEST_TR_AR_BYTES,
2704 (guest_tr_ar & ~AR_TYPE_MASK)
2705 | AR_TYPE_BUSY_64_TSS);
2707 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2710 static void exit_lmode(struct kvm_vcpu *vcpu)
2712 vmcs_write32(VM_ENTRY_CONTROLS,
2713 vmcs_read32(VM_ENTRY_CONTROLS)
2714 & ~VM_ENTRY_IA32E_MODE);
2715 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2720 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2722 vpid_sync_context(to_vmx(vcpu));
2724 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2726 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2730 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2732 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2734 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2735 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2738 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2740 if (enable_ept && is_paging(vcpu))
2741 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2742 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2745 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2747 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2749 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2750 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2753 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2755 if (!test_bit(VCPU_EXREG_PDPTR,
2756 (unsigned long *)&vcpu->arch.regs_dirty))
2759 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2760 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2761 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2762 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2763 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2767 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2769 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2770 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2771 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2772 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2773 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2776 __set_bit(VCPU_EXREG_PDPTR,
2777 (unsigned long *)&vcpu->arch.regs_avail);
2778 __set_bit(VCPU_EXREG_PDPTR,
2779 (unsigned long *)&vcpu->arch.regs_dirty);
2782 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2784 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2786 struct kvm_vcpu *vcpu)
2788 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2789 vmx_decache_cr3(vcpu);
2790 if (!(cr0 & X86_CR0_PG)) {
2791 /* From paging/starting to nonpaging */
2792 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2793 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2794 (CPU_BASED_CR3_LOAD_EXITING |
2795 CPU_BASED_CR3_STORE_EXITING));
2796 vcpu->arch.cr0 = cr0;
2797 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2798 } else if (!is_paging(vcpu)) {
2799 /* From nonpaging to paging */
2800 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2801 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2802 ~(CPU_BASED_CR3_LOAD_EXITING |
2803 CPU_BASED_CR3_STORE_EXITING));
2804 vcpu->arch.cr0 = cr0;
2805 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2808 if (!(cr0 & X86_CR0_WP))
2809 *hw_cr0 &= ~X86_CR0_WP;
2812 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2814 struct vcpu_vmx *vmx = to_vmx(vcpu);
2815 unsigned long hw_cr0;
2817 if (enable_unrestricted_guest)
2818 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2819 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2821 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2823 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2826 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2829 #ifdef CONFIG_X86_64
2830 if (vcpu->arch.efer & EFER_LME) {
2831 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2833 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2839 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2841 if (!vcpu->fpu_active)
2842 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2844 vmcs_writel(CR0_READ_SHADOW, cr0);
2845 vmcs_writel(GUEST_CR0, hw_cr0);
2846 vcpu->arch.cr0 = cr0;
2847 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2850 static u64 construct_eptp(unsigned long root_hpa)
2854 /* TODO write the value reading from MSR */
2855 eptp = VMX_EPT_DEFAULT_MT |
2856 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2857 eptp |= (root_hpa & PAGE_MASK);
2862 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2864 unsigned long guest_cr3;
2869 eptp = construct_eptp(cr3);
2870 vmcs_write64(EPT_POINTER, eptp);
2871 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2872 vcpu->kvm->arch.ept_identity_map_addr;
2873 ept_load_pdptrs(vcpu);
2876 vmx_flush_tlb(vcpu);
2877 vmcs_writel(GUEST_CR3, guest_cr3);
2880 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2882 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2883 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2885 if (cr4 & X86_CR4_VMXE) {
2887 * To use VMXON (and later other VMX instructions), a guest
2888 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2889 * So basically the check on whether to allow nested VMX
2892 if (!nested_vmx_allowed(vcpu))
2894 } else if (to_vmx(vcpu)->nested.vmxon)
2897 vcpu->arch.cr4 = cr4;
2899 if (!is_paging(vcpu)) {
2900 hw_cr4 &= ~X86_CR4_PAE;
2901 hw_cr4 |= X86_CR4_PSE;
2902 } else if (!(cr4 & X86_CR4_PAE)) {
2903 hw_cr4 &= ~X86_CR4_PAE;
2907 vmcs_writel(CR4_READ_SHADOW, cr4);
2908 vmcs_writel(GUEST_CR4, hw_cr4);
2912 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2913 struct kvm_segment *var, int seg)
2915 struct vcpu_vmx *vmx = to_vmx(vcpu);
2916 struct kvm_save_segment *save;
2919 if (vmx->rmode.vm86_active
2920 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2921 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2922 || seg == VCPU_SREG_GS)
2923 && !emulate_invalid_guest_state) {
2925 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2926 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2927 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2928 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2929 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2932 var->selector = save->selector;
2933 var->base = save->base;
2934 var->limit = save->limit;
2936 if (seg == VCPU_SREG_TR
2937 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2938 goto use_saved_rmode_seg;
2940 var->base = vmx_read_guest_seg_base(vmx, seg);
2941 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2942 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2943 ar = vmx_read_guest_seg_ar(vmx, seg);
2944 use_saved_rmode_seg:
2945 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2947 var->type = ar & 15;
2948 var->s = (ar >> 4) & 1;
2949 var->dpl = (ar >> 5) & 3;
2950 var->present = (ar >> 7) & 1;
2951 var->avl = (ar >> 12) & 1;
2952 var->l = (ar >> 13) & 1;
2953 var->db = (ar >> 14) & 1;
2954 var->g = (ar >> 15) & 1;
2955 var->unusable = (ar >> 16) & 1;
2958 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2960 struct kvm_segment s;
2962 if (to_vmx(vcpu)->rmode.vm86_active) {
2963 vmx_get_segment(vcpu, &s, seg);
2966 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
2969 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2971 if (!is_protmode(vcpu))
2974 if (!is_long_mode(vcpu)
2975 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2978 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2981 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2983 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2984 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2985 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2987 return to_vmx(vcpu)->cpl;
2991 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2998 ar = var->type & 15;
2999 ar |= (var->s & 1) << 4;
3000 ar |= (var->dpl & 3) << 5;
3001 ar |= (var->present & 1) << 7;
3002 ar |= (var->avl & 1) << 12;
3003 ar |= (var->l & 1) << 13;
3004 ar |= (var->db & 1) << 14;
3005 ar |= (var->g & 1) << 15;
3007 if (ar == 0) /* a 0 value means unusable */
3008 ar = AR_UNUSABLE_MASK;
3013 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3014 struct kvm_segment *var, int seg)
3016 struct vcpu_vmx *vmx = to_vmx(vcpu);
3017 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3020 vmx_segment_cache_clear(vmx);
3022 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3023 vmcs_write16(sf->selector, var->selector);
3024 vmx->rmode.tr.selector = var->selector;
3025 vmx->rmode.tr.base = var->base;
3026 vmx->rmode.tr.limit = var->limit;
3027 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3030 vmcs_writel(sf->base, var->base);
3031 vmcs_write32(sf->limit, var->limit);
3032 vmcs_write16(sf->selector, var->selector);
3033 if (vmx->rmode.vm86_active && var->s) {
3035 * Hack real-mode segments into vm86 compatibility.
3037 if (var->base == 0xffff0000 && var->selector == 0xf000)
3038 vmcs_writel(sf->base, 0xf0000);
3041 ar = vmx_segment_access_rights(var);
3044 * Fix the "Accessed" bit in AR field of segment registers for older
3046 * IA32 arch specifies that at the time of processor reset the
3047 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3048 * is setting it to 0 in the usedland code. This causes invalid guest
3049 * state vmexit when "unrestricted guest" mode is turned on.
3050 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3051 * tree. Newer qemu binaries with that qemu fix would not need this
3054 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3055 ar |= 0x1; /* Accessed */
3057 vmcs_write32(sf->ar_bytes, ar);
3058 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3061 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3063 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3065 *db = (ar >> 14) & 1;
3066 *l = (ar >> 13) & 1;
3069 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3071 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3072 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3075 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3077 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3078 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3081 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3083 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3084 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3087 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3089 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3090 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3093 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3095 struct kvm_segment var;
3098 vmx_get_segment(vcpu, &var, seg);
3099 ar = vmx_segment_access_rights(&var);
3101 if (var.base != (var.selector << 4))
3103 if (var.limit != 0xffff)
3111 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3113 struct kvm_segment cs;
3114 unsigned int cs_rpl;
3116 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3117 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3121 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3125 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3126 if (cs.dpl > cs_rpl)
3129 if (cs.dpl != cs_rpl)
3135 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3139 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3141 struct kvm_segment ss;
3142 unsigned int ss_rpl;
3144 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3145 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3149 if (ss.type != 3 && ss.type != 7)
3153 if (ss.dpl != ss_rpl) /* DPL != RPL */
3161 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3163 struct kvm_segment var;
3166 vmx_get_segment(vcpu, &var, seg);
3167 rpl = var.selector & SELECTOR_RPL_MASK;
3175 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3176 if (var.dpl < rpl) /* DPL < RPL */
3180 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3186 static bool tr_valid(struct kvm_vcpu *vcpu)
3188 struct kvm_segment tr;
3190 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3194 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3196 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3204 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3206 struct kvm_segment ldtr;
3208 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3212 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3222 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3224 struct kvm_segment cs, ss;
3226 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3227 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3229 return ((cs.selector & SELECTOR_RPL_MASK) ==
3230 (ss.selector & SELECTOR_RPL_MASK));
3234 * Check if guest state is valid. Returns true if valid, false if
3236 * We assume that registers are always usable
3238 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3240 /* real mode guest state checks */
3241 if (!is_protmode(vcpu)) {
3242 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3244 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3246 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3248 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3250 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3252 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3255 /* protected mode guest state checks */
3256 if (!cs_ss_rpl_check(vcpu))
3258 if (!code_segment_valid(vcpu))
3260 if (!stack_segment_valid(vcpu))
3262 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3264 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3266 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3268 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3270 if (!tr_valid(vcpu))
3272 if (!ldtr_valid(vcpu))
3276 * - Add checks on RIP
3277 * - Add checks on RFLAGS
3283 static int init_rmode_tss(struct kvm *kvm)
3287 int r, idx, ret = 0;
3289 idx = srcu_read_lock(&kvm->srcu);
3290 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3291 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3294 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3295 r = kvm_write_guest_page(kvm, fn++, &data,
3296 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3299 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3302 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3306 r = kvm_write_guest_page(kvm, fn, &data,
3307 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3314 srcu_read_unlock(&kvm->srcu, idx);
3318 static int init_rmode_identity_map(struct kvm *kvm)
3321 pfn_t identity_map_pfn;
3326 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3327 printk(KERN_ERR "EPT: identity-mapping pagetable "
3328 "haven't been allocated!\n");
3331 if (likely(kvm->arch.ept_identity_pagetable_done))
3334 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3335 idx = srcu_read_lock(&kvm->srcu);
3336 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3339 /* Set up identity-mapping pagetable for EPT in real mode */
3340 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3341 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3342 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3343 r = kvm_write_guest_page(kvm, identity_map_pfn,
3344 &tmp, i * sizeof(tmp), sizeof(tmp));
3348 kvm->arch.ept_identity_pagetable_done = true;
3351 srcu_read_unlock(&kvm->srcu, idx);
3355 static void seg_setup(int seg)
3357 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3360 vmcs_write16(sf->selector, 0);
3361 vmcs_writel(sf->base, 0);
3362 vmcs_write32(sf->limit, 0xffff);
3363 if (enable_unrestricted_guest) {
3365 if (seg == VCPU_SREG_CS)
3366 ar |= 0x08; /* code segment */
3370 vmcs_write32(sf->ar_bytes, ar);
3373 static int alloc_apic_access_page(struct kvm *kvm)
3375 struct kvm_userspace_memory_region kvm_userspace_mem;
3378 mutex_lock(&kvm->slots_lock);
3379 if (kvm->arch.apic_access_page)
3381 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3382 kvm_userspace_mem.flags = 0;
3383 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3384 kvm_userspace_mem.memory_size = PAGE_SIZE;
3385 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3389 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3391 mutex_unlock(&kvm->slots_lock);
3395 static int alloc_identity_pagetable(struct kvm *kvm)
3397 struct kvm_userspace_memory_region kvm_userspace_mem;
3400 mutex_lock(&kvm->slots_lock);
3401 if (kvm->arch.ept_identity_pagetable)
3403 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3404 kvm_userspace_mem.flags = 0;
3405 kvm_userspace_mem.guest_phys_addr =
3406 kvm->arch.ept_identity_map_addr;
3407 kvm_userspace_mem.memory_size = PAGE_SIZE;
3408 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3412 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3413 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3415 mutex_unlock(&kvm->slots_lock);
3419 static void allocate_vpid(struct vcpu_vmx *vmx)
3426 spin_lock(&vmx_vpid_lock);
3427 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3428 if (vpid < VMX_NR_VPIDS) {
3430 __set_bit(vpid, vmx_vpid_bitmap);
3432 spin_unlock(&vmx_vpid_lock);
3435 static void free_vpid(struct vcpu_vmx *vmx)
3439 spin_lock(&vmx_vpid_lock);
3441 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3442 spin_unlock(&vmx_vpid_lock);
3445 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3447 int f = sizeof(unsigned long);
3449 if (!cpu_has_vmx_msr_bitmap())
3453 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3454 * have the write-low and read-high bitmap offsets the wrong way round.
3455 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3457 if (msr <= 0x1fff) {
3458 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3459 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3460 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3462 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3463 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3467 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3470 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3471 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3475 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3476 * will not change in the lifetime of the guest.
3477 * Note that host-state that does change is set elsewhere. E.g., host-state
3478 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3480 static void vmx_set_constant_host_state(void)
3486 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3487 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3488 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3490 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3491 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3492 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3493 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3494 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3496 native_store_idt(&dt);
3497 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3499 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3500 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3502 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3503 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3504 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3505 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3507 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3508 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3509 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3513 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3515 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3517 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3518 if (is_guest_mode(&vmx->vcpu))
3519 vmx->vcpu.arch.cr4_guest_owned_bits &=
3520 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3521 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3524 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3526 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3527 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3528 exec_control &= ~CPU_BASED_TPR_SHADOW;
3529 #ifdef CONFIG_X86_64
3530 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3531 CPU_BASED_CR8_LOAD_EXITING;
3535 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3536 CPU_BASED_CR3_LOAD_EXITING |
3537 CPU_BASED_INVLPG_EXITING;
3538 return exec_control;
3541 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3543 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3544 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3545 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3547 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3549 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3550 enable_unrestricted_guest = 0;
3552 if (!enable_unrestricted_guest)
3553 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3555 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3556 return exec_control;
3560 * Sets up the vmcs for emulated real mode.
3562 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3568 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3569 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3571 if (cpu_has_vmx_msr_bitmap())
3572 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3574 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3577 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3578 vmcs_config.pin_based_exec_ctrl);
3580 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3582 if (cpu_has_secondary_exec_ctrls()) {
3583 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3584 vmx_secondary_exec_control(vmx));
3588 vmcs_write32(PLE_GAP, ple_gap);
3589 vmcs_write32(PLE_WINDOW, ple_window);
3592 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3593 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
3594 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3596 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3597 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
3598 vmx_set_constant_host_state();
3599 #ifdef CONFIG_X86_64
3600 rdmsrl(MSR_FS_BASE, a);
3601 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3602 rdmsrl(MSR_GS_BASE, a);
3603 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3605 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3606 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3609 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3610 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3611 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3612 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3613 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3615 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3616 u32 msr_low, msr_high;
3618 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3619 host_pat = msr_low | ((u64) msr_high << 32);
3620 /* Write the default value follow host pat */
3621 vmcs_write64(GUEST_IA32_PAT, host_pat);
3622 /* Keep arch.pat sync with GUEST_IA32_PAT */
3623 vmx->vcpu.arch.pat = host_pat;
3626 for (i = 0; i < NR_VMX_MSR; ++i) {
3627 u32 index = vmx_msr_index[i];
3628 u32 data_low, data_high;
3631 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3633 if (wrmsr_safe(index, data_low, data_high) < 0)
3635 vmx->guest_msrs[j].index = i;
3636 vmx->guest_msrs[j].data = 0;
3637 vmx->guest_msrs[j].mask = -1ull;
3641 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3643 /* 22.2.1, 20.8.1 */
3644 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3646 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3647 set_cr4_guest_host_mask(vmx);
3649 kvm_write_tsc(&vmx->vcpu, 0);
3654 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3656 struct vcpu_vmx *vmx = to_vmx(vcpu);
3660 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3662 vmx->rmode.vm86_active = 0;
3664 vmx->soft_vnmi_blocked = 0;
3666 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3667 kvm_set_cr8(&vmx->vcpu, 0);
3668 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3669 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3670 msr |= MSR_IA32_APICBASE_BSP;
3671 kvm_set_apic_base(&vmx->vcpu, msr);
3673 ret = fx_init(&vmx->vcpu);
3677 vmx_segment_cache_clear(vmx);
3679 seg_setup(VCPU_SREG_CS);
3681 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3682 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3684 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3685 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3686 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3688 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3689 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3692 seg_setup(VCPU_SREG_DS);
3693 seg_setup(VCPU_SREG_ES);
3694 seg_setup(VCPU_SREG_FS);
3695 seg_setup(VCPU_SREG_GS);
3696 seg_setup(VCPU_SREG_SS);
3698 vmcs_write16(GUEST_TR_SELECTOR, 0);
3699 vmcs_writel(GUEST_TR_BASE, 0);
3700 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3701 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3703 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3704 vmcs_writel(GUEST_LDTR_BASE, 0);
3705 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3706 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3708 vmcs_write32(GUEST_SYSENTER_CS, 0);
3709 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3710 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3712 vmcs_writel(GUEST_RFLAGS, 0x02);
3713 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3714 kvm_rip_write(vcpu, 0xfff0);
3716 kvm_rip_write(vcpu, 0);
3717 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3719 vmcs_writel(GUEST_DR7, 0x400);
3721 vmcs_writel(GUEST_GDTR_BASE, 0);
3722 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3724 vmcs_writel(GUEST_IDTR_BASE, 0);
3725 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3727 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3728 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3729 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3731 /* Special registers */
3732 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3736 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3738 if (cpu_has_vmx_tpr_shadow()) {
3739 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3740 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3741 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3742 __pa(vmx->vcpu.arch.apic->regs));
3743 vmcs_write32(TPR_THRESHOLD, 0);
3746 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3747 vmcs_write64(APIC_ACCESS_ADDR,
3748 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3751 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3753 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3754 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3755 vmx_set_cr4(&vmx->vcpu, 0);
3756 vmx_set_efer(&vmx->vcpu, 0);
3757 vmx_fpu_activate(&vmx->vcpu);
3758 update_exception_bitmap(&vmx->vcpu);
3760 vpid_sync_context(vmx);
3764 /* HACK: Don't enable emulation on guest boot/reset */
3765 vmx->emulation_required = 0;
3772 * In nested virtualization, check if L1 asked to exit on external interrupts.
3773 * For most existing hypervisors, this will always return true.
3775 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3777 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3778 PIN_BASED_EXT_INTR_MASK;
3781 static void enable_irq_window(struct kvm_vcpu *vcpu)
3783 u32 cpu_based_vm_exec_control;
3784 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3785 /* We can get here when nested_run_pending caused
3786 * vmx_interrupt_allowed() to return false. In this case, do
3787 * nothing - the interrupt will be injected later.
3791 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3792 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3793 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3796 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3798 u32 cpu_based_vm_exec_control;
3800 if (!cpu_has_virtual_nmis()) {
3801 enable_irq_window(vcpu);
3805 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3806 enable_irq_window(vcpu);
3809 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3810 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3811 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3814 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3816 struct vcpu_vmx *vmx = to_vmx(vcpu);
3818 int irq = vcpu->arch.interrupt.nr;
3820 trace_kvm_inj_virq(irq);
3822 ++vcpu->stat.irq_injections;
3823 if (vmx->rmode.vm86_active) {
3825 if (vcpu->arch.interrupt.soft)
3826 inc_eip = vcpu->arch.event_exit_inst_len;
3827 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3828 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3831 intr = irq | INTR_INFO_VALID_MASK;
3832 if (vcpu->arch.interrupt.soft) {
3833 intr |= INTR_TYPE_SOFT_INTR;
3834 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3835 vmx->vcpu.arch.event_exit_inst_len);
3837 intr |= INTR_TYPE_EXT_INTR;
3838 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3839 vmx_clear_hlt(vcpu);
3842 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3844 struct vcpu_vmx *vmx = to_vmx(vcpu);
3846 if (is_guest_mode(vcpu))
3849 if (!cpu_has_virtual_nmis()) {
3851 * Tracking the NMI-blocked state in software is built upon
3852 * finding the next open IRQ window. This, in turn, depends on
3853 * well-behaving guests: They have to keep IRQs disabled at
3854 * least as long as the NMI handler runs. Otherwise we may
3855 * cause NMI nesting, maybe breaking the guest. But as this is
3856 * highly unlikely, we can live with the residual risk.
3858 vmx->soft_vnmi_blocked = 1;
3859 vmx->vnmi_blocked_time = 0;
3862 ++vcpu->stat.nmi_injections;
3863 vmx->nmi_known_unmasked = false;
3864 if (vmx->rmode.vm86_active) {
3865 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3866 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3869 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3870 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3871 vmx_clear_hlt(vcpu);
3874 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3876 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3879 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3880 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3881 | GUEST_INTR_STATE_NMI));
3884 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3886 if (!cpu_has_virtual_nmis())
3887 return to_vmx(vcpu)->soft_vnmi_blocked;
3888 if (to_vmx(vcpu)->nmi_known_unmasked)
3890 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3893 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3895 struct vcpu_vmx *vmx = to_vmx(vcpu);
3897 if (!cpu_has_virtual_nmis()) {
3898 if (vmx->soft_vnmi_blocked != masked) {
3899 vmx->soft_vnmi_blocked = masked;
3900 vmx->vnmi_blocked_time = 0;
3903 vmx->nmi_known_unmasked = !masked;
3905 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3906 GUEST_INTR_STATE_NMI);
3908 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3909 GUEST_INTR_STATE_NMI);
3913 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3915 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3916 struct vmcs12 *vmcs12;
3917 if (to_vmx(vcpu)->nested.nested_run_pending)
3919 nested_vmx_vmexit(vcpu);
3920 vmcs12 = get_vmcs12(vcpu);
3921 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3922 vmcs12->vm_exit_intr_info = 0;
3923 /* fall through to normal code, but now in L1, not L2 */
3926 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3927 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3928 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3931 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3934 struct kvm_userspace_memory_region tss_mem = {
3935 .slot = TSS_PRIVATE_MEMSLOT,
3936 .guest_phys_addr = addr,
3937 .memory_size = PAGE_SIZE * 3,
3941 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3944 kvm->arch.tss_addr = addr;
3945 if (!init_rmode_tss(kvm))
3951 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3952 int vec, u32 err_code)
3955 * Instruction with address size override prefix opcode 0x67
3956 * Cause the #SS fault with 0 error code in VM86 mode.
3958 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3959 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3962 * Forward all other exceptions that are valid in real mode.
3963 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3964 * the required debugging infrastructure rework.
3968 if (vcpu->guest_debug &
3969 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3971 kvm_queue_exception(vcpu, vec);
3975 * Update instruction length as we may reinject the exception
3976 * from user space while in guest debugging mode.
3978 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3979 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3980 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3991 kvm_queue_exception(vcpu, vec);
3998 * Trigger machine check on the host. We assume all the MSRs are already set up
3999 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4000 * We pass a fake environment to the machine check handler because we want
4001 * the guest to be always treated like user space, no matter what context
4002 * it used internally.
4004 static void kvm_machine_check(void)
4006 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4007 struct pt_regs regs = {
4008 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4009 .flags = X86_EFLAGS_IF,
4012 do_machine_check(®s, 0);
4016 static int handle_machine_check(struct kvm_vcpu *vcpu)
4018 /* already handled by vcpu_run */
4022 static int handle_exception(struct kvm_vcpu *vcpu)
4024 struct vcpu_vmx *vmx = to_vmx(vcpu);
4025 struct kvm_run *kvm_run = vcpu->run;
4026 u32 intr_info, ex_no, error_code;
4027 unsigned long cr2, rip, dr6;
4029 enum emulation_result er;
4031 vect_info = vmx->idt_vectoring_info;
4032 intr_info = vmx->exit_intr_info;
4034 if (is_machine_check(intr_info))
4035 return handle_machine_check(vcpu);
4037 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4038 !is_page_fault(intr_info)) {
4039 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4040 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4041 vcpu->run->internal.ndata = 2;
4042 vcpu->run->internal.data[0] = vect_info;
4043 vcpu->run->internal.data[1] = intr_info;
4047 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4048 return 1; /* already handled by vmx_vcpu_run() */
4050 if (is_no_device(intr_info)) {
4051 vmx_fpu_activate(vcpu);
4055 if (is_invalid_opcode(intr_info)) {
4056 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4057 if (er != EMULATE_DONE)
4058 kvm_queue_exception(vcpu, UD_VECTOR);
4063 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4064 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4065 if (is_page_fault(intr_info)) {
4066 /* EPT won't cause page fault directly */
4069 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4070 trace_kvm_page_fault(cr2, error_code);
4072 if (kvm_event_needs_reinjection(vcpu))
4073 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4074 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4077 if (vmx->rmode.vm86_active &&
4078 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4080 if (vcpu->arch.halt_request) {
4081 vcpu->arch.halt_request = 0;
4082 return kvm_emulate_halt(vcpu);
4087 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4090 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4091 if (!(vcpu->guest_debug &
4092 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4093 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4094 kvm_queue_exception(vcpu, DB_VECTOR);
4097 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4098 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4102 * Update instruction length as we may reinject #BP from
4103 * user space while in guest debugging mode. Reading it for
4104 * #DB as well causes no harm, it is not used in that case.
4106 vmx->vcpu.arch.event_exit_inst_len =
4107 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4108 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4109 rip = kvm_rip_read(vcpu);
4110 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4111 kvm_run->debug.arch.exception = ex_no;
4114 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4115 kvm_run->ex.exception = ex_no;
4116 kvm_run->ex.error_code = error_code;
4122 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4124 ++vcpu->stat.irq_exits;
4128 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4130 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4134 static int handle_io(struct kvm_vcpu *vcpu)
4136 unsigned long exit_qualification;
4137 int size, in, string;
4140 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4141 string = (exit_qualification & 16) != 0;
4142 in = (exit_qualification & 8) != 0;
4144 ++vcpu->stat.io_exits;
4147 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4149 port = exit_qualification >> 16;
4150 size = (exit_qualification & 7) + 1;
4151 skip_emulated_instruction(vcpu);
4153 return kvm_fast_pio_out(vcpu, size, port);
4157 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4160 * Patch in the VMCALL instruction:
4162 hypercall[0] = 0x0f;
4163 hypercall[1] = 0x01;
4164 hypercall[2] = 0xc1;
4167 static int handle_cr(struct kvm_vcpu *vcpu)
4169 unsigned long exit_qualification, val;
4174 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4175 cr = exit_qualification & 15;
4176 reg = (exit_qualification >> 8) & 15;
4177 switch ((exit_qualification >> 4) & 3) {
4178 case 0: /* mov to cr */
4179 val = kvm_register_read(vcpu, reg);
4180 trace_kvm_cr_write(cr, val);
4183 err = kvm_set_cr0(vcpu, val);
4184 kvm_complete_insn_gp(vcpu, err);
4187 err = kvm_set_cr3(vcpu, val);
4188 kvm_complete_insn_gp(vcpu, err);
4191 err = kvm_set_cr4(vcpu, val);
4192 kvm_complete_insn_gp(vcpu, err);
4195 u8 cr8_prev = kvm_get_cr8(vcpu);
4196 u8 cr8 = kvm_register_read(vcpu, reg);
4197 err = kvm_set_cr8(vcpu, cr8);
4198 kvm_complete_insn_gp(vcpu, err);
4199 if (irqchip_in_kernel(vcpu->kvm))
4201 if (cr8_prev <= cr8)
4203 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4209 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4210 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4211 skip_emulated_instruction(vcpu);
4212 vmx_fpu_activate(vcpu);
4214 case 1: /*mov from cr*/
4217 val = kvm_read_cr3(vcpu);
4218 kvm_register_write(vcpu, reg, val);
4219 trace_kvm_cr_read(cr, val);
4220 skip_emulated_instruction(vcpu);
4223 val = kvm_get_cr8(vcpu);
4224 kvm_register_write(vcpu, reg, val);
4225 trace_kvm_cr_read(cr, val);
4226 skip_emulated_instruction(vcpu);
4231 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4232 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4233 kvm_lmsw(vcpu, val);
4235 skip_emulated_instruction(vcpu);
4240 vcpu->run->exit_reason = 0;
4241 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4242 (int)(exit_qualification >> 4) & 3, cr);
4246 static int handle_dr(struct kvm_vcpu *vcpu)
4248 unsigned long exit_qualification;
4251 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4252 if (!kvm_require_cpl(vcpu, 0))
4254 dr = vmcs_readl(GUEST_DR7);
4257 * As the vm-exit takes precedence over the debug trap, we
4258 * need to emulate the latter, either for the host or the
4259 * guest debugging itself.
4261 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4262 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4263 vcpu->run->debug.arch.dr7 = dr;
4264 vcpu->run->debug.arch.pc =
4265 vmcs_readl(GUEST_CS_BASE) +
4266 vmcs_readl(GUEST_RIP);
4267 vcpu->run->debug.arch.exception = DB_VECTOR;
4268 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4271 vcpu->arch.dr7 &= ~DR7_GD;
4272 vcpu->arch.dr6 |= DR6_BD;
4273 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4274 kvm_queue_exception(vcpu, DB_VECTOR);
4279 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4280 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4281 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4282 if (exit_qualification & TYPE_MOV_FROM_DR) {
4284 if (!kvm_get_dr(vcpu, dr, &val))
4285 kvm_register_write(vcpu, reg, val);
4287 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4288 skip_emulated_instruction(vcpu);
4292 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4294 vmcs_writel(GUEST_DR7, val);
4297 static int handle_cpuid(struct kvm_vcpu *vcpu)
4299 kvm_emulate_cpuid(vcpu);
4303 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4305 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4308 if (vmx_get_msr(vcpu, ecx, &data)) {
4309 trace_kvm_msr_read_ex(ecx);
4310 kvm_inject_gp(vcpu, 0);
4314 trace_kvm_msr_read(ecx, data);
4316 /* FIXME: handling of bits 32:63 of rax, rdx */
4317 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4318 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4319 skip_emulated_instruction(vcpu);
4323 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4325 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4326 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4327 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4329 if (vmx_set_msr(vcpu, ecx, data) != 0) {
4330 trace_kvm_msr_write_ex(ecx, data);
4331 kvm_inject_gp(vcpu, 0);
4335 trace_kvm_msr_write(ecx, data);
4336 skip_emulated_instruction(vcpu);
4340 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4342 kvm_make_request(KVM_REQ_EVENT, vcpu);
4346 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4348 u32 cpu_based_vm_exec_control;
4350 /* clear pending irq */
4351 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4352 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4353 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4355 kvm_make_request(KVM_REQ_EVENT, vcpu);
4357 ++vcpu->stat.irq_window_exits;
4360 * If the user space waits to inject interrupts, exit as soon as
4363 if (!irqchip_in_kernel(vcpu->kvm) &&
4364 vcpu->run->request_interrupt_window &&
4365 !kvm_cpu_has_interrupt(vcpu)) {
4366 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4372 static int handle_halt(struct kvm_vcpu *vcpu)
4374 skip_emulated_instruction(vcpu);
4375 return kvm_emulate_halt(vcpu);
4378 static int handle_vmcall(struct kvm_vcpu *vcpu)
4380 skip_emulated_instruction(vcpu);
4381 kvm_emulate_hypercall(vcpu);
4385 static int handle_invd(struct kvm_vcpu *vcpu)
4387 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4390 static int handle_invlpg(struct kvm_vcpu *vcpu)
4392 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4394 kvm_mmu_invlpg(vcpu, exit_qualification);
4395 skip_emulated_instruction(vcpu);
4399 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4401 skip_emulated_instruction(vcpu);
4402 kvm_emulate_wbinvd(vcpu);
4406 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4408 u64 new_bv = kvm_read_edx_eax(vcpu);
4409 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4411 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4412 skip_emulated_instruction(vcpu);
4416 static int handle_apic_access(struct kvm_vcpu *vcpu)
4418 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4421 static int handle_task_switch(struct kvm_vcpu *vcpu)
4423 struct vcpu_vmx *vmx = to_vmx(vcpu);
4424 unsigned long exit_qualification;
4425 bool has_error_code = false;
4428 int reason, type, idt_v;
4430 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4431 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4433 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4435 reason = (u32)exit_qualification >> 30;
4436 if (reason == TASK_SWITCH_GATE && idt_v) {
4438 case INTR_TYPE_NMI_INTR:
4439 vcpu->arch.nmi_injected = false;
4440 vmx_set_nmi_mask(vcpu, true);
4442 case INTR_TYPE_EXT_INTR:
4443 case INTR_TYPE_SOFT_INTR:
4444 kvm_clear_interrupt_queue(vcpu);
4446 case INTR_TYPE_HARD_EXCEPTION:
4447 if (vmx->idt_vectoring_info &
4448 VECTORING_INFO_DELIVER_CODE_MASK) {
4449 has_error_code = true;
4451 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4454 case INTR_TYPE_SOFT_EXCEPTION:
4455 kvm_clear_exception_queue(vcpu);
4461 tss_selector = exit_qualification;
4463 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4464 type != INTR_TYPE_EXT_INTR &&
4465 type != INTR_TYPE_NMI_INTR))
4466 skip_emulated_instruction(vcpu);
4468 if (kvm_task_switch(vcpu, tss_selector, reason,
4469 has_error_code, error_code) == EMULATE_FAIL) {
4470 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4471 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4472 vcpu->run->internal.ndata = 0;
4476 /* clear all local breakpoint enable flags */
4477 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4480 * TODO: What about debug traps on tss switch?
4481 * Are we supposed to inject them and update dr6?
4487 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4489 unsigned long exit_qualification;
4493 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4495 if (exit_qualification & (1 << 6)) {
4496 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4500 gla_validity = (exit_qualification >> 7) & 0x3;
4501 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4502 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4503 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4504 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4505 vmcs_readl(GUEST_LINEAR_ADDRESS));
4506 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4507 (long unsigned int)exit_qualification);
4508 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4509 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4513 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4514 trace_kvm_page_fault(gpa, exit_qualification);
4515 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4518 static u64 ept_rsvd_mask(u64 spte, int level)
4523 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4524 mask |= (1ULL << i);
4527 /* bits 7:3 reserved */
4529 else if (level == 2) {
4530 if (spte & (1ULL << 7))
4531 /* 2MB ref, bits 20:12 reserved */
4534 /* bits 6:3 reserved */
4541 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4544 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4546 /* 010b (write-only) */
4547 WARN_ON((spte & 0x7) == 0x2);
4549 /* 110b (write/execute) */
4550 WARN_ON((spte & 0x7) == 0x6);
4552 /* 100b (execute-only) and value not supported by logical processor */
4553 if (!cpu_has_vmx_ept_execute_only())
4554 WARN_ON((spte & 0x7) == 0x4);
4558 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4560 if (rsvd_bits != 0) {
4561 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4562 __func__, rsvd_bits);
4566 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4567 u64 ept_mem_type = (spte & 0x38) >> 3;
4569 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4570 ept_mem_type == 7) {
4571 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4572 __func__, ept_mem_type);
4579 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4585 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4587 printk(KERN_ERR "EPT: Misconfiguration.\n");
4588 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4590 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4592 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4593 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4595 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4596 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4601 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4603 u32 cpu_based_vm_exec_control;
4605 /* clear pending NMI */
4606 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4607 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4608 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4609 ++vcpu->stat.nmi_window_exits;
4610 kvm_make_request(KVM_REQ_EVENT, vcpu);
4615 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4617 struct vcpu_vmx *vmx = to_vmx(vcpu);
4618 enum emulation_result err = EMULATE_DONE;
4621 bool intr_window_requested;
4623 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4624 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4626 while (!guest_state_valid(vcpu)) {
4627 if (intr_window_requested
4628 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4629 return handle_interrupt_window(&vmx->vcpu);
4631 err = emulate_instruction(vcpu, 0);
4633 if (err == EMULATE_DO_MMIO) {
4638 if (err != EMULATE_DONE)
4641 if (signal_pending(current))
4647 vmx->emulation_required = 0;
4653 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4654 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4656 static int handle_pause(struct kvm_vcpu *vcpu)
4658 skip_emulated_instruction(vcpu);
4659 kvm_vcpu_on_spin(vcpu);
4664 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4666 kvm_queue_exception(vcpu, UD_VECTOR);
4671 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4672 * We could reuse a single VMCS for all the L2 guests, but we also want the
4673 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4674 * allows keeping them loaded on the processor, and in the future will allow
4675 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4676 * every entry if they never change.
4677 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4678 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4680 * The following functions allocate and free a vmcs02 in this pool.
4683 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4684 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4686 struct vmcs02_list *item;
4687 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4688 if (item->vmptr == vmx->nested.current_vmptr) {
4689 list_move(&item->list, &vmx->nested.vmcs02_pool);
4690 return &item->vmcs02;
4693 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4694 /* Recycle the least recently used VMCS. */
4695 item = list_entry(vmx->nested.vmcs02_pool.prev,
4696 struct vmcs02_list, list);
4697 item->vmptr = vmx->nested.current_vmptr;
4698 list_move(&item->list, &vmx->nested.vmcs02_pool);
4699 return &item->vmcs02;
4702 /* Create a new VMCS */
4703 item = (struct vmcs02_list *)
4704 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4707 item->vmcs02.vmcs = alloc_vmcs();
4708 if (!item->vmcs02.vmcs) {
4712 loaded_vmcs_init(&item->vmcs02);
4713 item->vmptr = vmx->nested.current_vmptr;
4714 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4715 vmx->nested.vmcs02_num++;
4716 return &item->vmcs02;
4719 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4720 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4722 struct vmcs02_list *item;
4723 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4724 if (item->vmptr == vmptr) {
4725 free_loaded_vmcs(&item->vmcs02);
4726 list_del(&item->list);
4728 vmx->nested.vmcs02_num--;
4734 * Free all VMCSs saved for this vcpu, except the one pointed by
4735 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4736 * currently used, if running L2), and vmcs01 when running L2.
4738 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4740 struct vmcs02_list *item, *n;
4741 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4742 if (vmx->loaded_vmcs != &item->vmcs02)
4743 free_loaded_vmcs(&item->vmcs02);
4744 list_del(&item->list);
4747 vmx->nested.vmcs02_num = 0;
4749 if (vmx->loaded_vmcs != &vmx->vmcs01)
4750 free_loaded_vmcs(&vmx->vmcs01);
4754 * Emulate the VMXON instruction.
4755 * Currently, we just remember that VMX is active, and do not save or even
4756 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4757 * do not currently need to store anything in that guest-allocated memory
4758 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4759 * argument is different from the VMXON pointer (which the spec says they do).
4761 static int handle_vmon(struct kvm_vcpu *vcpu)
4763 struct kvm_segment cs;
4764 struct vcpu_vmx *vmx = to_vmx(vcpu);
4766 /* The Intel VMX Instruction Reference lists a bunch of bits that
4767 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4768 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4769 * Otherwise, we should fail with #UD. We test these now:
4771 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4772 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4773 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4774 kvm_queue_exception(vcpu, UD_VECTOR);
4778 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4779 if (is_long_mode(vcpu) && !cs.l) {
4780 kvm_queue_exception(vcpu, UD_VECTOR);
4784 if (vmx_get_cpl(vcpu)) {
4785 kvm_inject_gp(vcpu, 0);
4789 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4790 vmx->nested.vmcs02_num = 0;
4792 vmx->nested.vmxon = true;
4794 skip_emulated_instruction(vcpu);
4799 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4800 * for running VMX instructions (except VMXON, whose prerequisites are
4801 * slightly different). It also specifies what exception to inject otherwise.
4803 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4805 struct kvm_segment cs;
4806 struct vcpu_vmx *vmx = to_vmx(vcpu);
4808 if (!vmx->nested.vmxon) {
4809 kvm_queue_exception(vcpu, UD_VECTOR);
4813 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4814 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4815 (is_long_mode(vcpu) && !cs.l)) {
4816 kvm_queue_exception(vcpu, UD_VECTOR);
4820 if (vmx_get_cpl(vcpu)) {
4821 kvm_inject_gp(vcpu, 0);
4829 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4830 * just stops using VMX.
4832 static void free_nested(struct vcpu_vmx *vmx)
4834 if (!vmx->nested.vmxon)
4836 vmx->nested.vmxon = false;
4837 if (vmx->nested.current_vmptr != -1ull) {
4838 kunmap(vmx->nested.current_vmcs12_page);
4839 nested_release_page(vmx->nested.current_vmcs12_page);
4840 vmx->nested.current_vmptr = -1ull;
4841 vmx->nested.current_vmcs12 = NULL;
4843 /* Unpin physical memory we referred to in current vmcs02 */
4844 if (vmx->nested.apic_access_page) {
4845 nested_release_page(vmx->nested.apic_access_page);
4846 vmx->nested.apic_access_page = 0;
4849 nested_free_all_saved_vmcss(vmx);
4852 /* Emulate the VMXOFF instruction */
4853 static int handle_vmoff(struct kvm_vcpu *vcpu)
4855 if (!nested_vmx_check_permission(vcpu))
4857 free_nested(to_vmx(vcpu));
4858 skip_emulated_instruction(vcpu);
4863 * Decode the memory-address operand of a vmx instruction, as recorded on an
4864 * exit caused by such an instruction (run by a guest hypervisor).
4865 * On success, returns 0. When the operand is invalid, returns 1 and throws
4868 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4869 unsigned long exit_qualification,
4870 u32 vmx_instruction_info, gva_t *ret)
4873 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4874 * Execution", on an exit, vmx_instruction_info holds most of the
4875 * addressing components of the operand. Only the displacement part
4876 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4877 * For how an actual address is calculated from all these components,
4878 * refer to Vol. 1, "Operand Addressing".
4880 int scaling = vmx_instruction_info & 3;
4881 int addr_size = (vmx_instruction_info >> 7) & 7;
4882 bool is_reg = vmx_instruction_info & (1u << 10);
4883 int seg_reg = (vmx_instruction_info >> 15) & 7;
4884 int index_reg = (vmx_instruction_info >> 18) & 0xf;
4885 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4886 int base_reg = (vmx_instruction_info >> 23) & 0xf;
4887 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
4890 kvm_queue_exception(vcpu, UD_VECTOR);
4894 /* Addr = segment_base + offset */
4895 /* offset = base + [index * scale] + displacement */
4896 *ret = vmx_get_segment_base(vcpu, seg_reg);
4898 *ret += kvm_register_read(vcpu, base_reg);
4900 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4901 *ret += exit_qualification; /* holds the displacement */
4903 if (addr_size == 1) /* 32 bit */
4907 * TODO: throw #GP (and return 1) in various cases that the VM*
4908 * instructions require it - e.g., offset beyond segment limit,
4909 * unusable or unreadable/unwritable segment, non-canonical 64-bit
4910 * address, and so on. Currently these are not checked.
4916 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
4917 * set the success or error code of an emulated VMX instruction, as specified
4918 * by Vol 2B, VMX Instruction Reference, "Conventions".
4920 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
4922 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
4923 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4924 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
4927 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
4929 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4930 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
4931 X86_EFLAGS_SF | X86_EFLAGS_OF))
4935 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
4936 u32 vm_instruction_error)
4938 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
4940 * failValid writes the error number to the current VMCS, which
4941 * can't be done there isn't a current VMCS.
4943 nested_vmx_failInvalid(vcpu);
4946 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4947 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4948 X86_EFLAGS_SF | X86_EFLAGS_OF))
4950 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
4953 /* Emulate the VMCLEAR instruction */
4954 static int handle_vmclear(struct kvm_vcpu *vcpu)
4956 struct vcpu_vmx *vmx = to_vmx(vcpu);
4959 struct vmcs12 *vmcs12;
4961 struct x86_exception e;
4963 if (!nested_vmx_check_permission(vcpu))
4966 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
4967 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
4970 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
4971 sizeof(vmptr), &e)) {
4972 kvm_inject_page_fault(vcpu, &e);
4976 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
4977 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
4978 skip_emulated_instruction(vcpu);
4982 if (vmptr == vmx->nested.current_vmptr) {
4983 kunmap(vmx->nested.current_vmcs12_page);
4984 nested_release_page(vmx->nested.current_vmcs12_page);
4985 vmx->nested.current_vmptr = -1ull;
4986 vmx->nested.current_vmcs12 = NULL;
4989 page = nested_get_page(vcpu, vmptr);
4992 * For accurate processor emulation, VMCLEAR beyond available
4993 * physical memory should do nothing at all. However, it is
4994 * possible that a nested vmx bug, not a guest hypervisor bug,
4995 * resulted in this case, so let's shut down before doing any
4998 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5001 vmcs12 = kmap(page);
5002 vmcs12->launch_state = 0;
5004 nested_release_page(page);
5006 nested_free_vmcs02(vmx, vmptr);
5008 skip_emulated_instruction(vcpu);
5009 nested_vmx_succeed(vcpu);
5013 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5015 /* Emulate the VMLAUNCH instruction */
5016 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5018 return nested_vmx_run(vcpu, true);
5021 /* Emulate the VMRESUME instruction */
5022 static int handle_vmresume(struct kvm_vcpu *vcpu)
5025 return nested_vmx_run(vcpu, false);
5028 enum vmcs_field_type {
5029 VMCS_FIELD_TYPE_U16 = 0,
5030 VMCS_FIELD_TYPE_U64 = 1,
5031 VMCS_FIELD_TYPE_U32 = 2,
5032 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5035 static inline int vmcs_field_type(unsigned long field)
5037 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5038 return VMCS_FIELD_TYPE_U32;
5039 return (field >> 13) & 0x3 ;
5042 static inline int vmcs_field_readonly(unsigned long field)
5044 return (((field >> 10) & 0x3) == 1);
5048 * Read a vmcs12 field. Since these can have varying lengths and we return
5049 * one type, we chose the biggest type (u64) and zero-extend the return value
5050 * to that size. Note that the caller, handle_vmread, might need to use only
5051 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5052 * 64-bit fields are to be returned).
5054 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5055 unsigned long field, u64 *ret)
5057 short offset = vmcs_field_to_offset(field);
5063 p = ((char *)(get_vmcs12(vcpu))) + offset;
5065 switch (vmcs_field_type(field)) {
5066 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5067 *ret = *((natural_width *)p);
5069 case VMCS_FIELD_TYPE_U16:
5072 case VMCS_FIELD_TYPE_U32:
5075 case VMCS_FIELD_TYPE_U64:
5079 return 0; /* can never happen. */
5084 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5085 * used before) all generate the same failure when it is missing.
5087 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5089 struct vcpu_vmx *vmx = to_vmx(vcpu);
5090 if (vmx->nested.current_vmptr == -1ull) {
5091 nested_vmx_failInvalid(vcpu);
5092 skip_emulated_instruction(vcpu);
5098 static int handle_vmread(struct kvm_vcpu *vcpu)
5100 unsigned long field;
5102 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5103 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5106 if (!nested_vmx_check_permission(vcpu) ||
5107 !nested_vmx_check_vmcs12(vcpu))
5110 /* Decode instruction info and find the field to read */
5111 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5112 /* Read the field, zero-extended to a u64 field_value */
5113 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5114 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5115 skip_emulated_instruction(vcpu);
5119 * Now copy part of this value to register or memory, as requested.
5120 * Note that the number of bits actually copied is 32 or 64 depending
5121 * on the guest's mode (32 or 64 bit), not on the given field's length.
5123 if (vmx_instruction_info & (1u << 10)) {
5124 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5127 if (get_vmx_mem_address(vcpu, exit_qualification,
5128 vmx_instruction_info, &gva))
5130 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5131 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5132 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5135 nested_vmx_succeed(vcpu);
5136 skip_emulated_instruction(vcpu);
5141 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5143 unsigned long field;
5145 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5146 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5149 /* The value to write might be 32 or 64 bits, depending on L1's long
5150 * mode, and eventually we need to write that into a field of several
5151 * possible lengths. The code below first zero-extends the value to 64
5152 * bit (field_value), and then copies only the approriate number of
5153 * bits into the vmcs12 field.
5155 u64 field_value = 0;
5156 struct x86_exception e;
5158 if (!nested_vmx_check_permission(vcpu) ||
5159 !nested_vmx_check_vmcs12(vcpu))
5162 if (vmx_instruction_info & (1u << 10))
5163 field_value = kvm_register_read(vcpu,
5164 (((vmx_instruction_info) >> 3) & 0xf));
5166 if (get_vmx_mem_address(vcpu, exit_qualification,
5167 vmx_instruction_info, &gva))
5169 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5170 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5171 kvm_inject_page_fault(vcpu, &e);
5177 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5178 if (vmcs_field_readonly(field)) {
5179 nested_vmx_failValid(vcpu,
5180 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5181 skip_emulated_instruction(vcpu);
5185 offset = vmcs_field_to_offset(field);
5187 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5188 skip_emulated_instruction(vcpu);
5191 p = ((char *) get_vmcs12(vcpu)) + offset;
5193 switch (vmcs_field_type(field)) {
5194 case VMCS_FIELD_TYPE_U16:
5195 *(u16 *)p = field_value;
5197 case VMCS_FIELD_TYPE_U32:
5198 *(u32 *)p = field_value;
5200 case VMCS_FIELD_TYPE_U64:
5201 *(u64 *)p = field_value;
5203 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5204 *(natural_width *)p = field_value;
5207 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5208 skip_emulated_instruction(vcpu);
5212 nested_vmx_succeed(vcpu);
5213 skip_emulated_instruction(vcpu);
5217 /* Emulate the VMPTRLD instruction */
5218 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5220 struct vcpu_vmx *vmx = to_vmx(vcpu);
5223 struct x86_exception e;
5225 if (!nested_vmx_check_permission(vcpu))
5228 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5229 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5232 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5233 sizeof(vmptr), &e)) {
5234 kvm_inject_page_fault(vcpu, &e);
5238 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5239 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5240 skip_emulated_instruction(vcpu);
5244 if (vmx->nested.current_vmptr != vmptr) {
5245 struct vmcs12 *new_vmcs12;
5247 page = nested_get_page(vcpu, vmptr);
5249 nested_vmx_failInvalid(vcpu);
5250 skip_emulated_instruction(vcpu);
5253 new_vmcs12 = kmap(page);
5254 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5256 nested_release_page_clean(page);
5257 nested_vmx_failValid(vcpu,
5258 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5259 skip_emulated_instruction(vcpu);
5262 if (vmx->nested.current_vmptr != -1ull) {
5263 kunmap(vmx->nested.current_vmcs12_page);
5264 nested_release_page(vmx->nested.current_vmcs12_page);
5267 vmx->nested.current_vmptr = vmptr;
5268 vmx->nested.current_vmcs12 = new_vmcs12;
5269 vmx->nested.current_vmcs12_page = page;
5272 nested_vmx_succeed(vcpu);
5273 skip_emulated_instruction(vcpu);
5277 /* Emulate the VMPTRST instruction */
5278 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5280 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5281 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5283 struct x86_exception e;
5285 if (!nested_vmx_check_permission(vcpu))
5288 if (get_vmx_mem_address(vcpu, exit_qualification,
5289 vmx_instruction_info, &vmcs_gva))
5291 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5292 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5293 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5295 kvm_inject_page_fault(vcpu, &e);
5298 nested_vmx_succeed(vcpu);
5299 skip_emulated_instruction(vcpu);
5304 * The exit handlers return 1 if the exit was handled fully and guest execution
5305 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5306 * to be done to userspace and return 0.
5308 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5309 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5310 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5311 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5312 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5313 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5314 [EXIT_REASON_CR_ACCESS] = handle_cr,
5315 [EXIT_REASON_DR_ACCESS] = handle_dr,
5316 [EXIT_REASON_CPUID] = handle_cpuid,
5317 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5318 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5319 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5320 [EXIT_REASON_HLT] = handle_halt,
5321 [EXIT_REASON_INVD] = handle_invd,
5322 [EXIT_REASON_INVLPG] = handle_invlpg,
5323 [EXIT_REASON_VMCALL] = handle_vmcall,
5324 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5325 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5326 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5327 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5328 [EXIT_REASON_VMREAD] = handle_vmread,
5329 [EXIT_REASON_VMRESUME] = handle_vmresume,
5330 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5331 [EXIT_REASON_VMOFF] = handle_vmoff,
5332 [EXIT_REASON_VMON] = handle_vmon,
5333 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5334 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5335 [EXIT_REASON_WBINVD] = handle_wbinvd,
5336 [EXIT_REASON_XSETBV] = handle_xsetbv,
5337 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5338 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5339 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5340 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5341 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5342 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5343 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5346 static const int kvm_vmx_max_exit_handlers =
5347 ARRAY_SIZE(kvm_vmx_exit_handlers);
5350 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5351 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5352 * disinterest in the current event (read or write a specific MSR) by using an
5353 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5355 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5356 struct vmcs12 *vmcs12, u32 exit_reason)
5358 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5361 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5365 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5366 * for the four combinations of read/write and low/high MSR numbers.
5367 * First we need to figure out which of the four to use:
5369 bitmap = vmcs12->msr_bitmap;
5370 if (exit_reason == EXIT_REASON_MSR_WRITE)
5372 if (msr_index >= 0xc0000000) {
5373 msr_index -= 0xc0000000;
5377 /* Then read the msr_index'th bit from this bitmap: */
5378 if (msr_index < 1024*8) {
5380 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5381 return 1 & (b >> (msr_index & 7));
5383 return 1; /* let L1 handle the wrong parameter */
5387 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5388 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5389 * intercept (via guest_host_mask etc.) the current event.
5391 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5392 struct vmcs12 *vmcs12)
5394 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5395 int cr = exit_qualification & 15;
5396 int reg = (exit_qualification >> 8) & 15;
5397 unsigned long val = kvm_register_read(vcpu, reg);
5399 switch ((exit_qualification >> 4) & 3) {
5400 case 0: /* mov to cr */
5403 if (vmcs12->cr0_guest_host_mask &
5404 (val ^ vmcs12->cr0_read_shadow))
5408 if ((vmcs12->cr3_target_count >= 1 &&
5409 vmcs12->cr3_target_value0 == val) ||
5410 (vmcs12->cr3_target_count >= 2 &&
5411 vmcs12->cr3_target_value1 == val) ||
5412 (vmcs12->cr3_target_count >= 3 &&
5413 vmcs12->cr3_target_value2 == val) ||
5414 (vmcs12->cr3_target_count >= 4 &&
5415 vmcs12->cr3_target_value3 == val))
5417 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5421 if (vmcs12->cr4_guest_host_mask &
5422 (vmcs12->cr4_read_shadow ^ val))
5426 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5432 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5433 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5436 case 1: /* mov from cr */
5439 if (vmcs12->cpu_based_vm_exec_control &
5440 CPU_BASED_CR3_STORE_EXITING)
5444 if (vmcs12->cpu_based_vm_exec_control &
5445 CPU_BASED_CR8_STORE_EXITING)
5452 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5453 * cr0. Other attempted changes are ignored, with no exit.
5455 if (vmcs12->cr0_guest_host_mask & 0xe &
5456 (val ^ vmcs12->cr0_read_shadow))
5458 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5459 !(vmcs12->cr0_read_shadow & 0x1) &&
5468 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5469 * should handle it ourselves in L0 (and then continue L2). Only call this
5470 * when in is_guest_mode (L2).
5472 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5474 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5475 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5476 struct vcpu_vmx *vmx = to_vmx(vcpu);
5477 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5479 if (vmx->nested.nested_run_pending)
5482 if (unlikely(vmx->fail)) {
5483 printk(KERN_INFO "%s failed vm entry %x\n",
5484 __func__, vmcs_read32(VM_INSTRUCTION_ERROR));
5488 switch (exit_reason) {
5489 case EXIT_REASON_EXCEPTION_NMI:
5490 if (!is_exception(intr_info))
5492 else if (is_page_fault(intr_info))
5494 return vmcs12->exception_bitmap &
5495 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5496 case EXIT_REASON_EXTERNAL_INTERRUPT:
5498 case EXIT_REASON_TRIPLE_FAULT:
5500 case EXIT_REASON_PENDING_INTERRUPT:
5501 case EXIT_REASON_NMI_WINDOW:
5503 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5504 * (aka Interrupt Window Exiting) only when L1 turned it on,
5505 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5506 * Same for NMI Window Exiting.
5509 case EXIT_REASON_TASK_SWITCH:
5511 case EXIT_REASON_CPUID:
5513 case EXIT_REASON_HLT:
5514 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5515 case EXIT_REASON_INVD:
5517 case EXIT_REASON_INVLPG:
5518 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5519 case EXIT_REASON_RDPMC:
5520 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5521 case EXIT_REASON_RDTSC:
5522 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5523 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5524 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5525 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5526 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5527 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5529 * VMX instructions trap unconditionally. This allows L1 to
5530 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5533 case EXIT_REASON_CR_ACCESS:
5534 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5535 case EXIT_REASON_DR_ACCESS:
5536 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5537 case EXIT_REASON_IO_INSTRUCTION:
5538 /* TODO: support IO bitmaps */
5540 case EXIT_REASON_MSR_READ:
5541 case EXIT_REASON_MSR_WRITE:
5542 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5543 case EXIT_REASON_INVALID_STATE:
5545 case EXIT_REASON_MWAIT_INSTRUCTION:
5546 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5547 case EXIT_REASON_MONITOR_INSTRUCTION:
5548 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5549 case EXIT_REASON_PAUSE_INSTRUCTION:
5550 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5551 nested_cpu_has2(vmcs12,
5552 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5553 case EXIT_REASON_MCE_DURING_VMENTRY:
5555 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5557 case EXIT_REASON_APIC_ACCESS:
5558 return nested_cpu_has2(vmcs12,
5559 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5560 case EXIT_REASON_EPT_VIOLATION:
5561 case EXIT_REASON_EPT_MISCONFIG:
5563 case EXIT_REASON_WBINVD:
5564 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5565 case EXIT_REASON_XSETBV:
5572 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5574 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5575 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5579 * The guest has exited. See if we can fix it or if we need userspace
5582 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5584 struct vcpu_vmx *vmx = to_vmx(vcpu);
5585 u32 exit_reason = vmx->exit_reason;
5586 u32 vectoring_info = vmx->idt_vectoring_info;
5588 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5590 /* If guest state is invalid, start emulating */
5591 if (vmx->emulation_required && emulate_invalid_guest_state)
5592 return handle_invalid_guest_state(vcpu);
5595 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5596 * we did not inject a still-pending event to L1 now because of
5597 * nested_run_pending, we need to re-enable this bit.
5599 if (vmx->nested.nested_run_pending)
5600 kvm_make_request(KVM_REQ_EVENT, vcpu);
5602 if (exit_reason == EXIT_REASON_VMLAUNCH ||
5603 exit_reason == EXIT_REASON_VMRESUME)
5604 vmx->nested.nested_run_pending = 1;
5606 vmx->nested.nested_run_pending = 0;
5608 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5609 nested_vmx_vmexit(vcpu);
5613 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5614 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5615 vcpu->run->fail_entry.hardware_entry_failure_reason
5620 if (unlikely(vmx->fail)) {
5621 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5622 vcpu->run->fail_entry.hardware_entry_failure_reason
5623 = vmcs_read32(VM_INSTRUCTION_ERROR);
5627 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5628 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5629 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5630 exit_reason != EXIT_REASON_TASK_SWITCH))
5631 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5632 "(0x%x) and exit reason is 0x%x\n",
5633 __func__, vectoring_info, exit_reason);
5635 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5636 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5637 get_vmcs12(vcpu), vcpu)))) {
5638 if (vmx_interrupt_allowed(vcpu)) {
5639 vmx->soft_vnmi_blocked = 0;
5640 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5641 vcpu->arch.nmi_pending) {
5643 * This CPU don't support us in finding the end of an
5644 * NMI-blocked window if the guest runs with IRQs
5645 * disabled. So we pull the trigger after 1 s of
5646 * futile waiting, but inform the user about this.
5648 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5649 "state on VCPU %d after 1 s timeout\n",
5650 __func__, vcpu->vcpu_id);
5651 vmx->soft_vnmi_blocked = 0;
5655 if (exit_reason < kvm_vmx_max_exit_handlers
5656 && kvm_vmx_exit_handlers[exit_reason])
5657 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5659 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5660 vcpu->run->hw.hardware_exit_reason = exit_reason;
5665 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5667 if (irr == -1 || tpr < irr) {
5668 vmcs_write32(TPR_THRESHOLD, 0);
5672 vmcs_write32(TPR_THRESHOLD, irr);
5675 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5679 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5680 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5683 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5684 exit_intr_info = vmx->exit_intr_info;
5686 /* Handle machine checks before interrupts are enabled */
5687 if (is_machine_check(exit_intr_info))
5688 kvm_machine_check();
5690 /* We need to handle NMIs before interrupts are enabled */
5691 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5692 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5693 kvm_before_handle_nmi(&vmx->vcpu);
5695 kvm_after_handle_nmi(&vmx->vcpu);
5699 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5704 bool idtv_info_valid;
5706 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5708 if (cpu_has_virtual_nmis()) {
5709 if (vmx->nmi_known_unmasked)
5712 * Can't use vmx->exit_intr_info since we're not sure what
5713 * the exit reason is.
5715 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5716 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5717 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5719 * SDM 3: 27.7.1.2 (September 2008)
5720 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5721 * a guest IRET fault.
5722 * SDM 3: 23.2.2 (September 2008)
5723 * Bit 12 is undefined in any of the following cases:
5724 * If the VM exit sets the valid bit in the IDT-vectoring
5725 * information field.
5726 * If the VM exit is due to a double fault.
5728 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5729 vector != DF_VECTOR && !idtv_info_valid)
5730 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5731 GUEST_INTR_STATE_NMI);
5733 vmx->nmi_known_unmasked =
5734 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5735 & GUEST_INTR_STATE_NMI);
5736 } else if (unlikely(vmx->soft_vnmi_blocked))
5737 vmx->vnmi_blocked_time +=
5738 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5741 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5742 u32 idt_vectoring_info,
5743 int instr_len_field,
5744 int error_code_field)
5748 bool idtv_info_valid;
5750 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5752 vmx->vcpu.arch.nmi_injected = false;
5753 kvm_clear_exception_queue(&vmx->vcpu);
5754 kvm_clear_interrupt_queue(&vmx->vcpu);
5756 if (!idtv_info_valid)
5759 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5761 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5762 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
5765 case INTR_TYPE_NMI_INTR:
5766 vmx->vcpu.arch.nmi_injected = true;
5768 * SDM 3: 27.7.1.2 (September 2008)
5769 * Clear bit "block by NMI" before VM entry if a NMI
5772 vmx_set_nmi_mask(&vmx->vcpu, false);
5774 case INTR_TYPE_SOFT_EXCEPTION:
5775 vmx->vcpu.arch.event_exit_inst_len =
5776 vmcs_read32(instr_len_field);
5778 case INTR_TYPE_HARD_EXCEPTION:
5779 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5780 u32 err = vmcs_read32(error_code_field);
5781 kvm_queue_exception_e(&vmx->vcpu, vector, err);
5783 kvm_queue_exception(&vmx->vcpu, vector);
5785 case INTR_TYPE_SOFT_INTR:
5786 vmx->vcpu.arch.event_exit_inst_len =
5787 vmcs_read32(instr_len_field);
5789 case INTR_TYPE_EXT_INTR:
5790 kvm_queue_interrupt(&vmx->vcpu, vector,
5791 type == INTR_TYPE_SOFT_INTR);
5798 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5800 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5801 VM_EXIT_INSTRUCTION_LEN,
5802 IDT_VECTORING_ERROR_CODE);
5805 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5807 __vmx_complete_interrupts(to_vmx(vcpu),
5808 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5809 VM_ENTRY_INSTRUCTION_LEN,
5810 VM_ENTRY_EXCEPTION_ERROR_CODE);
5812 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5815 #ifdef CONFIG_X86_64
5823 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
5825 struct vcpu_vmx *vmx = to_vmx(vcpu);
5827 /* Record the guest's net vcpu time for enforced NMI injections. */
5828 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5829 vmx->entry_time = ktime_get();
5831 /* Don't enter VMX if guest state is invalid, let the exit handler
5832 start emulation until we arrive back to a valid state */
5833 if (vmx->emulation_required && emulate_invalid_guest_state)
5836 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5837 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5838 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5839 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5841 /* When single-stepping over STI and MOV SS, we must clear the
5842 * corresponding interruptibility bits in the guest state. Otherwise
5843 * vmentry fails as it then expects bit 14 (BS) in pending debug
5844 * exceptions being set, but that's not correct for the guest debugging
5846 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5847 vmx_set_interrupt_shadow(vcpu, 0);
5849 vmx->__launched = vmx->loaded_vmcs->launched;
5851 /* Store host registers */
5852 "push %%"R"dx; push %%"R"bp;"
5853 "push %%"R"cx \n\t" /* placeholder for guest rcx */
5855 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5857 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
5858 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
5860 /* Reload cr2 if changed */
5861 "mov %c[cr2](%0), %%"R"ax \n\t"
5862 "mov %%cr2, %%"R"dx \n\t"
5863 "cmp %%"R"ax, %%"R"dx \n\t"
5865 "mov %%"R"ax, %%cr2 \n\t"
5867 /* Check if vmlaunch of vmresume is needed */
5868 "cmpl $0, %c[launched](%0) \n\t"
5869 /* Load guest registers. Don't clobber flags. */
5870 "mov %c[rax](%0), %%"R"ax \n\t"
5871 "mov %c[rbx](%0), %%"R"bx \n\t"
5872 "mov %c[rdx](%0), %%"R"dx \n\t"
5873 "mov %c[rsi](%0), %%"R"si \n\t"
5874 "mov %c[rdi](%0), %%"R"di \n\t"
5875 "mov %c[rbp](%0), %%"R"bp \n\t"
5876 #ifdef CONFIG_X86_64
5877 "mov %c[r8](%0), %%r8 \n\t"
5878 "mov %c[r9](%0), %%r9 \n\t"
5879 "mov %c[r10](%0), %%r10 \n\t"
5880 "mov %c[r11](%0), %%r11 \n\t"
5881 "mov %c[r12](%0), %%r12 \n\t"
5882 "mov %c[r13](%0), %%r13 \n\t"
5883 "mov %c[r14](%0), %%r14 \n\t"
5884 "mov %c[r15](%0), %%r15 \n\t"
5886 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5888 /* Enter guest mode */
5889 "jne .Llaunched \n\t"
5890 __ex(ASM_VMX_VMLAUNCH) "\n\t"
5891 "jmp .Lkvm_vmx_return \n\t"
5892 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
5893 ".Lkvm_vmx_return: "
5894 /* Save guest registers, load host registers, keep flags */
5895 "mov %0, %c[wordsize](%%"R"sp) \n\t"
5897 "mov %%"R"ax, %c[rax](%0) \n\t"
5898 "mov %%"R"bx, %c[rbx](%0) \n\t"
5899 "pop"Q" %c[rcx](%0) \n\t"
5900 "mov %%"R"dx, %c[rdx](%0) \n\t"
5901 "mov %%"R"si, %c[rsi](%0) \n\t"
5902 "mov %%"R"di, %c[rdi](%0) \n\t"
5903 "mov %%"R"bp, %c[rbp](%0) \n\t"
5904 #ifdef CONFIG_X86_64
5905 "mov %%r8, %c[r8](%0) \n\t"
5906 "mov %%r9, %c[r9](%0) \n\t"
5907 "mov %%r10, %c[r10](%0) \n\t"
5908 "mov %%r11, %c[r11](%0) \n\t"
5909 "mov %%r12, %c[r12](%0) \n\t"
5910 "mov %%r13, %c[r13](%0) \n\t"
5911 "mov %%r14, %c[r14](%0) \n\t"
5912 "mov %%r15, %c[r15](%0) \n\t"
5914 "mov %%cr2, %%"R"ax \n\t"
5915 "mov %%"R"ax, %c[cr2](%0) \n\t"
5917 "pop %%"R"bp; pop %%"R"dx \n\t"
5918 "setbe %c[fail](%0) \n\t"
5919 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
5920 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
5921 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
5922 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
5923 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
5924 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
5925 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
5926 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
5927 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
5928 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
5929 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
5930 #ifdef CONFIG_X86_64
5931 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
5932 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
5933 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
5934 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
5935 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
5936 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
5937 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
5938 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
5940 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
5941 [wordsize]"i"(sizeof(ulong))
5943 , R"ax", R"bx", R"di", R"si"
5944 #ifdef CONFIG_X86_64
5945 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5949 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
5950 | (1 << VCPU_EXREG_RFLAGS)
5951 | (1 << VCPU_EXREG_CPL)
5952 | (1 << VCPU_EXREG_PDPTR)
5953 | (1 << VCPU_EXREG_SEGMENTS)
5954 | (1 << VCPU_EXREG_CR3));
5955 vcpu->arch.regs_dirty = 0;
5957 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
5959 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
5960 vmx->loaded_vmcs->launched = 1;
5962 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
5964 vmx_complete_atomic_exit(vmx);
5965 vmx_recover_nmi_blocking(vmx);
5966 vmx_complete_interrupts(vmx);
5972 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
5974 struct vcpu_vmx *vmx = to_vmx(vcpu);
5978 free_loaded_vmcs(vmx->loaded_vmcs);
5979 kfree(vmx->guest_msrs);
5980 kvm_vcpu_uninit(vcpu);
5981 kmem_cache_free(kvm_vcpu_cache, vmx);
5984 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
5987 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
5991 return ERR_PTR(-ENOMEM);
5995 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
5999 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6001 if (!vmx->guest_msrs) {
6005 vmx->loaded_vmcs = &vmx->vmcs01;
6006 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6007 if (!vmx->loaded_vmcs->vmcs)
6010 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6011 loaded_vmcs_init(vmx->loaded_vmcs);
6016 vmx_vcpu_load(&vmx->vcpu, cpu);
6017 vmx->vcpu.cpu = cpu;
6018 err = vmx_vcpu_setup(vmx);
6019 vmx_vcpu_put(&vmx->vcpu);
6023 if (vm_need_virtualize_apic_accesses(kvm))
6024 err = alloc_apic_access_page(kvm);
6029 if (!kvm->arch.ept_identity_map_addr)
6030 kvm->arch.ept_identity_map_addr =
6031 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6033 if (alloc_identity_pagetable(kvm) != 0)
6035 if (!init_rmode_identity_map(kvm))
6039 vmx->nested.current_vmptr = -1ull;
6040 vmx->nested.current_vmcs12 = NULL;
6045 free_vmcs(vmx->loaded_vmcs->vmcs);
6047 kfree(vmx->guest_msrs);
6049 kvm_vcpu_uninit(&vmx->vcpu);
6052 kmem_cache_free(kvm_vcpu_cache, vmx);
6053 return ERR_PTR(err);
6056 static void __init vmx_check_processor_compat(void *rtn)
6058 struct vmcs_config vmcs_conf;
6061 if (setup_vmcs_config(&vmcs_conf) < 0)
6063 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6064 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6065 smp_processor_id());
6070 static int get_ept_level(void)
6072 return VMX_EPT_DEFAULT_GAW + 1;
6075 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6079 /* For VT-d and EPT combination
6080 * 1. MMIO: always map as UC
6082 * a. VT-d without snooping control feature: can't guarantee the
6083 * result, try to trust guest.
6084 * b. VT-d with snooping control feature: snooping control feature of
6085 * VT-d engine can guarantee the cache correctness. Just set it
6086 * to WB to keep consistent with host. So the same as item 3.
6087 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6088 * consistent with host MTRR
6091 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6092 else if (vcpu->kvm->arch.iommu_domain &&
6093 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6094 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6095 VMX_EPT_MT_EPTE_SHIFT;
6097 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6103 #define _ER(x) { EXIT_REASON_##x, #x }
6105 static const struct trace_print_flags vmx_exit_reasons_str[] = {
6107 _ER(EXTERNAL_INTERRUPT),
6109 _ER(PENDING_INTERRUPT),
6129 _ER(IO_INSTRUCTION),
6132 _ER(MWAIT_INSTRUCTION),
6133 _ER(MONITOR_INSTRUCTION),
6134 _ER(PAUSE_INSTRUCTION),
6135 _ER(MCE_DURING_VMENTRY),
6136 _ER(TPR_BELOW_THRESHOLD),
6146 static int vmx_get_lpage_level(void)
6148 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6149 return PT_DIRECTORY_LEVEL;
6151 /* For shadow and EPT supported 1GB page */
6152 return PT_PDPE_LEVEL;
6155 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6157 struct kvm_cpuid_entry2 *best;
6158 struct vcpu_vmx *vmx = to_vmx(vcpu);
6161 vmx->rdtscp_enabled = false;
6162 if (vmx_rdtscp_supported()) {
6163 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6164 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6165 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6166 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6167 vmx->rdtscp_enabled = true;
6169 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6170 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6177 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6182 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6183 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6184 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6185 * guest in a way that will both be appropriate to L1's requests, and our
6186 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6187 * function also has additional necessary side-effects, like setting various
6188 * vcpu->arch fields.
6190 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6192 struct vcpu_vmx *vmx = to_vmx(vcpu);
6195 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6196 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6197 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6198 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6199 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6200 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6201 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6202 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6203 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6204 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6205 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6206 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6207 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6208 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6209 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6210 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6211 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6212 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6213 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6214 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6215 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6216 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6217 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6218 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6219 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6220 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6221 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6222 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6223 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6224 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6225 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6226 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6227 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6228 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6229 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6230 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6232 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6233 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6234 vmcs12->vm_entry_intr_info_field);
6235 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6236 vmcs12->vm_entry_exception_error_code);
6237 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6238 vmcs12->vm_entry_instruction_len);
6239 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6240 vmcs12->guest_interruptibility_info);
6241 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6242 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6243 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6244 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6245 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6246 vmcs12->guest_pending_dbg_exceptions);
6247 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6248 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6250 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6252 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6253 (vmcs_config.pin_based_exec_ctrl |
6254 vmcs12->pin_based_vm_exec_control));
6257 * Whether page-faults are trapped is determined by a combination of
6258 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6259 * If enable_ept, L0 doesn't care about page faults and we should
6260 * set all of these to L1's desires. However, if !enable_ept, L0 does
6261 * care about (at least some) page faults, and because it is not easy
6262 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6263 * to exit on each and every L2 page fault. This is done by setting
6264 * MASK=MATCH=0 and (see below) EB.PF=1.
6265 * Note that below we don't need special code to set EB.PF beyond the
6266 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6267 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6268 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6270 * A problem with this approach (when !enable_ept) is that L1 may be
6271 * injected with more page faults than it asked for. This could have
6272 * caused problems, but in practice existing hypervisors don't care.
6273 * To fix this, we will need to emulate the PFEC checking (on the L1
6274 * page tables), using walk_addr(), when injecting PFs to L1.
6276 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6277 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6278 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6279 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6281 if (cpu_has_secondary_exec_ctrls()) {
6282 u32 exec_control = vmx_secondary_exec_control(vmx);
6283 if (!vmx->rdtscp_enabled)
6284 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6285 /* Take the following fields only from vmcs12 */
6286 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6287 if (nested_cpu_has(vmcs12,
6288 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6289 exec_control |= vmcs12->secondary_vm_exec_control;
6291 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6293 * Translate L1 physical address to host physical
6294 * address for vmcs02. Keep the page pinned, so this
6295 * physical address remains valid. We keep a reference
6296 * to it so we can release it later.
6298 if (vmx->nested.apic_access_page) /* shouldn't happen */
6299 nested_release_page(vmx->nested.apic_access_page);
6300 vmx->nested.apic_access_page =
6301 nested_get_page(vcpu, vmcs12->apic_access_addr);
6303 * If translation failed, no matter: This feature asks
6304 * to exit when accessing the given address, and if it
6305 * can never be accessed, this feature won't do
6308 if (!vmx->nested.apic_access_page)
6310 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6312 vmcs_write64(APIC_ACCESS_ADDR,
6313 page_to_phys(vmx->nested.apic_access_page));
6316 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6321 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6322 * Some constant fields are set here by vmx_set_constant_host_state().
6323 * Other fields are different per CPU, and will be set later when
6324 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6326 vmx_set_constant_host_state();
6329 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6330 * entry, but only if the current (host) sp changed from the value
6331 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6332 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6333 * here we just force the write to happen on entry.
6337 exec_control = vmx_exec_control(vmx); /* L0's desires */
6338 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6339 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6340 exec_control &= ~CPU_BASED_TPR_SHADOW;
6341 exec_control |= vmcs12->cpu_based_vm_exec_control;
6343 * Merging of IO and MSR bitmaps not currently supported.
6344 * Rather, exit every time.
6346 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6347 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6348 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6350 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6352 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6353 * bitwise-or of what L1 wants to trap for L2, and what we want to
6354 * trap. Note that CR0.TS also needs updating - we do this later.
6356 update_exception_bitmap(vcpu);
6357 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6358 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6360 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6361 vmcs_write32(VM_EXIT_CONTROLS,
6362 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6363 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6364 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6366 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6367 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6368 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6369 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6372 set_cr4_guest_host_mask(vmx);
6374 vmcs_write64(TSC_OFFSET,
6375 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6379 * Trivially support vpid by letting L2s share their parent
6380 * L1's vpid. TODO: move to a more elaborate solution, giving
6381 * each L2 its own vpid and exposing the vpid feature to L1.
6383 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6384 vmx_flush_tlb(vcpu);
6387 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6388 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6389 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6390 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6392 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6393 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6394 vmx_set_efer(vcpu, vcpu->arch.efer);
6397 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6398 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6399 * The CR0_READ_SHADOW is what L2 should have expected to read given
6400 * the specifications by L1; It's not enough to take
6401 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6402 * have more bits than L1 expected.
6404 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6405 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6407 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6408 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6410 /* shadow page tables on either EPT or shadow page tables */
6411 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6412 kvm_mmu_reset_context(vcpu);
6414 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6415 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6419 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6420 * for running an L2 nested guest.
6422 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6424 struct vmcs12 *vmcs12;
6425 struct vcpu_vmx *vmx = to_vmx(vcpu);
6427 struct loaded_vmcs *vmcs02;
6429 if (!nested_vmx_check_permission(vcpu) ||
6430 !nested_vmx_check_vmcs12(vcpu))
6433 skip_emulated_instruction(vcpu);
6434 vmcs12 = get_vmcs12(vcpu);
6437 * The nested entry process starts with enforcing various prerequisites
6438 * on vmcs12 as required by the Intel SDM, and act appropriately when
6439 * they fail: As the SDM explains, some conditions should cause the
6440 * instruction to fail, while others will cause the instruction to seem
6441 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6442 * To speed up the normal (success) code path, we should avoid checking
6443 * for misconfigurations which will anyway be caught by the processor
6444 * when using the merged vmcs02.
6446 if (vmcs12->launch_state == launch) {
6447 nested_vmx_failValid(vcpu,
6448 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6449 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6453 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6454 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6455 /*TODO: Also verify bits beyond physical address width are 0*/
6456 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6460 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6461 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6462 /*TODO: Also verify bits beyond physical address width are 0*/
6463 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6467 if (vmcs12->vm_entry_msr_load_count > 0 ||
6468 vmcs12->vm_exit_msr_load_count > 0 ||
6469 vmcs12->vm_exit_msr_store_count > 0) {
6470 if (printk_ratelimit())
6472 "%s: VMCS MSR_{LOAD,STORE} unsupported\n", __func__);
6473 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6477 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6478 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6479 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6480 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6481 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6482 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6483 !vmx_control_verify(vmcs12->vm_exit_controls,
6484 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6485 !vmx_control_verify(vmcs12->vm_entry_controls,
6486 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6488 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6492 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6493 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6494 nested_vmx_failValid(vcpu,
6495 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6499 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6500 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6501 nested_vmx_entry_failure(vcpu, vmcs12,
6502 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6505 if (vmcs12->vmcs_link_pointer != -1ull) {
6506 nested_vmx_entry_failure(vcpu, vmcs12,
6507 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6512 * We're finally done with prerequisite checking, and can start with
6516 vmcs02 = nested_get_current_vmcs02(vmx);
6520 enter_guest_mode(vcpu);
6522 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6525 vmx->loaded_vmcs = vmcs02;
6527 vmx_vcpu_load(vcpu, cpu);
6531 vmcs12->launch_state = 1;
6533 prepare_vmcs02(vcpu, vmcs12);
6536 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6537 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6538 * returned as far as L1 is concerned. It will only return (and set
6539 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6545 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6546 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6547 * This function returns the new value we should put in vmcs12.guest_cr0.
6548 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6549 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6550 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6551 * didn't trap the bit, because if L1 did, so would L0).
6552 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6553 * been modified by L2, and L1 knows it. So just leave the old value of
6554 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6555 * isn't relevant, because if L0 traps this bit it can set it to anything.
6556 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6557 * changed these bits, and therefore they need to be updated, but L0
6558 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6559 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6561 static inline unsigned long
6562 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6565 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6566 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6567 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6568 vcpu->arch.cr0_guest_owned_bits));
6571 static inline unsigned long
6572 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6575 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6576 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6577 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6578 vcpu->arch.cr4_guest_owned_bits));
6582 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6583 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6584 * and this function updates it to reflect the changes to the guest state while
6585 * L2 was running (and perhaps made some exits which were handled directly by L0
6586 * without going back to L1), and to reflect the exit reason.
6587 * Note that we do not have to copy here all VMCS fields, just those that
6588 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6589 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6590 * which already writes to vmcs12 directly.
6592 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6594 /* update guest state fields: */
6595 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6596 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6598 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6599 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6600 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6601 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6603 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6604 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6605 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6606 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6607 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6608 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6609 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6610 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6611 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6612 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6613 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6614 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6615 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6616 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6617 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6618 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6619 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6620 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6621 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6622 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6623 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6624 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6625 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6626 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6627 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6628 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6629 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6630 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6631 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6632 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6633 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6634 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6635 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6636 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6637 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6638 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6640 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6641 vmcs12->guest_interruptibility_info =
6642 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6643 vmcs12->guest_pending_dbg_exceptions =
6644 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6646 /* TODO: These cannot have changed unless we have MSR bitmaps and
6647 * the relevant bit asks not to trap the change */
6648 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6649 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6650 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6651 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6652 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6653 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6655 /* update exit information fields: */
6657 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6658 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6660 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6661 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6662 vmcs12->idt_vectoring_info_field =
6663 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6664 vmcs12->idt_vectoring_error_code =
6665 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6666 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6667 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6669 /* clear vm-entry fields which are to be cleared on exit */
6670 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6671 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6675 * A part of what we need to when the nested L2 guest exits and we want to
6676 * run its L1 parent, is to reset L1's guest state to the host state specified
6678 * This function is to be called not only on normal nested exit, but also on
6679 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6680 * Failures During or After Loading Guest State").
6681 * This function should be called when the active VMCS is L1's (vmcs01).
6683 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6685 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6686 vcpu->arch.efer = vmcs12->host_ia32_efer;
6687 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6688 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6690 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6691 vmx_set_efer(vcpu, vcpu->arch.efer);
6693 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6694 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6696 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6697 * actually changed, because it depends on the current state of
6698 * fpu_active (which may have changed).
6699 * Note that vmx_set_cr0 refers to efer set above.
6701 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6703 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6704 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6705 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6707 update_exception_bitmap(vcpu);
6708 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6709 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6712 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6713 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6715 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6716 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6718 /* shadow page tables on either EPT or shadow page tables */
6719 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6720 kvm_mmu_reset_context(vcpu);
6724 * Trivially support vpid by letting L2s share their parent
6725 * L1's vpid. TODO: move to a more elaborate solution, giving
6726 * each L2 its own vpid and exposing the vpid feature to L1.
6728 vmx_flush_tlb(vcpu);
6732 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6733 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6734 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6735 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6736 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6737 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6738 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6739 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6740 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6741 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6742 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6743 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6744 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6745 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6746 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6748 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6749 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6750 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6751 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6752 vmcs12->host_ia32_perf_global_ctrl);
6756 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6757 * and modify vmcs12 to make it see what it would expect to see there if
6758 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6760 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6762 struct vcpu_vmx *vmx = to_vmx(vcpu);
6764 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6766 leave_guest_mode(vcpu);
6767 prepare_vmcs12(vcpu, vmcs12);
6770 vmx->loaded_vmcs = &vmx->vmcs01;
6772 vmx_vcpu_load(vcpu, cpu);
6776 /* if no vmcs02 cache requested, remove the one we used */
6777 if (VMCS02_POOL_SIZE == 0)
6778 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
6780 load_vmcs12_host_state(vcpu, vmcs12);
6782 /* Update TSC_OFFSET if vmx_adjust_tsc_offset() was used while L2 ran */
6783 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6785 /* This is needed for same reason as it was needed in prepare_vmcs02 */
6788 /* Unpin physical memory we referred to in vmcs02 */
6789 if (vmx->nested.apic_access_page) {
6790 nested_release_page(vmx->nested.apic_access_page);
6791 vmx->nested.apic_access_page = 0;
6795 * Exiting from L2 to L1, we're now back to L1 which thinks it just
6796 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6797 * success or failure flag accordingly.
6799 if (unlikely(vmx->fail)) {
6801 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
6803 nested_vmx_succeed(vcpu);
6807 * L1's failure to enter L2 is a subset of a normal exit, as explained in
6808 * 23.7 "VM-entry failures during or after loading guest state" (this also
6809 * lists the acceptable exit-reason and exit-qualification parameters).
6810 * It should only be called before L2 actually succeeded to run, and when
6811 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6813 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
6814 struct vmcs12 *vmcs12,
6815 u32 reason, unsigned long qualification)
6817 load_vmcs12_host_state(vcpu, vmcs12);
6818 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
6819 vmcs12->exit_qualification = qualification;
6820 nested_vmx_succeed(vcpu);
6823 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6824 struct x86_instruction_info *info,
6825 enum x86_intercept_stage stage)
6827 return X86EMUL_CONTINUE;
6830 static struct kvm_x86_ops vmx_x86_ops = {
6831 .cpu_has_kvm_support = cpu_has_kvm_support,
6832 .disabled_by_bios = vmx_disabled_by_bios,
6833 .hardware_setup = hardware_setup,
6834 .hardware_unsetup = hardware_unsetup,
6835 .check_processor_compatibility = vmx_check_processor_compat,
6836 .hardware_enable = hardware_enable,
6837 .hardware_disable = hardware_disable,
6838 .cpu_has_accelerated_tpr = report_flexpriority,
6840 .vcpu_create = vmx_create_vcpu,
6841 .vcpu_free = vmx_free_vcpu,
6842 .vcpu_reset = vmx_vcpu_reset,
6844 .prepare_guest_switch = vmx_save_host_state,
6845 .vcpu_load = vmx_vcpu_load,
6846 .vcpu_put = vmx_vcpu_put,
6848 .set_guest_debug = set_guest_debug,
6849 .get_msr = vmx_get_msr,
6850 .set_msr = vmx_set_msr,
6851 .get_segment_base = vmx_get_segment_base,
6852 .get_segment = vmx_get_segment,
6853 .set_segment = vmx_set_segment,
6854 .get_cpl = vmx_get_cpl,
6855 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
6856 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
6857 .decache_cr3 = vmx_decache_cr3,
6858 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6859 .set_cr0 = vmx_set_cr0,
6860 .set_cr3 = vmx_set_cr3,
6861 .set_cr4 = vmx_set_cr4,
6862 .set_efer = vmx_set_efer,
6863 .get_idt = vmx_get_idt,
6864 .set_idt = vmx_set_idt,
6865 .get_gdt = vmx_get_gdt,
6866 .set_gdt = vmx_set_gdt,
6867 .set_dr7 = vmx_set_dr7,
6868 .cache_reg = vmx_cache_reg,
6869 .get_rflags = vmx_get_rflags,
6870 .set_rflags = vmx_set_rflags,
6871 .fpu_activate = vmx_fpu_activate,
6872 .fpu_deactivate = vmx_fpu_deactivate,
6874 .tlb_flush = vmx_flush_tlb,
6876 .run = vmx_vcpu_run,
6877 .handle_exit = vmx_handle_exit,
6878 .skip_emulated_instruction = skip_emulated_instruction,
6879 .set_interrupt_shadow = vmx_set_interrupt_shadow,
6880 .get_interrupt_shadow = vmx_get_interrupt_shadow,
6881 .patch_hypercall = vmx_patch_hypercall,
6882 .set_irq = vmx_inject_irq,
6883 .set_nmi = vmx_inject_nmi,
6884 .queue_exception = vmx_queue_exception,
6885 .cancel_injection = vmx_cancel_injection,
6886 .interrupt_allowed = vmx_interrupt_allowed,
6887 .nmi_allowed = vmx_nmi_allowed,
6888 .get_nmi_mask = vmx_get_nmi_mask,
6889 .set_nmi_mask = vmx_set_nmi_mask,
6890 .enable_nmi_window = enable_nmi_window,
6891 .enable_irq_window = enable_irq_window,
6892 .update_cr8_intercept = update_cr8_intercept,
6894 .set_tss_addr = vmx_set_tss_addr,
6895 .get_tdp_level = get_ept_level,
6896 .get_mt_mask = vmx_get_mt_mask,
6898 .get_exit_info = vmx_get_exit_info,
6899 .exit_reasons_str = vmx_exit_reasons_str,
6901 .get_lpage_level = vmx_get_lpage_level,
6903 .cpuid_update = vmx_cpuid_update,
6905 .rdtscp_supported = vmx_rdtscp_supported,
6907 .set_supported_cpuid = vmx_set_supported_cpuid,
6909 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
6911 .set_tsc_khz = vmx_set_tsc_khz,
6912 .write_tsc_offset = vmx_write_tsc_offset,
6913 .adjust_tsc_offset = vmx_adjust_tsc_offset,
6914 .compute_tsc_offset = vmx_compute_tsc_offset,
6916 .set_tdp_cr3 = vmx_set_cr3,
6918 .check_intercept = vmx_check_intercept,
6921 static int __init vmx_init(void)
6925 rdmsrl_safe(MSR_EFER, &host_efer);
6927 for (i = 0; i < NR_VMX_MSR; ++i)
6928 kvm_define_shared_msr(i, vmx_msr_index[i]);
6930 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6931 if (!vmx_io_bitmap_a)
6934 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6935 if (!vmx_io_bitmap_b) {
6940 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6941 if (!vmx_msr_bitmap_legacy) {
6946 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6947 if (!vmx_msr_bitmap_longmode) {
6953 * Allow direct access to the PC debug port (it is often used for I/O
6954 * delays, but the vmexits simply slow things down).
6956 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6957 clear_bit(0x80, vmx_io_bitmap_a);
6959 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6961 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6962 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6964 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6966 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
6967 __alignof__(struct vcpu_vmx), THIS_MODULE);
6971 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6972 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6973 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6974 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6975 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6976 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6979 bypass_guest_pf = 0;
6980 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
6981 VMX_EPT_EXECUTABLE_MASK);
6986 if (bypass_guest_pf)
6987 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
6992 free_page((unsigned long)vmx_msr_bitmap_longmode);
6994 free_page((unsigned long)vmx_msr_bitmap_legacy);
6996 free_page((unsigned long)vmx_io_bitmap_b);
6998 free_page((unsigned long)vmx_io_bitmap_a);
7002 static void __exit vmx_exit(void)
7004 free_page((unsigned long)vmx_msr_bitmap_legacy);
7005 free_page((unsigned long)vmx_msr_bitmap_longmode);
7006 free_page((unsigned long)vmx_io_bitmap_b);
7007 free_page((unsigned long)vmx_io_bitmap_a);
7012 module_init(vmx_init)
7013 module_exit(vmx_exit)