2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
50 static int __read_mostly bypass_guest_pf = 1;
51 module_param(bypass_guest_pf, bool, S_IRUGO);
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74 #define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
77 (X86_CR0_WP | X86_CR0_NE)
78 #define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
80 #define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
100 #define KVM_VMX_DEFAULT_PLE_GAP 41
101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103 module_param(ple_gap, int, S_IRUGO);
105 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106 module_param(ple_window, int, S_IRUGO);
108 #define NR_AUTOLOAD_MSRS 1
116 struct shared_msr_entry {
123 struct kvm_vcpu vcpu;
124 struct list_head local_vcpus_link;
125 unsigned long host_rsp;
129 u32 idt_vectoring_info;
130 struct shared_msr_entry *guest_msrs;
134 u64 msr_host_kernel_gs_base;
135 u64 msr_guest_kernel_gs_base;
138 struct msr_autoload {
140 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
141 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
145 u16 fs_sel, gs_sel, ldt_sel;
146 int gs_ldt_reload_needed;
147 int fs_reload_needed;
152 struct kvm_save_segment {
157 } tr, es, ds, fs, gs;
160 bool emulation_required;
162 /* Support for vnmi-less CPUs */
163 int soft_vnmi_blocked;
165 s64 vnmi_blocked_time;
171 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
173 return container_of(vcpu, struct vcpu_vmx, vcpu);
176 static int init_rmode(struct kvm *kvm);
177 static u64 construct_eptp(unsigned long root_hpa);
178 static void kvm_cpu_vmxon(u64 addr);
179 static void kvm_cpu_vmxoff(void);
181 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
182 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
183 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
184 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
186 static unsigned long *vmx_io_bitmap_a;
187 static unsigned long *vmx_io_bitmap_b;
188 static unsigned long *vmx_msr_bitmap_legacy;
189 static unsigned long *vmx_msr_bitmap_longmode;
191 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
192 static DEFINE_SPINLOCK(vmx_vpid_lock);
194 static struct vmcs_config {
198 u32 pin_based_exec_ctrl;
199 u32 cpu_based_exec_ctrl;
200 u32 cpu_based_2nd_exec_ctrl;
205 static struct vmx_capability {
210 #define VMX_SEGMENT_FIELD(seg) \
211 [VCPU_SREG_##seg] = { \
212 .selector = GUEST_##seg##_SELECTOR, \
213 .base = GUEST_##seg##_BASE, \
214 .limit = GUEST_##seg##_LIMIT, \
215 .ar_bytes = GUEST_##seg##_AR_BYTES, \
218 static struct kvm_vmx_segment_field {
223 } kvm_vmx_segment_fields[] = {
224 VMX_SEGMENT_FIELD(CS),
225 VMX_SEGMENT_FIELD(DS),
226 VMX_SEGMENT_FIELD(ES),
227 VMX_SEGMENT_FIELD(FS),
228 VMX_SEGMENT_FIELD(GS),
229 VMX_SEGMENT_FIELD(SS),
230 VMX_SEGMENT_FIELD(TR),
231 VMX_SEGMENT_FIELD(LDTR),
234 static u64 host_efer;
236 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
239 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
240 * away by decrementing the array size.
242 static const u32 vmx_msr_index[] = {
244 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
246 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
248 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
250 static inline bool is_page_fault(u32 intr_info)
252 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
253 INTR_INFO_VALID_MASK)) ==
254 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
257 static inline bool is_no_device(u32 intr_info)
259 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
260 INTR_INFO_VALID_MASK)) ==
261 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
264 static inline bool is_invalid_opcode(u32 intr_info)
266 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
267 INTR_INFO_VALID_MASK)) ==
268 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
271 static inline bool is_external_interrupt(u32 intr_info)
273 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
274 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
277 static inline bool is_machine_check(u32 intr_info)
279 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
280 INTR_INFO_VALID_MASK)) ==
281 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
284 static inline bool cpu_has_vmx_msr_bitmap(void)
286 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
289 static inline bool cpu_has_vmx_tpr_shadow(void)
291 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
294 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
296 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
299 static inline bool cpu_has_secondary_exec_ctrls(void)
301 return vmcs_config.cpu_based_exec_ctrl &
302 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
305 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
307 return vmcs_config.cpu_based_2nd_exec_ctrl &
308 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
311 static inline bool cpu_has_vmx_flexpriority(void)
313 return cpu_has_vmx_tpr_shadow() &&
314 cpu_has_vmx_virtualize_apic_accesses();
317 static inline bool cpu_has_vmx_ept_execute_only(void)
319 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
322 static inline bool cpu_has_vmx_eptp_uncacheable(void)
324 return vmx_capability.ept & VMX_EPTP_UC_BIT;
327 static inline bool cpu_has_vmx_eptp_writeback(void)
329 return vmx_capability.ept & VMX_EPTP_WB_BIT;
332 static inline bool cpu_has_vmx_ept_2m_page(void)
334 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
337 static inline bool cpu_has_vmx_ept_1g_page(void)
339 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
342 static inline bool cpu_has_vmx_ept_4levels(void)
344 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
347 static inline bool cpu_has_vmx_invept_individual_addr(void)
349 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
352 static inline bool cpu_has_vmx_invept_context(void)
354 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
357 static inline bool cpu_has_vmx_invept_global(void)
359 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
362 static inline bool cpu_has_vmx_invvpid_single(void)
364 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
367 static inline bool cpu_has_vmx_invvpid_global(void)
369 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
372 static inline bool cpu_has_vmx_ept(void)
374 return vmcs_config.cpu_based_2nd_exec_ctrl &
375 SECONDARY_EXEC_ENABLE_EPT;
378 static inline bool cpu_has_vmx_unrestricted_guest(void)
380 return vmcs_config.cpu_based_2nd_exec_ctrl &
381 SECONDARY_EXEC_UNRESTRICTED_GUEST;
384 static inline bool cpu_has_vmx_ple(void)
386 return vmcs_config.cpu_based_2nd_exec_ctrl &
387 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
390 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
392 return flexpriority_enabled && irqchip_in_kernel(kvm);
395 static inline bool cpu_has_vmx_vpid(void)
397 return vmcs_config.cpu_based_2nd_exec_ctrl &
398 SECONDARY_EXEC_ENABLE_VPID;
401 static inline bool cpu_has_vmx_rdtscp(void)
403 return vmcs_config.cpu_based_2nd_exec_ctrl &
404 SECONDARY_EXEC_RDTSCP;
407 static inline bool cpu_has_virtual_nmis(void)
409 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
412 static inline bool cpu_has_vmx_wbinvd_exit(void)
414 return vmcs_config.cpu_based_2nd_exec_ctrl &
415 SECONDARY_EXEC_WBINVD_EXITING;
418 static inline bool report_flexpriority(void)
420 return flexpriority_enabled;
423 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
427 for (i = 0; i < vmx->nmsrs; ++i)
428 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
433 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
439 } operand = { vpid, 0, gva };
441 asm volatile (__ex(ASM_VMX_INVVPID)
442 /* CF==1 or ZF==1 --> rc = -1 */
444 : : "a"(&operand), "c"(ext) : "cc", "memory");
447 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
451 } operand = {eptp, gpa};
453 asm volatile (__ex(ASM_VMX_INVEPT)
454 /* CF==1 or ZF==1 --> rc = -1 */
455 "; ja 1f ; ud2 ; 1:\n"
456 : : "a" (&operand), "c" (ext) : "cc", "memory");
459 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
463 i = __find_msr_index(vmx, msr);
465 return &vmx->guest_msrs[i];
469 static void vmcs_clear(struct vmcs *vmcs)
471 u64 phys_addr = __pa(vmcs);
474 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
475 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
478 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
482 static void vmcs_load(struct vmcs *vmcs)
484 u64 phys_addr = __pa(vmcs);
487 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
488 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
491 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
495 static void __vcpu_clear(void *arg)
497 struct vcpu_vmx *vmx = arg;
498 int cpu = raw_smp_processor_id();
500 if (vmx->vcpu.cpu == cpu)
501 vmcs_clear(vmx->vmcs);
502 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
503 per_cpu(current_vmcs, cpu) = NULL;
504 list_del(&vmx->local_vcpus_link);
509 static void vcpu_clear(struct vcpu_vmx *vmx)
511 if (vmx->vcpu.cpu == -1)
513 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
516 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
521 if (cpu_has_vmx_invvpid_single())
522 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
525 static inline void vpid_sync_vcpu_global(void)
527 if (cpu_has_vmx_invvpid_global())
528 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
531 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
533 if (cpu_has_vmx_invvpid_single())
534 vpid_sync_vcpu_single(vmx);
536 vpid_sync_vcpu_global();
539 static inline void ept_sync_global(void)
541 if (cpu_has_vmx_invept_global())
542 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
545 static inline void ept_sync_context(u64 eptp)
548 if (cpu_has_vmx_invept_context())
549 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
555 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
558 if (cpu_has_vmx_invept_individual_addr())
559 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
562 ept_sync_context(eptp);
566 static unsigned long vmcs_readl(unsigned long field)
570 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
571 : "=a"(value) : "d"(field) : "cc");
575 static u16 vmcs_read16(unsigned long field)
577 return vmcs_readl(field);
580 static u32 vmcs_read32(unsigned long field)
582 return vmcs_readl(field);
585 static u64 vmcs_read64(unsigned long field)
588 return vmcs_readl(field);
590 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
594 static noinline void vmwrite_error(unsigned long field, unsigned long value)
596 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
597 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
601 static void vmcs_writel(unsigned long field, unsigned long value)
605 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
606 : "=q"(error) : "a"(value), "d"(field) : "cc");
608 vmwrite_error(field, value);
611 static void vmcs_write16(unsigned long field, u16 value)
613 vmcs_writel(field, value);
616 static void vmcs_write32(unsigned long field, u32 value)
618 vmcs_writel(field, value);
621 static void vmcs_write64(unsigned long field, u64 value)
623 vmcs_writel(field, value);
624 #ifndef CONFIG_X86_64
626 vmcs_writel(field+1, value >> 32);
630 static void vmcs_clear_bits(unsigned long field, u32 mask)
632 vmcs_writel(field, vmcs_readl(field) & ~mask);
635 static void vmcs_set_bits(unsigned long field, u32 mask)
637 vmcs_writel(field, vmcs_readl(field) | mask);
640 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
644 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
645 (1u << NM_VECTOR) | (1u << DB_VECTOR);
646 if ((vcpu->guest_debug &
647 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
648 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
649 eb |= 1u << BP_VECTOR;
650 if (to_vmx(vcpu)->rmode.vm86_active)
653 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
654 if (vcpu->fpu_active)
655 eb &= ~(1u << NM_VECTOR);
656 vmcs_write32(EXCEPTION_BITMAP, eb);
659 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
662 struct msr_autoload *m = &vmx->msr_autoload;
664 for (i = 0; i < m->nr; ++i)
665 if (m->guest[i].index == msr)
671 m->guest[i] = m->guest[m->nr];
672 m->host[i] = m->host[m->nr];
673 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
674 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
677 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
678 u64 guest_val, u64 host_val)
681 struct msr_autoload *m = &vmx->msr_autoload;
683 for (i = 0; i < m->nr; ++i)
684 if (m->guest[i].index == msr)
689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
693 m->guest[i].index = msr;
694 m->guest[i].value = guest_val;
695 m->host[i].index = msr;
696 m->host[i].value = host_val;
699 static void reload_tss(void)
702 * VT restores TR but not its size. Useless.
704 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
705 struct desc_struct *descs;
707 descs = (void *)gdt->address;
708 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
712 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
717 guest_efer = vmx->vcpu.arch.efer;
720 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
723 ignore_bits = EFER_NX | EFER_SCE;
725 ignore_bits |= EFER_LMA | EFER_LME;
726 /* SCE is meaningful only in long mode on Intel */
727 if (guest_efer & EFER_LMA)
728 ignore_bits &= ~(u64)EFER_SCE;
730 guest_efer &= ~ignore_bits;
731 guest_efer |= host_efer & ignore_bits;
732 vmx->guest_msrs[efer_offset].data = guest_efer;
733 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
735 clear_atomic_switch_msr(vmx, MSR_EFER);
736 /* On ept, can't emulate nx, and must switch nx atomically */
737 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
738 guest_efer = vmx->vcpu.arch.efer;
739 if (!(guest_efer & EFER_LMA))
740 guest_efer &= ~EFER_LME;
741 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
748 static unsigned long segment_base(u16 selector)
750 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
751 struct desc_struct *d;
752 unsigned long table_base;
755 if (!(selector & ~3))
758 table_base = gdt->address;
760 if (selector & 4) { /* from ldt */
761 u16 ldt_selector = kvm_read_ldt();
763 if (!(ldt_selector & ~3))
766 table_base = segment_base(ldt_selector);
768 d = (struct desc_struct *)(table_base + (selector & ~7));
769 v = get_desc_base(d);
771 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
772 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
777 static inline unsigned long kvm_read_tr_base(void)
780 asm("str %0" : "=g"(tr));
781 return segment_base(tr);
784 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
786 struct vcpu_vmx *vmx = to_vmx(vcpu);
789 if (vmx->host_state.loaded)
792 vmx->host_state.loaded = 1;
794 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
795 * allow segment selectors with cpl > 0 or ti == 1.
797 vmx->host_state.ldt_sel = kvm_read_ldt();
798 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
799 savesegment(fs, vmx->host_state.fs_sel);
800 if (!(vmx->host_state.fs_sel & 7)) {
801 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
802 vmx->host_state.fs_reload_needed = 0;
804 vmcs_write16(HOST_FS_SELECTOR, 0);
805 vmx->host_state.fs_reload_needed = 1;
807 savesegment(gs, vmx->host_state.gs_sel);
808 if (!(vmx->host_state.gs_sel & 7))
809 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
811 vmcs_write16(HOST_GS_SELECTOR, 0);
812 vmx->host_state.gs_ldt_reload_needed = 1;
816 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
817 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
819 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
820 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
824 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
825 if (is_long_mode(&vmx->vcpu))
826 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
828 for (i = 0; i < vmx->save_nmsrs; ++i)
829 kvm_set_shared_msr(vmx->guest_msrs[i].index,
830 vmx->guest_msrs[i].data,
831 vmx->guest_msrs[i].mask);
834 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
836 if (!vmx->host_state.loaded)
839 ++vmx->vcpu.stat.host_state_reload;
840 vmx->host_state.loaded = 0;
842 if (is_long_mode(&vmx->vcpu))
843 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
845 if (vmx->host_state.gs_ldt_reload_needed) {
846 kvm_load_ldt(vmx->host_state.ldt_sel);
848 load_gs_index(vmx->host_state.gs_sel);
850 loadsegment(gs, vmx->host_state.gs_sel);
853 if (vmx->host_state.fs_reload_needed)
854 loadsegment(fs, vmx->host_state.fs_sel);
857 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
859 if (current_thread_info()->status & TS_USEDFPU)
861 load_gdt(&__get_cpu_var(host_gdt));
864 static void vmx_load_host_state(struct vcpu_vmx *vmx)
867 __vmx_load_host_state(vmx);
872 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
873 * vcpu mutex is already taken.
875 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
877 struct vcpu_vmx *vmx = to_vmx(vcpu);
878 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
881 kvm_cpu_vmxon(phys_addr);
882 else if (vcpu->cpu != cpu)
885 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
886 per_cpu(current_vmcs, cpu) = vmx->vmcs;
887 vmcs_load(vmx->vmcs);
890 if (vcpu->cpu != cpu) {
891 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
892 unsigned long sysenter_esp;
894 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
896 list_add(&vmx->local_vcpus_link,
897 &per_cpu(vcpus_on_cpu, cpu));
901 * Linux uses per-cpu TSS and GDT, so set these when switching
904 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
905 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
907 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
908 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
912 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
914 __vmx_load_host_state(to_vmx(vcpu));
915 if (!vmm_exclusive) {
916 __vcpu_clear(to_vmx(vcpu));
921 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
925 if (vcpu->fpu_active)
927 vcpu->fpu_active = 1;
928 cr0 = vmcs_readl(GUEST_CR0);
929 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
930 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
931 vmcs_writel(GUEST_CR0, cr0);
932 update_exception_bitmap(vcpu);
933 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
934 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
937 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
939 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
941 vmx_decache_cr0_guest_bits(vcpu);
942 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
943 update_exception_bitmap(vcpu);
944 vcpu->arch.cr0_guest_owned_bits = 0;
945 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
946 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
949 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
951 unsigned long rflags, save_rflags;
953 rflags = vmcs_readl(GUEST_RFLAGS);
954 if (to_vmx(vcpu)->rmode.vm86_active) {
955 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
956 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
957 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
962 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
964 if (to_vmx(vcpu)->rmode.vm86_active) {
965 to_vmx(vcpu)->rmode.save_rflags = rflags;
966 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
968 vmcs_writel(GUEST_RFLAGS, rflags);
971 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
973 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
976 if (interruptibility & GUEST_INTR_STATE_STI)
977 ret |= KVM_X86_SHADOW_INT_STI;
978 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
979 ret |= KVM_X86_SHADOW_INT_MOV_SS;
984 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
986 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
987 u32 interruptibility = interruptibility_old;
989 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
991 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
992 interruptibility |= GUEST_INTR_STATE_MOV_SS;
993 else if (mask & KVM_X86_SHADOW_INT_STI)
994 interruptibility |= GUEST_INTR_STATE_STI;
996 if ((interruptibility != interruptibility_old))
997 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1000 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1004 rip = kvm_rip_read(vcpu);
1005 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1006 kvm_rip_write(vcpu, rip);
1008 /* skipping an emulated instruction also counts */
1009 vmx_set_interrupt_shadow(vcpu, 0);
1012 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1013 bool has_error_code, u32 error_code,
1016 struct vcpu_vmx *vmx = to_vmx(vcpu);
1017 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1019 if (has_error_code) {
1020 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1021 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1024 if (vmx->rmode.vm86_active) {
1025 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1026 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1030 if (kvm_exception_is_soft(nr)) {
1031 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1032 vmx->vcpu.arch.event_exit_inst_len);
1033 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1035 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1037 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1040 static bool vmx_rdtscp_supported(void)
1042 return cpu_has_vmx_rdtscp();
1046 * Swap MSR entry in host/guest MSR entry array.
1048 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1050 struct shared_msr_entry tmp;
1052 tmp = vmx->guest_msrs[to];
1053 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1054 vmx->guest_msrs[from] = tmp;
1058 * Set up the vmcs to automatically save and restore system
1059 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1060 * mode, as fiddling with msrs is very expensive.
1062 static void setup_msrs(struct vcpu_vmx *vmx)
1064 int save_nmsrs, index;
1065 unsigned long *msr_bitmap;
1067 vmx_load_host_state(vmx);
1069 #ifdef CONFIG_X86_64
1070 if (is_long_mode(&vmx->vcpu)) {
1071 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1073 move_msr_up(vmx, index, save_nmsrs++);
1074 index = __find_msr_index(vmx, MSR_LSTAR);
1076 move_msr_up(vmx, index, save_nmsrs++);
1077 index = __find_msr_index(vmx, MSR_CSTAR);
1079 move_msr_up(vmx, index, save_nmsrs++);
1080 index = __find_msr_index(vmx, MSR_TSC_AUX);
1081 if (index >= 0 && vmx->rdtscp_enabled)
1082 move_msr_up(vmx, index, save_nmsrs++);
1084 * MSR_STAR is only needed on long mode guests, and only
1085 * if efer.sce is enabled.
1087 index = __find_msr_index(vmx, MSR_STAR);
1088 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1089 move_msr_up(vmx, index, save_nmsrs++);
1092 index = __find_msr_index(vmx, MSR_EFER);
1093 if (index >= 0 && update_transition_efer(vmx, index))
1094 move_msr_up(vmx, index, save_nmsrs++);
1096 vmx->save_nmsrs = save_nmsrs;
1098 if (cpu_has_vmx_msr_bitmap()) {
1099 if (is_long_mode(&vmx->vcpu))
1100 msr_bitmap = vmx_msr_bitmap_longmode;
1102 msr_bitmap = vmx_msr_bitmap_legacy;
1104 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1109 * reads and returns guest's timestamp counter "register"
1110 * guest_tsc = host_tsc + tsc_offset -- 21.3
1112 static u64 guest_read_tsc(void)
1114 u64 host_tsc, tsc_offset;
1117 tsc_offset = vmcs_read64(TSC_OFFSET);
1118 return host_tsc + tsc_offset;
1122 * writes 'offset' into guest's timestamp counter offset register
1124 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1126 vmcs_write64(TSC_OFFSET, offset);
1129 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1131 u64 offset = vmcs_read64(TSC_OFFSET);
1132 vmcs_write64(TSC_OFFSET, offset + adjustment);
1136 * Reads an msr value (of 'msr_index') into 'pdata'.
1137 * Returns 0 on success, non-0 otherwise.
1138 * Assumes vcpu_load() was already called.
1140 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1143 struct shared_msr_entry *msr;
1146 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1150 switch (msr_index) {
1151 #ifdef CONFIG_X86_64
1153 data = vmcs_readl(GUEST_FS_BASE);
1156 data = vmcs_readl(GUEST_GS_BASE);
1158 case MSR_KERNEL_GS_BASE:
1159 vmx_load_host_state(to_vmx(vcpu));
1160 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1164 return kvm_get_msr_common(vcpu, msr_index, pdata);
1166 data = guest_read_tsc();
1168 case MSR_IA32_SYSENTER_CS:
1169 data = vmcs_read32(GUEST_SYSENTER_CS);
1171 case MSR_IA32_SYSENTER_EIP:
1172 data = vmcs_readl(GUEST_SYSENTER_EIP);
1174 case MSR_IA32_SYSENTER_ESP:
1175 data = vmcs_readl(GUEST_SYSENTER_ESP);
1178 if (!to_vmx(vcpu)->rdtscp_enabled)
1180 /* Otherwise falls through */
1182 vmx_load_host_state(to_vmx(vcpu));
1183 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1185 vmx_load_host_state(to_vmx(vcpu));
1189 return kvm_get_msr_common(vcpu, msr_index, pdata);
1197 * Writes msr value into into the appropriate "register".
1198 * Returns 0 on success, non-0 otherwise.
1199 * Assumes vcpu_load() was already called.
1201 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1203 struct vcpu_vmx *vmx = to_vmx(vcpu);
1204 struct shared_msr_entry *msr;
1207 switch (msr_index) {
1209 vmx_load_host_state(vmx);
1210 ret = kvm_set_msr_common(vcpu, msr_index, data);
1212 #ifdef CONFIG_X86_64
1214 vmcs_writel(GUEST_FS_BASE, data);
1217 vmcs_writel(GUEST_GS_BASE, data);
1219 case MSR_KERNEL_GS_BASE:
1220 vmx_load_host_state(vmx);
1221 vmx->msr_guest_kernel_gs_base = data;
1224 case MSR_IA32_SYSENTER_CS:
1225 vmcs_write32(GUEST_SYSENTER_CS, data);
1227 case MSR_IA32_SYSENTER_EIP:
1228 vmcs_writel(GUEST_SYSENTER_EIP, data);
1230 case MSR_IA32_SYSENTER_ESP:
1231 vmcs_writel(GUEST_SYSENTER_ESP, data);
1234 kvm_write_tsc(vcpu, data);
1236 case MSR_IA32_CR_PAT:
1237 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1238 vmcs_write64(GUEST_IA32_PAT, data);
1239 vcpu->arch.pat = data;
1242 ret = kvm_set_msr_common(vcpu, msr_index, data);
1245 if (!vmx->rdtscp_enabled)
1247 /* Check reserved bit, higher 32 bits should be zero */
1248 if ((data >> 32) != 0)
1250 /* Otherwise falls through */
1252 msr = find_msr_entry(vmx, msr_index);
1254 vmx_load_host_state(vmx);
1258 ret = kvm_set_msr_common(vcpu, msr_index, data);
1264 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1266 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1269 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1272 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1274 case VCPU_EXREG_PDPTR:
1276 ept_save_pdptrs(vcpu);
1283 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1285 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1286 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1288 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1290 update_exception_bitmap(vcpu);
1293 static __init int cpu_has_kvm_support(void)
1295 return cpu_has_vmx();
1298 static __init int vmx_disabled_by_bios(void)
1302 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1303 if (msr & FEATURE_CONTROL_LOCKED) {
1304 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1307 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1308 && !tboot_enabled()) {
1309 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1310 " activate TXT before enabling KVM\n");
1316 /* locked but not enabled */
1319 static void kvm_cpu_vmxon(u64 addr)
1321 asm volatile (ASM_VMX_VMXON_RAX
1322 : : "a"(&addr), "m"(addr)
1326 static int hardware_enable(void *garbage)
1328 int cpu = raw_smp_processor_id();
1329 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1332 if (read_cr4() & X86_CR4_VMXE)
1335 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1336 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1338 test_bits = FEATURE_CONTROL_LOCKED;
1339 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1340 if (tboot_enabled())
1341 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1343 if ((old & test_bits) != test_bits) {
1344 /* enable and lock */
1345 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1347 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1349 if (vmm_exclusive) {
1350 kvm_cpu_vmxon(phys_addr);
1354 store_gdt(&__get_cpu_var(host_gdt));
1359 static void vmclear_local_vcpus(void)
1361 int cpu = raw_smp_processor_id();
1362 struct vcpu_vmx *vmx, *n;
1364 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1370 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1373 static void kvm_cpu_vmxoff(void)
1375 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1378 static void hardware_disable(void *garbage)
1380 if (vmm_exclusive) {
1381 vmclear_local_vcpus();
1384 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1387 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1388 u32 msr, u32 *result)
1390 u32 vmx_msr_low, vmx_msr_high;
1391 u32 ctl = ctl_min | ctl_opt;
1393 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1395 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1396 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1398 /* Ensure minimum (required) set of control bits are supported. */
1406 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1408 u32 vmx_msr_low, vmx_msr_high;
1409 u32 min, opt, min2, opt2;
1410 u32 _pin_based_exec_control = 0;
1411 u32 _cpu_based_exec_control = 0;
1412 u32 _cpu_based_2nd_exec_control = 0;
1413 u32 _vmexit_control = 0;
1414 u32 _vmentry_control = 0;
1416 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1417 opt = PIN_BASED_VIRTUAL_NMIS;
1418 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1419 &_pin_based_exec_control) < 0)
1422 min = CPU_BASED_HLT_EXITING |
1423 #ifdef CONFIG_X86_64
1424 CPU_BASED_CR8_LOAD_EXITING |
1425 CPU_BASED_CR8_STORE_EXITING |
1427 CPU_BASED_CR3_LOAD_EXITING |
1428 CPU_BASED_CR3_STORE_EXITING |
1429 CPU_BASED_USE_IO_BITMAPS |
1430 CPU_BASED_MOV_DR_EXITING |
1431 CPU_BASED_USE_TSC_OFFSETING |
1432 CPU_BASED_MWAIT_EXITING |
1433 CPU_BASED_MONITOR_EXITING |
1434 CPU_BASED_INVLPG_EXITING;
1435 opt = CPU_BASED_TPR_SHADOW |
1436 CPU_BASED_USE_MSR_BITMAPS |
1437 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1438 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1439 &_cpu_based_exec_control) < 0)
1441 #ifdef CONFIG_X86_64
1442 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1443 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1444 ~CPU_BASED_CR8_STORE_EXITING;
1446 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1448 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1449 SECONDARY_EXEC_WBINVD_EXITING |
1450 SECONDARY_EXEC_ENABLE_VPID |
1451 SECONDARY_EXEC_ENABLE_EPT |
1452 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1453 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1454 SECONDARY_EXEC_RDTSCP;
1455 if (adjust_vmx_controls(min2, opt2,
1456 MSR_IA32_VMX_PROCBASED_CTLS2,
1457 &_cpu_based_2nd_exec_control) < 0)
1460 #ifndef CONFIG_X86_64
1461 if (!(_cpu_based_2nd_exec_control &
1462 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1463 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1465 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1466 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1468 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1469 CPU_BASED_CR3_STORE_EXITING |
1470 CPU_BASED_INVLPG_EXITING);
1471 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1472 vmx_capability.ept, vmx_capability.vpid);
1476 #ifdef CONFIG_X86_64
1477 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1479 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1480 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1481 &_vmexit_control) < 0)
1485 opt = VM_ENTRY_LOAD_IA32_PAT;
1486 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1487 &_vmentry_control) < 0)
1490 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1492 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1493 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1496 #ifdef CONFIG_X86_64
1497 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1498 if (vmx_msr_high & (1u<<16))
1502 /* Require Write-Back (WB) memory type for VMCS accesses. */
1503 if (((vmx_msr_high >> 18) & 15) != 6)
1506 vmcs_conf->size = vmx_msr_high & 0x1fff;
1507 vmcs_conf->order = get_order(vmcs_config.size);
1508 vmcs_conf->revision_id = vmx_msr_low;
1510 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1511 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1512 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1513 vmcs_conf->vmexit_ctrl = _vmexit_control;
1514 vmcs_conf->vmentry_ctrl = _vmentry_control;
1519 static struct vmcs *alloc_vmcs_cpu(int cpu)
1521 int node = cpu_to_node(cpu);
1525 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1528 vmcs = page_address(pages);
1529 memset(vmcs, 0, vmcs_config.size);
1530 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1534 static struct vmcs *alloc_vmcs(void)
1536 return alloc_vmcs_cpu(raw_smp_processor_id());
1539 static void free_vmcs(struct vmcs *vmcs)
1541 free_pages((unsigned long)vmcs, vmcs_config.order);
1544 static void free_kvm_area(void)
1548 for_each_possible_cpu(cpu) {
1549 free_vmcs(per_cpu(vmxarea, cpu));
1550 per_cpu(vmxarea, cpu) = NULL;
1554 static __init int alloc_kvm_area(void)
1558 for_each_possible_cpu(cpu) {
1561 vmcs = alloc_vmcs_cpu(cpu);
1567 per_cpu(vmxarea, cpu) = vmcs;
1572 static __init int hardware_setup(void)
1574 if (setup_vmcs_config(&vmcs_config) < 0)
1577 if (boot_cpu_has(X86_FEATURE_NX))
1578 kvm_enable_efer_bits(EFER_NX);
1580 if (!cpu_has_vmx_vpid())
1583 if (!cpu_has_vmx_ept() ||
1584 !cpu_has_vmx_ept_4levels()) {
1586 enable_unrestricted_guest = 0;
1589 if (!cpu_has_vmx_unrestricted_guest())
1590 enable_unrestricted_guest = 0;
1592 if (!cpu_has_vmx_flexpriority())
1593 flexpriority_enabled = 0;
1595 if (!cpu_has_vmx_tpr_shadow())
1596 kvm_x86_ops->update_cr8_intercept = NULL;
1598 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1599 kvm_disable_largepages();
1601 if (!cpu_has_vmx_ple())
1604 return alloc_kvm_area();
1607 static __exit void hardware_unsetup(void)
1612 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1614 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1616 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1617 vmcs_write16(sf->selector, save->selector);
1618 vmcs_writel(sf->base, save->base);
1619 vmcs_write32(sf->limit, save->limit);
1620 vmcs_write32(sf->ar_bytes, save->ar);
1622 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1624 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1628 static void enter_pmode(struct kvm_vcpu *vcpu)
1630 unsigned long flags;
1631 struct vcpu_vmx *vmx = to_vmx(vcpu);
1633 vmx->emulation_required = 1;
1634 vmx->rmode.vm86_active = 0;
1636 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1637 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1638 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1640 flags = vmcs_readl(GUEST_RFLAGS);
1641 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1642 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1643 vmcs_writel(GUEST_RFLAGS, flags);
1645 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1646 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1648 update_exception_bitmap(vcpu);
1650 if (emulate_invalid_guest_state)
1653 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1654 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1655 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1656 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1658 vmcs_write16(GUEST_SS_SELECTOR, 0);
1659 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1661 vmcs_write16(GUEST_CS_SELECTOR,
1662 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1663 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1666 static gva_t rmode_tss_base(struct kvm *kvm)
1668 if (!kvm->arch.tss_addr) {
1669 struct kvm_memslots *slots;
1672 slots = kvm_memslots(kvm);
1673 base_gfn = slots->memslots[0].base_gfn +
1674 kvm->memslots->memslots[0].npages - 3;
1675 return base_gfn << PAGE_SHIFT;
1677 return kvm->arch.tss_addr;
1680 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1682 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1684 save->selector = vmcs_read16(sf->selector);
1685 save->base = vmcs_readl(sf->base);
1686 save->limit = vmcs_read32(sf->limit);
1687 save->ar = vmcs_read32(sf->ar_bytes);
1688 vmcs_write16(sf->selector, save->base >> 4);
1689 vmcs_write32(sf->base, save->base & 0xfffff);
1690 vmcs_write32(sf->limit, 0xffff);
1691 vmcs_write32(sf->ar_bytes, 0xf3);
1694 static void enter_rmode(struct kvm_vcpu *vcpu)
1696 unsigned long flags;
1697 struct vcpu_vmx *vmx = to_vmx(vcpu);
1699 if (enable_unrestricted_guest)
1702 vmx->emulation_required = 1;
1703 vmx->rmode.vm86_active = 1;
1705 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1706 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1708 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1709 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1711 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1712 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1714 flags = vmcs_readl(GUEST_RFLAGS);
1715 vmx->rmode.save_rflags = flags;
1717 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1719 vmcs_writel(GUEST_RFLAGS, flags);
1720 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1721 update_exception_bitmap(vcpu);
1723 if (emulate_invalid_guest_state)
1724 goto continue_rmode;
1726 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1727 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1728 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1730 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1731 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1732 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1733 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1734 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1736 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1737 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1738 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1739 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1742 kvm_mmu_reset_context(vcpu);
1743 init_rmode(vcpu->kvm);
1746 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1748 struct vcpu_vmx *vmx = to_vmx(vcpu);
1749 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1755 * Force kernel_gs_base reloading before EFER changes, as control
1756 * of this msr depends on is_long_mode().
1758 vmx_load_host_state(to_vmx(vcpu));
1759 vcpu->arch.efer = efer;
1760 if (efer & EFER_LMA) {
1761 vmcs_write32(VM_ENTRY_CONTROLS,
1762 vmcs_read32(VM_ENTRY_CONTROLS) |
1763 VM_ENTRY_IA32E_MODE);
1766 vmcs_write32(VM_ENTRY_CONTROLS,
1767 vmcs_read32(VM_ENTRY_CONTROLS) &
1768 ~VM_ENTRY_IA32E_MODE);
1770 msr->data = efer & ~EFER_LME;
1775 #ifdef CONFIG_X86_64
1777 static void enter_lmode(struct kvm_vcpu *vcpu)
1781 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1782 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1783 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1785 vmcs_write32(GUEST_TR_AR_BYTES,
1786 (guest_tr_ar & ~AR_TYPE_MASK)
1787 | AR_TYPE_BUSY_64_TSS);
1789 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1792 static void exit_lmode(struct kvm_vcpu *vcpu)
1794 vmcs_write32(VM_ENTRY_CONTROLS,
1795 vmcs_read32(VM_ENTRY_CONTROLS)
1796 & ~VM_ENTRY_IA32E_MODE);
1797 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1802 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1804 vpid_sync_context(to_vmx(vcpu));
1806 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1808 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1812 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1814 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1816 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1817 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1820 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1822 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1824 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1825 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1828 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1830 if (!test_bit(VCPU_EXREG_PDPTR,
1831 (unsigned long *)&vcpu->arch.regs_dirty))
1834 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1835 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1836 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1837 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1838 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1842 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1844 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1845 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1846 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1847 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1848 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1851 __set_bit(VCPU_EXREG_PDPTR,
1852 (unsigned long *)&vcpu->arch.regs_avail);
1853 __set_bit(VCPU_EXREG_PDPTR,
1854 (unsigned long *)&vcpu->arch.regs_dirty);
1857 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1859 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1861 struct kvm_vcpu *vcpu)
1863 if (!(cr0 & X86_CR0_PG)) {
1864 /* From paging/starting to nonpaging */
1865 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1866 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1867 (CPU_BASED_CR3_LOAD_EXITING |
1868 CPU_BASED_CR3_STORE_EXITING));
1869 vcpu->arch.cr0 = cr0;
1870 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1871 } else if (!is_paging(vcpu)) {
1872 /* From nonpaging to paging */
1873 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1874 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1875 ~(CPU_BASED_CR3_LOAD_EXITING |
1876 CPU_BASED_CR3_STORE_EXITING));
1877 vcpu->arch.cr0 = cr0;
1878 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1881 if (!(cr0 & X86_CR0_WP))
1882 *hw_cr0 &= ~X86_CR0_WP;
1885 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1887 struct vcpu_vmx *vmx = to_vmx(vcpu);
1888 unsigned long hw_cr0;
1890 if (enable_unrestricted_guest)
1891 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1892 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1894 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1896 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1899 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1902 #ifdef CONFIG_X86_64
1903 if (vcpu->arch.efer & EFER_LME) {
1904 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1906 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1912 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1914 if (!vcpu->fpu_active)
1915 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1917 vmcs_writel(CR0_READ_SHADOW, cr0);
1918 vmcs_writel(GUEST_CR0, hw_cr0);
1919 vcpu->arch.cr0 = cr0;
1922 static u64 construct_eptp(unsigned long root_hpa)
1926 /* TODO write the value reading from MSR */
1927 eptp = VMX_EPT_DEFAULT_MT |
1928 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1929 eptp |= (root_hpa & PAGE_MASK);
1934 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1936 unsigned long guest_cr3;
1941 eptp = construct_eptp(cr3);
1942 vmcs_write64(EPT_POINTER, eptp);
1943 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1944 vcpu->kvm->arch.ept_identity_map_addr;
1945 ept_load_pdptrs(vcpu);
1948 vmx_flush_tlb(vcpu);
1949 vmcs_writel(GUEST_CR3, guest_cr3);
1952 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1954 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1955 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1957 vcpu->arch.cr4 = cr4;
1959 if (!is_paging(vcpu)) {
1960 hw_cr4 &= ~X86_CR4_PAE;
1961 hw_cr4 |= X86_CR4_PSE;
1962 } else if (!(cr4 & X86_CR4_PAE)) {
1963 hw_cr4 &= ~X86_CR4_PAE;
1967 vmcs_writel(CR4_READ_SHADOW, cr4);
1968 vmcs_writel(GUEST_CR4, hw_cr4);
1971 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1973 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1975 return vmcs_readl(sf->base);
1978 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1979 struct kvm_segment *var, int seg)
1981 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1984 var->base = vmcs_readl(sf->base);
1985 var->limit = vmcs_read32(sf->limit);
1986 var->selector = vmcs_read16(sf->selector);
1987 ar = vmcs_read32(sf->ar_bytes);
1988 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1990 var->type = ar & 15;
1991 var->s = (ar >> 4) & 1;
1992 var->dpl = (ar >> 5) & 3;
1993 var->present = (ar >> 7) & 1;
1994 var->avl = (ar >> 12) & 1;
1995 var->l = (ar >> 13) & 1;
1996 var->db = (ar >> 14) & 1;
1997 var->g = (ar >> 15) & 1;
1998 var->unusable = (ar >> 16) & 1;
2001 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2003 if (!is_protmode(vcpu))
2006 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2009 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2012 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2019 ar = var->type & 15;
2020 ar |= (var->s & 1) << 4;
2021 ar |= (var->dpl & 3) << 5;
2022 ar |= (var->present & 1) << 7;
2023 ar |= (var->avl & 1) << 12;
2024 ar |= (var->l & 1) << 13;
2025 ar |= (var->db & 1) << 14;
2026 ar |= (var->g & 1) << 15;
2028 if (ar == 0) /* a 0 value means unusable */
2029 ar = AR_UNUSABLE_MASK;
2034 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2035 struct kvm_segment *var, int seg)
2037 struct vcpu_vmx *vmx = to_vmx(vcpu);
2038 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2041 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2042 vmx->rmode.tr.selector = var->selector;
2043 vmx->rmode.tr.base = var->base;
2044 vmx->rmode.tr.limit = var->limit;
2045 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2048 vmcs_writel(sf->base, var->base);
2049 vmcs_write32(sf->limit, var->limit);
2050 vmcs_write16(sf->selector, var->selector);
2051 if (vmx->rmode.vm86_active && var->s) {
2053 * Hack real-mode segments into vm86 compatibility.
2055 if (var->base == 0xffff0000 && var->selector == 0xf000)
2056 vmcs_writel(sf->base, 0xf0000);
2059 ar = vmx_segment_access_rights(var);
2062 * Fix the "Accessed" bit in AR field of segment registers for older
2064 * IA32 arch specifies that at the time of processor reset the
2065 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2066 * is setting it to 0 in the usedland code. This causes invalid guest
2067 * state vmexit when "unrestricted guest" mode is turned on.
2068 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2069 * tree. Newer qemu binaries with that qemu fix would not need this
2072 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2073 ar |= 0x1; /* Accessed */
2075 vmcs_write32(sf->ar_bytes, ar);
2078 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2080 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2082 *db = (ar >> 14) & 1;
2083 *l = (ar >> 13) & 1;
2086 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2088 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2089 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2092 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2094 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2095 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2098 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2100 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2101 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2104 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2106 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2107 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2110 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2112 struct kvm_segment var;
2115 vmx_get_segment(vcpu, &var, seg);
2116 ar = vmx_segment_access_rights(&var);
2118 if (var.base != (var.selector << 4))
2120 if (var.limit != 0xffff)
2128 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2130 struct kvm_segment cs;
2131 unsigned int cs_rpl;
2133 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2134 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2138 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2142 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2143 if (cs.dpl > cs_rpl)
2146 if (cs.dpl != cs_rpl)
2152 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2156 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2158 struct kvm_segment ss;
2159 unsigned int ss_rpl;
2161 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2162 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2166 if (ss.type != 3 && ss.type != 7)
2170 if (ss.dpl != ss_rpl) /* DPL != RPL */
2178 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2180 struct kvm_segment var;
2183 vmx_get_segment(vcpu, &var, seg);
2184 rpl = var.selector & SELECTOR_RPL_MASK;
2192 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2193 if (var.dpl < rpl) /* DPL < RPL */
2197 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2203 static bool tr_valid(struct kvm_vcpu *vcpu)
2205 struct kvm_segment tr;
2207 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2211 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2213 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2221 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2223 struct kvm_segment ldtr;
2225 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2229 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2239 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2241 struct kvm_segment cs, ss;
2243 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2244 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2246 return ((cs.selector & SELECTOR_RPL_MASK) ==
2247 (ss.selector & SELECTOR_RPL_MASK));
2251 * Check if guest state is valid. Returns true if valid, false if
2253 * We assume that registers are always usable
2255 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2257 /* real mode guest state checks */
2258 if (!is_protmode(vcpu)) {
2259 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2261 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2263 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2265 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2267 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2269 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2272 /* protected mode guest state checks */
2273 if (!cs_ss_rpl_check(vcpu))
2275 if (!code_segment_valid(vcpu))
2277 if (!stack_segment_valid(vcpu))
2279 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2281 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2283 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2285 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2287 if (!tr_valid(vcpu))
2289 if (!ldtr_valid(vcpu))
2293 * - Add checks on RIP
2294 * - Add checks on RFLAGS
2300 static int init_rmode_tss(struct kvm *kvm)
2302 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2307 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2310 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2311 r = kvm_write_guest_page(kvm, fn++, &data,
2312 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2315 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2318 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2322 r = kvm_write_guest_page(kvm, fn, &data,
2323 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2333 static int init_rmode_identity_map(struct kvm *kvm)
2336 pfn_t identity_map_pfn;
2341 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2342 printk(KERN_ERR "EPT: identity-mapping pagetable "
2343 "haven't been allocated!\n");
2346 if (likely(kvm->arch.ept_identity_pagetable_done))
2349 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2350 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2353 /* Set up identity-mapping pagetable for EPT in real mode */
2354 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2355 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2356 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2357 r = kvm_write_guest_page(kvm, identity_map_pfn,
2358 &tmp, i * sizeof(tmp), sizeof(tmp));
2362 kvm->arch.ept_identity_pagetable_done = true;
2368 static void seg_setup(int seg)
2370 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2373 vmcs_write16(sf->selector, 0);
2374 vmcs_writel(sf->base, 0);
2375 vmcs_write32(sf->limit, 0xffff);
2376 if (enable_unrestricted_guest) {
2378 if (seg == VCPU_SREG_CS)
2379 ar |= 0x08; /* code segment */
2383 vmcs_write32(sf->ar_bytes, ar);
2386 static int alloc_apic_access_page(struct kvm *kvm)
2388 struct kvm_userspace_memory_region kvm_userspace_mem;
2391 mutex_lock(&kvm->slots_lock);
2392 if (kvm->arch.apic_access_page)
2394 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2395 kvm_userspace_mem.flags = 0;
2396 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2397 kvm_userspace_mem.memory_size = PAGE_SIZE;
2398 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2402 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2404 mutex_unlock(&kvm->slots_lock);
2408 static int alloc_identity_pagetable(struct kvm *kvm)
2410 struct kvm_userspace_memory_region kvm_userspace_mem;
2413 mutex_lock(&kvm->slots_lock);
2414 if (kvm->arch.ept_identity_pagetable)
2416 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2417 kvm_userspace_mem.flags = 0;
2418 kvm_userspace_mem.guest_phys_addr =
2419 kvm->arch.ept_identity_map_addr;
2420 kvm_userspace_mem.memory_size = PAGE_SIZE;
2421 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2425 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2426 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2428 mutex_unlock(&kvm->slots_lock);
2432 static void allocate_vpid(struct vcpu_vmx *vmx)
2439 spin_lock(&vmx_vpid_lock);
2440 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2441 if (vpid < VMX_NR_VPIDS) {
2443 __set_bit(vpid, vmx_vpid_bitmap);
2445 spin_unlock(&vmx_vpid_lock);
2448 static void free_vpid(struct vcpu_vmx *vmx)
2452 spin_lock(&vmx_vpid_lock);
2454 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2455 spin_unlock(&vmx_vpid_lock);
2458 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2460 int f = sizeof(unsigned long);
2462 if (!cpu_has_vmx_msr_bitmap())
2466 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2467 * have the write-low and read-high bitmap offsets the wrong way round.
2468 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2470 if (msr <= 0x1fff) {
2471 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2472 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2473 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2475 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2476 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2480 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2483 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2484 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2488 * Sets up the vmcs for emulated real mode.
2490 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2492 u32 host_sysenter_cs, msr_low, msr_high;
2498 unsigned long kvm_vmx_return;
2502 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2503 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2505 if (cpu_has_vmx_msr_bitmap())
2506 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2508 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2511 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2512 vmcs_config.pin_based_exec_ctrl);
2514 exec_control = vmcs_config.cpu_based_exec_ctrl;
2515 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2516 exec_control &= ~CPU_BASED_TPR_SHADOW;
2517 #ifdef CONFIG_X86_64
2518 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2519 CPU_BASED_CR8_LOAD_EXITING;
2523 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2524 CPU_BASED_CR3_LOAD_EXITING |
2525 CPU_BASED_INVLPG_EXITING;
2526 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2528 if (cpu_has_secondary_exec_ctrls()) {
2529 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2530 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2532 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2534 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2536 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2537 enable_unrestricted_guest = 0;
2539 if (!enable_unrestricted_guest)
2540 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2542 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2543 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2547 vmcs_write32(PLE_GAP, ple_gap);
2548 vmcs_write32(PLE_WINDOW, ple_window);
2551 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2552 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2553 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2555 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2556 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2557 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2559 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2560 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2561 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2562 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2563 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
2564 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2565 #ifdef CONFIG_X86_64
2566 rdmsrl(MSR_FS_BASE, a);
2567 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2568 rdmsrl(MSR_GS_BASE, a);
2569 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2571 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2572 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2575 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2577 native_store_idt(&dt);
2578 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2580 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2581 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2582 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2583 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2584 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2585 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2586 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2588 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2589 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2590 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2591 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2592 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2593 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2595 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2596 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2597 host_pat = msr_low | ((u64) msr_high << 32);
2598 vmcs_write64(HOST_IA32_PAT, host_pat);
2600 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2601 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2602 host_pat = msr_low | ((u64) msr_high << 32);
2603 /* Write the default value follow host pat */
2604 vmcs_write64(GUEST_IA32_PAT, host_pat);
2605 /* Keep arch.pat sync with GUEST_IA32_PAT */
2606 vmx->vcpu.arch.pat = host_pat;
2609 for (i = 0; i < NR_VMX_MSR; ++i) {
2610 u32 index = vmx_msr_index[i];
2611 u32 data_low, data_high;
2614 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2616 if (wrmsr_safe(index, data_low, data_high) < 0)
2618 vmx->guest_msrs[j].index = i;
2619 vmx->guest_msrs[j].data = 0;
2620 vmx->guest_msrs[j].mask = -1ull;
2624 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2626 /* 22.2.1, 20.8.1 */
2627 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2629 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2630 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2632 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2633 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2635 kvm_write_tsc(&vmx->vcpu, 0);
2640 static int init_rmode(struct kvm *kvm)
2644 idx = srcu_read_lock(&kvm->srcu);
2645 if (!init_rmode_tss(kvm))
2647 if (!init_rmode_identity_map(kvm))
2652 srcu_read_unlock(&kvm->srcu, idx);
2656 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2658 struct vcpu_vmx *vmx = to_vmx(vcpu);
2662 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2663 if (!init_rmode(vmx->vcpu.kvm)) {
2668 vmx->rmode.vm86_active = 0;
2670 vmx->soft_vnmi_blocked = 0;
2672 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2673 kvm_set_cr8(&vmx->vcpu, 0);
2674 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2675 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2676 msr |= MSR_IA32_APICBASE_BSP;
2677 kvm_set_apic_base(&vmx->vcpu, msr);
2679 ret = fx_init(&vmx->vcpu);
2683 seg_setup(VCPU_SREG_CS);
2685 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2686 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2688 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2689 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2690 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2692 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2693 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2696 seg_setup(VCPU_SREG_DS);
2697 seg_setup(VCPU_SREG_ES);
2698 seg_setup(VCPU_SREG_FS);
2699 seg_setup(VCPU_SREG_GS);
2700 seg_setup(VCPU_SREG_SS);
2702 vmcs_write16(GUEST_TR_SELECTOR, 0);
2703 vmcs_writel(GUEST_TR_BASE, 0);
2704 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2705 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2707 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2708 vmcs_writel(GUEST_LDTR_BASE, 0);
2709 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2710 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2712 vmcs_write32(GUEST_SYSENTER_CS, 0);
2713 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2714 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2716 vmcs_writel(GUEST_RFLAGS, 0x02);
2717 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2718 kvm_rip_write(vcpu, 0xfff0);
2720 kvm_rip_write(vcpu, 0);
2721 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2723 vmcs_writel(GUEST_DR7, 0x400);
2725 vmcs_writel(GUEST_GDTR_BASE, 0);
2726 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2728 vmcs_writel(GUEST_IDTR_BASE, 0);
2729 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2731 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2732 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2733 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2735 /* Special registers */
2736 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2740 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2742 if (cpu_has_vmx_tpr_shadow()) {
2743 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2744 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2745 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2746 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2747 vmcs_write32(TPR_THRESHOLD, 0);
2750 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2751 vmcs_write64(APIC_ACCESS_ADDR,
2752 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2755 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2757 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2758 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2759 vmx_set_cr4(&vmx->vcpu, 0);
2760 vmx_set_efer(&vmx->vcpu, 0);
2761 vmx_fpu_activate(&vmx->vcpu);
2762 update_exception_bitmap(&vmx->vcpu);
2764 vpid_sync_context(vmx);
2768 /* HACK: Don't enable emulation on guest boot/reset */
2769 vmx->emulation_required = 0;
2775 static void enable_irq_window(struct kvm_vcpu *vcpu)
2777 u32 cpu_based_vm_exec_control;
2779 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2780 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2781 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2784 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2786 u32 cpu_based_vm_exec_control;
2788 if (!cpu_has_virtual_nmis()) {
2789 enable_irq_window(vcpu);
2793 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2794 enable_irq_window(vcpu);
2797 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2798 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2799 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2802 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2804 struct vcpu_vmx *vmx = to_vmx(vcpu);
2806 int irq = vcpu->arch.interrupt.nr;
2808 trace_kvm_inj_virq(irq);
2810 ++vcpu->stat.irq_injections;
2811 if (vmx->rmode.vm86_active) {
2812 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2813 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2816 intr = irq | INTR_INFO_VALID_MASK;
2817 if (vcpu->arch.interrupt.soft) {
2818 intr |= INTR_TYPE_SOFT_INTR;
2819 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2820 vmx->vcpu.arch.event_exit_inst_len);
2822 intr |= INTR_TYPE_EXT_INTR;
2823 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2826 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2828 struct vcpu_vmx *vmx = to_vmx(vcpu);
2830 if (!cpu_has_virtual_nmis()) {
2832 * Tracking the NMI-blocked state in software is built upon
2833 * finding the next open IRQ window. This, in turn, depends on
2834 * well-behaving guests: They have to keep IRQs disabled at
2835 * least as long as the NMI handler runs. Otherwise we may
2836 * cause NMI nesting, maybe breaking the guest. But as this is
2837 * highly unlikely, we can live with the residual risk.
2839 vmx->soft_vnmi_blocked = 1;
2840 vmx->vnmi_blocked_time = 0;
2843 ++vcpu->stat.nmi_injections;
2844 if (vmx->rmode.vm86_active) {
2845 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2846 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2849 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2850 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2853 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2855 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2858 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2859 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2860 | GUEST_INTR_STATE_NMI));
2863 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2865 if (!cpu_has_virtual_nmis())
2866 return to_vmx(vcpu)->soft_vnmi_blocked;
2867 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2870 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2872 struct vcpu_vmx *vmx = to_vmx(vcpu);
2874 if (!cpu_has_virtual_nmis()) {
2875 if (vmx->soft_vnmi_blocked != masked) {
2876 vmx->soft_vnmi_blocked = masked;
2877 vmx->vnmi_blocked_time = 0;
2881 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2882 GUEST_INTR_STATE_NMI);
2884 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2885 GUEST_INTR_STATE_NMI);
2889 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2891 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2892 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2893 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2896 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2899 struct kvm_userspace_memory_region tss_mem = {
2900 .slot = TSS_PRIVATE_MEMSLOT,
2901 .guest_phys_addr = addr,
2902 .memory_size = PAGE_SIZE * 3,
2906 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2909 kvm->arch.tss_addr = addr;
2913 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2914 int vec, u32 err_code)
2917 * Instruction with address size override prefix opcode 0x67
2918 * Cause the #SS fault with 0 error code in VM86 mode.
2920 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2921 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2924 * Forward all other exceptions that are valid in real mode.
2925 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2926 * the required debugging infrastructure rework.
2930 if (vcpu->guest_debug &
2931 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2933 kvm_queue_exception(vcpu, vec);
2937 * Update instruction length as we may reinject the exception
2938 * from user space while in guest debugging mode.
2940 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2941 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2942 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2953 kvm_queue_exception(vcpu, vec);
2960 * Trigger machine check on the host. We assume all the MSRs are already set up
2961 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2962 * We pass a fake environment to the machine check handler because we want
2963 * the guest to be always treated like user space, no matter what context
2964 * it used internally.
2966 static void kvm_machine_check(void)
2968 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2969 struct pt_regs regs = {
2970 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2971 .flags = X86_EFLAGS_IF,
2974 do_machine_check(®s, 0);
2978 static int handle_machine_check(struct kvm_vcpu *vcpu)
2980 /* already handled by vcpu_run */
2984 static int handle_exception(struct kvm_vcpu *vcpu)
2986 struct vcpu_vmx *vmx = to_vmx(vcpu);
2987 struct kvm_run *kvm_run = vcpu->run;
2988 u32 intr_info, ex_no, error_code;
2989 unsigned long cr2, rip, dr6;
2991 enum emulation_result er;
2993 vect_info = vmx->idt_vectoring_info;
2994 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2996 if (is_machine_check(intr_info))
2997 return handle_machine_check(vcpu);
2999 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3000 !is_page_fault(intr_info)) {
3001 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3002 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3003 vcpu->run->internal.ndata = 2;
3004 vcpu->run->internal.data[0] = vect_info;
3005 vcpu->run->internal.data[1] = intr_info;
3009 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3010 return 1; /* already handled by vmx_vcpu_run() */
3012 if (is_no_device(intr_info)) {
3013 vmx_fpu_activate(vcpu);
3017 if (is_invalid_opcode(intr_info)) {
3018 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3019 if (er != EMULATE_DONE)
3020 kvm_queue_exception(vcpu, UD_VECTOR);
3025 rip = kvm_rip_read(vcpu);
3026 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3027 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3028 if (is_page_fault(intr_info)) {
3029 /* EPT won't cause page fault directly */
3032 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3033 trace_kvm_page_fault(cr2, error_code);
3035 if (kvm_event_needs_reinjection(vcpu))
3036 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3037 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3040 if (vmx->rmode.vm86_active &&
3041 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3043 if (vcpu->arch.halt_request) {
3044 vcpu->arch.halt_request = 0;
3045 return kvm_emulate_halt(vcpu);
3050 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3053 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3054 if (!(vcpu->guest_debug &
3055 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3056 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3057 kvm_queue_exception(vcpu, DB_VECTOR);
3060 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3061 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3065 * Update instruction length as we may reinject #BP from
3066 * user space while in guest debugging mode. Reading it for
3067 * #DB as well causes no harm, it is not used in that case.
3069 vmx->vcpu.arch.event_exit_inst_len =
3070 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3071 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3072 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3073 kvm_run->debug.arch.exception = ex_no;
3076 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3077 kvm_run->ex.exception = ex_no;
3078 kvm_run->ex.error_code = error_code;
3084 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3086 ++vcpu->stat.irq_exits;
3090 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3092 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3096 static int handle_io(struct kvm_vcpu *vcpu)
3098 unsigned long exit_qualification;
3099 int size, in, string;
3102 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3103 string = (exit_qualification & 16) != 0;
3104 in = (exit_qualification & 8) != 0;
3106 ++vcpu->stat.io_exits;
3109 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3111 port = exit_qualification >> 16;
3112 size = (exit_qualification & 7) + 1;
3113 skip_emulated_instruction(vcpu);
3115 return kvm_fast_pio_out(vcpu, size, port);
3119 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3122 * Patch in the VMCALL instruction:
3124 hypercall[0] = 0x0f;
3125 hypercall[1] = 0x01;
3126 hypercall[2] = 0xc1;
3129 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3132 kvm_inject_gp(vcpu, 0);
3134 skip_emulated_instruction(vcpu);
3137 static int handle_cr(struct kvm_vcpu *vcpu)
3139 unsigned long exit_qualification, val;
3144 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3145 cr = exit_qualification & 15;
3146 reg = (exit_qualification >> 8) & 15;
3147 switch ((exit_qualification >> 4) & 3) {
3148 case 0: /* mov to cr */
3149 val = kvm_register_read(vcpu, reg);
3150 trace_kvm_cr_write(cr, val);
3153 err = kvm_set_cr0(vcpu, val);
3154 complete_insn_gp(vcpu, err);
3157 err = kvm_set_cr3(vcpu, val);
3158 complete_insn_gp(vcpu, err);
3161 err = kvm_set_cr4(vcpu, val);
3162 complete_insn_gp(vcpu, err);
3165 u8 cr8_prev = kvm_get_cr8(vcpu);
3166 u8 cr8 = kvm_register_read(vcpu, reg);
3167 kvm_set_cr8(vcpu, cr8);
3168 skip_emulated_instruction(vcpu);
3169 if (irqchip_in_kernel(vcpu->kvm))
3171 if (cr8_prev <= cr8)
3173 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3179 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3180 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3181 skip_emulated_instruction(vcpu);
3182 vmx_fpu_activate(vcpu);
3184 case 1: /*mov from cr*/
3187 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3188 trace_kvm_cr_read(cr, vcpu->arch.cr3);
3189 skip_emulated_instruction(vcpu);
3192 val = kvm_get_cr8(vcpu);
3193 kvm_register_write(vcpu, reg, val);
3194 trace_kvm_cr_read(cr, val);
3195 skip_emulated_instruction(vcpu);
3200 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3201 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3202 kvm_lmsw(vcpu, val);
3204 skip_emulated_instruction(vcpu);
3209 vcpu->run->exit_reason = 0;
3210 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3211 (int)(exit_qualification >> 4) & 3, cr);
3215 static int handle_dr(struct kvm_vcpu *vcpu)
3217 unsigned long exit_qualification;
3220 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3221 if (!kvm_require_cpl(vcpu, 0))
3223 dr = vmcs_readl(GUEST_DR7);
3226 * As the vm-exit takes precedence over the debug trap, we
3227 * need to emulate the latter, either for the host or the
3228 * guest debugging itself.
3230 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3231 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3232 vcpu->run->debug.arch.dr7 = dr;
3233 vcpu->run->debug.arch.pc =
3234 vmcs_readl(GUEST_CS_BASE) +
3235 vmcs_readl(GUEST_RIP);
3236 vcpu->run->debug.arch.exception = DB_VECTOR;
3237 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3240 vcpu->arch.dr7 &= ~DR7_GD;
3241 vcpu->arch.dr6 |= DR6_BD;
3242 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3243 kvm_queue_exception(vcpu, DB_VECTOR);
3248 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3249 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3250 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3251 if (exit_qualification & TYPE_MOV_FROM_DR) {
3253 if (!kvm_get_dr(vcpu, dr, &val))
3254 kvm_register_write(vcpu, reg, val);
3256 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3257 skip_emulated_instruction(vcpu);
3261 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3263 vmcs_writel(GUEST_DR7, val);
3266 static int handle_cpuid(struct kvm_vcpu *vcpu)
3268 kvm_emulate_cpuid(vcpu);
3272 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3274 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3277 if (vmx_get_msr(vcpu, ecx, &data)) {
3278 trace_kvm_msr_read_ex(ecx);
3279 kvm_inject_gp(vcpu, 0);
3283 trace_kvm_msr_read(ecx, data);
3285 /* FIXME: handling of bits 32:63 of rax, rdx */
3286 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3287 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3288 skip_emulated_instruction(vcpu);
3292 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3294 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3295 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3296 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3298 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3299 trace_kvm_msr_write_ex(ecx, data);
3300 kvm_inject_gp(vcpu, 0);
3304 trace_kvm_msr_write(ecx, data);
3305 skip_emulated_instruction(vcpu);
3309 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3311 kvm_make_request(KVM_REQ_EVENT, vcpu);
3315 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3317 u32 cpu_based_vm_exec_control;
3319 /* clear pending irq */
3320 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3321 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3322 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3324 kvm_make_request(KVM_REQ_EVENT, vcpu);
3326 ++vcpu->stat.irq_window_exits;
3329 * If the user space waits to inject interrupts, exit as soon as
3332 if (!irqchip_in_kernel(vcpu->kvm) &&
3333 vcpu->run->request_interrupt_window &&
3334 !kvm_cpu_has_interrupt(vcpu)) {
3335 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3341 static int handle_halt(struct kvm_vcpu *vcpu)
3343 skip_emulated_instruction(vcpu);
3344 return kvm_emulate_halt(vcpu);
3347 static int handle_vmcall(struct kvm_vcpu *vcpu)
3349 skip_emulated_instruction(vcpu);
3350 kvm_emulate_hypercall(vcpu);
3354 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3356 kvm_queue_exception(vcpu, UD_VECTOR);
3360 static int handle_invd(struct kvm_vcpu *vcpu)
3362 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3365 static int handle_invlpg(struct kvm_vcpu *vcpu)
3367 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3369 kvm_mmu_invlpg(vcpu, exit_qualification);
3370 skip_emulated_instruction(vcpu);
3374 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3376 skip_emulated_instruction(vcpu);
3377 kvm_emulate_wbinvd(vcpu);
3381 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3383 u64 new_bv = kvm_read_edx_eax(vcpu);
3384 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3386 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3387 skip_emulated_instruction(vcpu);
3391 static int handle_apic_access(struct kvm_vcpu *vcpu)
3393 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3396 static int handle_task_switch(struct kvm_vcpu *vcpu)
3398 struct vcpu_vmx *vmx = to_vmx(vcpu);
3399 unsigned long exit_qualification;
3400 bool has_error_code = false;
3403 int reason, type, idt_v;
3405 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3406 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3408 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3410 reason = (u32)exit_qualification >> 30;
3411 if (reason == TASK_SWITCH_GATE && idt_v) {
3413 case INTR_TYPE_NMI_INTR:
3414 vcpu->arch.nmi_injected = false;
3415 if (cpu_has_virtual_nmis())
3416 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3417 GUEST_INTR_STATE_NMI);
3419 case INTR_TYPE_EXT_INTR:
3420 case INTR_TYPE_SOFT_INTR:
3421 kvm_clear_interrupt_queue(vcpu);
3423 case INTR_TYPE_HARD_EXCEPTION:
3424 if (vmx->idt_vectoring_info &
3425 VECTORING_INFO_DELIVER_CODE_MASK) {
3426 has_error_code = true;
3428 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3431 case INTR_TYPE_SOFT_EXCEPTION:
3432 kvm_clear_exception_queue(vcpu);
3438 tss_selector = exit_qualification;
3440 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3441 type != INTR_TYPE_EXT_INTR &&
3442 type != INTR_TYPE_NMI_INTR))
3443 skip_emulated_instruction(vcpu);
3445 if (kvm_task_switch(vcpu, tss_selector, reason,
3446 has_error_code, error_code) == EMULATE_FAIL) {
3447 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3448 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3449 vcpu->run->internal.ndata = 0;
3453 /* clear all local breakpoint enable flags */
3454 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3457 * TODO: What about debug traps on tss switch?
3458 * Are we supposed to inject them and update dr6?
3464 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3466 unsigned long exit_qualification;
3470 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3472 if (exit_qualification & (1 << 6)) {
3473 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3477 gla_validity = (exit_qualification >> 7) & 0x3;
3478 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3479 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3480 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3481 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3482 vmcs_readl(GUEST_LINEAR_ADDRESS));
3483 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3484 (long unsigned int)exit_qualification);
3485 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3486 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3490 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3491 trace_kvm_page_fault(gpa, exit_qualification);
3492 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3);
3495 static u64 ept_rsvd_mask(u64 spte, int level)
3500 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3501 mask |= (1ULL << i);
3504 /* bits 7:3 reserved */
3506 else if (level == 2) {
3507 if (spte & (1ULL << 7))
3508 /* 2MB ref, bits 20:12 reserved */
3511 /* bits 6:3 reserved */
3518 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3521 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3523 /* 010b (write-only) */
3524 WARN_ON((spte & 0x7) == 0x2);
3526 /* 110b (write/execute) */
3527 WARN_ON((spte & 0x7) == 0x6);
3529 /* 100b (execute-only) and value not supported by logical processor */
3530 if (!cpu_has_vmx_ept_execute_only())
3531 WARN_ON((spte & 0x7) == 0x4);
3535 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3537 if (rsvd_bits != 0) {
3538 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3539 __func__, rsvd_bits);
3543 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3544 u64 ept_mem_type = (spte & 0x38) >> 3;
3546 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3547 ept_mem_type == 7) {
3548 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3549 __func__, ept_mem_type);
3556 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3562 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3564 printk(KERN_ERR "EPT: Misconfiguration.\n");
3565 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3567 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3569 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3570 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3572 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3573 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3578 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3580 u32 cpu_based_vm_exec_control;
3582 /* clear pending NMI */
3583 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3584 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3585 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3586 ++vcpu->stat.nmi_window_exits;
3587 kvm_make_request(KVM_REQ_EVENT, vcpu);
3592 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3594 struct vcpu_vmx *vmx = to_vmx(vcpu);
3595 enum emulation_result err = EMULATE_DONE;
3598 bool intr_window_requested;
3600 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3601 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3603 while (!guest_state_valid(vcpu)) {
3604 if (intr_window_requested
3605 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3606 return handle_interrupt_window(&vmx->vcpu);
3608 err = emulate_instruction(vcpu, 0, 0, 0);
3610 if (err == EMULATE_DO_MMIO) {
3615 if (err != EMULATE_DONE)
3618 if (signal_pending(current))
3624 vmx->emulation_required = 0;
3630 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3631 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3633 static int handle_pause(struct kvm_vcpu *vcpu)
3635 skip_emulated_instruction(vcpu);
3636 kvm_vcpu_on_spin(vcpu);
3641 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3643 kvm_queue_exception(vcpu, UD_VECTOR);
3648 * The exit handlers return 1 if the exit was handled fully and guest execution
3649 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3650 * to be done to userspace and return 0.
3652 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3653 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3654 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3655 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3656 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3657 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3658 [EXIT_REASON_CR_ACCESS] = handle_cr,
3659 [EXIT_REASON_DR_ACCESS] = handle_dr,
3660 [EXIT_REASON_CPUID] = handle_cpuid,
3661 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3662 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3663 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3664 [EXIT_REASON_HLT] = handle_halt,
3665 [EXIT_REASON_INVD] = handle_invd,
3666 [EXIT_REASON_INVLPG] = handle_invlpg,
3667 [EXIT_REASON_VMCALL] = handle_vmcall,
3668 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3669 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3670 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3671 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3672 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3673 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3674 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3675 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3676 [EXIT_REASON_VMON] = handle_vmx_insn,
3677 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3678 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3679 [EXIT_REASON_WBINVD] = handle_wbinvd,
3680 [EXIT_REASON_XSETBV] = handle_xsetbv,
3681 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3682 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3683 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3684 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3685 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3686 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3687 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3690 static const int kvm_vmx_max_exit_handlers =
3691 ARRAY_SIZE(kvm_vmx_exit_handlers);
3694 * The guest has exited. See if we can fix it or if we need userspace
3697 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3699 struct vcpu_vmx *vmx = to_vmx(vcpu);
3700 u32 exit_reason = vmx->exit_reason;
3701 u32 vectoring_info = vmx->idt_vectoring_info;
3703 trace_kvm_exit(exit_reason, vcpu);
3705 /* If guest state is invalid, start emulating */
3706 if (vmx->emulation_required && emulate_invalid_guest_state)
3707 return handle_invalid_guest_state(vcpu);
3709 /* Access CR3 don't cause VMExit in paging mode, so we need
3710 * to sync with guest real CR3. */
3711 if (enable_ept && is_paging(vcpu))
3712 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3714 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3715 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3716 vcpu->run->fail_entry.hardware_entry_failure_reason
3721 if (unlikely(vmx->fail)) {
3722 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3723 vcpu->run->fail_entry.hardware_entry_failure_reason
3724 = vmcs_read32(VM_INSTRUCTION_ERROR);
3728 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3729 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3730 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3731 exit_reason != EXIT_REASON_TASK_SWITCH))
3732 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3733 "(0x%x) and exit reason is 0x%x\n",
3734 __func__, vectoring_info, exit_reason);
3736 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3737 if (vmx_interrupt_allowed(vcpu)) {
3738 vmx->soft_vnmi_blocked = 0;
3739 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3740 vcpu->arch.nmi_pending) {
3742 * This CPU don't support us in finding the end of an
3743 * NMI-blocked window if the guest runs with IRQs
3744 * disabled. So we pull the trigger after 1 s of
3745 * futile waiting, but inform the user about this.
3747 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3748 "state on VCPU %d after 1 s timeout\n",
3749 __func__, vcpu->vcpu_id);
3750 vmx->soft_vnmi_blocked = 0;
3754 if (exit_reason < kvm_vmx_max_exit_handlers
3755 && kvm_vmx_exit_handlers[exit_reason])
3756 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3758 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3759 vcpu->run->hw.hardware_exit_reason = exit_reason;
3764 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3766 if (irr == -1 || tpr < irr) {
3767 vmcs_write32(TPR_THRESHOLD, 0);
3771 vmcs_write32(TPR_THRESHOLD, irr);
3774 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3776 u32 exit_intr_info = vmx->exit_intr_info;
3778 /* Handle machine checks before interrupts are enabled */
3779 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3780 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3781 && is_machine_check(exit_intr_info)))
3782 kvm_machine_check();
3784 /* We need to handle NMIs before interrupts are enabled */
3785 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3786 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3787 kvm_before_handle_nmi(&vmx->vcpu);
3789 kvm_after_handle_nmi(&vmx->vcpu);
3793 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3795 u32 exit_intr_info = vmx->exit_intr_info;
3798 bool idtv_info_valid;
3800 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3802 if (cpu_has_virtual_nmis()) {
3803 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3804 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3806 * SDM 3: 27.7.1.2 (September 2008)
3807 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3808 * a guest IRET fault.
3809 * SDM 3: 23.2.2 (September 2008)
3810 * Bit 12 is undefined in any of the following cases:
3811 * If the VM exit sets the valid bit in the IDT-vectoring
3812 * information field.
3813 * If the VM exit is due to a double fault.
3815 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3816 vector != DF_VECTOR && !idtv_info_valid)
3817 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3818 GUEST_INTR_STATE_NMI);
3819 } else if (unlikely(vmx->soft_vnmi_blocked))
3820 vmx->vnmi_blocked_time +=
3821 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3824 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3825 u32 idt_vectoring_info,
3826 int instr_len_field,
3827 int error_code_field)
3831 bool idtv_info_valid;
3833 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3835 vmx->vcpu.arch.nmi_injected = false;
3836 kvm_clear_exception_queue(&vmx->vcpu);
3837 kvm_clear_interrupt_queue(&vmx->vcpu);
3839 if (!idtv_info_valid)
3842 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3844 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3845 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3848 case INTR_TYPE_NMI_INTR:
3849 vmx->vcpu.arch.nmi_injected = true;
3851 * SDM 3: 27.7.1.2 (September 2008)
3852 * Clear bit "block by NMI" before VM entry if a NMI
3855 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3856 GUEST_INTR_STATE_NMI);
3858 case INTR_TYPE_SOFT_EXCEPTION:
3859 vmx->vcpu.arch.event_exit_inst_len =
3860 vmcs_read32(instr_len_field);
3862 case INTR_TYPE_HARD_EXCEPTION:
3863 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3864 u32 err = vmcs_read32(error_code_field);
3865 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3867 kvm_queue_exception(&vmx->vcpu, vector);
3869 case INTR_TYPE_SOFT_INTR:
3870 vmx->vcpu.arch.event_exit_inst_len =
3871 vmcs_read32(instr_len_field);
3873 case INTR_TYPE_EXT_INTR:
3874 kvm_queue_interrupt(&vmx->vcpu, vector,
3875 type == INTR_TYPE_SOFT_INTR);
3882 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3884 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3885 VM_EXIT_INSTRUCTION_LEN,
3886 IDT_VECTORING_ERROR_CODE);
3889 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3891 __vmx_complete_interrupts(to_vmx(vcpu),
3892 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3893 VM_ENTRY_INSTRUCTION_LEN,
3894 VM_ENTRY_EXCEPTION_ERROR_CODE);
3896 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3899 #ifdef CONFIG_X86_64
3908 * We put this into a separate noinline function to prevent the compiler
3909 * from duplicating the code. This is needed because this code
3910 * uses non local labels that cannot be duplicated.
3911 * Do not put any flow control into this function.
3912 * Better would be to put this whole monstrosity into a .S file.
3914 static void noinline do_vmx_vcpu_run(struct kvm_vcpu *vcpu)
3916 struct vcpu_vmx *vmx = to_vmx(vcpu);
3918 /* Store host registers */
3919 "push %%"R"dx; push %%"R"bp;"
3921 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3923 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3924 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3926 /* Reload cr2 if changed */
3927 "mov %c[cr2](%0), %%"R"ax \n\t"
3928 "mov %%cr2, %%"R"dx \n\t"
3929 "cmp %%"R"ax, %%"R"dx \n\t"
3931 "mov %%"R"ax, %%cr2 \n\t"
3933 /* Check if vmlaunch of vmresume is needed */
3934 "cmpl $0, %c[launched](%0) \n\t"
3935 /* Load guest registers. Don't clobber flags. */
3936 "mov %c[rax](%0), %%"R"ax \n\t"
3937 "mov %c[rbx](%0), %%"R"bx \n\t"
3938 "mov %c[rdx](%0), %%"R"dx \n\t"
3939 "mov %c[rsi](%0), %%"R"si \n\t"
3940 "mov %c[rdi](%0), %%"R"di \n\t"
3941 "mov %c[rbp](%0), %%"R"bp \n\t"
3942 #ifdef CONFIG_X86_64
3943 "mov %c[r8](%0), %%r8 \n\t"
3944 "mov %c[r9](%0), %%r9 \n\t"
3945 "mov %c[r10](%0), %%r10 \n\t"
3946 "mov %c[r11](%0), %%r11 \n\t"
3947 "mov %c[r12](%0), %%r12 \n\t"
3948 "mov %c[r13](%0), %%r13 \n\t"
3949 "mov %c[r14](%0), %%r14 \n\t"
3950 "mov %c[r15](%0), %%r15 \n\t"
3952 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3954 /* Enter guest mode */
3955 "jne .Llaunched \n\t"
3956 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3957 "jmp .Lkvm_vmx_return \n\t"
3958 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3959 ".Lkvm_vmx_return: "
3960 /* Save guest registers, load host registers, keep flags */
3961 "xchg %0, (%%"R"sp) \n\t"
3962 "mov %%"R"ax, %c[rax](%0) \n\t"
3963 "mov %%"R"bx, %c[rbx](%0) \n\t"
3964 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3965 "mov %%"R"dx, %c[rdx](%0) \n\t"
3966 "mov %%"R"si, %c[rsi](%0) \n\t"
3967 "mov %%"R"di, %c[rdi](%0) \n\t"
3968 "mov %%"R"bp, %c[rbp](%0) \n\t"
3969 #ifdef CONFIG_X86_64
3970 "mov %%r8, %c[r8](%0) \n\t"
3971 "mov %%r9, %c[r9](%0) \n\t"
3972 "mov %%r10, %c[r10](%0) \n\t"
3973 "mov %%r11, %c[r11](%0) \n\t"
3974 "mov %%r12, %c[r12](%0) \n\t"
3975 "mov %%r13, %c[r13](%0) \n\t"
3976 "mov %%r14, %c[r14](%0) \n\t"
3977 "mov %%r15, %c[r15](%0) \n\t"
3979 "mov %%cr2, %%"R"ax \n\t"
3980 "mov %%"R"ax, %c[cr2](%0) \n\t"
3982 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3983 "setbe %c[fail](%0) \n\t"
3984 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3985 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3986 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3987 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3988 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3989 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3990 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3991 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3992 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3993 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3994 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3995 #ifdef CONFIG_X86_64
3996 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3997 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3998 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3999 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4000 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4001 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4002 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4003 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4005 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4007 , R"ax", R"bx", R"di", R"si"
4008 #ifdef CONFIG_X86_64
4009 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4014 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
4016 struct vcpu_vmx *vmx = to_vmx(vcpu);
4018 /* Record the guest's net vcpu time for enforced NMI injections. */
4019 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4020 vmx->entry_time = ktime_get();
4022 /* Don't enter VMX if guest state is invalid, let the exit handler
4023 start emulation until we arrive back to a valid state */
4024 if (vmx->emulation_required && emulate_invalid_guest_state)
4027 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4028 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4029 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4030 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4032 /* When single-stepping over STI and MOV SS, we must clear the
4033 * corresponding interruptibility bits in the guest state. Otherwise
4034 * vmentry fails as it then expects bit 14 (BS) in pending debug
4035 * exceptions being set, but that's not correct for the guest debugging
4037 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4038 vmx_set_interrupt_shadow(vcpu, 0);
4040 do_vmx_vcpu_run(vcpu);
4042 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4043 | (1 << VCPU_EXREG_PDPTR));
4044 vcpu->arch.regs_dirty = 0;
4046 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4048 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4051 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4052 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4054 vmx_complete_atomic_exit(vmx);
4055 vmx_recover_nmi_blocking(vmx);
4056 vmx_complete_interrupts(vmx);
4062 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4064 struct vcpu_vmx *vmx = to_vmx(vcpu);
4068 free_vmcs(vmx->vmcs);
4073 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4075 struct vcpu_vmx *vmx = to_vmx(vcpu);
4078 vmx_free_vmcs(vcpu);
4079 kfree(vmx->guest_msrs);
4080 kvm_vcpu_uninit(vcpu);
4081 kmem_cache_free(kvm_vcpu_cache, vmx);
4084 static inline void vmcs_init(struct vmcs *vmcs)
4086 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4089 kvm_cpu_vmxon(phys_addr);
4097 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4100 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4104 return ERR_PTR(-ENOMEM);
4108 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4112 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4113 if (!vmx->guest_msrs) {
4118 vmx->vmcs = alloc_vmcs();
4122 vmcs_init(vmx->vmcs);
4125 vmx_vcpu_load(&vmx->vcpu, cpu);
4126 vmx->vcpu.cpu = cpu;
4127 err = vmx_vcpu_setup(vmx);
4128 vmx_vcpu_put(&vmx->vcpu);
4132 if (vm_need_virtualize_apic_accesses(kvm))
4133 if (alloc_apic_access_page(kvm) != 0)
4137 if (!kvm->arch.ept_identity_map_addr)
4138 kvm->arch.ept_identity_map_addr =
4139 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4140 if (alloc_identity_pagetable(kvm) != 0)
4147 free_vmcs(vmx->vmcs);
4149 kfree(vmx->guest_msrs);
4151 kvm_vcpu_uninit(&vmx->vcpu);
4154 kmem_cache_free(kvm_vcpu_cache, vmx);
4155 return ERR_PTR(err);
4158 static void __init vmx_check_processor_compat(void *rtn)
4160 struct vmcs_config vmcs_conf;
4163 if (setup_vmcs_config(&vmcs_conf) < 0)
4165 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4166 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4167 smp_processor_id());
4172 static int get_ept_level(void)
4174 return VMX_EPT_DEFAULT_GAW + 1;
4177 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4181 /* For VT-d and EPT combination
4182 * 1. MMIO: always map as UC
4184 * a. VT-d without snooping control feature: can't guarantee the
4185 * result, try to trust guest.
4186 * b. VT-d with snooping control feature: snooping control feature of
4187 * VT-d engine can guarantee the cache correctness. Just set it
4188 * to WB to keep consistent with host. So the same as item 3.
4189 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4190 * consistent with host MTRR
4193 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4194 else if (vcpu->kvm->arch.iommu_domain &&
4195 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4196 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4197 VMX_EPT_MT_EPTE_SHIFT;
4199 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4205 #define _ER(x) { EXIT_REASON_##x, #x }
4207 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4209 _ER(EXTERNAL_INTERRUPT),
4211 _ER(PENDING_INTERRUPT),
4231 _ER(IO_INSTRUCTION),
4234 _ER(MWAIT_INSTRUCTION),
4235 _ER(MONITOR_INSTRUCTION),
4236 _ER(PAUSE_INSTRUCTION),
4237 _ER(MCE_DURING_VMENTRY),
4238 _ER(TPR_BELOW_THRESHOLD),
4248 static int vmx_get_lpage_level(void)
4250 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4251 return PT_DIRECTORY_LEVEL;
4253 /* For shadow and EPT supported 1GB page */
4254 return PT_PDPE_LEVEL;
4257 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4259 struct kvm_cpuid_entry2 *best;
4260 struct vcpu_vmx *vmx = to_vmx(vcpu);
4263 vmx->rdtscp_enabled = false;
4264 if (vmx_rdtscp_supported()) {
4265 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4266 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4267 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4268 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4269 vmx->rdtscp_enabled = true;
4271 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4272 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4279 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4283 static struct kvm_x86_ops vmx_x86_ops = {
4284 .cpu_has_kvm_support = cpu_has_kvm_support,
4285 .disabled_by_bios = vmx_disabled_by_bios,
4286 .hardware_setup = hardware_setup,
4287 .hardware_unsetup = hardware_unsetup,
4288 .check_processor_compatibility = vmx_check_processor_compat,
4289 .hardware_enable = hardware_enable,
4290 .hardware_disable = hardware_disable,
4291 .cpu_has_accelerated_tpr = report_flexpriority,
4293 .vcpu_create = vmx_create_vcpu,
4294 .vcpu_free = vmx_free_vcpu,
4295 .vcpu_reset = vmx_vcpu_reset,
4297 .prepare_guest_switch = vmx_save_host_state,
4298 .vcpu_load = vmx_vcpu_load,
4299 .vcpu_put = vmx_vcpu_put,
4301 .set_guest_debug = set_guest_debug,
4302 .get_msr = vmx_get_msr,
4303 .set_msr = vmx_set_msr,
4304 .get_segment_base = vmx_get_segment_base,
4305 .get_segment = vmx_get_segment,
4306 .set_segment = vmx_set_segment,
4307 .get_cpl = vmx_get_cpl,
4308 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4309 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4310 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4311 .set_cr0 = vmx_set_cr0,
4312 .set_cr3 = vmx_set_cr3,
4313 .set_cr4 = vmx_set_cr4,
4314 .set_efer = vmx_set_efer,
4315 .get_idt = vmx_get_idt,
4316 .set_idt = vmx_set_idt,
4317 .get_gdt = vmx_get_gdt,
4318 .set_gdt = vmx_set_gdt,
4319 .set_dr7 = vmx_set_dr7,
4320 .cache_reg = vmx_cache_reg,
4321 .get_rflags = vmx_get_rflags,
4322 .set_rflags = vmx_set_rflags,
4323 .fpu_activate = vmx_fpu_activate,
4324 .fpu_deactivate = vmx_fpu_deactivate,
4326 .tlb_flush = vmx_flush_tlb,
4328 .run = vmx_vcpu_run,
4329 .handle_exit = vmx_handle_exit,
4330 .skip_emulated_instruction = skip_emulated_instruction,
4331 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4332 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4333 .patch_hypercall = vmx_patch_hypercall,
4334 .set_irq = vmx_inject_irq,
4335 .set_nmi = vmx_inject_nmi,
4336 .queue_exception = vmx_queue_exception,
4337 .cancel_injection = vmx_cancel_injection,
4338 .interrupt_allowed = vmx_interrupt_allowed,
4339 .nmi_allowed = vmx_nmi_allowed,
4340 .get_nmi_mask = vmx_get_nmi_mask,
4341 .set_nmi_mask = vmx_set_nmi_mask,
4342 .enable_nmi_window = enable_nmi_window,
4343 .enable_irq_window = enable_irq_window,
4344 .update_cr8_intercept = update_cr8_intercept,
4346 .set_tss_addr = vmx_set_tss_addr,
4347 .get_tdp_level = get_ept_level,
4348 .get_mt_mask = vmx_get_mt_mask,
4350 .exit_reasons_str = vmx_exit_reasons_str,
4351 .get_lpage_level = vmx_get_lpage_level,
4353 .cpuid_update = vmx_cpuid_update,
4355 .rdtscp_supported = vmx_rdtscp_supported,
4357 .set_supported_cpuid = vmx_set_supported_cpuid,
4359 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4361 .write_tsc_offset = vmx_write_tsc_offset,
4362 .adjust_tsc_offset = vmx_adjust_tsc_offset,
4364 .set_tdp_cr3 = vmx_set_cr3,
4367 static int __init vmx_init(void)
4371 rdmsrl_safe(MSR_EFER, &host_efer);
4373 for (i = 0; i < NR_VMX_MSR; ++i)
4374 kvm_define_shared_msr(i, vmx_msr_index[i]);
4376 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4377 if (!vmx_io_bitmap_a)
4380 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4381 if (!vmx_io_bitmap_b) {
4386 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4387 if (!vmx_msr_bitmap_legacy) {
4392 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4393 if (!vmx_msr_bitmap_longmode) {
4399 * Allow direct access to the PC debug port (it is often used for I/O
4400 * delays, but the vmexits simply slow things down).
4402 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4403 clear_bit(0x80, vmx_io_bitmap_a);
4405 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4407 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4408 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4410 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4412 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4413 __alignof__(struct vcpu_vmx), THIS_MODULE);
4417 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4418 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4419 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4420 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4421 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4422 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4425 bypass_guest_pf = 0;
4426 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4427 VMX_EPT_EXECUTABLE_MASK);
4432 if (bypass_guest_pf)
4433 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4438 free_page((unsigned long)vmx_msr_bitmap_longmode);
4440 free_page((unsigned long)vmx_msr_bitmap_legacy);
4442 free_page((unsigned long)vmx_io_bitmap_b);
4444 free_page((unsigned long)vmx_io_bitmap_a);
4448 static void __exit vmx_exit(void)
4450 free_page((unsigned long)vmx_msr_bitmap_legacy);
4451 free_page((unsigned long)vmx_msr_bitmap_longmode);
4452 free_page((unsigned long)vmx_io_bitmap_b);
4453 free_page((unsigned long)vmx_io_bitmap_a);
4458 module_init(vmx_init)
4459 module_exit(vmx_exit)