2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
52 static int __read_mostly bypass_guest_pf = 1;
53 module_param(bypass_guest_pf, bool, S_IRUGO);
55 static int __read_mostly enable_vpid = 1;
56 module_param_named(vpid, enable_vpid, bool, 0444);
58 static int __read_mostly flexpriority_enabled = 1;
59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
61 static int __read_mostly enable_ept = 1;
62 module_param_named(ept, enable_ept, bool, S_IRUGO);
64 static int __read_mostly enable_unrestricted_guest = 1;
65 module_param_named(unrestricted_guest,
66 enable_unrestricted_guest, bool, S_IRUGO);
68 static int __read_mostly emulate_invalid_guest_state = 0;
69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
71 static int __read_mostly vmm_exclusive = 1;
72 module_param(vmm_exclusive, bool, S_IRUGO);
74 static int __read_mostly yield_on_hlt = 1;
75 module_param(yield_on_hlt, bool, S_IRUGO);
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
82 static int __read_mostly nested = 0;
83 module_param(nested, bool, S_IRUGO);
85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87 #define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
90 (X86_CR0_WP | X86_CR0_NE)
91 #define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
93 #define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
106 * According to test, this time is usually smaller than 128 cycles.
107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
113 #define KVM_VMX_DEFAULT_PLE_GAP 128
114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116 module_param(ple_gap, int, S_IRUGO);
118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119 module_param(ple_window, int, S_IRUGO);
121 #define NR_AUTOLOAD_MSRS 1
122 #define VMCS02_POOL_SIZE 1
131 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133 * loaded on this CPU (so we can clear them if the CPU goes down).
139 struct list_head loaded_vmcss_on_cpu_link;
142 struct shared_msr_entry {
149 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154 * More than one of these structures may exist, if L1 runs multiple L2 guests.
155 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156 * underlying hardware which will be used to run L2.
157 * This structure is packed to ensure that its layout is identical across
158 * machines (necessary for live migration).
159 * If there are changes in this struct, VMCS12_REVISION must be changed.
161 typedef u64 natural_width;
162 struct __packed vmcs12 {
163 /* According to the Intel spec, a VMCS region must start with the
164 * following two fields. Then follow implementation-specific data.
172 u64 vm_exit_msr_store_addr;
173 u64 vm_exit_msr_load_addr;
174 u64 vm_entry_msr_load_addr;
176 u64 virtual_apic_page_addr;
177 u64 apic_access_addr;
179 u64 guest_physical_address;
180 u64 vmcs_link_pointer;
181 u64 guest_ia32_debugctl;
184 u64 guest_ia32_perf_global_ctrl;
191 u64 host_ia32_perf_global_ctrl;
192 u64 padding64[8]; /* room for future expansion */
194 * To allow migration of L1 (complete with its L2 guests) between
195 * machines of different natural widths (32 or 64 bit), we cannot have
196 * unsigned long fields with no explict size. We use u64 (aliased
197 * natural_width) instead. Luckily, x86 is little-endian.
199 natural_width cr0_guest_host_mask;
200 natural_width cr4_guest_host_mask;
201 natural_width cr0_read_shadow;
202 natural_width cr4_read_shadow;
203 natural_width cr3_target_value0;
204 natural_width cr3_target_value1;
205 natural_width cr3_target_value2;
206 natural_width cr3_target_value3;
207 natural_width exit_qualification;
208 natural_width guest_linear_address;
209 natural_width guest_cr0;
210 natural_width guest_cr3;
211 natural_width guest_cr4;
212 natural_width guest_es_base;
213 natural_width guest_cs_base;
214 natural_width guest_ss_base;
215 natural_width guest_ds_base;
216 natural_width guest_fs_base;
217 natural_width guest_gs_base;
218 natural_width guest_ldtr_base;
219 natural_width guest_tr_base;
220 natural_width guest_gdtr_base;
221 natural_width guest_idtr_base;
222 natural_width guest_dr7;
223 natural_width guest_rsp;
224 natural_width guest_rip;
225 natural_width guest_rflags;
226 natural_width guest_pending_dbg_exceptions;
227 natural_width guest_sysenter_esp;
228 natural_width guest_sysenter_eip;
229 natural_width host_cr0;
230 natural_width host_cr3;
231 natural_width host_cr4;
232 natural_width host_fs_base;
233 natural_width host_gs_base;
234 natural_width host_tr_base;
235 natural_width host_gdtr_base;
236 natural_width host_idtr_base;
237 natural_width host_ia32_sysenter_esp;
238 natural_width host_ia32_sysenter_eip;
239 natural_width host_rsp;
240 natural_width host_rip;
241 natural_width paddingl[8]; /* room for future expansion */
242 u32 pin_based_vm_exec_control;
243 u32 cpu_based_vm_exec_control;
244 u32 exception_bitmap;
245 u32 page_fault_error_code_mask;
246 u32 page_fault_error_code_match;
247 u32 cr3_target_count;
248 u32 vm_exit_controls;
249 u32 vm_exit_msr_store_count;
250 u32 vm_exit_msr_load_count;
251 u32 vm_entry_controls;
252 u32 vm_entry_msr_load_count;
253 u32 vm_entry_intr_info_field;
254 u32 vm_entry_exception_error_code;
255 u32 vm_entry_instruction_len;
257 u32 secondary_vm_exec_control;
258 u32 vm_instruction_error;
260 u32 vm_exit_intr_info;
261 u32 vm_exit_intr_error_code;
262 u32 idt_vectoring_info_field;
263 u32 idt_vectoring_error_code;
264 u32 vm_exit_instruction_len;
265 u32 vmx_instruction_info;
272 u32 guest_ldtr_limit;
274 u32 guest_gdtr_limit;
275 u32 guest_idtr_limit;
276 u32 guest_es_ar_bytes;
277 u32 guest_cs_ar_bytes;
278 u32 guest_ss_ar_bytes;
279 u32 guest_ds_ar_bytes;
280 u32 guest_fs_ar_bytes;
281 u32 guest_gs_ar_bytes;
282 u32 guest_ldtr_ar_bytes;
283 u32 guest_tr_ar_bytes;
284 u32 guest_interruptibility_info;
285 u32 guest_activity_state;
286 u32 guest_sysenter_cs;
287 u32 host_ia32_sysenter_cs;
288 u32 padding32[8]; /* room for future expansion */
289 u16 virtual_processor_id;
290 u16 guest_es_selector;
291 u16 guest_cs_selector;
292 u16 guest_ss_selector;
293 u16 guest_ds_selector;
294 u16 guest_fs_selector;
295 u16 guest_gs_selector;
296 u16 guest_ldtr_selector;
297 u16 guest_tr_selector;
298 u16 host_es_selector;
299 u16 host_cs_selector;
300 u16 host_ss_selector;
301 u16 host_ds_selector;
302 u16 host_fs_selector;
303 u16 host_gs_selector;
304 u16 host_tr_selector;
308 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
309 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
310 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
312 #define VMCS12_REVISION 0x11e57ed0
315 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
316 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
317 * current implementation, 4K are reserved to avoid future complications.
319 #define VMCS12_SIZE 0x1000
321 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
323 struct list_head list;
325 struct loaded_vmcs vmcs02;
329 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
330 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
333 /* Has the level1 guest done vmxon? */
336 /* The guest-physical address of the current VMCS L1 keeps for L2 */
338 /* The host-usable pointer to the above */
339 struct page *current_vmcs12_page;
340 struct vmcs12 *current_vmcs12;
342 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
343 struct list_head vmcs02_pool;
348 struct kvm_vcpu vcpu;
349 unsigned long host_rsp;
352 bool nmi_known_unmasked;
354 u32 idt_vectoring_info;
356 struct shared_msr_entry *guest_msrs;
360 u64 msr_host_kernel_gs_base;
361 u64 msr_guest_kernel_gs_base;
364 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
365 * non-nested (L1) guest, it always points to vmcs01. For a nested
366 * guest (L2), it points to a different VMCS.
368 struct loaded_vmcs vmcs01;
369 struct loaded_vmcs *loaded_vmcs;
370 bool __launched; /* temporary, used in vmx_vcpu_run */
371 struct msr_autoload {
373 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
374 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
378 u16 fs_sel, gs_sel, ldt_sel;
379 int gs_ldt_reload_needed;
380 int fs_reload_needed;
385 struct kvm_save_segment {
390 } tr, es, ds, fs, gs;
393 u32 bitmask; /* 4 bits per segment (1 bit per field) */
394 struct kvm_save_segment seg[8];
397 bool emulation_required;
399 /* Support for vnmi-less CPUs */
400 int soft_vnmi_blocked;
402 s64 vnmi_blocked_time;
407 /* Support for a guest hypervisor (nested VMX) */
408 struct nested_vmx nested;
411 enum segment_cache_field {
420 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
422 return container_of(vcpu, struct vcpu_vmx, vcpu);
425 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
426 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
427 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
428 [number##_HIGH] = VMCS12_OFFSET(name)+4
430 static unsigned short vmcs_field_to_offset_table[] = {
431 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
432 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
433 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
434 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
435 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
436 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
437 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
438 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
439 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
440 FIELD(HOST_ES_SELECTOR, host_es_selector),
441 FIELD(HOST_CS_SELECTOR, host_cs_selector),
442 FIELD(HOST_SS_SELECTOR, host_ss_selector),
443 FIELD(HOST_DS_SELECTOR, host_ds_selector),
444 FIELD(HOST_FS_SELECTOR, host_fs_selector),
445 FIELD(HOST_GS_SELECTOR, host_gs_selector),
446 FIELD(HOST_TR_SELECTOR, host_tr_selector),
447 FIELD64(IO_BITMAP_A, io_bitmap_a),
448 FIELD64(IO_BITMAP_B, io_bitmap_b),
449 FIELD64(MSR_BITMAP, msr_bitmap),
450 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
451 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
452 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
453 FIELD64(TSC_OFFSET, tsc_offset),
454 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
455 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
456 FIELD64(EPT_POINTER, ept_pointer),
457 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
458 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
459 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
460 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
461 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
462 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
463 FIELD64(GUEST_PDPTR0, guest_pdptr0),
464 FIELD64(GUEST_PDPTR1, guest_pdptr1),
465 FIELD64(GUEST_PDPTR2, guest_pdptr2),
466 FIELD64(GUEST_PDPTR3, guest_pdptr3),
467 FIELD64(HOST_IA32_PAT, host_ia32_pat),
468 FIELD64(HOST_IA32_EFER, host_ia32_efer),
469 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
470 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
471 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
472 FIELD(EXCEPTION_BITMAP, exception_bitmap),
473 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
474 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
475 FIELD(CR3_TARGET_COUNT, cr3_target_count),
476 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
477 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
478 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
479 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
480 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
481 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
482 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
483 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
484 FIELD(TPR_THRESHOLD, tpr_threshold),
485 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
486 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
487 FIELD(VM_EXIT_REASON, vm_exit_reason),
488 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
489 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
490 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
491 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
492 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
493 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
494 FIELD(GUEST_ES_LIMIT, guest_es_limit),
495 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
496 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
497 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
498 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
499 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
500 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
501 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
502 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
503 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
504 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
505 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
506 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
507 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
508 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
509 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
510 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
511 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
512 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
513 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
514 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
515 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
516 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
517 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
518 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
519 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
520 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
521 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
522 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
523 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
524 FIELD(EXIT_QUALIFICATION, exit_qualification),
525 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
526 FIELD(GUEST_CR0, guest_cr0),
527 FIELD(GUEST_CR3, guest_cr3),
528 FIELD(GUEST_CR4, guest_cr4),
529 FIELD(GUEST_ES_BASE, guest_es_base),
530 FIELD(GUEST_CS_BASE, guest_cs_base),
531 FIELD(GUEST_SS_BASE, guest_ss_base),
532 FIELD(GUEST_DS_BASE, guest_ds_base),
533 FIELD(GUEST_FS_BASE, guest_fs_base),
534 FIELD(GUEST_GS_BASE, guest_gs_base),
535 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
536 FIELD(GUEST_TR_BASE, guest_tr_base),
537 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
538 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
539 FIELD(GUEST_DR7, guest_dr7),
540 FIELD(GUEST_RSP, guest_rsp),
541 FIELD(GUEST_RIP, guest_rip),
542 FIELD(GUEST_RFLAGS, guest_rflags),
543 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
544 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
545 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
546 FIELD(HOST_CR0, host_cr0),
547 FIELD(HOST_CR3, host_cr3),
548 FIELD(HOST_CR4, host_cr4),
549 FIELD(HOST_FS_BASE, host_fs_base),
550 FIELD(HOST_GS_BASE, host_gs_base),
551 FIELD(HOST_TR_BASE, host_tr_base),
552 FIELD(HOST_GDTR_BASE, host_gdtr_base),
553 FIELD(HOST_IDTR_BASE, host_idtr_base),
554 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
555 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
556 FIELD(HOST_RSP, host_rsp),
557 FIELD(HOST_RIP, host_rip),
559 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
561 static inline short vmcs_field_to_offset(unsigned long field)
563 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
565 return vmcs_field_to_offset_table[field];
568 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
570 return to_vmx(vcpu)->nested.current_vmcs12;
573 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
575 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
576 if (is_error_page(page)) {
577 kvm_release_page_clean(page);
583 static void nested_release_page(struct page *page)
585 kvm_release_page_dirty(page);
588 static void nested_release_page_clean(struct page *page)
590 kvm_release_page_clean(page);
593 static u64 construct_eptp(unsigned long root_hpa);
594 static void kvm_cpu_vmxon(u64 addr);
595 static void kvm_cpu_vmxoff(void);
596 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
597 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
599 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
600 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
602 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
603 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
605 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
606 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
608 static unsigned long *vmx_io_bitmap_a;
609 static unsigned long *vmx_io_bitmap_b;
610 static unsigned long *vmx_msr_bitmap_legacy;
611 static unsigned long *vmx_msr_bitmap_longmode;
613 static bool cpu_has_load_ia32_efer;
615 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
616 static DEFINE_SPINLOCK(vmx_vpid_lock);
618 static struct vmcs_config {
622 u32 pin_based_exec_ctrl;
623 u32 cpu_based_exec_ctrl;
624 u32 cpu_based_2nd_exec_ctrl;
629 static struct vmx_capability {
634 #define VMX_SEGMENT_FIELD(seg) \
635 [VCPU_SREG_##seg] = { \
636 .selector = GUEST_##seg##_SELECTOR, \
637 .base = GUEST_##seg##_BASE, \
638 .limit = GUEST_##seg##_LIMIT, \
639 .ar_bytes = GUEST_##seg##_AR_BYTES, \
642 static struct kvm_vmx_segment_field {
647 } kvm_vmx_segment_fields[] = {
648 VMX_SEGMENT_FIELD(CS),
649 VMX_SEGMENT_FIELD(DS),
650 VMX_SEGMENT_FIELD(ES),
651 VMX_SEGMENT_FIELD(FS),
652 VMX_SEGMENT_FIELD(GS),
653 VMX_SEGMENT_FIELD(SS),
654 VMX_SEGMENT_FIELD(TR),
655 VMX_SEGMENT_FIELD(LDTR),
658 static u64 host_efer;
660 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
663 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
664 * away by decrementing the array size.
666 static const u32 vmx_msr_index[] = {
668 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
670 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
672 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
674 static inline bool is_page_fault(u32 intr_info)
676 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
677 INTR_INFO_VALID_MASK)) ==
678 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
681 static inline bool is_no_device(u32 intr_info)
683 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
684 INTR_INFO_VALID_MASK)) ==
685 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
688 static inline bool is_invalid_opcode(u32 intr_info)
690 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
691 INTR_INFO_VALID_MASK)) ==
692 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
695 static inline bool is_external_interrupt(u32 intr_info)
697 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
698 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
701 static inline bool is_machine_check(u32 intr_info)
703 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
704 INTR_INFO_VALID_MASK)) ==
705 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
708 static inline bool cpu_has_vmx_msr_bitmap(void)
710 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
713 static inline bool cpu_has_vmx_tpr_shadow(void)
715 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
718 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
720 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
723 static inline bool cpu_has_secondary_exec_ctrls(void)
725 return vmcs_config.cpu_based_exec_ctrl &
726 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
729 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
731 return vmcs_config.cpu_based_2nd_exec_ctrl &
732 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
735 static inline bool cpu_has_vmx_flexpriority(void)
737 return cpu_has_vmx_tpr_shadow() &&
738 cpu_has_vmx_virtualize_apic_accesses();
741 static inline bool cpu_has_vmx_ept_execute_only(void)
743 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
746 static inline bool cpu_has_vmx_eptp_uncacheable(void)
748 return vmx_capability.ept & VMX_EPTP_UC_BIT;
751 static inline bool cpu_has_vmx_eptp_writeback(void)
753 return vmx_capability.ept & VMX_EPTP_WB_BIT;
756 static inline bool cpu_has_vmx_ept_2m_page(void)
758 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
761 static inline bool cpu_has_vmx_ept_1g_page(void)
763 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
766 static inline bool cpu_has_vmx_ept_4levels(void)
768 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
771 static inline bool cpu_has_vmx_invept_individual_addr(void)
773 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
776 static inline bool cpu_has_vmx_invept_context(void)
778 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
781 static inline bool cpu_has_vmx_invept_global(void)
783 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
786 static inline bool cpu_has_vmx_invvpid_single(void)
788 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
791 static inline bool cpu_has_vmx_invvpid_global(void)
793 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
796 static inline bool cpu_has_vmx_ept(void)
798 return vmcs_config.cpu_based_2nd_exec_ctrl &
799 SECONDARY_EXEC_ENABLE_EPT;
802 static inline bool cpu_has_vmx_unrestricted_guest(void)
804 return vmcs_config.cpu_based_2nd_exec_ctrl &
805 SECONDARY_EXEC_UNRESTRICTED_GUEST;
808 static inline bool cpu_has_vmx_ple(void)
810 return vmcs_config.cpu_based_2nd_exec_ctrl &
811 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
814 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
816 return flexpriority_enabled && irqchip_in_kernel(kvm);
819 static inline bool cpu_has_vmx_vpid(void)
821 return vmcs_config.cpu_based_2nd_exec_ctrl &
822 SECONDARY_EXEC_ENABLE_VPID;
825 static inline bool cpu_has_vmx_rdtscp(void)
827 return vmcs_config.cpu_based_2nd_exec_ctrl &
828 SECONDARY_EXEC_RDTSCP;
831 static inline bool cpu_has_virtual_nmis(void)
833 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
836 static inline bool cpu_has_vmx_wbinvd_exit(void)
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_WBINVD_EXITING;
842 static inline bool report_flexpriority(void)
844 return flexpriority_enabled;
847 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
851 for (i = 0; i < vmx->nmsrs; ++i)
852 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
857 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
863 } operand = { vpid, 0, gva };
865 asm volatile (__ex(ASM_VMX_INVVPID)
866 /* CF==1 or ZF==1 --> rc = -1 */
868 : : "a"(&operand), "c"(ext) : "cc", "memory");
871 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
875 } operand = {eptp, gpa};
877 asm volatile (__ex(ASM_VMX_INVEPT)
878 /* CF==1 or ZF==1 --> rc = -1 */
879 "; ja 1f ; ud2 ; 1:\n"
880 : : "a" (&operand), "c" (ext) : "cc", "memory");
883 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
887 i = __find_msr_index(vmx, msr);
889 return &vmx->guest_msrs[i];
893 static void vmcs_clear(struct vmcs *vmcs)
895 u64 phys_addr = __pa(vmcs);
898 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
899 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
902 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
906 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
908 vmcs_clear(loaded_vmcs->vmcs);
909 loaded_vmcs->cpu = -1;
910 loaded_vmcs->launched = 0;
913 static void vmcs_load(struct vmcs *vmcs)
915 u64 phys_addr = __pa(vmcs);
918 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
919 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
922 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
926 static void __loaded_vmcs_clear(void *arg)
928 struct loaded_vmcs *loaded_vmcs = arg;
929 int cpu = raw_smp_processor_id();
931 if (loaded_vmcs->cpu != cpu)
932 return; /* vcpu migration can race with cpu offline */
933 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
934 per_cpu(current_vmcs, cpu) = NULL;
935 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
936 loaded_vmcs_init(loaded_vmcs);
939 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
941 if (loaded_vmcs->cpu != -1)
942 smp_call_function_single(
943 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
946 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
951 if (cpu_has_vmx_invvpid_single())
952 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
955 static inline void vpid_sync_vcpu_global(void)
957 if (cpu_has_vmx_invvpid_global())
958 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
961 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
963 if (cpu_has_vmx_invvpid_single())
964 vpid_sync_vcpu_single(vmx);
966 vpid_sync_vcpu_global();
969 static inline void ept_sync_global(void)
971 if (cpu_has_vmx_invept_global())
972 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
975 static inline void ept_sync_context(u64 eptp)
978 if (cpu_has_vmx_invept_context())
979 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
985 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
988 if (cpu_has_vmx_invept_individual_addr())
989 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
992 ept_sync_context(eptp);
996 static __always_inline unsigned long vmcs_readl(unsigned long field)
1000 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1001 : "=a"(value) : "d"(field) : "cc");
1005 static __always_inline u16 vmcs_read16(unsigned long field)
1007 return vmcs_readl(field);
1010 static __always_inline u32 vmcs_read32(unsigned long field)
1012 return vmcs_readl(field);
1015 static __always_inline u64 vmcs_read64(unsigned long field)
1017 #ifdef CONFIG_X86_64
1018 return vmcs_readl(field);
1020 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1024 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1026 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1027 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1031 static void vmcs_writel(unsigned long field, unsigned long value)
1035 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1036 : "=q"(error) : "a"(value), "d"(field) : "cc");
1037 if (unlikely(error))
1038 vmwrite_error(field, value);
1041 static void vmcs_write16(unsigned long field, u16 value)
1043 vmcs_writel(field, value);
1046 static void vmcs_write32(unsigned long field, u32 value)
1048 vmcs_writel(field, value);
1051 static void vmcs_write64(unsigned long field, u64 value)
1053 vmcs_writel(field, value);
1054 #ifndef CONFIG_X86_64
1056 vmcs_writel(field+1, value >> 32);
1060 static void vmcs_clear_bits(unsigned long field, u32 mask)
1062 vmcs_writel(field, vmcs_readl(field) & ~mask);
1065 static void vmcs_set_bits(unsigned long field, u32 mask)
1067 vmcs_writel(field, vmcs_readl(field) | mask);
1070 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1072 vmx->segment_cache.bitmask = 0;
1075 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1079 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1081 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1082 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1083 vmx->segment_cache.bitmask = 0;
1085 ret = vmx->segment_cache.bitmask & mask;
1086 vmx->segment_cache.bitmask |= mask;
1090 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1092 u16 *p = &vmx->segment_cache.seg[seg].selector;
1094 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1095 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1099 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1101 ulong *p = &vmx->segment_cache.seg[seg].base;
1103 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1104 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1108 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1110 u32 *p = &vmx->segment_cache.seg[seg].limit;
1112 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1113 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1117 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1119 u32 *p = &vmx->segment_cache.seg[seg].ar;
1121 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1122 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1126 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1130 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1131 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1132 if ((vcpu->guest_debug &
1133 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1134 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1135 eb |= 1u << BP_VECTOR;
1136 if (to_vmx(vcpu)->rmode.vm86_active)
1139 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1140 if (vcpu->fpu_active)
1141 eb &= ~(1u << NM_VECTOR);
1142 vmcs_write32(EXCEPTION_BITMAP, eb);
1145 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1148 struct msr_autoload *m = &vmx->msr_autoload;
1150 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1151 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1152 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1156 for (i = 0; i < m->nr; ++i)
1157 if (m->guest[i].index == msr)
1163 m->guest[i] = m->guest[m->nr];
1164 m->host[i] = m->host[m->nr];
1165 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1166 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1169 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1170 u64 guest_val, u64 host_val)
1173 struct msr_autoload *m = &vmx->msr_autoload;
1175 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1176 vmcs_write64(GUEST_IA32_EFER, guest_val);
1177 vmcs_write64(HOST_IA32_EFER, host_val);
1178 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1179 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1183 for (i = 0; i < m->nr; ++i)
1184 if (m->guest[i].index == msr)
1189 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1190 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1193 m->guest[i].index = msr;
1194 m->guest[i].value = guest_val;
1195 m->host[i].index = msr;
1196 m->host[i].value = host_val;
1199 static void reload_tss(void)
1202 * VT restores TR but not its size. Useless.
1204 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1205 struct desc_struct *descs;
1207 descs = (void *)gdt->address;
1208 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1212 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1217 guest_efer = vmx->vcpu.arch.efer;
1220 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1223 ignore_bits = EFER_NX | EFER_SCE;
1224 #ifdef CONFIG_X86_64
1225 ignore_bits |= EFER_LMA | EFER_LME;
1226 /* SCE is meaningful only in long mode on Intel */
1227 if (guest_efer & EFER_LMA)
1228 ignore_bits &= ~(u64)EFER_SCE;
1230 guest_efer &= ~ignore_bits;
1231 guest_efer |= host_efer & ignore_bits;
1232 vmx->guest_msrs[efer_offset].data = guest_efer;
1233 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1235 clear_atomic_switch_msr(vmx, MSR_EFER);
1236 /* On ept, can't emulate nx, and must switch nx atomically */
1237 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1238 guest_efer = vmx->vcpu.arch.efer;
1239 if (!(guest_efer & EFER_LMA))
1240 guest_efer &= ~EFER_LME;
1241 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1248 static unsigned long segment_base(u16 selector)
1250 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1251 struct desc_struct *d;
1252 unsigned long table_base;
1255 if (!(selector & ~3))
1258 table_base = gdt->address;
1260 if (selector & 4) { /* from ldt */
1261 u16 ldt_selector = kvm_read_ldt();
1263 if (!(ldt_selector & ~3))
1266 table_base = segment_base(ldt_selector);
1268 d = (struct desc_struct *)(table_base + (selector & ~7));
1269 v = get_desc_base(d);
1270 #ifdef CONFIG_X86_64
1271 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1272 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1277 static inline unsigned long kvm_read_tr_base(void)
1280 asm("str %0" : "=g"(tr));
1281 return segment_base(tr);
1284 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1286 struct vcpu_vmx *vmx = to_vmx(vcpu);
1289 if (vmx->host_state.loaded)
1292 vmx->host_state.loaded = 1;
1294 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1295 * allow segment selectors with cpl > 0 or ti == 1.
1297 vmx->host_state.ldt_sel = kvm_read_ldt();
1298 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1299 savesegment(fs, vmx->host_state.fs_sel);
1300 if (!(vmx->host_state.fs_sel & 7)) {
1301 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1302 vmx->host_state.fs_reload_needed = 0;
1304 vmcs_write16(HOST_FS_SELECTOR, 0);
1305 vmx->host_state.fs_reload_needed = 1;
1307 savesegment(gs, vmx->host_state.gs_sel);
1308 if (!(vmx->host_state.gs_sel & 7))
1309 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1311 vmcs_write16(HOST_GS_SELECTOR, 0);
1312 vmx->host_state.gs_ldt_reload_needed = 1;
1315 #ifdef CONFIG_X86_64
1316 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1317 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1319 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1320 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1323 #ifdef CONFIG_X86_64
1324 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1325 if (is_long_mode(&vmx->vcpu))
1326 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1328 for (i = 0; i < vmx->save_nmsrs; ++i)
1329 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1330 vmx->guest_msrs[i].data,
1331 vmx->guest_msrs[i].mask);
1334 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1336 if (!vmx->host_state.loaded)
1339 ++vmx->vcpu.stat.host_state_reload;
1340 vmx->host_state.loaded = 0;
1341 #ifdef CONFIG_X86_64
1342 if (is_long_mode(&vmx->vcpu))
1343 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1345 if (vmx->host_state.gs_ldt_reload_needed) {
1346 kvm_load_ldt(vmx->host_state.ldt_sel);
1347 #ifdef CONFIG_X86_64
1348 load_gs_index(vmx->host_state.gs_sel);
1350 loadsegment(gs, vmx->host_state.gs_sel);
1353 if (vmx->host_state.fs_reload_needed)
1354 loadsegment(fs, vmx->host_state.fs_sel);
1356 #ifdef CONFIG_X86_64
1357 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1359 if (current_thread_info()->status & TS_USEDFPU)
1361 load_gdt(&__get_cpu_var(host_gdt));
1364 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1367 __vmx_load_host_state(vmx);
1372 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1373 * vcpu mutex is already taken.
1375 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1377 struct vcpu_vmx *vmx = to_vmx(vcpu);
1378 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1381 kvm_cpu_vmxon(phys_addr);
1382 else if (vmx->loaded_vmcs->cpu != cpu)
1383 loaded_vmcs_clear(vmx->loaded_vmcs);
1385 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1386 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1387 vmcs_load(vmx->loaded_vmcs->vmcs);
1390 if (vmx->loaded_vmcs->cpu != cpu) {
1391 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1392 unsigned long sysenter_esp;
1394 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1395 local_irq_disable();
1396 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1397 &per_cpu(loaded_vmcss_on_cpu, cpu));
1401 * Linux uses per-cpu TSS and GDT, so set these when switching
1404 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1405 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1407 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1408 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1409 vmx->loaded_vmcs->cpu = cpu;
1413 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1415 __vmx_load_host_state(to_vmx(vcpu));
1416 if (!vmm_exclusive) {
1417 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1423 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1427 if (vcpu->fpu_active)
1429 vcpu->fpu_active = 1;
1430 cr0 = vmcs_readl(GUEST_CR0);
1431 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1432 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1433 vmcs_writel(GUEST_CR0, cr0);
1434 update_exception_bitmap(vcpu);
1435 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1436 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1439 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1441 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1443 vmx_decache_cr0_guest_bits(vcpu);
1444 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1445 update_exception_bitmap(vcpu);
1446 vcpu->arch.cr0_guest_owned_bits = 0;
1447 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1448 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1451 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1453 unsigned long rflags, save_rflags;
1455 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1456 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1457 rflags = vmcs_readl(GUEST_RFLAGS);
1458 if (to_vmx(vcpu)->rmode.vm86_active) {
1459 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1460 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1461 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1463 to_vmx(vcpu)->rflags = rflags;
1465 return to_vmx(vcpu)->rflags;
1468 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1470 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1471 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1472 to_vmx(vcpu)->rflags = rflags;
1473 if (to_vmx(vcpu)->rmode.vm86_active) {
1474 to_vmx(vcpu)->rmode.save_rflags = rflags;
1475 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1477 vmcs_writel(GUEST_RFLAGS, rflags);
1480 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1482 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1485 if (interruptibility & GUEST_INTR_STATE_STI)
1486 ret |= KVM_X86_SHADOW_INT_STI;
1487 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1488 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1493 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1495 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1496 u32 interruptibility = interruptibility_old;
1498 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1500 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1501 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1502 else if (mask & KVM_X86_SHADOW_INT_STI)
1503 interruptibility |= GUEST_INTR_STATE_STI;
1505 if ((interruptibility != interruptibility_old))
1506 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1509 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1513 rip = kvm_rip_read(vcpu);
1514 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1515 kvm_rip_write(vcpu, rip);
1517 /* skipping an emulated instruction also counts */
1518 vmx_set_interrupt_shadow(vcpu, 0);
1521 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1523 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1524 * explicitly skip the instruction because if the HLT state is set, then
1525 * the instruction is already executing and RIP has already been
1527 if (!yield_on_hlt &&
1528 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1529 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1532 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1533 bool has_error_code, u32 error_code,
1536 struct vcpu_vmx *vmx = to_vmx(vcpu);
1537 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1539 if (has_error_code) {
1540 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1541 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1544 if (vmx->rmode.vm86_active) {
1546 if (kvm_exception_is_soft(nr))
1547 inc_eip = vcpu->arch.event_exit_inst_len;
1548 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1549 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1553 if (kvm_exception_is_soft(nr)) {
1554 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1555 vmx->vcpu.arch.event_exit_inst_len);
1556 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1558 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1560 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1561 vmx_clear_hlt(vcpu);
1564 static bool vmx_rdtscp_supported(void)
1566 return cpu_has_vmx_rdtscp();
1570 * Swap MSR entry in host/guest MSR entry array.
1572 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1574 struct shared_msr_entry tmp;
1576 tmp = vmx->guest_msrs[to];
1577 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1578 vmx->guest_msrs[from] = tmp;
1582 * Set up the vmcs to automatically save and restore system
1583 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1584 * mode, as fiddling with msrs is very expensive.
1586 static void setup_msrs(struct vcpu_vmx *vmx)
1588 int save_nmsrs, index;
1589 unsigned long *msr_bitmap;
1591 vmx_load_host_state(vmx);
1593 #ifdef CONFIG_X86_64
1594 if (is_long_mode(&vmx->vcpu)) {
1595 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1597 move_msr_up(vmx, index, save_nmsrs++);
1598 index = __find_msr_index(vmx, MSR_LSTAR);
1600 move_msr_up(vmx, index, save_nmsrs++);
1601 index = __find_msr_index(vmx, MSR_CSTAR);
1603 move_msr_up(vmx, index, save_nmsrs++);
1604 index = __find_msr_index(vmx, MSR_TSC_AUX);
1605 if (index >= 0 && vmx->rdtscp_enabled)
1606 move_msr_up(vmx, index, save_nmsrs++);
1608 * MSR_STAR is only needed on long mode guests, and only
1609 * if efer.sce is enabled.
1611 index = __find_msr_index(vmx, MSR_STAR);
1612 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1613 move_msr_up(vmx, index, save_nmsrs++);
1616 index = __find_msr_index(vmx, MSR_EFER);
1617 if (index >= 0 && update_transition_efer(vmx, index))
1618 move_msr_up(vmx, index, save_nmsrs++);
1620 vmx->save_nmsrs = save_nmsrs;
1622 if (cpu_has_vmx_msr_bitmap()) {
1623 if (is_long_mode(&vmx->vcpu))
1624 msr_bitmap = vmx_msr_bitmap_longmode;
1626 msr_bitmap = vmx_msr_bitmap_legacy;
1628 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1633 * reads and returns guest's timestamp counter "register"
1634 * guest_tsc = host_tsc + tsc_offset -- 21.3
1636 static u64 guest_read_tsc(void)
1638 u64 host_tsc, tsc_offset;
1641 tsc_offset = vmcs_read64(TSC_OFFSET);
1642 return host_tsc + tsc_offset;
1646 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1647 * ioctl. In this case the call-back should update internal vmx state to make
1648 * the changes effective.
1650 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1652 /* Nothing to do here */
1656 * writes 'offset' into guest's timestamp counter offset register
1658 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1660 vmcs_write64(TSC_OFFSET, offset);
1663 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1665 u64 offset = vmcs_read64(TSC_OFFSET);
1666 vmcs_write64(TSC_OFFSET, offset + adjustment);
1669 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1671 return target_tsc - native_read_tsc();
1674 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1676 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1677 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1681 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1682 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1683 * all guests if the "nested" module option is off, and can also be disabled
1684 * for a single guest by disabling its VMX cpuid bit.
1686 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1688 return nested && guest_cpuid_has_vmx(vcpu);
1692 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1693 * returned for the various VMX controls MSRs when nested VMX is enabled.
1694 * The same values should also be used to verify that vmcs12 control fields are
1695 * valid during nested entry from L1 to L2.
1696 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1697 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1698 * bit in the high half is on if the corresponding bit in the control field
1699 * may be on. See also vmx_control_verify().
1700 * TODO: allow these variables to be modified (downgraded) by module options
1703 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1704 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1705 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1706 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1707 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1708 static __init void nested_vmx_setup_ctls_msrs(void)
1711 * Note that as a general rule, the high half of the MSRs (bits in
1712 * the control fields which may be 1) should be initialized by the
1713 * intersection of the underlying hardware's MSR (i.e., features which
1714 * can be supported) and the list of features we want to expose -
1715 * because they are known to be properly supported in our code.
1716 * Also, usually, the low half of the MSRs (bits which must be 1) can
1717 * be set to 0, meaning that L1 may turn off any of these bits. The
1718 * reason is that if one of these bits is necessary, it will appear
1719 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1720 * fields of vmcs01 and vmcs02, will turn these bits off - and
1721 * nested_vmx_exit_handled() will not pass related exits to L1.
1722 * These rules have exceptions below.
1725 /* pin-based controls */
1727 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1728 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1730 nested_vmx_pinbased_ctls_low = 0x16 ;
1731 nested_vmx_pinbased_ctls_high = 0x16 |
1732 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1733 PIN_BASED_VIRTUAL_NMIS;
1736 nested_vmx_exit_ctls_low = 0;
1737 #ifdef CONFIG_X86_64
1738 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1740 nested_vmx_exit_ctls_high = 0;
1743 /* entry controls */
1744 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1745 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1746 nested_vmx_entry_ctls_low = 0;
1747 nested_vmx_entry_ctls_high &=
1748 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1750 /* cpu-based controls */
1751 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1752 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1753 nested_vmx_procbased_ctls_low = 0;
1754 nested_vmx_procbased_ctls_high &=
1755 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1756 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1757 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1758 CPU_BASED_CR3_STORE_EXITING |
1759 #ifdef CONFIG_X86_64
1760 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1762 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1763 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1764 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1766 * We can allow some features even when not supported by the
1767 * hardware. For example, L1 can specify an MSR bitmap - and we
1768 * can use it to avoid exits to L1 - even when L0 runs L2
1769 * without MSR bitmaps.
1771 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1773 /* secondary cpu-based controls */
1774 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1775 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1776 nested_vmx_secondary_ctls_low = 0;
1777 nested_vmx_secondary_ctls_high &=
1778 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1781 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1784 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1786 return ((control & high) | low) == control;
1789 static inline u64 vmx_control_msr(u32 low, u32 high)
1791 return low | ((u64)high << 32);
1795 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1796 * also let it use VMX-specific MSRs.
1797 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1798 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1799 * like all other MSRs).
1801 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1803 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1804 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1806 * According to the spec, processors which do not support VMX
1807 * should throw a #GP(0) when VMX capability MSRs are read.
1809 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1813 switch (msr_index) {
1814 case MSR_IA32_FEATURE_CONTROL:
1817 case MSR_IA32_VMX_BASIC:
1819 * This MSR reports some information about VMX support. We
1820 * should return information about the VMX we emulate for the
1821 * guest, and the VMCS structure we give it - not about the
1822 * VMX support of the underlying hardware.
1824 *pdata = VMCS12_REVISION |
1825 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1826 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1828 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1829 case MSR_IA32_VMX_PINBASED_CTLS:
1830 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1831 nested_vmx_pinbased_ctls_high);
1833 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1834 case MSR_IA32_VMX_PROCBASED_CTLS:
1835 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1836 nested_vmx_procbased_ctls_high);
1838 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1839 case MSR_IA32_VMX_EXIT_CTLS:
1840 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1841 nested_vmx_exit_ctls_high);
1843 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1844 case MSR_IA32_VMX_ENTRY_CTLS:
1845 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1846 nested_vmx_entry_ctls_high);
1848 case MSR_IA32_VMX_MISC:
1852 * These MSRs specify bits which the guest must keep fixed (on or off)
1853 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1854 * We picked the standard core2 setting.
1856 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1857 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1858 case MSR_IA32_VMX_CR0_FIXED0:
1859 *pdata = VMXON_CR0_ALWAYSON;
1861 case MSR_IA32_VMX_CR0_FIXED1:
1864 case MSR_IA32_VMX_CR4_FIXED0:
1865 *pdata = VMXON_CR4_ALWAYSON;
1867 case MSR_IA32_VMX_CR4_FIXED1:
1870 case MSR_IA32_VMX_VMCS_ENUM:
1873 case MSR_IA32_VMX_PROCBASED_CTLS2:
1874 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1875 nested_vmx_secondary_ctls_high);
1877 case MSR_IA32_VMX_EPT_VPID_CAP:
1878 /* Currently, no nested ept or nested vpid */
1888 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1890 if (!nested_vmx_allowed(vcpu))
1893 if (msr_index == MSR_IA32_FEATURE_CONTROL)
1894 /* TODO: the right thing. */
1897 * No need to treat VMX capability MSRs specially: If we don't handle
1898 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1904 * Reads an msr value (of 'msr_index') into 'pdata'.
1905 * Returns 0 on success, non-0 otherwise.
1906 * Assumes vcpu_load() was already called.
1908 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1911 struct shared_msr_entry *msr;
1914 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1918 switch (msr_index) {
1919 #ifdef CONFIG_X86_64
1921 data = vmcs_readl(GUEST_FS_BASE);
1924 data = vmcs_readl(GUEST_GS_BASE);
1926 case MSR_KERNEL_GS_BASE:
1927 vmx_load_host_state(to_vmx(vcpu));
1928 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1932 return kvm_get_msr_common(vcpu, msr_index, pdata);
1934 data = guest_read_tsc();
1936 case MSR_IA32_SYSENTER_CS:
1937 data = vmcs_read32(GUEST_SYSENTER_CS);
1939 case MSR_IA32_SYSENTER_EIP:
1940 data = vmcs_readl(GUEST_SYSENTER_EIP);
1942 case MSR_IA32_SYSENTER_ESP:
1943 data = vmcs_readl(GUEST_SYSENTER_ESP);
1946 if (!to_vmx(vcpu)->rdtscp_enabled)
1948 /* Otherwise falls through */
1950 vmx_load_host_state(to_vmx(vcpu));
1951 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
1953 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1955 vmx_load_host_state(to_vmx(vcpu));
1959 return kvm_get_msr_common(vcpu, msr_index, pdata);
1967 * Writes msr value into into the appropriate "register".
1968 * Returns 0 on success, non-0 otherwise.
1969 * Assumes vcpu_load() was already called.
1971 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1973 struct vcpu_vmx *vmx = to_vmx(vcpu);
1974 struct shared_msr_entry *msr;
1977 switch (msr_index) {
1979 vmx_load_host_state(vmx);
1980 ret = kvm_set_msr_common(vcpu, msr_index, data);
1982 #ifdef CONFIG_X86_64
1984 vmx_segment_cache_clear(vmx);
1985 vmcs_writel(GUEST_FS_BASE, data);
1988 vmx_segment_cache_clear(vmx);
1989 vmcs_writel(GUEST_GS_BASE, data);
1991 case MSR_KERNEL_GS_BASE:
1992 vmx_load_host_state(vmx);
1993 vmx->msr_guest_kernel_gs_base = data;
1996 case MSR_IA32_SYSENTER_CS:
1997 vmcs_write32(GUEST_SYSENTER_CS, data);
1999 case MSR_IA32_SYSENTER_EIP:
2000 vmcs_writel(GUEST_SYSENTER_EIP, data);
2002 case MSR_IA32_SYSENTER_ESP:
2003 vmcs_writel(GUEST_SYSENTER_ESP, data);
2006 kvm_write_tsc(vcpu, data);
2008 case MSR_IA32_CR_PAT:
2009 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2010 vmcs_write64(GUEST_IA32_PAT, data);
2011 vcpu->arch.pat = data;
2014 ret = kvm_set_msr_common(vcpu, msr_index, data);
2017 if (!vmx->rdtscp_enabled)
2019 /* Check reserved bit, higher 32 bits should be zero */
2020 if ((data >> 32) != 0)
2022 /* Otherwise falls through */
2024 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2026 msr = find_msr_entry(vmx, msr_index);
2028 vmx_load_host_state(vmx);
2032 ret = kvm_set_msr_common(vcpu, msr_index, data);
2038 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2040 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2043 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2046 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2048 case VCPU_EXREG_PDPTR:
2050 ept_save_pdptrs(vcpu);
2057 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2059 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2060 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2062 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2064 update_exception_bitmap(vcpu);
2067 static __init int cpu_has_kvm_support(void)
2069 return cpu_has_vmx();
2072 static __init int vmx_disabled_by_bios(void)
2076 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2077 if (msr & FEATURE_CONTROL_LOCKED) {
2078 /* launched w/ TXT and VMX disabled */
2079 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2082 /* launched w/o TXT and VMX only enabled w/ TXT */
2083 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2084 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2085 && !tboot_enabled()) {
2086 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2087 "activate TXT before enabling KVM\n");
2090 /* launched w/o TXT and VMX disabled */
2091 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2092 && !tboot_enabled())
2099 static void kvm_cpu_vmxon(u64 addr)
2101 asm volatile (ASM_VMX_VMXON_RAX
2102 : : "a"(&addr), "m"(addr)
2106 static int hardware_enable(void *garbage)
2108 int cpu = raw_smp_processor_id();
2109 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2112 if (read_cr4() & X86_CR4_VMXE)
2115 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2116 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2118 test_bits = FEATURE_CONTROL_LOCKED;
2119 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2120 if (tboot_enabled())
2121 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2123 if ((old & test_bits) != test_bits) {
2124 /* enable and lock */
2125 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2127 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2129 if (vmm_exclusive) {
2130 kvm_cpu_vmxon(phys_addr);
2134 store_gdt(&__get_cpu_var(host_gdt));
2139 static void vmclear_local_loaded_vmcss(void)
2141 int cpu = raw_smp_processor_id();
2142 struct loaded_vmcs *v, *n;
2144 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2145 loaded_vmcss_on_cpu_link)
2146 __loaded_vmcs_clear(v);
2150 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2153 static void kvm_cpu_vmxoff(void)
2155 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2158 static void hardware_disable(void *garbage)
2160 if (vmm_exclusive) {
2161 vmclear_local_loaded_vmcss();
2164 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2167 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2168 u32 msr, u32 *result)
2170 u32 vmx_msr_low, vmx_msr_high;
2171 u32 ctl = ctl_min | ctl_opt;
2173 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2175 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2176 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2178 /* Ensure minimum (required) set of control bits are supported. */
2186 static __init bool allow_1_setting(u32 msr, u32 ctl)
2188 u32 vmx_msr_low, vmx_msr_high;
2190 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2191 return vmx_msr_high & ctl;
2194 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2196 u32 vmx_msr_low, vmx_msr_high;
2197 u32 min, opt, min2, opt2;
2198 u32 _pin_based_exec_control = 0;
2199 u32 _cpu_based_exec_control = 0;
2200 u32 _cpu_based_2nd_exec_control = 0;
2201 u32 _vmexit_control = 0;
2202 u32 _vmentry_control = 0;
2204 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2205 opt = PIN_BASED_VIRTUAL_NMIS;
2206 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2207 &_pin_based_exec_control) < 0)
2211 #ifdef CONFIG_X86_64
2212 CPU_BASED_CR8_LOAD_EXITING |
2213 CPU_BASED_CR8_STORE_EXITING |
2215 CPU_BASED_CR3_LOAD_EXITING |
2216 CPU_BASED_CR3_STORE_EXITING |
2217 CPU_BASED_USE_IO_BITMAPS |
2218 CPU_BASED_MOV_DR_EXITING |
2219 CPU_BASED_USE_TSC_OFFSETING |
2220 CPU_BASED_MWAIT_EXITING |
2221 CPU_BASED_MONITOR_EXITING |
2222 CPU_BASED_INVLPG_EXITING;
2225 min |= CPU_BASED_HLT_EXITING;
2227 opt = CPU_BASED_TPR_SHADOW |
2228 CPU_BASED_USE_MSR_BITMAPS |
2229 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2230 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2231 &_cpu_based_exec_control) < 0)
2233 #ifdef CONFIG_X86_64
2234 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2235 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2236 ~CPU_BASED_CR8_STORE_EXITING;
2238 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2240 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2241 SECONDARY_EXEC_WBINVD_EXITING |
2242 SECONDARY_EXEC_ENABLE_VPID |
2243 SECONDARY_EXEC_ENABLE_EPT |
2244 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2245 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2246 SECONDARY_EXEC_RDTSCP;
2247 if (adjust_vmx_controls(min2, opt2,
2248 MSR_IA32_VMX_PROCBASED_CTLS2,
2249 &_cpu_based_2nd_exec_control) < 0)
2252 #ifndef CONFIG_X86_64
2253 if (!(_cpu_based_2nd_exec_control &
2254 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2255 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2257 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2258 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2260 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2261 CPU_BASED_CR3_STORE_EXITING |
2262 CPU_BASED_INVLPG_EXITING);
2263 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2264 vmx_capability.ept, vmx_capability.vpid);
2268 #ifdef CONFIG_X86_64
2269 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2271 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2272 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2273 &_vmexit_control) < 0)
2277 opt = VM_ENTRY_LOAD_IA32_PAT;
2278 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2279 &_vmentry_control) < 0)
2282 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2284 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2285 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2288 #ifdef CONFIG_X86_64
2289 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2290 if (vmx_msr_high & (1u<<16))
2294 /* Require Write-Back (WB) memory type for VMCS accesses. */
2295 if (((vmx_msr_high >> 18) & 15) != 6)
2298 vmcs_conf->size = vmx_msr_high & 0x1fff;
2299 vmcs_conf->order = get_order(vmcs_config.size);
2300 vmcs_conf->revision_id = vmx_msr_low;
2302 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2303 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2304 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2305 vmcs_conf->vmexit_ctrl = _vmexit_control;
2306 vmcs_conf->vmentry_ctrl = _vmentry_control;
2308 cpu_has_load_ia32_efer =
2309 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2310 VM_ENTRY_LOAD_IA32_EFER)
2311 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2312 VM_EXIT_LOAD_IA32_EFER);
2317 static struct vmcs *alloc_vmcs_cpu(int cpu)
2319 int node = cpu_to_node(cpu);
2323 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2326 vmcs = page_address(pages);
2327 memset(vmcs, 0, vmcs_config.size);
2328 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2332 static struct vmcs *alloc_vmcs(void)
2334 return alloc_vmcs_cpu(raw_smp_processor_id());
2337 static void free_vmcs(struct vmcs *vmcs)
2339 free_pages((unsigned long)vmcs, vmcs_config.order);
2343 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2345 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2347 if (!loaded_vmcs->vmcs)
2349 loaded_vmcs_clear(loaded_vmcs);
2350 free_vmcs(loaded_vmcs->vmcs);
2351 loaded_vmcs->vmcs = NULL;
2354 static void free_kvm_area(void)
2358 for_each_possible_cpu(cpu) {
2359 free_vmcs(per_cpu(vmxarea, cpu));
2360 per_cpu(vmxarea, cpu) = NULL;
2364 static __init int alloc_kvm_area(void)
2368 for_each_possible_cpu(cpu) {
2371 vmcs = alloc_vmcs_cpu(cpu);
2377 per_cpu(vmxarea, cpu) = vmcs;
2382 static __init int hardware_setup(void)
2384 if (setup_vmcs_config(&vmcs_config) < 0)
2387 if (boot_cpu_has(X86_FEATURE_NX))
2388 kvm_enable_efer_bits(EFER_NX);
2390 if (!cpu_has_vmx_vpid())
2393 if (!cpu_has_vmx_ept() ||
2394 !cpu_has_vmx_ept_4levels()) {
2396 enable_unrestricted_guest = 0;
2399 if (!cpu_has_vmx_unrestricted_guest())
2400 enable_unrestricted_guest = 0;
2402 if (!cpu_has_vmx_flexpriority())
2403 flexpriority_enabled = 0;
2405 if (!cpu_has_vmx_tpr_shadow())
2406 kvm_x86_ops->update_cr8_intercept = NULL;
2408 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2409 kvm_disable_largepages();
2411 if (!cpu_has_vmx_ple())
2415 nested_vmx_setup_ctls_msrs();
2417 return alloc_kvm_area();
2420 static __exit void hardware_unsetup(void)
2425 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2427 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2429 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2430 vmcs_write16(sf->selector, save->selector);
2431 vmcs_writel(sf->base, save->base);
2432 vmcs_write32(sf->limit, save->limit);
2433 vmcs_write32(sf->ar_bytes, save->ar);
2435 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2437 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2441 static void enter_pmode(struct kvm_vcpu *vcpu)
2443 unsigned long flags;
2444 struct vcpu_vmx *vmx = to_vmx(vcpu);
2446 vmx->emulation_required = 1;
2447 vmx->rmode.vm86_active = 0;
2449 vmx_segment_cache_clear(vmx);
2451 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2452 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2453 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2454 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2456 flags = vmcs_readl(GUEST_RFLAGS);
2457 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2458 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2459 vmcs_writel(GUEST_RFLAGS, flags);
2461 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2462 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2464 update_exception_bitmap(vcpu);
2466 if (emulate_invalid_guest_state)
2469 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2470 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2471 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2472 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2474 vmx_segment_cache_clear(vmx);
2476 vmcs_write16(GUEST_SS_SELECTOR, 0);
2477 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2479 vmcs_write16(GUEST_CS_SELECTOR,
2480 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2481 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2484 static gva_t rmode_tss_base(struct kvm *kvm)
2486 if (!kvm->arch.tss_addr) {
2487 struct kvm_memslots *slots;
2490 slots = kvm_memslots(kvm);
2491 base_gfn = slots->memslots[0].base_gfn +
2492 kvm->memslots->memslots[0].npages - 3;
2493 return base_gfn << PAGE_SHIFT;
2495 return kvm->arch.tss_addr;
2498 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2500 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2502 save->selector = vmcs_read16(sf->selector);
2503 save->base = vmcs_readl(sf->base);
2504 save->limit = vmcs_read32(sf->limit);
2505 save->ar = vmcs_read32(sf->ar_bytes);
2506 vmcs_write16(sf->selector, save->base >> 4);
2507 vmcs_write32(sf->base, save->base & 0xffff0);
2508 vmcs_write32(sf->limit, 0xffff);
2509 vmcs_write32(sf->ar_bytes, 0xf3);
2510 if (save->base & 0xf)
2511 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2512 " aligned when entering protected mode (seg=%d)",
2516 static void enter_rmode(struct kvm_vcpu *vcpu)
2518 unsigned long flags;
2519 struct vcpu_vmx *vmx = to_vmx(vcpu);
2521 if (enable_unrestricted_guest)
2524 vmx->emulation_required = 1;
2525 vmx->rmode.vm86_active = 1;
2528 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2529 * vcpu. Call it here with phys address pointing 16M below 4G.
2531 if (!vcpu->kvm->arch.tss_addr) {
2532 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2533 "called before entering vcpu\n");
2534 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2535 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2536 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2539 vmx_segment_cache_clear(vmx);
2541 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2542 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2543 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2545 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2546 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2548 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2549 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2551 flags = vmcs_readl(GUEST_RFLAGS);
2552 vmx->rmode.save_rflags = flags;
2554 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2556 vmcs_writel(GUEST_RFLAGS, flags);
2557 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2558 update_exception_bitmap(vcpu);
2560 if (emulate_invalid_guest_state)
2561 goto continue_rmode;
2563 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2564 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2565 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2567 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2568 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2569 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2570 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2571 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2573 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2574 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2575 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2576 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2579 kvm_mmu_reset_context(vcpu);
2582 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2584 struct vcpu_vmx *vmx = to_vmx(vcpu);
2585 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2591 * Force kernel_gs_base reloading before EFER changes, as control
2592 * of this msr depends on is_long_mode().
2594 vmx_load_host_state(to_vmx(vcpu));
2595 vcpu->arch.efer = efer;
2596 if (efer & EFER_LMA) {
2597 vmcs_write32(VM_ENTRY_CONTROLS,
2598 vmcs_read32(VM_ENTRY_CONTROLS) |
2599 VM_ENTRY_IA32E_MODE);
2602 vmcs_write32(VM_ENTRY_CONTROLS,
2603 vmcs_read32(VM_ENTRY_CONTROLS) &
2604 ~VM_ENTRY_IA32E_MODE);
2606 msr->data = efer & ~EFER_LME;
2611 #ifdef CONFIG_X86_64
2613 static void enter_lmode(struct kvm_vcpu *vcpu)
2617 vmx_segment_cache_clear(to_vmx(vcpu));
2619 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2620 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2621 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2623 vmcs_write32(GUEST_TR_AR_BYTES,
2624 (guest_tr_ar & ~AR_TYPE_MASK)
2625 | AR_TYPE_BUSY_64_TSS);
2627 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2630 static void exit_lmode(struct kvm_vcpu *vcpu)
2632 vmcs_write32(VM_ENTRY_CONTROLS,
2633 vmcs_read32(VM_ENTRY_CONTROLS)
2634 & ~VM_ENTRY_IA32E_MODE);
2635 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2640 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2642 vpid_sync_context(to_vmx(vcpu));
2644 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2646 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2650 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2652 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2654 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2655 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2658 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2660 if (enable_ept && is_paging(vcpu))
2661 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2662 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2665 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2667 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2669 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2670 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2673 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2675 if (!test_bit(VCPU_EXREG_PDPTR,
2676 (unsigned long *)&vcpu->arch.regs_dirty))
2679 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2680 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2681 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2682 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2683 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2687 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2689 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2690 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2691 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2692 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2693 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2696 __set_bit(VCPU_EXREG_PDPTR,
2697 (unsigned long *)&vcpu->arch.regs_avail);
2698 __set_bit(VCPU_EXREG_PDPTR,
2699 (unsigned long *)&vcpu->arch.regs_dirty);
2702 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2704 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2706 struct kvm_vcpu *vcpu)
2708 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2709 vmx_decache_cr3(vcpu);
2710 if (!(cr0 & X86_CR0_PG)) {
2711 /* From paging/starting to nonpaging */
2712 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2713 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2714 (CPU_BASED_CR3_LOAD_EXITING |
2715 CPU_BASED_CR3_STORE_EXITING));
2716 vcpu->arch.cr0 = cr0;
2717 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2718 } else if (!is_paging(vcpu)) {
2719 /* From nonpaging to paging */
2720 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2721 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2722 ~(CPU_BASED_CR3_LOAD_EXITING |
2723 CPU_BASED_CR3_STORE_EXITING));
2724 vcpu->arch.cr0 = cr0;
2725 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2728 if (!(cr0 & X86_CR0_WP))
2729 *hw_cr0 &= ~X86_CR0_WP;
2732 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2734 struct vcpu_vmx *vmx = to_vmx(vcpu);
2735 unsigned long hw_cr0;
2737 if (enable_unrestricted_guest)
2738 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2739 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2741 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2743 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2746 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2749 #ifdef CONFIG_X86_64
2750 if (vcpu->arch.efer & EFER_LME) {
2751 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2753 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2759 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2761 if (!vcpu->fpu_active)
2762 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2764 vmcs_writel(CR0_READ_SHADOW, cr0);
2765 vmcs_writel(GUEST_CR0, hw_cr0);
2766 vcpu->arch.cr0 = cr0;
2767 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2770 static u64 construct_eptp(unsigned long root_hpa)
2774 /* TODO write the value reading from MSR */
2775 eptp = VMX_EPT_DEFAULT_MT |
2776 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2777 eptp |= (root_hpa & PAGE_MASK);
2782 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2784 unsigned long guest_cr3;
2789 eptp = construct_eptp(cr3);
2790 vmcs_write64(EPT_POINTER, eptp);
2791 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2792 vcpu->kvm->arch.ept_identity_map_addr;
2793 ept_load_pdptrs(vcpu);
2796 vmx_flush_tlb(vcpu);
2797 vmcs_writel(GUEST_CR3, guest_cr3);
2800 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2802 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2803 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2805 if (cr4 & X86_CR4_VMXE) {
2807 * To use VMXON (and later other VMX instructions), a guest
2808 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2809 * So basically the check on whether to allow nested VMX
2812 if (!nested_vmx_allowed(vcpu))
2814 } else if (to_vmx(vcpu)->nested.vmxon)
2817 vcpu->arch.cr4 = cr4;
2819 if (!is_paging(vcpu)) {
2820 hw_cr4 &= ~X86_CR4_PAE;
2821 hw_cr4 |= X86_CR4_PSE;
2822 } else if (!(cr4 & X86_CR4_PAE)) {
2823 hw_cr4 &= ~X86_CR4_PAE;
2827 vmcs_writel(CR4_READ_SHADOW, cr4);
2828 vmcs_writel(GUEST_CR4, hw_cr4);
2832 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2833 struct kvm_segment *var, int seg)
2835 struct vcpu_vmx *vmx = to_vmx(vcpu);
2836 struct kvm_save_segment *save;
2839 if (vmx->rmode.vm86_active
2840 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2841 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2842 || seg == VCPU_SREG_GS)
2843 && !emulate_invalid_guest_state) {
2845 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2846 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2847 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2848 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2849 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2852 var->selector = save->selector;
2853 var->base = save->base;
2854 var->limit = save->limit;
2856 if (seg == VCPU_SREG_TR
2857 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2858 goto use_saved_rmode_seg;
2860 var->base = vmx_read_guest_seg_base(vmx, seg);
2861 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2862 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2863 ar = vmx_read_guest_seg_ar(vmx, seg);
2864 use_saved_rmode_seg:
2865 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2867 var->type = ar & 15;
2868 var->s = (ar >> 4) & 1;
2869 var->dpl = (ar >> 5) & 3;
2870 var->present = (ar >> 7) & 1;
2871 var->avl = (ar >> 12) & 1;
2872 var->l = (ar >> 13) & 1;
2873 var->db = (ar >> 14) & 1;
2874 var->g = (ar >> 15) & 1;
2875 var->unusable = (ar >> 16) & 1;
2878 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2880 struct kvm_segment s;
2882 if (to_vmx(vcpu)->rmode.vm86_active) {
2883 vmx_get_segment(vcpu, &s, seg);
2886 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
2889 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2891 if (!is_protmode(vcpu))
2894 if (!is_long_mode(vcpu)
2895 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2898 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2901 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2903 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2904 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2905 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2907 return to_vmx(vcpu)->cpl;
2911 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2918 ar = var->type & 15;
2919 ar |= (var->s & 1) << 4;
2920 ar |= (var->dpl & 3) << 5;
2921 ar |= (var->present & 1) << 7;
2922 ar |= (var->avl & 1) << 12;
2923 ar |= (var->l & 1) << 13;
2924 ar |= (var->db & 1) << 14;
2925 ar |= (var->g & 1) << 15;
2927 if (ar == 0) /* a 0 value means unusable */
2928 ar = AR_UNUSABLE_MASK;
2933 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2934 struct kvm_segment *var, int seg)
2936 struct vcpu_vmx *vmx = to_vmx(vcpu);
2937 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2940 vmx_segment_cache_clear(vmx);
2942 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2943 vmcs_write16(sf->selector, var->selector);
2944 vmx->rmode.tr.selector = var->selector;
2945 vmx->rmode.tr.base = var->base;
2946 vmx->rmode.tr.limit = var->limit;
2947 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2950 vmcs_writel(sf->base, var->base);
2951 vmcs_write32(sf->limit, var->limit);
2952 vmcs_write16(sf->selector, var->selector);
2953 if (vmx->rmode.vm86_active && var->s) {
2955 * Hack real-mode segments into vm86 compatibility.
2957 if (var->base == 0xffff0000 && var->selector == 0xf000)
2958 vmcs_writel(sf->base, 0xf0000);
2961 ar = vmx_segment_access_rights(var);
2964 * Fix the "Accessed" bit in AR field of segment registers for older
2966 * IA32 arch specifies that at the time of processor reset the
2967 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2968 * is setting it to 0 in the usedland code. This causes invalid guest
2969 * state vmexit when "unrestricted guest" mode is turned on.
2970 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2971 * tree. Newer qemu binaries with that qemu fix would not need this
2974 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2975 ar |= 0x1; /* Accessed */
2977 vmcs_write32(sf->ar_bytes, ar);
2978 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2981 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2983 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
2985 *db = (ar >> 14) & 1;
2986 *l = (ar >> 13) & 1;
2989 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2991 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2992 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2995 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2997 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2998 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3001 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3003 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3004 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3007 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3009 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3010 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3013 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3015 struct kvm_segment var;
3018 vmx_get_segment(vcpu, &var, seg);
3019 ar = vmx_segment_access_rights(&var);
3021 if (var.base != (var.selector << 4))
3023 if (var.limit != 0xffff)
3031 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3033 struct kvm_segment cs;
3034 unsigned int cs_rpl;
3036 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3037 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3041 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3045 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3046 if (cs.dpl > cs_rpl)
3049 if (cs.dpl != cs_rpl)
3055 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3059 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3061 struct kvm_segment ss;
3062 unsigned int ss_rpl;
3064 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3065 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3069 if (ss.type != 3 && ss.type != 7)
3073 if (ss.dpl != ss_rpl) /* DPL != RPL */
3081 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3083 struct kvm_segment var;
3086 vmx_get_segment(vcpu, &var, seg);
3087 rpl = var.selector & SELECTOR_RPL_MASK;
3095 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3096 if (var.dpl < rpl) /* DPL < RPL */
3100 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3106 static bool tr_valid(struct kvm_vcpu *vcpu)
3108 struct kvm_segment tr;
3110 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3114 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3116 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3124 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3126 struct kvm_segment ldtr;
3128 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3132 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3142 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3144 struct kvm_segment cs, ss;
3146 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3147 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3149 return ((cs.selector & SELECTOR_RPL_MASK) ==
3150 (ss.selector & SELECTOR_RPL_MASK));
3154 * Check if guest state is valid. Returns true if valid, false if
3156 * We assume that registers are always usable
3158 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3160 /* real mode guest state checks */
3161 if (!is_protmode(vcpu)) {
3162 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3164 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3166 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3168 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3170 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3172 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3175 /* protected mode guest state checks */
3176 if (!cs_ss_rpl_check(vcpu))
3178 if (!code_segment_valid(vcpu))
3180 if (!stack_segment_valid(vcpu))
3182 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3184 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3186 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3188 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3190 if (!tr_valid(vcpu))
3192 if (!ldtr_valid(vcpu))
3196 * - Add checks on RIP
3197 * - Add checks on RFLAGS
3203 static int init_rmode_tss(struct kvm *kvm)
3207 int r, idx, ret = 0;
3209 idx = srcu_read_lock(&kvm->srcu);
3210 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3211 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3214 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3215 r = kvm_write_guest_page(kvm, fn++, &data,
3216 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3219 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3222 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3226 r = kvm_write_guest_page(kvm, fn, &data,
3227 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3234 srcu_read_unlock(&kvm->srcu, idx);
3238 static int init_rmode_identity_map(struct kvm *kvm)
3241 pfn_t identity_map_pfn;
3246 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3247 printk(KERN_ERR "EPT: identity-mapping pagetable "
3248 "haven't been allocated!\n");
3251 if (likely(kvm->arch.ept_identity_pagetable_done))
3254 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3255 idx = srcu_read_lock(&kvm->srcu);
3256 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3259 /* Set up identity-mapping pagetable for EPT in real mode */
3260 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3261 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3262 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3263 r = kvm_write_guest_page(kvm, identity_map_pfn,
3264 &tmp, i * sizeof(tmp), sizeof(tmp));
3268 kvm->arch.ept_identity_pagetable_done = true;
3271 srcu_read_unlock(&kvm->srcu, idx);
3275 static void seg_setup(int seg)
3277 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3280 vmcs_write16(sf->selector, 0);
3281 vmcs_writel(sf->base, 0);
3282 vmcs_write32(sf->limit, 0xffff);
3283 if (enable_unrestricted_guest) {
3285 if (seg == VCPU_SREG_CS)
3286 ar |= 0x08; /* code segment */
3290 vmcs_write32(sf->ar_bytes, ar);
3293 static int alloc_apic_access_page(struct kvm *kvm)
3295 struct kvm_userspace_memory_region kvm_userspace_mem;
3298 mutex_lock(&kvm->slots_lock);
3299 if (kvm->arch.apic_access_page)
3301 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3302 kvm_userspace_mem.flags = 0;
3303 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3304 kvm_userspace_mem.memory_size = PAGE_SIZE;
3305 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3309 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3311 mutex_unlock(&kvm->slots_lock);
3315 static int alloc_identity_pagetable(struct kvm *kvm)
3317 struct kvm_userspace_memory_region kvm_userspace_mem;
3320 mutex_lock(&kvm->slots_lock);
3321 if (kvm->arch.ept_identity_pagetable)
3323 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3324 kvm_userspace_mem.flags = 0;
3325 kvm_userspace_mem.guest_phys_addr =
3326 kvm->arch.ept_identity_map_addr;
3327 kvm_userspace_mem.memory_size = PAGE_SIZE;
3328 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3332 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3333 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3335 mutex_unlock(&kvm->slots_lock);
3339 static void allocate_vpid(struct vcpu_vmx *vmx)
3346 spin_lock(&vmx_vpid_lock);
3347 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3348 if (vpid < VMX_NR_VPIDS) {
3350 __set_bit(vpid, vmx_vpid_bitmap);
3352 spin_unlock(&vmx_vpid_lock);
3355 static void free_vpid(struct vcpu_vmx *vmx)
3359 spin_lock(&vmx_vpid_lock);
3361 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3362 spin_unlock(&vmx_vpid_lock);
3365 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3367 int f = sizeof(unsigned long);
3369 if (!cpu_has_vmx_msr_bitmap())
3373 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3374 * have the write-low and read-high bitmap offsets the wrong way round.
3375 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3377 if (msr <= 0x1fff) {
3378 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3379 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3380 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3382 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3383 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3387 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3390 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3391 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3395 * Sets up the vmcs for emulated real mode.
3397 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3399 u32 host_sysenter_cs, msr_low, msr_high;
3405 unsigned long kvm_vmx_return;
3409 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3410 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3412 if (cpu_has_vmx_msr_bitmap())
3413 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3415 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3418 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3419 vmcs_config.pin_based_exec_ctrl);
3421 exec_control = vmcs_config.cpu_based_exec_ctrl;
3422 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3423 exec_control &= ~CPU_BASED_TPR_SHADOW;
3424 #ifdef CONFIG_X86_64
3425 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3426 CPU_BASED_CR8_LOAD_EXITING;
3430 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3431 CPU_BASED_CR3_LOAD_EXITING |
3432 CPU_BASED_INVLPG_EXITING;
3433 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
3435 if (cpu_has_secondary_exec_ctrls()) {
3436 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3437 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3439 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3441 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3443 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3444 enable_unrestricted_guest = 0;
3446 if (!enable_unrestricted_guest)
3447 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3449 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3450 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
3454 vmcs_write32(PLE_GAP, ple_gap);
3455 vmcs_write32(PLE_WINDOW, ple_window);
3458 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3459 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
3460 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3462 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3463 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3464 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3466 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3467 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3468 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3469 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3470 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
3471 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3472 #ifdef CONFIG_X86_64
3473 rdmsrl(MSR_FS_BASE, a);
3474 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3475 rdmsrl(MSR_GS_BASE, a);
3476 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3478 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3479 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3482 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3484 native_store_idt(&dt);
3485 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3487 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
3488 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
3489 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3490 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3491 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3492 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3493 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3495 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
3496 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
3497 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
3498 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
3499 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
3500 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
3502 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3503 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3504 host_pat = msr_low | ((u64) msr_high << 32);
3505 vmcs_write64(HOST_IA32_PAT, host_pat);
3507 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3508 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3509 host_pat = msr_low | ((u64) msr_high << 32);
3510 /* Write the default value follow host pat */
3511 vmcs_write64(GUEST_IA32_PAT, host_pat);
3512 /* Keep arch.pat sync with GUEST_IA32_PAT */
3513 vmx->vcpu.arch.pat = host_pat;
3516 for (i = 0; i < NR_VMX_MSR; ++i) {
3517 u32 index = vmx_msr_index[i];
3518 u32 data_low, data_high;
3521 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3523 if (wrmsr_safe(index, data_low, data_high) < 0)
3525 vmx->guest_msrs[j].index = i;
3526 vmx->guest_msrs[j].data = 0;
3527 vmx->guest_msrs[j].mask = -1ull;
3531 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3533 /* 22.2.1, 20.8.1 */
3534 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3536 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3537 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3539 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3540 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3542 kvm_write_tsc(&vmx->vcpu, 0);
3547 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3549 struct vcpu_vmx *vmx = to_vmx(vcpu);
3553 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3555 vmx->rmode.vm86_active = 0;
3557 vmx->soft_vnmi_blocked = 0;
3559 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3560 kvm_set_cr8(&vmx->vcpu, 0);
3561 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3562 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3563 msr |= MSR_IA32_APICBASE_BSP;
3564 kvm_set_apic_base(&vmx->vcpu, msr);
3566 ret = fx_init(&vmx->vcpu);
3570 vmx_segment_cache_clear(vmx);
3572 seg_setup(VCPU_SREG_CS);
3574 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3575 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3577 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3578 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3579 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3581 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3582 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3585 seg_setup(VCPU_SREG_DS);
3586 seg_setup(VCPU_SREG_ES);
3587 seg_setup(VCPU_SREG_FS);
3588 seg_setup(VCPU_SREG_GS);
3589 seg_setup(VCPU_SREG_SS);
3591 vmcs_write16(GUEST_TR_SELECTOR, 0);
3592 vmcs_writel(GUEST_TR_BASE, 0);
3593 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3594 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3596 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3597 vmcs_writel(GUEST_LDTR_BASE, 0);
3598 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3599 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3601 vmcs_write32(GUEST_SYSENTER_CS, 0);
3602 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3603 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3605 vmcs_writel(GUEST_RFLAGS, 0x02);
3606 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3607 kvm_rip_write(vcpu, 0xfff0);
3609 kvm_rip_write(vcpu, 0);
3610 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3612 vmcs_writel(GUEST_DR7, 0x400);
3614 vmcs_writel(GUEST_GDTR_BASE, 0);
3615 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3617 vmcs_writel(GUEST_IDTR_BASE, 0);
3618 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3620 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3621 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3622 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3624 /* Special registers */
3625 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3629 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3631 if (cpu_has_vmx_tpr_shadow()) {
3632 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3633 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3634 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3635 __pa(vmx->vcpu.arch.apic->regs));
3636 vmcs_write32(TPR_THRESHOLD, 0);
3639 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3640 vmcs_write64(APIC_ACCESS_ADDR,
3641 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3644 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3646 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3647 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3648 vmx_set_cr4(&vmx->vcpu, 0);
3649 vmx_set_efer(&vmx->vcpu, 0);
3650 vmx_fpu_activate(&vmx->vcpu);
3651 update_exception_bitmap(&vmx->vcpu);
3653 vpid_sync_context(vmx);
3657 /* HACK: Don't enable emulation on guest boot/reset */
3658 vmx->emulation_required = 0;
3664 static void enable_irq_window(struct kvm_vcpu *vcpu)
3666 u32 cpu_based_vm_exec_control;
3668 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3669 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3670 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3673 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3675 u32 cpu_based_vm_exec_control;
3677 if (!cpu_has_virtual_nmis()) {
3678 enable_irq_window(vcpu);
3682 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3683 enable_irq_window(vcpu);
3686 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3687 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3688 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3691 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3693 struct vcpu_vmx *vmx = to_vmx(vcpu);
3695 int irq = vcpu->arch.interrupt.nr;
3697 trace_kvm_inj_virq(irq);
3699 ++vcpu->stat.irq_injections;
3700 if (vmx->rmode.vm86_active) {
3702 if (vcpu->arch.interrupt.soft)
3703 inc_eip = vcpu->arch.event_exit_inst_len;
3704 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3705 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3708 intr = irq | INTR_INFO_VALID_MASK;
3709 if (vcpu->arch.interrupt.soft) {
3710 intr |= INTR_TYPE_SOFT_INTR;
3711 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3712 vmx->vcpu.arch.event_exit_inst_len);
3714 intr |= INTR_TYPE_EXT_INTR;
3715 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3716 vmx_clear_hlt(vcpu);
3719 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3721 struct vcpu_vmx *vmx = to_vmx(vcpu);
3723 if (!cpu_has_virtual_nmis()) {
3725 * Tracking the NMI-blocked state in software is built upon
3726 * finding the next open IRQ window. This, in turn, depends on
3727 * well-behaving guests: They have to keep IRQs disabled at
3728 * least as long as the NMI handler runs. Otherwise we may
3729 * cause NMI nesting, maybe breaking the guest. But as this is
3730 * highly unlikely, we can live with the residual risk.
3732 vmx->soft_vnmi_blocked = 1;
3733 vmx->vnmi_blocked_time = 0;
3736 ++vcpu->stat.nmi_injections;
3737 vmx->nmi_known_unmasked = false;
3738 if (vmx->rmode.vm86_active) {
3739 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3740 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3743 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3744 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3745 vmx_clear_hlt(vcpu);
3748 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3750 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3753 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3754 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3755 | GUEST_INTR_STATE_NMI));
3758 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3760 if (!cpu_has_virtual_nmis())
3761 return to_vmx(vcpu)->soft_vnmi_blocked;
3762 if (to_vmx(vcpu)->nmi_known_unmasked)
3764 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3767 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3769 struct vcpu_vmx *vmx = to_vmx(vcpu);
3771 if (!cpu_has_virtual_nmis()) {
3772 if (vmx->soft_vnmi_blocked != masked) {
3773 vmx->soft_vnmi_blocked = masked;
3774 vmx->vnmi_blocked_time = 0;
3777 vmx->nmi_known_unmasked = !masked;
3779 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3780 GUEST_INTR_STATE_NMI);
3782 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3783 GUEST_INTR_STATE_NMI);
3787 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3789 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3790 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3791 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3794 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3797 struct kvm_userspace_memory_region tss_mem = {
3798 .slot = TSS_PRIVATE_MEMSLOT,
3799 .guest_phys_addr = addr,
3800 .memory_size = PAGE_SIZE * 3,
3804 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3807 kvm->arch.tss_addr = addr;
3808 if (!init_rmode_tss(kvm))
3814 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3815 int vec, u32 err_code)
3818 * Instruction with address size override prefix opcode 0x67
3819 * Cause the #SS fault with 0 error code in VM86 mode.
3821 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3822 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3825 * Forward all other exceptions that are valid in real mode.
3826 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3827 * the required debugging infrastructure rework.
3831 if (vcpu->guest_debug &
3832 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3834 kvm_queue_exception(vcpu, vec);
3838 * Update instruction length as we may reinject the exception
3839 * from user space while in guest debugging mode.
3841 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3842 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3843 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3854 kvm_queue_exception(vcpu, vec);
3861 * Trigger machine check on the host. We assume all the MSRs are already set up
3862 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3863 * We pass a fake environment to the machine check handler because we want
3864 * the guest to be always treated like user space, no matter what context
3865 * it used internally.
3867 static void kvm_machine_check(void)
3869 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3870 struct pt_regs regs = {
3871 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3872 .flags = X86_EFLAGS_IF,
3875 do_machine_check(®s, 0);
3879 static int handle_machine_check(struct kvm_vcpu *vcpu)
3881 /* already handled by vcpu_run */
3885 static int handle_exception(struct kvm_vcpu *vcpu)
3887 struct vcpu_vmx *vmx = to_vmx(vcpu);
3888 struct kvm_run *kvm_run = vcpu->run;
3889 u32 intr_info, ex_no, error_code;
3890 unsigned long cr2, rip, dr6;
3892 enum emulation_result er;
3894 vect_info = vmx->idt_vectoring_info;
3895 intr_info = vmx->exit_intr_info;
3897 if (is_machine_check(intr_info))
3898 return handle_machine_check(vcpu);
3900 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3901 !is_page_fault(intr_info)) {
3902 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3903 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3904 vcpu->run->internal.ndata = 2;
3905 vcpu->run->internal.data[0] = vect_info;
3906 vcpu->run->internal.data[1] = intr_info;
3910 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3911 return 1; /* already handled by vmx_vcpu_run() */
3913 if (is_no_device(intr_info)) {
3914 vmx_fpu_activate(vcpu);
3918 if (is_invalid_opcode(intr_info)) {
3919 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3920 if (er != EMULATE_DONE)
3921 kvm_queue_exception(vcpu, UD_VECTOR);
3926 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3927 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3928 if (is_page_fault(intr_info)) {
3929 /* EPT won't cause page fault directly */
3932 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3933 trace_kvm_page_fault(cr2, error_code);
3935 if (kvm_event_needs_reinjection(vcpu))
3936 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3937 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3940 if (vmx->rmode.vm86_active &&
3941 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3943 if (vcpu->arch.halt_request) {
3944 vcpu->arch.halt_request = 0;
3945 return kvm_emulate_halt(vcpu);
3950 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3953 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3954 if (!(vcpu->guest_debug &
3955 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3956 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3957 kvm_queue_exception(vcpu, DB_VECTOR);
3960 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3961 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3965 * Update instruction length as we may reinject #BP from
3966 * user space while in guest debugging mode. Reading it for
3967 * #DB as well causes no harm, it is not used in that case.
3969 vmx->vcpu.arch.event_exit_inst_len =
3970 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3971 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3972 rip = kvm_rip_read(vcpu);
3973 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3974 kvm_run->debug.arch.exception = ex_no;
3977 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3978 kvm_run->ex.exception = ex_no;
3979 kvm_run->ex.error_code = error_code;
3985 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3987 ++vcpu->stat.irq_exits;
3991 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3993 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3997 static int handle_io(struct kvm_vcpu *vcpu)
3999 unsigned long exit_qualification;
4000 int size, in, string;
4003 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4004 string = (exit_qualification & 16) != 0;
4005 in = (exit_qualification & 8) != 0;
4007 ++vcpu->stat.io_exits;
4010 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4012 port = exit_qualification >> 16;
4013 size = (exit_qualification & 7) + 1;
4014 skip_emulated_instruction(vcpu);
4016 return kvm_fast_pio_out(vcpu, size, port);
4020 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4023 * Patch in the VMCALL instruction:
4025 hypercall[0] = 0x0f;
4026 hypercall[1] = 0x01;
4027 hypercall[2] = 0xc1;
4030 static int handle_cr(struct kvm_vcpu *vcpu)
4032 unsigned long exit_qualification, val;
4037 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4038 cr = exit_qualification & 15;
4039 reg = (exit_qualification >> 8) & 15;
4040 switch ((exit_qualification >> 4) & 3) {
4041 case 0: /* mov to cr */
4042 val = kvm_register_read(vcpu, reg);
4043 trace_kvm_cr_write(cr, val);
4046 err = kvm_set_cr0(vcpu, val);
4047 kvm_complete_insn_gp(vcpu, err);
4050 err = kvm_set_cr3(vcpu, val);
4051 kvm_complete_insn_gp(vcpu, err);
4054 err = kvm_set_cr4(vcpu, val);
4055 kvm_complete_insn_gp(vcpu, err);
4058 u8 cr8_prev = kvm_get_cr8(vcpu);
4059 u8 cr8 = kvm_register_read(vcpu, reg);
4060 err = kvm_set_cr8(vcpu, cr8);
4061 kvm_complete_insn_gp(vcpu, err);
4062 if (irqchip_in_kernel(vcpu->kvm))
4064 if (cr8_prev <= cr8)
4066 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4072 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4073 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4074 skip_emulated_instruction(vcpu);
4075 vmx_fpu_activate(vcpu);
4077 case 1: /*mov from cr*/
4080 val = kvm_read_cr3(vcpu);
4081 kvm_register_write(vcpu, reg, val);
4082 trace_kvm_cr_read(cr, val);
4083 skip_emulated_instruction(vcpu);
4086 val = kvm_get_cr8(vcpu);
4087 kvm_register_write(vcpu, reg, val);
4088 trace_kvm_cr_read(cr, val);
4089 skip_emulated_instruction(vcpu);
4094 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4095 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4096 kvm_lmsw(vcpu, val);
4098 skip_emulated_instruction(vcpu);
4103 vcpu->run->exit_reason = 0;
4104 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4105 (int)(exit_qualification >> 4) & 3, cr);
4109 static int handle_dr(struct kvm_vcpu *vcpu)
4111 unsigned long exit_qualification;
4114 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4115 if (!kvm_require_cpl(vcpu, 0))
4117 dr = vmcs_readl(GUEST_DR7);
4120 * As the vm-exit takes precedence over the debug trap, we
4121 * need to emulate the latter, either for the host or the
4122 * guest debugging itself.
4124 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4125 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4126 vcpu->run->debug.arch.dr7 = dr;
4127 vcpu->run->debug.arch.pc =
4128 vmcs_readl(GUEST_CS_BASE) +
4129 vmcs_readl(GUEST_RIP);
4130 vcpu->run->debug.arch.exception = DB_VECTOR;
4131 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4134 vcpu->arch.dr7 &= ~DR7_GD;
4135 vcpu->arch.dr6 |= DR6_BD;
4136 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4137 kvm_queue_exception(vcpu, DB_VECTOR);
4142 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4143 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4144 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4145 if (exit_qualification & TYPE_MOV_FROM_DR) {
4147 if (!kvm_get_dr(vcpu, dr, &val))
4148 kvm_register_write(vcpu, reg, val);
4150 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4151 skip_emulated_instruction(vcpu);
4155 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4157 vmcs_writel(GUEST_DR7, val);
4160 static int handle_cpuid(struct kvm_vcpu *vcpu)
4162 kvm_emulate_cpuid(vcpu);
4166 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4168 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4171 if (vmx_get_msr(vcpu, ecx, &data)) {
4172 trace_kvm_msr_read_ex(ecx);
4173 kvm_inject_gp(vcpu, 0);
4177 trace_kvm_msr_read(ecx, data);
4179 /* FIXME: handling of bits 32:63 of rax, rdx */
4180 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4181 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4182 skip_emulated_instruction(vcpu);
4186 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4188 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4189 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4190 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4192 if (vmx_set_msr(vcpu, ecx, data) != 0) {
4193 trace_kvm_msr_write_ex(ecx, data);
4194 kvm_inject_gp(vcpu, 0);
4198 trace_kvm_msr_write(ecx, data);
4199 skip_emulated_instruction(vcpu);
4203 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4205 kvm_make_request(KVM_REQ_EVENT, vcpu);
4209 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4211 u32 cpu_based_vm_exec_control;
4213 /* clear pending irq */
4214 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4215 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4216 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4218 kvm_make_request(KVM_REQ_EVENT, vcpu);
4220 ++vcpu->stat.irq_window_exits;
4223 * If the user space waits to inject interrupts, exit as soon as
4226 if (!irqchip_in_kernel(vcpu->kvm) &&
4227 vcpu->run->request_interrupt_window &&
4228 !kvm_cpu_has_interrupt(vcpu)) {
4229 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4235 static int handle_halt(struct kvm_vcpu *vcpu)
4237 skip_emulated_instruction(vcpu);
4238 return kvm_emulate_halt(vcpu);
4241 static int handle_vmcall(struct kvm_vcpu *vcpu)
4243 skip_emulated_instruction(vcpu);
4244 kvm_emulate_hypercall(vcpu);
4248 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
4250 kvm_queue_exception(vcpu, UD_VECTOR);
4254 static int handle_invd(struct kvm_vcpu *vcpu)
4256 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4259 static int handle_invlpg(struct kvm_vcpu *vcpu)
4261 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4263 kvm_mmu_invlpg(vcpu, exit_qualification);
4264 skip_emulated_instruction(vcpu);
4268 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4270 skip_emulated_instruction(vcpu);
4271 kvm_emulate_wbinvd(vcpu);
4275 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4277 u64 new_bv = kvm_read_edx_eax(vcpu);
4278 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4280 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4281 skip_emulated_instruction(vcpu);
4285 static int handle_apic_access(struct kvm_vcpu *vcpu)
4287 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4290 static int handle_task_switch(struct kvm_vcpu *vcpu)
4292 struct vcpu_vmx *vmx = to_vmx(vcpu);
4293 unsigned long exit_qualification;
4294 bool has_error_code = false;
4297 int reason, type, idt_v;
4299 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4300 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4302 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4304 reason = (u32)exit_qualification >> 30;
4305 if (reason == TASK_SWITCH_GATE && idt_v) {
4307 case INTR_TYPE_NMI_INTR:
4308 vcpu->arch.nmi_injected = false;
4309 vmx_set_nmi_mask(vcpu, true);
4311 case INTR_TYPE_EXT_INTR:
4312 case INTR_TYPE_SOFT_INTR:
4313 kvm_clear_interrupt_queue(vcpu);
4315 case INTR_TYPE_HARD_EXCEPTION:
4316 if (vmx->idt_vectoring_info &
4317 VECTORING_INFO_DELIVER_CODE_MASK) {
4318 has_error_code = true;
4320 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4323 case INTR_TYPE_SOFT_EXCEPTION:
4324 kvm_clear_exception_queue(vcpu);
4330 tss_selector = exit_qualification;
4332 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4333 type != INTR_TYPE_EXT_INTR &&
4334 type != INTR_TYPE_NMI_INTR))
4335 skip_emulated_instruction(vcpu);
4337 if (kvm_task_switch(vcpu, tss_selector, reason,
4338 has_error_code, error_code) == EMULATE_FAIL) {
4339 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4340 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4341 vcpu->run->internal.ndata = 0;
4345 /* clear all local breakpoint enable flags */
4346 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4349 * TODO: What about debug traps on tss switch?
4350 * Are we supposed to inject them and update dr6?
4356 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4358 unsigned long exit_qualification;
4362 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4364 if (exit_qualification & (1 << 6)) {
4365 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4369 gla_validity = (exit_qualification >> 7) & 0x3;
4370 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4371 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4372 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4373 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4374 vmcs_readl(GUEST_LINEAR_ADDRESS));
4375 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4376 (long unsigned int)exit_qualification);
4377 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4378 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4382 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4383 trace_kvm_page_fault(gpa, exit_qualification);
4384 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4387 static u64 ept_rsvd_mask(u64 spte, int level)
4392 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4393 mask |= (1ULL << i);
4396 /* bits 7:3 reserved */
4398 else if (level == 2) {
4399 if (spte & (1ULL << 7))
4400 /* 2MB ref, bits 20:12 reserved */
4403 /* bits 6:3 reserved */
4410 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4413 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4415 /* 010b (write-only) */
4416 WARN_ON((spte & 0x7) == 0x2);
4418 /* 110b (write/execute) */
4419 WARN_ON((spte & 0x7) == 0x6);
4421 /* 100b (execute-only) and value not supported by logical processor */
4422 if (!cpu_has_vmx_ept_execute_only())
4423 WARN_ON((spte & 0x7) == 0x4);
4427 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4429 if (rsvd_bits != 0) {
4430 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4431 __func__, rsvd_bits);
4435 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4436 u64 ept_mem_type = (spte & 0x38) >> 3;
4438 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4439 ept_mem_type == 7) {
4440 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4441 __func__, ept_mem_type);
4448 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4454 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4456 printk(KERN_ERR "EPT: Misconfiguration.\n");
4457 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4459 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4461 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4462 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4464 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4465 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4470 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4472 u32 cpu_based_vm_exec_control;
4474 /* clear pending NMI */
4475 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4476 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4477 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4478 ++vcpu->stat.nmi_window_exits;
4479 kvm_make_request(KVM_REQ_EVENT, vcpu);
4484 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4486 struct vcpu_vmx *vmx = to_vmx(vcpu);
4487 enum emulation_result err = EMULATE_DONE;
4490 bool intr_window_requested;
4492 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4493 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4495 while (!guest_state_valid(vcpu)) {
4496 if (intr_window_requested
4497 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4498 return handle_interrupt_window(&vmx->vcpu);
4500 err = emulate_instruction(vcpu, 0);
4502 if (err == EMULATE_DO_MMIO) {
4507 if (err != EMULATE_DONE)
4510 if (signal_pending(current))
4516 vmx->emulation_required = 0;
4522 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4523 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4525 static int handle_pause(struct kvm_vcpu *vcpu)
4527 skip_emulated_instruction(vcpu);
4528 kvm_vcpu_on_spin(vcpu);
4533 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4535 kvm_queue_exception(vcpu, UD_VECTOR);
4540 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4541 * We could reuse a single VMCS for all the L2 guests, but we also want the
4542 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4543 * allows keeping them loaded on the processor, and in the future will allow
4544 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4545 * every entry if they never change.
4546 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4547 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4549 * The following functions allocate and free a vmcs02 in this pool.
4552 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4553 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4555 struct vmcs02_list *item;
4556 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4557 if (item->vmptr == vmx->nested.current_vmptr) {
4558 list_move(&item->list, &vmx->nested.vmcs02_pool);
4559 return &item->vmcs02;
4562 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4563 /* Recycle the least recently used VMCS. */
4564 item = list_entry(vmx->nested.vmcs02_pool.prev,
4565 struct vmcs02_list, list);
4566 item->vmptr = vmx->nested.current_vmptr;
4567 list_move(&item->list, &vmx->nested.vmcs02_pool);
4568 return &item->vmcs02;
4571 /* Create a new VMCS */
4572 item = (struct vmcs02_list *)
4573 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4576 item->vmcs02.vmcs = alloc_vmcs();
4577 if (!item->vmcs02.vmcs) {
4581 loaded_vmcs_init(&item->vmcs02);
4582 item->vmptr = vmx->nested.current_vmptr;
4583 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4584 vmx->nested.vmcs02_num++;
4585 return &item->vmcs02;
4588 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4589 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4591 struct vmcs02_list *item;
4592 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4593 if (item->vmptr == vmptr) {
4594 free_loaded_vmcs(&item->vmcs02);
4595 list_del(&item->list);
4597 vmx->nested.vmcs02_num--;
4603 * Free all VMCSs saved for this vcpu, except the one pointed by
4604 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4605 * currently used, if running L2), and vmcs01 when running L2.
4607 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4609 struct vmcs02_list *item, *n;
4610 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4611 if (vmx->loaded_vmcs != &item->vmcs02)
4612 free_loaded_vmcs(&item->vmcs02);
4613 list_del(&item->list);
4616 vmx->nested.vmcs02_num = 0;
4618 if (vmx->loaded_vmcs != &vmx->vmcs01)
4619 free_loaded_vmcs(&vmx->vmcs01);
4623 * Emulate the VMXON instruction.
4624 * Currently, we just remember that VMX is active, and do not save or even
4625 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4626 * do not currently need to store anything in that guest-allocated memory
4627 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4628 * argument is different from the VMXON pointer (which the spec says they do).
4630 static int handle_vmon(struct kvm_vcpu *vcpu)
4632 struct kvm_segment cs;
4633 struct vcpu_vmx *vmx = to_vmx(vcpu);
4635 /* The Intel VMX Instruction Reference lists a bunch of bits that
4636 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4637 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4638 * Otherwise, we should fail with #UD. We test these now:
4640 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4641 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4642 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4643 kvm_queue_exception(vcpu, UD_VECTOR);
4647 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4648 if (is_long_mode(vcpu) && !cs.l) {
4649 kvm_queue_exception(vcpu, UD_VECTOR);
4653 if (vmx_get_cpl(vcpu)) {
4654 kvm_inject_gp(vcpu, 0);
4658 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4659 vmx->nested.vmcs02_num = 0;
4661 vmx->nested.vmxon = true;
4663 skip_emulated_instruction(vcpu);
4668 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4669 * for running VMX instructions (except VMXON, whose prerequisites are
4670 * slightly different). It also specifies what exception to inject otherwise.
4672 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4674 struct kvm_segment cs;
4675 struct vcpu_vmx *vmx = to_vmx(vcpu);
4677 if (!vmx->nested.vmxon) {
4678 kvm_queue_exception(vcpu, UD_VECTOR);
4682 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4683 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4684 (is_long_mode(vcpu) && !cs.l)) {
4685 kvm_queue_exception(vcpu, UD_VECTOR);
4689 if (vmx_get_cpl(vcpu)) {
4690 kvm_inject_gp(vcpu, 0);
4698 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4699 * just stops using VMX.
4701 static void free_nested(struct vcpu_vmx *vmx)
4703 if (!vmx->nested.vmxon)
4705 vmx->nested.vmxon = false;
4706 if (vmx->nested.current_vmptr != -1ull) {
4707 kunmap(vmx->nested.current_vmcs12_page);
4708 nested_release_page(vmx->nested.current_vmcs12_page);
4709 vmx->nested.current_vmptr = -1ull;
4710 vmx->nested.current_vmcs12 = NULL;
4713 nested_free_all_saved_vmcss(vmx);
4716 /* Emulate the VMXOFF instruction */
4717 static int handle_vmoff(struct kvm_vcpu *vcpu)
4719 if (!nested_vmx_check_permission(vcpu))
4721 free_nested(to_vmx(vcpu));
4722 skip_emulated_instruction(vcpu);
4727 * Decode the memory-address operand of a vmx instruction, as recorded on an
4728 * exit caused by such an instruction (run by a guest hypervisor).
4729 * On success, returns 0. When the operand is invalid, returns 1 and throws
4732 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4733 unsigned long exit_qualification,
4734 u32 vmx_instruction_info, gva_t *ret)
4737 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4738 * Execution", on an exit, vmx_instruction_info holds most of the
4739 * addressing components of the operand. Only the displacement part
4740 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4741 * For how an actual address is calculated from all these components,
4742 * refer to Vol. 1, "Operand Addressing".
4744 int scaling = vmx_instruction_info & 3;
4745 int addr_size = (vmx_instruction_info >> 7) & 7;
4746 bool is_reg = vmx_instruction_info & (1u << 10);
4747 int seg_reg = (vmx_instruction_info >> 15) & 7;
4748 int index_reg = (vmx_instruction_info >> 18) & 0xf;
4749 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4750 int base_reg = (vmx_instruction_info >> 23) & 0xf;
4751 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
4754 kvm_queue_exception(vcpu, UD_VECTOR);
4758 /* Addr = segment_base + offset */
4759 /* offset = base + [index * scale] + displacement */
4760 *ret = vmx_get_segment_base(vcpu, seg_reg);
4762 *ret += kvm_register_read(vcpu, base_reg);
4764 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4765 *ret += exit_qualification; /* holds the displacement */
4767 if (addr_size == 1) /* 32 bit */
4771 * TODO: throw #GP (and return 1) in various cases that the VM*
4772 * instructions require it - e.g., offset beyond segment limit,
4773 * unusable or unreadable/unwritable segment, non-canonical 64-bit
4774 * address, and so on. Currently these are not checked.
4780 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
4781 * set the success or error code of an emulated VMX instruction, as specified
4782 * by Vol 2B, VMX Instruction Reference, "Conventions".
4784 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
4786 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
4787 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4788 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
4791 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
4793 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4794 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
4795 X86_EFLAGS_SF | X86_EFLAGS_OF))
4799 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
4800 u32 vm_instruction_error)
4802 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
4804 * failValid writes the error number to the current VMCS, which
4805 * can't be done there isn't a current VMCS.
4807 nested_vmx_failInvalid(vcpu);
4810 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4811 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4812 X86_EFLAGS_SF | X86_EFLAGS_OF))
4814 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
4818 * The exit handlers return 1 if the exit was handled fully and guest execution
4819 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
4820 * to be done to userspace and return 0.
4822 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
4823 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
4824 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
4825 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
4826 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
4827 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
4828 [EXIT_REASON_CR_ACCESS] = handle_cr,
4829 [EXIT_REASON_DR_ACCESS] = handle_dr,
4830 [EXIT_REASON_CPUID] = handle_cpuid,
4831 [EXIT_REASON_MSR_READ] = handle_rdmsr,
4832 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
4833 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
4834 [EXIT_REASON_HLT] = handle_halt,
4835 [EXIT_REASON_INVD] = handle_invd,
4836 [EXIT_REASON_INVLPG] = handle_invlpg,
4837 [EXIT_REASON_VMCALL] = handle_vmcall,
4838 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
4839 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
4840 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
4841 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
4842 [EXIT_REASON_VMREAD] = handle_vmx_insn,
4843 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
4844 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
4845 [EXIT_REASON_VMOFF] = handle_vmoff,
4846 [EXIT_REASON_VMON] = handle_vmon,
4847 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
4848 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
4849 [EXIT_REASON_WBINVD] = handle_wbinvd,
4850 [EXIT_REASON_XSETBV] = handle_xsetbv,
4851 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
4852 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
4853 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
4854 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4855 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
4856 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
4857 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
4860 static const int kvm_vmx_max_exit_handlers =
4861 ARRAY_SIZE(kvm_vmx_exit_handlers);
4863 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4865 *info1 = vmcs_readl(EXIT_QUALIFICATION);
4866 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
4870 * The guest has exited. See if we can fix it or if we need userspace
4873 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
4875 struct vcpu_vmx *vmx = to_vmx(vcpu);
4876 u32 exit_reason = vmx->exit_reason;
4877 u32 vectoring_info = vmx->idt_vectoring_info;
4879 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
4881 /* If guest state is invalid, start emulating */
4882 if (vmx->emulation_required && emulate_invalid_guest_state)
4883 return handle_invalid_guest_state(vcpu);
4885 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4886 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4887 vcpu->run->fail_entry.hardware_entry_failure_reason
4892 if (unlikely(vmx->fail)) {
4893 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4894 vcpu->run->fail_entry.hardware_entry_failure_reason
4895 = vmcs_read32(VM_INSTRUCTION_ERROR);
4899 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
4900 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
4901 exit_reason != EXIT_REASON_EPT_VIOLATION &&
4902 exit_reason != EXIT_REASON_TASK_SWITCH))
4903 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
4904 "(0x%x) and exit reason is 0x%x\n",
4905 __func__, vectoring_info, exit_reason);
4907 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
4908 if (vmx_interrupt_allowed(vcpu)) {
4909 vmx->soft_vnmi_blocked = 0;
4910 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4911 vcpu->arch.nmi_pending) {
4913 * This CPU don't support us in finding the end of an
4914 * NMI-blocked window if the guest runs with IRQs
4915 * disabled. So we pull the trigger after 1 s of
4916 * futile waiting, but inform the user about this.
4918 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
4919 "state on VCPU %d after 1 s timeout\n",
4920 __func__, vcpu->vcpu_id);
4921 vmx->soft_vnmi_blocked = 0;
4925 if (exit_reason < kvm_vmx_max_exit_handlers
4926 && kvm_vmx_exit_handlers[exit_reason])
4927 return kvm_vmx_exit_handlers[exit_reason](vcpu);
4929 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4930 vcpu->run->hw.hardware_exit_reason = exit_reason;
4935 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4937 if (irr == -1 || tpr < irr) {
4938 vmcs_write32(TPR_THRESHOLD, 0);
4942 vmcs_write32(TPR_THRESHOLD, irr);
4945 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
4949 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
4950 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
4953 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4954 exit_intr_info = vmx->exit_intr_info;
4956 /* Handle machine checks before interrupts are enabled */
4957 if (is_machine_check(exit_intr_info))
4958 kvm_machine_check();
4960 /* We need to handle NMIs before interrupts are enabled */
4961 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
4962 (exit_intr_info & INTR_INFO_VALID_MASK)) {
4963 kvm_before_handle_nmi(&vmx->vcpu);
4965 kvm_after_handle_nmi(&vmx->vcpu);
4969 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
4974 bool idtv_info_valid;
4976 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
4978 if (cpu_has_virtual_nmis()) {
4979 if (vmx->nmi_known_unmasked)
4982 * Can't use vmx->exit_intr_info since we're not sure what
4983 * the exit reason is.
4985 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4986 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
4987 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
4989 * SDM 3: 27.7.1.2 (September 2008)
4990 * Re-set bit "block by NMI" before VM entry if vmexit caused by
4991 * a guest IRET fault.
4992 * SDM 3: 23.2.2 (September 2008)
4993 * Bit 12 is undefined in any of the following cases:
4994 * If the VM exit sets the valid bit in the IDT-vectoring
4995 * information field.
4996 * If the VM exit is due to a double fault.
4998 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
4999 vector != DF_VECTOR && !idtv_info_valid)
5000 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5001 GUEST_INTR_STATE_NMI);
5003 vmx->nmi_known_unmasked =
5004 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5005 & GUEST_INTR_STATE_NMI);
5006 } else if (unlikely(vmx->soft_vnmi_blocked))
5007 vmx->vnmi_blocked_time +=
5008 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5011 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5012 u32 idt_vectoring_info,
5013 int instr_len_field,
5014 int error_code_field)
5018 bool idtv_info_valid;
5020 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5022 vmx->vcpu.arch.nmi_injected = false;
5023 kvm_clear_exception_queue(&vmx->vcpu);
5024 kvm_clear_interrupt_queue(&vmx->vcpu);
5026 if (!idtv_info_valid)
5029 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5031 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5032 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
5035 case INTR_TYPE_NMI_INTR:
5036 vmx->vcpu.arch.nmi_injected = true;
5038 * SDM 3: 27.7.1.2 (September 2008)
5039 * Clear bit "block by NMI" before VM entry if a NMI
5042 vmx_set_nmi_mask(&vmx->vcpu, false);
5044 case INTR_TYPE_SOFT_EXCEPTION:
5045 vmx->vcpu.arch.event_exit_inst_len =
5046 vmcs_read32(instr_len_field);
5048 case INTR_TYPE_HARD_EXCEPTION:
5049 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5050 u32 err = vmcs_read32(error_code_field);
5051 kvm_queue_exception_e(&vmx->vcpu, vector, err);
5053 kvm_queue_exception(&vmx->vcpu, vector);
5055 case INTR_TYPE_SOFT_INTR:
5056 vmx->vcpu.arch.event_exit_inst_len =
5057 vmcs_read32(instr_len_field);
5059 case INTR_TYPE_EXT_INTR:
5060 kvm_queue_interrupt(&vmx->vcpu, vector,
5061 type == INTR_TYPE_SOFT_INTR);
5068 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5070 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5071 VM_EXIT_INSTRUCTION_LEN,
5072 IDT_VECTORING_ERROR_CODE);
5075 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5077 __vmx_complete_interrupts(to_vmx(vcpu),
5078 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5079 VM_ENTRY_INSTRUCTION_LEN,
5080 VM_ENTRY_EXCEPTION_ERROR_CODE);
5082 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5085 #ifdef CONFIG_X86_64
5093 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
5095 struct vcpu_vmx *vmx = to_vmx(vcpu);
5097 /* Record the guest's net vcpu time for enforced NMI injections. */
5098 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5099 vmx->entry_time = ktime_get();
5101 /* Don't enter VMX if guest state is invalid, let the exit handler
5102 start emulation until we arrive back to a valid state */
5103 if (vmx->emulation_required && emulate_invalid_guest_state)
5106 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5107 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5108 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5109 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5111 /* When single-stepping over STI and MOV SS, we must clear the
5112 * corresponding interruptibility bits in the guest state. Otherwise
5113 * vmentry fails as it then expects bit 14 (BS) in pending debug
5114 * exceptions being set, but that's not correct for the guest debugging
5116 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5117 vmx_set_interrupt_shadow(vcpu, 0);
5119 vmx->__launched = vmx->loaded_vmcs->launched;
5121 /* Store host registers */
5122 "push %%"R"dx; push %%"R"bp;"
5123 "push %%"R"cx \n\t" /* placeholder for guest rcx */
5125 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5127 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
5128 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
5130 /* Reload cr2 if changed */
5131 "mov %c[cr2](%0), %%"R"ax \n\t"
5132 "mov %%cr2, %%"R"dx \n\t"
5133 "cmp %%"R"ax, %%"R"dx \n\t"
5135 "mov %%"R"ax, %%cr2 \n\t"
5137 /* Check if vmlaunch of vmresume is needed */
5138 "cmpl $0, %c[launched](%0) \n\t"
5139 /* Load guest registers. Don't clobber flags. */
5140 "mov %c[rax](%0), %%"R"ax \n\t"
5141 "mov %c[rbx](%0), %%"R"bx \n\t"
5142 "mov %c[rdx](%0), %%"R"dx \n\t"
5143 "mov %c[rsi](%0), %%"R"si \n\t"
5144 "mov %c[rdi](%0), %%"R"di \n\t"
5145 "mov %c[rbp](%0), %%"R"bp \n\t"
5146 #ifdef CONFIG_X86_64
5147 "mov %c[r8](%0), %%r8 \n\t"
5148 "mov %c[r9](%0), %%r9 \n\t"
5149 "mov %c[r10](%0), %%r10 \n\t"
5150 "mov %c[r11](%0), %%r11 \n\t"
5151 "mov %c[r12](%0), %%r12 \n\t"
5152 "mov %c[r13](%0), %%r13 \n\t"
5153 "mov %c[r14](%0), %%r14 \n\t"
5154 "mov %c[r15](%0), %%r15 \n\t"
5156 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5158 /* Enter guest mode */
5159 "jne .Llaunched \n\t"
5160 __ex(ASM_VMX_VMLAUNCH) "\n\t"
5161 "jmp .Lkvm_vmx_return \n\t"
5162 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
5163 ".Lkvm_vmx_return: "
5164 /* Save guest registers, load host registers, keep flags */
5165 "mov %0, %c[wordsize](%%"R"sp) \n\t"
5167 "mov %%"R"ax, %c[rax](%0) \n\t"
5168 "mov %%"R"bx, %c[rbx](%0) \n\t"
5169 "pop"Q" %c[rcx](%0) \n\t"
5170 "mov %%"R"dx, %c[rdx](%0) \n\t"
5171 "mov %%"R"si, %c[rsi](%0) \n\t"
5172 "mov %%"R"di, %c[rdi](%0) \n\t"
5173 "mov %%"R"bp, %c[rbp](%0) \n\t"
5174 #ifdef CONFIG_X86_64
5175 "mov %%r8, %c[r8](%0) \n\t"
5176 "mov %%r9, %c[r9](%0) \n\t"
5177 "mov %%r10, %c[r10](%0) \n\t"
5178 "mov %%r11, %c[r11](%0) \n\t"
5179 "mov %%r12, %c[r12](%0) \n\t"
5180 "mov %%r13, %c[r13](%0) \n\t"
5181 "mov %%r14, %c[r14](%0) \n\t"
5182 "mov %%r15, %c[r15](%0) \n\t"
5184 "mov %%cr2, %%"R"ax \n\t"
5185 "mov %%"R"ax, %c[cr2](%0) \n\t"
5187 "pop %%"R"bp; pop %%"R"dx \n\t"
5188 "setbe %c[fail](%0) \n\t"
5189 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
5190 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
5191 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
5192 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
5193 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
5194 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
5195 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
5196 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
5197 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
5198 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
5199 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
5200 #ifdef CONFIG_X86_64
5201 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
5202 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
5203 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
5204 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
5205 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
5206 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
5207 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
5208 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
5210 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
5211 [wordsize]"i"(sizeof(ulong))
5213 , R"ax", R"bx", R"di", R"si"
5214 #ifdef CONFIG_X86_64
5215 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5219 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
5220 | (1 << VCPU_EXREG_RFLAGS)
5221 | (1 << VCPU_EXREG_CPL)
5222 | (1 << VCPU_EXREG_PDPTR)
5223 | (1 << VCPU_EXREG_SEGMENTS)
5224 | (1 << VCPU_EXREG_CR3));
5225 vcpu->arch.regs_dirty = 0;
5227 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
5229 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
5230 vmx->loaded_vmcs->launched = 1;
5232 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
5234 vmx_complete_atomic_exit(vmx);
5235 vmx_recover_nmi_blocking(vmx);
5236 vmx_complete_interrupts(vmx);
5242 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
5244 struct vcpu_vmx *vmx = to_vmx(vcpu);
5248 free_loaded_vmcs(vmx->loaded_vmcs);
5249 kfree(vmx->guest_msrs);
5250 kvm_vcpu_uninit(vcpu);
5251 kmem_cache_free(kvm_vcpu_cache, vmx);
5254 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
5257 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
5261 return ERR_PTR(-ENOMEM);
5265 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
5269 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
5271 if (!vmx->guest_msrs) {
5275 vmx->loaded_vmcs = &vmx->vmcs01;
5276 vmx->loaded_vmcs->vmcs = alloc_vmcs();
5277 if (!vmx->loaded_vmcs->vmcs)
5280 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
5281 loaded_vmcs_init(vmx->loaded_vmcs);
5286 vmx_vcpu_load(&vmx->vcpu, cpu);
5287 vmx->vcpu.cpu = cpu;
5288 err = vmx_vcpu_setup(vmx);
5289 vmx_vcpu_put(&vmx->vcpu);
5293 if (vm_need_virtualize_apic_accesses(kvm))
5294 err = alloc_apic_access_page(kvm);
5299 if (!kvm->arch.ept_identity_map_addr)
5300 kvm->arch.ept_identity_map_addr =
5301 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5303 if (alloc_identity_pagetable(kvm) != 0)
5305 if (!init_rmode_identity_map(kvm))
5309 vmx->nested.current_vmptr = -1ull;
5310 vmx->nested.current_vmcs12 = NULL;
5315 free_vmcs(vmx->loaded_vmcs->vmcs);
5317 kfree(vmx->guest_msrs);
5319 kvm_vcpu_uninit(&vmx->vcpu);
5322 kmem_cache_free(kvm_vcpu_cache, vmx);
5323 return ERR_PTR(err);
5326 static void __init vmx_check_processor_compat(void *rtn)
5328 struct vmcs_config vmcs_conf;
5331 if (setup_vmcs_config(&vmcs_conf) < 0)
5333 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
5334 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
5335 smp_processor_id());
5340 static int get_ept_level(void)
5342 return VMX_EPT_DEFAULT_GAW + 1;
5345 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5349 /* For VT-d and EPT combination
5350 * 1. MMIO: always map as UC
5352 * a. VT-d without snooping control feature: can't guarantee the
5353 * result, try to trust guest.
5354 * b. VT-d with snooping control feature: snooping control feature of
5355 * VT-d engine can guarantee the cache correctness. Just set it
5356 * to WB to keep consistent with host. So the same as item 3.
5357 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
5358 * consistent with host MTRR
5361 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
5362 else if (vcpu->kvm->arch.iommu_domain &&
5363 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
5364 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
5365 VMX_EPT_MT_EPTE_SHIFT;
5367 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
5373 #define _ER(x) { EXIT_REASON_##x, #x }
5375 static const struct trace_print_flags vmx_exit_reasons_str[] = {
5377 _ER(EXTERNAL_INTERRUPT),
5379 _ER(PENDING_INTERRUPT),
5399 _ER(IO_INSTRUCTION),
5402 _ER(MWAIT_INSTRUCTION),
5403 _ER(MONITOR_INSTRUCTION),
5404 _ER(PAUSE_INSTRUCTION),
5405 _ER(MCE_DURING_VMENTRY),
5406 _ER(TPR_BELOW_THRESHOLD),
5416 static int vmx_get_lpage_level(void)
5418 if (enable_ept && !cpu_has_vmx_ept_1g_page())
5419 return PT_DIRECTORY_LEVEL;
5421 /* For shadow and EPT supported 1GB page */
5422 return PT_PDPE_LEVEL;
5425 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
5427 struct kvm_cpuid_entry2 *best;
5428 struct vcpu_vmx *vmx = to_vmx(vcpu);
5431 vmx->rdtscp_enabled = false;
5432 if (vmx_rdtscp_supported()) {
5433 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5434 if (exec_control & SECONDARY_EXEC_RDTSCP) {
5435 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
5436 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
5437 vmx->rdtscp_enabled = true;
5439 exec_control &= ~SECONDARY_EXEC_RDTSCP;
5440 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5447 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5451 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
5452 struct x86_instruction_info *info,
5453 enum x86_intercept_stage stage)
5455 return X86EMUL_CONTINUE;
5458 static struct kvm_x86_ops vmx_x86_ops = {
5459 .cpu_has_kvm_support = cpu_has_kvm_support,
5460 .disabled_by_bios = vmx_disabled_by_bios,
5461 .hardware_setup = hardware_setup,
5462 .hardware_unsetup = hardware_unsetup,
5463 .check_processor_compatibility = vmx_check_processor_compat,
5464 .hardware_enable = hardware_enable,
5465 .hardware_disable = hardware_disable,
5466 .cpu_has_accelerated_tpr = report_flexpriority,
5468 .vcpu_create = vmx_create_vcpu,
5469 .vcpu_free = vmx_free_vcpu,
5470 .vcpu_reset = vmx_vcpu_reset,
5472 .prepare_guest_switch = vmx_save_host_state,
5473 .vcpu_load = vmx_vcpu_load,
5474 .vcpu_put = vmx_vcpu_put,
5476 .set_guest_debug = set_guest_debug,
5477 .get_msr = vmx_get_msr,
5478 .set_msr = vmx_set_msr,
5479 .get_segment_base = vmx_get_segment_base,
5480 .get_segment = vmx_get_segment,
5481 .set_segment = vmx_set_segment,
5482 .get_cpl = vmx_get_cpl,
5483 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
5484 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
5485 .decache_cr3 = vmx_decache_cr3,
5486 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
5487 .set_cr0 = vmx_set_cr0,
5488 .set_cr3 = vmx_set_cr3,
5489 .set_cr4 = vmx_set_cr4,
5490 .set_efer = vmx_set_efer,
5491 .get_idt = vmx_get_idt,
5492 .set_idt = vmx_set_idt,
5493 .get_gdt = vmx_get_gdt,
5494 .set_gdt = vmx_set_gdt,
5495 .set_dr7 = vmx_set_dr7,
5496 .cache_reg = vmx_cache_reg,
5497 .get_rflags = vmx_get_rflags,
5498 .set_rflags = vmx_set_rflags,
5499 .fpu_activate = vmx_fpu_activate,
5500 .fpu_deactivate = vmx_fpu_deactivate,
5502 .tlb_flush = vmx_flush_tlb,
5504 .run = vmx_vcpu_run,
5505 .handle_exit = vmx_handle_exit,
5506 .skip_emulated_instruction = skip_emulated_instruction,
5507 .set_interrupt_shadow = vmx_set_interrupt_shadow,
5508 .get_interrupt_shadow = vmx_get_interrupt_shadow,
5509 .patch_hypercall = vmx_patch_hypercall,
5510 .set_irq = vmx_inject_irq,
5511 .set_nmi = vmx_inject_nmi,
5512 .queue_exception = vmx_queue_exception,
5513 .cancel_injection = vmx_cancel_injection,
5514 .interrupt_allowed = vmx_interrupt_allowed,
5515 .nmi_allowed = vmx_nmi_allowed,
5516 .get_nmi_mask = vmx_get_nmi_mask,
5517 .set_nmi_mask = vmx_set_nmi_mask,
5518 .enable_nmi_window = enable_nmi_window,
5519 .enable_irq_window = enable_irq_window,
5520 .update_cr8_intercept = update_cr8_intercept,
5522 .set_tss_addr = vmx_set_tss_addr,
5523 .get_tdp_level = get_ept_level,
5524 .get_mt_mask = vmx_get_mt_mask,
5526 .get_exit_info = vmx_get_exit_info,
5527 .exit_reasons_str = vmx_exit_reasons_str,
5529 .get_lpage_level = vmx_get_lpage_level,
5531 .cpuid_update = vmx_cpuid_update,
5533 .rdtscp_supported = vmx_rdtscp_supported,
5535 .set_supported_cpuid = vmx_set_supported_cpuid,
5537 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
5539 .set_tsc_khz = vmx_set_tsc_khz,
5540 .write_tsc_offset = vmx_write_tsc_offset,
5541 .adjust_tsc_offset = vmx_adjust_tsc_offset,
5542 .compute_tsc_offset = vmx_compute_tsc_offset,
5544 .set_tdp_cr3 = vmx_set_cr3,
5546 .check_intercept = vmx_check_intercept,
5549 static int __init vmx_init(void)
5553 rdmsrl_safe(MSR_EFER, &host_efer);
5555 for (i = 0; i < NR_VMX_MSR; ++i)
5556 kvm_define_shared_msr(i, vmx_msr_index[i]);
5558 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5559 if (!vmx_io_bitmap_a)
5562 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5563 if (!vmx_io_bitmap_b) {
5568 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5569 if (!vmx_msr_bitmap_legacy) {
5574 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5575 if (!vmx_msr_bitmap_longmode) {
5581 * Allow direct access to the PC debug port (it is often used for I/O
5582 * delays, but the vmexits simply slow things down).
5584 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5585 clear_bit(0x80, vmx_io_bitmap_a);
5587 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5589 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5590 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
5592 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
5594 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
5595 __alignof__(struct vcpu_vmx), THIS_MODULE);
5599 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5600 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5601 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5602 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5603 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5604 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5607 bypass_guest_pf = 0;
5608 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
5609 VMX_EPT_EXECUTABLE_MASK);
5614 if (bypass_guest_pf)
5615 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
5620 free_page((unsigned long)vmx_msr_bitmap_longmode);
5622 free_page((unsigned long)vmx_msr_bitmap_legacy);
5624 free_page((unsigned long)vmx_io_bitmap_b);
5626 free_page((unsigned long)vmx_io_bitmap_a);
5630 static void __exit vmx_exit(void)
5632 free_page((unsigned long)vmx_msr_bitmap_legacy);
5633 free_page((unsigned long)vmx_msr_bitmap_longmode);
5634 free_page((unsigned long)vmx_io_bitmap_b);
5635 free_page((unsigned long)vmx_io_bitmap_a);
5640 module_init(vmx_init)
5641 module_exit(vmx_exit)