arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 104 #define KVM_VM_CR0_ALWAYS_ON                                            \
 105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 108          | X86_CR4_OSXMMEXCPT)
 109
 110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 112
 113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 114
 115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * ple_gap:    upper bound on the amount of time between two successive
 120  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 121  *             According to test, this time is usually smaller than 128 cycles.
 122  * ple_window: upper bound on the amount of time a guest is allowed to execute
 123  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 124  *             less than 2^12 cycles
 125  * Time is measured based on a counter that runs at the same rate as the TSC,
 126  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 127  */
 128 #define KVM_VMX_DEFAULT_PLE_GAP    128
 129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 130 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 131 module_param(ple_gap, int, S_IRUGO);
 132
 133 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 134 module_param(ple_window, int, S_IRUGO);
 135
 136 extern const ulong vmx_return;
 137
 138 #define NR_AUTOLOAD_MSRS 8
 139 #define VMCS02_POOL_SIZE 1
 140
 141 struct vmcs {
 142         u32 revision_id;
 143         u32 abort;
 144         char data[0];
 145 };
 146
 147 /*
 148  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 149  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 150  * loaded on this CPU (so we can clear them if the CPU goes down).
 151  */
 152 struct loaded_vmcs {
 153         struct vmcs *vmcs;
 154         int cpu;
 155         int launched;
 156         struct list_head loaded_vmcss_on_cpu_link;
 157 };
 158
 159 struct shared_msr_entry {
 160         unsigned index;
 161         u64 data;
 162         u64 mask;
 163 };
 164
 165 /*
 166  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 167  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 168  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 169  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 170  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 171  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 172  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 173  * underlying hardware which will be used to run L2.
 174  * This structure is packed to ensure that its layout is identical across
 175  * machines (necessary for live migration).
 176  * If there are changes in this struct, VMCS12_REVISION must be changed.
 177  */
 178 typedef u64 natural_width;
 179 struct __packed vmcs12 {
 180         /* According to the Intel spec, a VMCS region must start with the
 181          * following two fields. Then follow implementation-specific data.
 182          */
 183         u32 revision_id;
 184         u32 abort;
 185
 186         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 187         u32 padding[7]; /* room for future expansion */
 188
 189         u64 io_bitmap_a;
 190         u64 io_bitmap_b;
 191         u64 msr_bitmap;
 192         u64 vm_exit_msr_store_addr;
 193         u64 vm_exit_msr_load_addr;
 194         u64 vm_entry_msr_load_addr;
 195         u64 tsc_offset;
 196         u64 virtual_apic_page_addr;
 197         u64 apic_access_addr;
 198         u64 ept_pointer;
 199         u64 guest_physical_address;
 200         u64 vmcs_link_pointer;
 201         u64 guest_ia32_debugctl;
 202         u64 guest_ia32_pat;
 203         u64 guest_ia32_efer;
 204         u64 guest_ia32_perf_global_ctrl;
 205         u64 guest_pdptr0;
 206         u64 guest_pdptr1;
 207         u64 guest_pdptr2;
 208         u64 guest_pdptr3;
 209         u64 guest_bndcfgs;
 210         u64 host_ia32_pat;
 211         u64 host_ia32_efer;
 212         u64 host_ia32_perf_global_ctrl;
 213         u64 padding64[8]; /* room for future expansion */
 214         /*
 215          * To allow migration of L1 (complete with its L2 guests) between
 216          * machines of different natural widths (32 or 64 bit), we cannot have
 217          * unsigned long fields with no explict size. We use u64 (aliased
 218          * natural_width) instead. Luckily, x86 is little-endian.
 219          */
 220         natural_width cr0_guest_host_mask;
 221         natural_width cr4_guest_host_mask;
 222         natural_width cr0_read_shadow;
 223         natural_width cr4_read_shadow;
 224         natural_width cr3_target_value0;
 225         natural_width cr3_target_value1;
 226         natural_width cr3_target_value2;
 227         natural_width cr3_target_value3;
 228         natural_width exit_qualification;
 229         natural_width guest_linear_address;
 230         natural_width guest_cr0;
 231         natural_width guest_cr3;
 232         natural_width guest_cr4;
 233         natural_width guest_es_base;
 234         natural_width guest_cs_base;
 235         natural_width guest_ss_base;
 236         natural_width guest_ds_base;
 237         natural_width guest_fs_base;
 238         natural_width guest_gs_base;
 239         natural_width guest_ldtr_base;
 240         natural_width guest_tr_base;
 241         natural_width guest_gdtr_base;
 242         natural_width guest_idtr_base;
 243         natural_width guest_dr7;
 244         natural_width guest_rsp;
 245         natural_width guest_rip;
 246         natural_width guest_rflags;
 247         natural_width guest_pending_dbg_exceptions;
 248         natural_width guest_sysenter_esp;
 249         natural_width guest_sysenter_eip;
 250         natural_width host_cr0;
 251         natural_width host_cr3;
 252         natural_width host_cr4;
 253         natural_width host_fs_base;
 254         natural_width host_gs_base;
 255         natural_width host_tr_base;
 256         natural_width host_gdtr_base;
 257         natural_width host_idtr_base;
 258         natural_width host_ia32_sysenter_esp;
 259         natural_width host_ia32_sysenter_eip;
 260         natural_width host_rsp;
 261         natural_width host_rip;
 262         natural_width paddingl[8]; /* room for future expansion */
 263         u32 pin_based_vm_exec_control;
 264         u32 cpu_based_vm_exec_control;
 265         u32 exception_bitmap;
 266         u32 page_fault_error_code_mask;
 267         u32 page_fault_error_code_match;
 268         u32 cr3_target_count;
 269         u32 vm_exit_controls;
 270         u32 vm_exit_msr_store_count;
 271         u32 vm_exit_msr_load_count;
 272         u32 vm_entry_controls;
 273         u32 vm_entry_msr_load_count;
 274         u32 vm_entry_intr_info_field;
 275         u32 vm_entry_exception_error_code;
 276         u32 vm_entry_instruction_len;
 277         u32 tpr_threshold;
 278         u32 secondary_vm_exec_control;
 279         u32 vm_instruction_error;
 280         u32 vm_exit_reason;
 281         u32 vm_exit_intr_info;
 282         u32 vm_exit_intr_error_code;
 283         u32 idt_vectoring_info_field;
 284         u32 idt_vectoring_error_code;
 285         u32 vm_exit_instruction_len;
 286         u32 vmx_instruction_info;
 287         u32 guest_es_limit;
 288         u32 guest_cs_limit;
 289         u32 guest_ss_limit;
 290         u32 guest_ds_limit;
 291         u32 guest_fs_limit;
 292         u32 guest_gs_limit;
 293         u32 guest_ldtr_limit;
 294         u32 guest_tr_limit;
 295         u32 guest_gdtr_limit;
 296         u32 guest_idtr_limit;
 297         u32 guest_es_ar_bytes;
 298         u32 guest_cs_ar_bytes;
 299         u32 guest_ss_ar_bytes;
 300         u32 guest_ds_ar_bytes;
 301         u32 guest_fs_ar_bytes;
 302         u32 guest_gs_ar_bytes;
 303         u32 guest_ldtr_ar_bytes;
 304         u32 guest_tr_ar_bytes;
 305         u32 guest_interruptibility_info;
 306         u32 guest_activity_state;
 307         u32 guest_sysenter_cs;
 308         u32 host_ia32_sysenter_cs;
 309         u32 vmx_preemption_timer_value;
 310         u32 padding32[7]; /* room for future expansion */
 311         u16 virtual_processor_id;
 312         u16 guest_es_selector;
 313         u16 guest_cs_selector;
 314         u16 guest_ss_selector;
 315         u16 guest_ds_selector;
 316         u16 guest_fs_selector;
 317         u16 guest_gs_selector;
 318         u16 guest_ldtr_selector;
 319         u16 guest_tr_selector;
 320         u16 host_es_selector;
 321         u16 host_cs_selector;
 322         u16 host_ss_selector;
 323         u16 host_ds_selector;
 324         u16 host_fs_selector;
 325         u16 host_gs_selector;
 326         u16 host_tr_selector;
 327 };
 328
 329 /*
 330  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 331  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 332  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 333  */
 334 #define VMCS12_REVISION 0x11e57ed0
 335
 336 /*
 337  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 338  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 339  * current implementation, 4K are reserved to avoid future complications.
 340  */
 341 #define VMCS12_SIZE 0x1000
 342
 343 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 344 struct vmcs02_list {
 345         struct list_head list;
 346         gpa_t vmptr;
 347         struct loaded_vmcs vmcs02;
 348 };
 349
 350 /*
 351  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 352  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 353  */
 354 struct nested_vmx {
 355         /* Has the level1 guest done vmxon? */
 356         bool vmxon;
 357
 358         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 359         gpa_t current_vmptr;
 360         /* The host-usable pointer to the above */
 361         struct page *current_vmcs12_page;
 362         struct vmcs12 *current_vmcs12;
 363         struct vmcs *current_shadow_vmcs;
 364         /*
 365          * Indicates if the shadow vmcs must be updated with the
 366          * data hold by vmcs12
 367          */
 368         bool sync_shadow_vmcs;
 369
 370         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 371         struct list_head vmcs02_pool;
 372         int vmcs02_num;
 373         u64 vmcs01_tsc_offset;
 374         /* L2 must run next, and mustn't decide to exit to L1. */
 375         bool nested_run_pending;
 376         /*
 377          * Guest pages referred to in vmcs02 with host-physical pointers, so
 378          * we must keep them pinned while L2 runs.
 379          */
 380         struct page *apic_access_page;
 381         u64 msr_ia32_feature_control;
 382
 383         struct hrtimer preemption_timer;
 384         bool preemption_timer_expired;
 385 };
 386
 387 #define POSTED_INTR_ON  0
 388 /* Posted-Interrupt Descriptor */
 389 struct pi_desc {
 390         u32 pir[8];     /* Posted interrupt requested */
 391         u32 control;    /* bit 0 of control is outstanding notification bit */
 392         u32 rsvd[7];
 393 } __aligned(64);
 394
 395 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 396 {
 397         return test_and_set_bit(POSTED_INTR_ON,
 398                         (unsigned long *)&pi_desc->control);
 399 }
 400
 401 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 402 {
 403         return test_and_clear_bit(POSTED_INTR_ON,
 404                         (unsigned long *)&pi_desc->control);
 405 }
 406
 407 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 408 {
 409         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 410 }
 411
 412 struct vcpu_vmx {
 413         struct kvm_vcpu       vcpu;
 414         unsigned long         host_rsp;
 415         u8                    fail;
 416         u8                    cpl;
 417         bool                  nmi_known_unmasked;
 418         u32                   exit_intr_info;
 419         u32                   idt_vectoring_info;
 420         ulong                 rflags;
 421         struct shared_msr_entry *guest_msrs;
 422         int                   nmsrs;
 423         int                   save_nmsrs;
 424         unsigned long         host_idt_base;
 425 #ifdef CONFIG_X86_64
 426         u64                   msr_host_kernel_gs_base;
 427         u64                   msr_guest_kernel_gs_base;
 428 #endif
 429         u32 vm_entry_controls_shadow;
 430         u32 vm_exit_controls_shadow;
 431         /*
 432          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 433          * non-nested (L1) guest, it always points to vmcs01. For a nested
 434          * guest (L2), it points to a different VMCS.
 435          */
 436         struct loaded_vmcs    vmcs01;
 437         struct loaded_vmcs   *loaded_vmcs;
 438         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 439         struct msr_autoload {
 440                 unsigned nr;
 441                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 442                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 443         } msr_autoload;
 444         struct {
 445                 int           loaded;
 446                 u16           fs_sel, gs_sel, ldt_sel;
 447 #ifdef CONFIG_X86_64
 448                 u16           ds_sel, es_sel;
 449 #endif
 450                 int           gs_ldt_reload_needed;
 451                 int           fs_reload_needed;
 452                 u64           msr_host_bndcfgs;
 453         } host_state;
 454         struct {
 455                 int vm86_active;
 456                 ulong save_rflags;
 457                 struct kvm_segment segs[8];
 458         } rmode;
 459         struct {
 460                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 461                 struct kvm_save_segment {
 462                         u16 selector;
 463                         unsigned long base;
 464                         u32 limit;
 465                         u32 ar;
 466                 } seg[8];
 467         } segment_cache;
 468         int vpid;
 469         bool emulation_required;
 470
 471         /* Support for vnmi-less CPUs */
 472         int soft_vnmi_blocked;
 473         ktime_t entry_time;
 474         s64 vnmi_blocked_time;
 475         u32 exit_reason;
 476
 477         bool rdtscp_enabled;
 478
 479         /* Posted interrupt descriptor */
 480         struct pi_desc pi_desc;
 481
 482         /* Support for a guest hypervisor (nested VMX) */
 483         struct nested_vmx nested;
 484 };
 485
 486 enum segment_cache_field {
 487         SEG_FIELD_SEL = 0,
 488         SEG_FIELD_BASE = 1,
 489         SEG_FIELD_LIMIT = 2,
 490         SEG_FIELD_AR = 3,
 491
 492         SEG_FIELD_NR = 4
 493 };
 494
 495 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 496 {
 497         return container_of(vcpu, struct vcpu_vmx, vcpu);
 498 }
 499
 500 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 501 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 502 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 503                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 504
 505
 506 static const unsigned long shadow_read_only_fields[] = {
 507         /*
 508          * We do NOT shadow fields that are modified when L0
 509          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 510          * VMXON...) executed by L1.
 511          * For example, VM_INSTRUCTION_ERROR is read
 512          * by L1 if a vmx instruction fails (part of the error path).
 513          * Note the code assumes this logic. If for some reason
 514          * we start shadowing these fields then we need to
 515          * force a shadow sync when L0 emulates vmx instructions
 516          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 517          * by nested_vmx_failValid)
 518          */
 519         VM_EXIT_REASON,
 520         VM_EXIT_INTR_INFO,
 521         VM_EXIT_INSTRUCTION_LEN,
 522         IDT_VECTORING_INFO_FIELD,
 523         IDT_VECTORING_ERROR_CODE,
 524         VM_EXIT_INTR_ERROR_CODE,
 525         EXIT_QUALIFICATION,
 526         GUEST_LINEAR_ADDRESS,
 527         GUEST_PHYSICAL_ADDRESS
 528 };
 529 static const int max_shadow_read_only_fields =
 530         ARRAY_SIZE(shadow_read_only_fields);
 531
 532 static const unsigned long shadow_read_write_fields[] = {
 533         GUEST_RIP,
 534         GUEST_RSP,
 535         GUEST_CR0,
 536         GUEST_CR3,
 537         GUEST_CR4,
 538         GUEST_INTERRUPTIBILITY_INFO,
 539         GUEST_RFLAGS,
 540         GUEST_CS_SELECTOR,
 541         GUEST_CS_AR_BYTES,
 542         GUEST_CS_LIMIT,
 543         GUEST_CS_BASE,
 544         GUEST_ES_BASE,
 545         GUEST_BNDCFGS,
 546         CR0_GUEST_HOST_MASK,
 547         CR0_READ_SHADOW,
 548         CR4_READ_SHADOW,
 549         TSC_OFFSET,
 550         EXCEPTION_BITMAP,
 551         CPU_BASED_VM_EXEC_CONTROL,
 552         VM_ENTRY_EXCEPTION_ERROR_CODE,
 553         VM_ENTRY_INTR_INFO_FIELD,
 554         VM_ENTRY_INSTRUCTION_LEN,
 555         VM_ENTRY_EXCEPTION_ERROR_CODE,
 556         HOST_FS_BASE,
 557         HOST_GS_BASE,
 558         HOST_FS_SELECTOR,
 559         HOST_GS_SELECTOR
 560 };
 561 static const int max_shadow_read_write_fields =
 562         ARRAY_SIZE(shadow_read_write_fields);
 563
 564 static const unsigned short vmcs_field_to_offset_table[] = {
 565         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 566         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 567         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 568         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 569         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 570         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 571         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 572         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 573         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 574         FIELD(HOST_ES_SELECTOR, host_es_selector),
 575         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 576         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 577         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 578         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 579         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 580         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 581         FIELD64(IO_BITMAP_A, io_bitmap_a),
 582         FIELD64(IO_BITMAP_B, io_bitmap_b),
 583         FIELD64(MSR_BITMAP, msr_bitmap),
 584         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 585         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 586         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 587         FIELD64(TSC_OFFSET, tsc_offset),
 588         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 589         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 590         FIELD64(EPT_POINTER, ept_pointer),
 591         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 592         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 593         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 594         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 595         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 596         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 597         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 598         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 599         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 600         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 601         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 602         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 603         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 604         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 605         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 606         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 607         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 608         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 609         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 610         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 611         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 612         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 613         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 614         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 615         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 616         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 617         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 618         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 619         FIELD(TPR_THRESHOLD, tpr_threshold),
 620         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 621         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 622         FIELD(VM_EXIT_REASON, vm_exit_reason),
 623         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 624         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 625         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 626         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 627         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 628         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 629         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 630         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 631         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 632         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 633         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 634         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 635         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 636         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 637         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 638         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 639         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 640         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 641         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 642         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 643         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 644         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 645         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 646         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 647         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 648         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 649         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 650         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 651         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 652         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 653         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 654         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 655         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 656         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 657         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 658         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 659         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 660         FIELD(EXIT_QUALIFICATION, exit_qualification),
 661         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 662         FIELD(GUEST_CR0, guest_cr0),
 663         FIELD(GUEST_CR3, guest_cr3),
 664         FIELD(GUEST_CR4, guest_cr4),
 665         FIELD(GUEST_ES_BASE, guest_es_base),
 666         FIELD(GUEST_CS_BASE, guest_cs_base),
 667         FIELD(GUEST_SS_BASE, guest_ss_base),
 668         FIELD(GUEST_DS_BASE, guest_ds_base),
 669         FIELD(GUEST_FS_BASE, guest_fs_base),
 670         FIELD(GUEST_GS_BASE, guest_gs_base),
 671         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 672         FIELD(GUEST_TR_BASE, guest_tr_base),
 673         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 674         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 675         FIELD(GUEST_DR7, guest_dr7),
 676         FIELD(GUEST_RSP, guest_rsp),
 677         FIELD(GUEST_RIP, guest_rip),
 678         FIELD(GUEST_RFLAGS, guest_rflags),
 679         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 680         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 681         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 682         FIELD(HOST_CR0, host_cr0),
 683         FIELD(HOST_CR3, host_cr3),
 684         FIELD(HOST_CR4, host_cr4),
 685         FIELD(HOST_FS_BASE, host_fs_base),
 686         FIELD(HOST_GS_BASE, host_gs_base),
 687         FIELD(HOST_TR_BASE, host_tr_base),
 688         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 689         FIELD(HOST_IDTR_BASE, host_idtr_base),
 690         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 691         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 692         FIELD(HOST_RSP, host_rsp),
 693         FIELD(HOST_RIP, host_rip),
 694 };
 695 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 696
 697 static inline short vmcs_field_to_offset(unsigned long field)
 698 {
 699         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 700                 return -1;
 701         return vmcs_field_to_offset_table[field];
 702 }
 703
 704 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 705 {
 706         return to_vmx(vcpu)->nested.current_vmcs12;
 707 }
 708
 709 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 710 {
 711         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 712         if (is_error_page(page))
 713                 return NULL;
 714
 715         return page;
 716 }
 717
 718 static void nested_release_page(struct page *page)
 719 {
 720         kvm_release_page_dirty(page);
 721 }
 722
 723 static void nested_release_page_clean(struct page *page)
 724 {
 725         kvm_release_page_clean(page);
 726 }
 727
 728 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 729 static u64 construct_eptp(unsigned long root_hpa);
 730 static void kvm_cpu_vmxon(u64 addr);
 731 static void kvm_cpu_vmxoff(void);
 732 static bool vmx_mpx_supported(void);
 733 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 734 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 735                             struct kvm_segment *var, int seg);
 736 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 737                             struct kvm_segment *var, int seg);
 738 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 739 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 740 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 741 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 742 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 743 static bool vmx_mpx_supported(void);
 744
 745 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 746 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 747 /*
 748  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 749  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 750  */
 751 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 752 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 753
 754 static unsigned long *vmx_io_bitmap_a;
 755 static unsigned long *vmx_io_bitmap_b;
 756 static unsigned long *vmx_msr_bitmap_legacy;
 757 static unsigned long *vmx_msr_bitmap_longmode;
 758 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 759 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 760 static unsigned long *vmx_vmread_bitmap;
 761 static unsigned long *vmx_vmwrite_bitmap;
 762
 763 static bool cpu_has_load_ia32_efer;
 764 static bool cpu_has_load_perf_global_ctrl;
 765
 766 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 767 static DEFINE_SPINLOCK(vmx_vpid_lock);
 768
 769 static struct vmcs_config {
 770         int size;
 771         int order;
 772         u32 revision_id;
 773         u32 pin_based_exec_ctrl;
 774         u32 cpu_based_exec_ctrl;
 775         u32 cpu_based_2nd_exec_ctrl;
 776         u32 vmexit_ctrl;
 777         u32 vmentry_ctrl;
 778 } vmcs_config;
 779
 780 static struct vmx_capability {
 781         u32 ept;
 782         u32 vpid;
 783 } vmx_capability;
 784
 785 #define VMX_SEGMENT_FIELD(seg)                                  \
 786         [VCPU_SREG_##seg] = {                                   \
 787                 .selector = GUEST_##seg##_SELECTOR,             \
 788                 .base = GUEST_##seg##_BASE,                     \
 789                 .limit = GUEST_##seg##_LIMIT,                   \
 790                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 791         }
 792
 793 static const struct kvm_vmx_segment_field {
 794         unsigned selector;
 795         unsigned base;
 796         unsigned limit;
 797         unsigned ar_bytes;
 798 } kvm_vmx_segment_fields[] = {
 799         VMX_SEGMENT_FIELD(CS),
 800         VMX_SEGMENT_FIELD(DS),
 801         VMX_SEGMENT_FIELD(ES),
 802         VMX_SEGMENT_FIELD(FS),
 803         VMX_SEGMENT_FIELD(GS),
 804         VMX_SEGMENT_FIELD(SS),
 805         VMX_SEGMENT_FIELD(TR),
 806         VMX_SEGMENT_FIELD(LDTR),
 807 };
 808
 809 static u64 host_efer;
 810
 811 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 812
 813 /*
 814  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 815  * away by decrementing the array size.
 816  */
 817 static const u32 vmx_msr_index[] = {
 818 #ifdef CONFIG_X86_64
 819         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 820 #endif
 821         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 822 };
 823 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 824
 825 static inline bool is_page_fault(u32 intr_info)
 826 {
 827         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 828                              INTR_INFO_VALID_MASK)) ==
 829                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 830 }
 831
 832 static inline bool is_no_device(u32 intr_info)
 833 {
 834         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 835                              INTR_INFO_VALID_MASK)) ==
 836                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 837 }
 838
 839 static inline bool is_invalid_opcode(u32 intr_info)
 840 {
 841         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 842                              INTR_INFO_VALID_MASK)) ==
 843                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 844 }
 845
 846 static inline bool is_external_interrupt(u32 intr_info)
 847 {
 848         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 849                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 850 }
 851
 852 static inline bool is_machine_check(u32 intr_info)
 853 {
 854         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 855                              INTR_INFO_VALID_MASK)) ==
 856                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 857 }
 858
 859 static inline bool cpu_has_vmx_msr_bitmap(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 862 }
 863
 864 static inline bool cpu_has_vmx_tpr_shadow(void)
 865 {
 866         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 867 }
 868
 869 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 870 {
 871         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 872 }
 873
 874 static inline bool cpu_has_secondary_exec_ctrls(void)
 875 {
 876         return vmcs_config.cpu_based_exec_ctrl &
 877                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 878 }
 879
 880 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 881 {
 882         return vmcs_config.cpu_based_2nd_exec_ctrl &
 883                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 884 }
 885
 886 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 887 {
 888         return vmcs_config.cpu_based_2nd_exec_ctrl &
 889                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 890 }
 891
 892 static inline bool cpu_has_vmx_apic_register_virt(void)
 893 {
 894         return vmcs_config.cpu_based_2nd_exec_ctrl &
 895                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 896 }
 897
 898 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 899 {
 900         return vmcs_config.cpu_based_2nd_exec_ctrl &
 901                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 902 }
 903
 904 static inline bool cpu_has_vmx_posted_intr(void)
 905 {
 906         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 907 }
 908
 909 static inline bool cpu_has_vmx_apicv(void)
 910 {
 911         return cpu_has_vmx_apic_register_virt() &&
 912                 cpu_has_vmx_virtual_intr_delivery() &&
 913                 cpu_has_vmx_posted_intr();
 914 }
 915
 916 static inline bool cpu_has_vmx_flexpriority(void)
 917 {
 918         return cpu_has_vmx_tpr_shadow() &&
 919                 cpu_has_vmx_virtualize_apic_accesses();
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_execute_only(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 928 {
 929         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_eptp_writeback(void)
 933 {
 934         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_2m_page(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_ept_1g_page(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_ept_4levels(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_ept_ad_bits(void)
 953 {
 954         return vmx_capability.ept & VMX_EPT_AD_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invept_context(void)
 958 {
 959         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_invept_global(void)
 963 {
 964         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 965 }
 966
 967 static inline bool cpu_has_vmx_invvpid_single(void)
 968 {
 969         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 970 }
 971
 972 static inline bool cpu_has_vmx_invvpid_global(void)
 973 {
 974         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 975 }
 976
 977 static inline bool cpu_has_vmx_ept(void)
 978 {
 979         return vmcs_config.cpu_based_2nd_exec_ctrl &
 980                 SECONDARY_EXEC_ENABLE_EPT;
 981 }
 982
 983 static inline bool cpu_has_vmx_unrestricted_guest(void)
 984 {
 985         return vmcs_config.cpu_based_2nd_exec_ctrl &
 986                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 987 }
 988
 989 static inline bool cpu_has_vmx_ple(void)
 990 {
 991         return vmcs_config.cpu_based_2nd_exec_ctrl &
 992                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 993 }
 994
 995 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 996 {
 997         return flexpriority_enabled && irqchip_in_kernel(kvm);
 998 }
 999
1000 static inline bool cpu_has_vmx_vpid(void)
1001 {
1002         return vmcs_config.cpu_based_2nd_exec_ctrl &
1003                 SECONDARY_EXEC_ENABLE_VPID;
1004 }
1005
1006 static inline bool cpu_has_vmx_rdtscp(void)
1007 {
1008         return vmcs_config.cpu_based_2nd_exec_ctrl &
1009                 SECONDARY_EXEC_RDTSCP;
1010 }
1011
1012 static inline bool cpu_has_vmx_invpcid(void)
1013 {
1014         return vmcs_config.cpu_based_2nd_exec_ctrl &
1015                 SECONDARY_EXEC_ENABLE_INVPCID;
1016 }
1017
1018 static inline bool cpu_has_virtual_nmis(void)
1019 {
1020         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1021 }
1022
1023 static inline bool cpu_has_vmx_wbinvd_exit(void)
1024 {
1025         return vmcs_config.cpu_based_2nd_exec_ctrl &
1026                 SECONDARY_EXEC_WBINVD_EXITING;
1027 }
1028
1029 static inline bool cpu_has_vmx_shadow_vmcs(void)
1030 {
1031         u64 vmx_msr;
1032         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1033         /* check if the cpu supports writing r/o exit information fields */
1034         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1035                 return false;
1036
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_SHADOW_VMCS;
1039 }
1040
1041 static inline bool report_flexpriority(void)
1042 {
1043         return flexpriority_enabled;
1044 }
1045
1046 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1047 {
1048         return vmcs12->cpu_based_vm_exec_control & bit;
1049 }
1050
1051 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1052 {
1053         return (vmcs12->cpu_based_vm_exec_control &
1054                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1055                 (vmcs12->secondary_vm_exec_control & bit);
1056 }
1057
1058 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1059 {
1060         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1061 }
1062
1063 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1064 {
1065         return vmcs12->pin_based_vm_exec_control &
1066                 PIN_BASED_VMX_PREEMPTION_TIMER;
1067 }
1068
1069 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1070 {
1071         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1072 }
1073
1074 static inline bool is_exception(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1078 }
1079
1080 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1081                               u32 exit_intr_info,
1082                               unsigned long exit_qualification);
1083 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1084                         struct vmcs12 *vmcs12,
1085                         u32 reason, unsigned long qualification);
1086
1087 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1088 {
1089         int i;
1090
1091         for (i = 0; i < vmx->nmsrs; ++i)
1092                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1093                         return i;
1094         return -1;
1095 }
1096
1097 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1098 {
1099     struct {
1100         u64 vpid : 16;
1101         u64 rsvd : 48;
1102         u64 gva;
1103     } operand = { vpid, 0, gva };
1104
1105     asm volatile (__ex(ASM_VMX_INVVPID)
1106                   /* CF==1 or ZF==1 --> rc = -1 */
1107                   "; ja 1f ; ud2 ; 1:"
1108                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1109 }
1110
1111 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1112 {
1113         struct {
1114                 u64 eptp, gpa;
1115         } operand = {eptp, gpa};
1116
1117         asm volatile (__ex(ASM_VMX_INVEPT)
1118                         /* CF==1 or ZF==1 --> rc = -1 */
1119                         "; ja 1f ; ud2 ; 1:\n"
1120                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1121 }
1122
1123 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1124 {
1125         int i;
1126
1127         i = __find_msr_index(vmx, msr);
1128         if (i >= 0)
1129                 return &vmx->guest_msrs[i];
1130         return NULL;
1131 }
1132
1133 static void vmcs_clear(struct vmcs *vmcs)
1134 {
1135         u64 phys_addr = __pa(vmcs);
1136         u8 error;
1137
1138         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1139                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1140                       : "cc", "memory");
1141         if (error)
1142                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1143                        vmcs, phys_addr);
1144 }
1145
1146 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1147 {
1148         vmcs_clear(loaded_vmcs->vmcs);
1149         loaded_vmcs->cpu = -1;
1150         loaded_vmcs->launched = 0;
1151 }
1152
1153 static void vmcs_load(struct vmcs *vmcs)
1154 {
1155         u64 phys_addr = __pa(vmcs);
1156         u8 error;
1157
1158         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1159                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1160                         : "cc", "memory");
1161         if (error)
1162                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1163                        vmcs, phys_addr);
1164 }
1165
1166 #ifdef CONFIG_KEXEC
1167 /*
1168  * This bitmap is used to indicate whether the vmclear
1169  * operation is enabled on all cpus. All disabled by
1170  * default.
1171  */
1172 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1173
1174 static inline void crash_enable_local_vmclear(int cpu)
1175 {
1176         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177 }
1178
1179 static inline void crash_disable_local_vmclear(int cpu)
1180 {
1181         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182 }
1183
1184 static inline int crash_local_vmclear_enabled(int cpu)
1185 {
1186         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1187 }
1188
1189 static void crash_vmclear_local_loaded_vmcss(void)
1190 {
1191         int cpu = raw_smp_processor_id();
1192         struct loaded_vmcs *v;
1193
1194         if (!crash_local_vmclear_enabled(cpu))
1195                 return;
1196
1197         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1198                             loaded_vmcss_on_cpu_link)
1199                 vmcs_clear(v->vmcs);
1200 }
1201 #else
1202 static inline void crash_enable_local_vmclear(int cpu) { }
1203 static inline void crash_disable_local_vmclear(int cpu) { }
1204 #endif /* CONFIG_KEXEC */
1205
1206 static void __loaded_vmcs_clear(void *arg)
1207 {
1208         struct loaded_vmcs *loaded_vmcs = arg;
1209         int cpu = raw_smp_processor_id();
1210
1211         if (loaded_vmcs->cpu != cpu)
1212                 return; /* vcpu migration can race with cpu offline */
1213         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1214                 per_cpu(current_vmcs, cpu) = NULL;
1215         crash_disable_local_vmclear(cpu);
1216         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1217
1218         /*
1219          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220          * is before setting loaded_vmcs->vcpu to -1 which is done in
1221          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222          * then adds the vmcs into percpu list before it is deleted.
1223          */
1224         smp_wmb();
1225
1226         loaded_vmcs_init(loaded_vmcs);
1227         crash_enable_local_vmclear(cpu);
1228 }
1229
1230 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1231 {
1232         int cpu = loaded_vmcs->cpu;
1233
1234         if (cpu != -1)
1235                 smp_call_function_single(cpu,
1236                          __loaded_vmcs_clear, loaded_vmcs, 1);
1237 }
1238
1239 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1240 {
1241         if (vmx->vpid == 0)
1242                 return;
1243
1244         if (cpu_has_vmx_invvpid_single())
1245                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1246 }
1247
1248 static inline void vpid_sync_vcpu_global(void)
1249 {
1250         if (cpu_has_vmx_invvpid_global())
1251                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1252 }
1253
1254 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1255 {
1256         if (cpu_has_vmx_invvpid_single())
1257                 vpid_sync_vcpu_single(vmx);
1258         else
1259                 vpid_sync_vcpu_global();
1260 }
1261
1262 static inline void ept_sync_global(void)
1263 {
1264         if (cpu_has_vmx_invept_global())
1265                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1266 }
1267
1268 static inline void ept_sync_context(u64 eptp)
1269 {
1270         if (enable_ept) {
1271                 if (cpu_has_vmx_invept_context())
1272                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1273                 else
1274                         ept_sync_global();
1275         }
1276 }
1277
1278 static __always_inline unsigned long vmcs_readl(unsigned long field)
1279 {
1280         unsigned long value;
1281
1282         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1283                       : "=a"(value) : "d"(field) : "cc");
1284         return value;
1285 }
1286
1287 static __always_inline u16 vmcs_read16(unsigned long field)
1288 {
1289         return vmcs_readl(field);
1290 }
1291
1292 static __always_inline u32 vmcs_read32(unsigned long field)
1293 {
1294         return vmcs_readl(field);
1295 }
1296
1297 static __always_inline u64 vmcs_read64(unsigned long field)
1298 {
1299 #ifdef CONFIG_X86_64
1300         return vmcs_readl(field);
1301 #else
1302         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1303 #endif
1304 }
1305
1306 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1307 {
1308         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1309                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1310         dump_stack();
1311 }
1312
1313 static void vmcs_writel(unsigned long field, unsigned long value)
1314 {
1315         u8 error;
1316
1317         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1318                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1319         if (unlikely(error))
1320                 vmwrite_error(field, value);
1321 }
1322
1323 static void vmcs_write16(unsigned long field, u16 value)
1324 {
1325         vmcs_writel(field, value);
1326 }
1327
1328 static void vmcs_write32(unsigned long field, u32 value)
1329 {
1330         vmcs_writel(field, value);
1331 }
1332
1333 static void vmcs_write64(unsigned long field, u64 value)
1334 {
1335         vmcs_writel(field, value);
1336 #ifndef CONFIG_X86_64
1337         asm volatile ("");
1338         vmcs_writel(field+1, value >> 32);
1339 #endif
1340 }
1341
1342 static void vmcs_clear_bits(unsigned long field, u32 mask)
1343 {
1344         vmcs_writel(field, vmcs_readl(field) & ~mask);
1345 }
1346
1347 static void vmcs_set_bits(unsigned long field, u32 mask)
1348 {
1349         vmcs_writel(field, vmcs_readl(field) | mask);
1350 }
1351
1352 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1353 {
1354         vmcs_write32(VM_ENTRY_CONTROLS, val);
1355         vmx->vm_entry_controls_shadow = val;
1356 }
1357
1358 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1359 {
1360         if (vmx->vm_entry_controls_shadow != val)
1361                 vm_entry_controls_init(vmx, val);
1362 }
1363
1364 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1365 {
1366         return vmx->vm_entry_controls_shadow;
1367 }
1368
1369
1370 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1371 {
1372         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1373 }
1374
1375 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1376 {
1377         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1378 }
1379
1380 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1381 {
1382         vmcs_write32(VM_EXIT_CONTROLS, val);
1383         vmx->vm_exit_controls_shadow = val;
1384 }
1385
1386 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1387 {
1388         if (vmx->vm_exit_controls_shadow != val)
1389                 vm_exit_controls_init(vmx, val);
1390 }
1391
1392 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1393 {
1394         return vmx->vm_exit_controls_shadow;
1395 }
1396
1397
1398 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1399 {
1400         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1401 }
1402
1403 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1404 {
1405         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1406 }
1407
1408 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1409 {
1410         vmx->segment_cache.bitmask = 0;
1411 }
1412
1413 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1414                                        unsigned field)
1415 {
1416         bool ret;
1417         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1418
1419         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1420                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1421                 vmx->segment_cache.bitmask = 0;
1422         }
1423         ret = vmx->segment_cache.bitmask & mask;
1424         vmx->segment_cache.bitmask |= mask;
1425         return ret;
1426 }
1427
1428 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1429 {
1430         u16 *p = &vmx->segment_cache.seg[seg].selector;
1431
1432         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1433                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1434         return *p;
1435 }
1436
1437 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1438 {
1439         ulong *p = &vmx->segment_cache.seg[seg].base;
1440
1441         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1442                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1443         return *p;
1444 }
1445
1446 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1447 {
1448         u32 *p = &vmx->segment_cache.seg[seg].limit;
1449
1450         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1451                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1452         return *p;
1453 }
1454
1455 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1456 {
1457         u32 *p = &vmx->segment_cache.seg[seg].ar;
1458
1459         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1460                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1461         return *p;
1462 }
1463
1464 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1465 {
1466         u32 eb;
1467
1468         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1469              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1470         if ((vcpu->guest_debug &
1471              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1472             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1473                 eb |= 1u << BP_VECTOR;
1474         if (to_vmx(vcpu)->rmode.vm86_active)
1475                 eb = ~0;
1476         if (enable_ept)
1477                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1478         if (vcpu->fpu_active)
1479                 eb &= ~(1u << NM_VECTOR);
1480
1481         /* When we are running a nested L2 guest and L1 specified for it a
1482          * certain exception bitmap, we must trap the same exceptions and pass
1483          * them to L1. When running L2, we will only handle the exceptions
1484          * specified above if L1 did not want them.
1485          */
1486         if (is_guest_mode(vcpu))
1487                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1488
1489         vmcs_write32(EXCEPTION_BITMAP, eb);
1490 }
1491
1492 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1493                 unsigned long entry, unsigned long exit)
1494 {
1495         vm_entry_controls_clearbit(vmx, entry);
1496         vm_exit_controls_clearbit(vmx, exit);
1497 }
1498
1499 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1500 {
1501         unsigned i;
1502         struct msr_autoload *m = &vmx->msr_autoload;
1503
1504         switch (msr) {
1505         case MSR_EFER:
1506                 if (cpu_has_load_ia32_efer) {
1507                         clear_atomic_switch_msr_special(vmx,
1508                                         VM_ENTRY_LOAD_IA32_EFER,
1509                                         VM_EXIT_LOAD_IA32_EFER);
1510                         return;
1511                 }
1512                 break;
1513         case MSR_CORE_PERF_GLOBAL_CTRL:
1514                 if (cpu_has_load_perf_global_ctrl) {
1515                         clear_atomic_switch_msr_special(vmx,
1516                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1517                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1518                         return;
1519                 }
1520                 break;
1521         }
1522
1523         for (i = 0; i < m->nr; ++i)
1524                 if (m->guest[i].index == msr)
1525                         break;
1526
1527         if (i == m->nr)
1528                 return;
1529         --m->nr;
1530         m->guest[i] = m->guest[m->nr];
1531         m->host[i] = m->host[m->nr];
1532         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1533         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1534 }
1535
1536 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1537                 unsigned long entry, unsigned long exit,
1538                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1539                 u64 guest_val, u64 host_val)
1540 {
1541         vmcs_write64(guest_val_vmcs, guest_val);
1542         vmcs_write64(host_val_vmcs, host_val);
1543         vm_entry_controls_setbit(vmx, entry);
1544         vm_exit_controls_setbit(vmx, exit);
1545 }
1546
1547 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1548                                   u64 guest_val, u64 host_val)
1549 {
1550         unsigned i;
1551         struct msr_autoload *m = &vmx->msr_autoload;
1552
1553         switch (msr) {
1554         case MSR_EFER:
1555                 if (cpu_has_load_ia32_efer) {
1556                         add_atomic_switch_msr_special(vmx,
1557                                         VM_ENTRY_LOAD_IA32_EFER,
1558                                         VM_EXIT_LOAD_IA32_EFER,
1559                                         GUEST_IA32_EFER,
1560                                         HOST_IA32_EFER,
1561                                         guest_val, host_val);
1562                         return;
1563                 }
1564                 break;
1565         case MSR_CORE_PERF_GLOBAL_CTRL:
1566                 if (cpu_has_load_perf_global_ctrl) {
1567                         add_atomic_switch_msr_special(vmx,
1568                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1569                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1570                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1571                                         HOST_IA32_PERF_GLOBAL_CTRL,
1572                                         guest_val, host_val);
1573                         return;
1574                 }
1575                 break;
1576         }
1577
1578         for (i = 0; i < m->nr; ++i)
1579                 if (m->guest[i].index == msr)
1580                         break;
1581
1582         if (i == NR_AUTOLOAD_MSRS) {
1583                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1584                                 "Can't add msr %x\n", msr);
1585                 return;
1586         } else if (i == m->nr) {
1587                 ++m->nr;
1588                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1589                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1590         }
1591
1592         m->guest[i].index = msr;
1593         m->guest[i].value = guest_val;
1594         m->host[i].index = msr;
1595         m->host[i].value = host_val;
1596 }
1597
1598 static void reload_tss(void)
1599 {
1600         /*
1601          * VT restores TR but not its size.  Useless.
1602          */
1603         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1604         struct desc_struct *descs;
1605
1606         descs = (void *)gdt->address;
1607         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1608         load_TR_desc();
1609 }
1610
1611 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1612 {
1613         u64 guest_efer;
1614         u64 ignore_bits;
1615
1616         guest_efer = vmx->vcpu.arch.efer;
1617
1618         /*
1619          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1620          * outside long mode
1621          */
1622         ignore_bits = EFER_NX | EFER_SCE;
1623 #ifdef CONFIG_X86_64
1624         ignore_bits |= EFER_LMA | EFER_LME;
1625         /* SCE is meaningful only in long mode on Intel */
1626         if (guest_efer & EFER_LMA)
1627                 ignore_bits &= ~(u64)EFER_SCE;
1628 #endif
1629         guest_efer &= ~ignore_bits;
1630         guest_efer |= host_efer & ignore_bits;
1631         vmx->guest_msrs[efer_offset].data = guest_efer;
1632         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1633
1634         clear_atomic_switch_msr(vmx, MSR_EFER);
1635         /* On ept, can't emulate nx, and must switch nx atomically */
1636         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1637                 guest_efer = vmx->vcpu.arch.efer;
1638                 if (!(guest_efer & EFER_LMA))
1639                         guest_efer &= ~EFER_LME;
1640                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1641                 return false;
1642         }
1643
1644         return true;
1645 }
1646
1647 static unsigned long segment_base(u16 selector)
1648 {
1649         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1650         struct desc_struct *d;
1651         unsigned long table_base;
1652         unsigned long v;
1653
1654         if (!(selector & ~3))
1655                 return 0;
1656
1657         table_base = gdt->address;
1658
1659         if (selector & 4) {           /* from ldt */
1660                 u16 ldt_selector = kvm_read_ldt();
1661
1662                 if (!(ldt_selector & ~3))
1663                         return 0;
1664
1665                 table_base = segment_base(ldt_selector);
1666         }
1667         d = (struct desc_struct *)(table_base + (selector & ~7));
1668         v = get_desc_base(d);
1669 #ifdef CONFIG_X86_64
1670        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1671                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1672 #endif
1673         return v;
1674 }
1675
1676 static inline unsigned long kvm_read_tr_base(void)
1677 {
1678         u16 tr;
1679         asm("str %0" : "=g"(tr));
1680         return segment_base(tr);
1681 }
1682
1683 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1684 {
1685         struct vcpu_vmx *vmx = to_vmx(vcpu);
1686         int i;
1687
1688         if (vmx->host_state.loaded)
1689                 return;
1690
1691         vmx->host_state.loaded = 1;
1692         /*
1693          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1694          * allow segment selectors with cpl > 0 or ti == 1.
1695          */
1696         vmx->host_state.ldt_sel = kvm_read_ldt();
1697         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1698         savesegment(fs, vmx->host_state.fs_sel);
1699         if (!(vmx->host_state.fs_sel & 7)) {
1700                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1701                 vmx->host_state.fs_reload_needed = 0;
1702         } else {
1703                 vmcs_write16(HOST_FS_SELECTOR, 0);
1704                 vmx->host_state.fs_reload_needed = 1;
1705         }
1706         savesegment(gs, vmx->host_state.gs_sel);
1707         if (!(vmx->host_state.gs_sel & 7))
1708                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1709         else {
1710                 vmcs_write16(HOST_GS_SELECTOR, 0);
1711                 vmx->host_state.gs_ldt_reload_needed = 1;
1712         }
1713
1714 #ifdef CONFIG_X86_64
1715         savesegment(ds, vmx->host_state.ds_sel);
1716         savesegment(es, vmx->host_state.es_sel);
1717 #endif
1718
1719 #ifdef CONFIG_X86_64
1720         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1721         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1722 #else
1723         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1724         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1725 #endif
1726
1727 #ifdef CONFIG_X86_64
1728         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1729         if (is_long_mode(&vmx->vcpu))
1730                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1731 #endif
1732         if (boot_cpu_has(X86_FEATURE_MPX))
1733                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1734         for (i = 0; i < vmx->save_nmsrs; ++i)
1735                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1736                                    vmx->guest_msrs[i].data,
1737                                    vmx->guest_msrs[i].mask);
1738 }
1739
1740 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1741 {
1742         if (!vmx->host_state.loaded)
1743                 return;
1744
1745         ++vmx->vcpu.stat.host_state_reload;
1746         vmx->host_state.loaded = 0;
1747 #ifdef CONFIG_X86_64
1748         if (is_long_mode(&vmx->vcpu))
1749                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1750 #endif
1751         if (vmx->host_state.gs_ldt_reload_needed) {
1752                 kvm_load_ldt(vmx->host_state.ldt_sel);
1753 #ifdef CONFIG_X86_64
1754                 load_gs_index(vmx->host_state.gs_sel);
1755 #else
1756                 loadsegment(gs, vmx->host_state.gs_sel);
1757 #endif
1758         }
1759         if (vmx->host_state.fs_reload_needed)
1760                 loadsegment(fs, vmx->host_state.fs_sel);
1761 #ifdef CONFIG_X86_64
1762         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1763                 loadsegment(ds, vmx->host_state.ds_sel);
1764                 loadsegment(es, vmx->host_state.es_sel);
1765         }
1766 #endif
1767         reload_tss();
1768 #ifdef CONFIG_X86_64
1769         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1770 #endif
1771         if (vmx->host_state.msr_host_bndcfgs)
1772                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1773         /*
1774          * If the FPU is not active (through the host task or
1775          * the guest vcpu), then restore the cr0.TS bit.
1776          */
1777         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1778                 stts();
1779         load_gdt(&__get_cpu_var(host_gdt));
1780 }
1781
1782 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1783 {
1784         preempt_disable();
1785         __vmx_load_host_state(vmx);
1786         preempt_enable();
1787 }
1788
1789 /*
1790  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791  * vcpu mutex is already taken.
1792  */
1793 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1794 {
1795         struct vcpu_vmx *vmx = to_vmx(vcpu);
1796         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1797
1798         if (!vmm_exclusive)
1799                 kvm_cpu_vmxon(phys_addr);
1800         else if (vmx->loaded_vmcs->cpu != cpu)
1801                 loaded_vmcs_clear(vmx->loaded_vmcs);
1802
1803         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1804                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1805                 vmcs_load(vmx->loaded_vmcs->vmcs);
1806         }
1807
1808         if (vmx->loaded_vmcs->cpu != cpu) {
1809                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1810                 unsigned long sysenter_esp;
1811
1812                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1813                 local_irq_disable();
1814                 crash_disable_local_vmclear(cpu);
1815
1816                 /*
1817                  * Read loaded_vmcs->cpu should be before fetching
1818                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819                  * See the comments in __loaded_vmcs_clear().
1820                  */
1821                 smp_rmb();
1822
1823                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1824                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1825                 crash_enable_local_vmclear(cpu);
1826                 local_irq_enable();
1827
1828                 /*
1829                  * Linux uses per-cpu TSS and GDT, so set these when switching
1830                  * processors.
1831                  */
1832                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1833                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1834
1835                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1836                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1837                 vmx->loaded_vmcs->cpu = cpu;
1838         }
1839 }
1840
1841 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1842 {
1843         __vmx_load_host_state(to_vmx(vcpu));
1844         if (!vmm_exclusive) {
1845                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1846                 vcpu->cpu = -1;
1847                 kvm_cpu_vmxoff();
1848         }
1849 }
1850
1851 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1852 {
1853         ulong cr0;
1854
1855         if (vcpu->fpu_active)
1856                 return;
1857         vcpu->fpu_active = 1;
1858         cr0 = vmcs_readl(GUEST_CR0);
1859         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1860         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1861         vmcs_writel(GUEST_CR0, cr0);
1862         update_exception_bitmap(vcpu);
1863         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1864         if (is_guest_mode(vcpu))
1865                 vcpu->arch.cr0_guest_owned_bits &=
1866                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1867         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1868 }
1869
1870 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1871
1872 /*
1873  * Return the cr0 value that a nested guest would read. This is a combination
1874  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875  * its hypervisor (cr0_read_shadow).
1876  */
1877 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1878 {
1879         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1880                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1881 }
1882 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1883 {
1884         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1885                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1886 }
1887
1888 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1889 {
1890         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891          * set this *before* calling this function.
1892          */
1893         vmx_decache_cr0_guest_bits(vcpu);
1894         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1895         update_exception_bitmap(vcpu);
1896         vcpu->arch.cr0_guest_owned_bits = 0;
1897         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1898         if (is_guest_mode(vcpu)) {
1899                 /*
1900                  * L1's specified read shadow might not contain the TS bit,
1901                  * so now that we turned on shadowing of this bit, we need to
1902                  * set this bit of the shadow. Like in nested_vmx_run we need
1903                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904                  * up-to-date here because we just decached cr0.TS (and we'll
1905                  * only update vmcs12->guest_cr0 on nested exit).
1906                  */
1907                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1909                         (vcpu->arch.cr0 & X86_CR0_TS);
1910                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1911         } else
1912                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1913 }
1914
1915 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1916 {
1917         unsigned long rflags, save_rflags;
1918
1919         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1920                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1921                 rflags = vmcs_readl(GUEST_RFLAGS);
1922                 if (to_vmx(vcpu)->rmode.vm86_active) {
1923                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1924                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1925                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1926                 }
1927                 to_vmx(vcpu)->rflags = rflags;
1928         }
1929         return to_vmx(vcpu)->rflags;
1930 }
1931
1932 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1933 {
1934         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1935         to_vmx(vcpu)->rflags = rflags;
1936         if (to_vmx(vcpu)->rmode.vm86_active) {
1937                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1938                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1939         }
1940         vmcs_writel(GUEST_RFLAGS, rflags);
1941 }
1942
1943 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1944 {
1945         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1946         int ret = 0;
1947
1948         if (interruptibility & GUEST_INTR_STATE_STI)
1949                 ret |= KVM_X86_SHADOW_INT_STI;
1950         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1951                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1952
1953         return ret & mask;
1954 }
1955
1956 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1957 {
1958         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1959         u32 interruptibility = interruptibility_old;
1960
1961         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1962
1963         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1964                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1965         else if (mask & KVM_X86_SHADOW_INT_STI)
1966                 interruptibility |= GUEST_INTR_STATE_STI;
1967
1968         if ((interruptibility != interruptibility_old))
1969                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1970 }
1971
1972 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1973 {
1974         unsigned long rip;
1975
1976         rip = kvm_rip_read(vcpu);
1977         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1978         kvm_rip_write(vcpu, rip);
1979
1980         /* skipping an emulated instruction also counts */
1981         vmx_set_interrupt_shadow(vcpu, 0);
1982 }
1983
1984 /*
1985  * KVM wants to inject page-faults which it got to the guest. This function
1986  * checks whether in a nested guest, we need to inject them to L1 or L2.
1987  */
1988 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
1989 {
1990         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1991
1992         if (!(vmcs12->exception_bitmap & (1u << nr)))
1993                 return 0;
1994
1995         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1996                           vmcs_read32(VM_EXIT_INTR_INFO),
1997                           vmcs_readl(EXIT_QUALIFICATION));
1998         return 1;
1999 }
2000
2001 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2002                                 bool has_error_code, u32 error_code,
2003                                 bool reinject)
2004 {
2005         struct vcpu_vmx *vmx = to_vmx(vcpu);
2006         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2007
2008         if (!reinject && is_guest_mode(vcpu) &&
2009             nested_vmx_check_exception(vcpu, nr))
2010                 return;
2011
2012         if (has_error_code) {
2013                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2014                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2015         }
2016
2017         if (vmx->rmode.vm86_active) {
2018                 int inc_eip = 0;
2019                 if (kvm_exception_is_soft(nr))
2020                         inc_eip = vcpu->arch.event_exit_inst_len;
2021                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2022                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2023                 return;
2024         }
2025
2026         if (kvm_exception_is_soft(nr)) {
2027                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2028                              vmx->vcpu.arch.event_exit_inst_len);
2029                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2030         } else
2031                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2032
2033         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2034 }
2035
2036 static bool vmx_rdtscp_supported(void)
2037 {
2038         return cpu_has_vmx_rdtscp();
2039 }
2040
2041 static bool vmx_invpcid_supported(void)
2042 {
2043         return cpu_has_vmx_invpcid() && enable_ept;
2044 }
2045
2046 /*
2047  * Swap MSR entry in host/guest MSR entry array.
2048  */
2049 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2050 {
2051         struct shared_msr_entry tmp;
2052
2053         tmp = vmx->guest_msrs[to];
2054         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2055         vmx->guest_msrs[from] = tmp;
2056 }
2057
2058 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2059 {
2060         unsigned long *msr_bitmap;
2061
2062         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2063                 if (is_long_mode(vcpu))
2064                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2065                 else
2066                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2067         } else {
2068                 if (is_long_mode(vcpu))
2069                         msr_bitmap = vmx_msr_bitmap_longmode;
2070                 else
2071                         msr_bitmap = vmx_msr_bitmap_legacy;
2072         }
2073
2074         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2075 }
2076
2077 /*
2078  * Set up the vmcs to automatically save and restore system
2079  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2080  * mode, as fiddling with msrs is very expensive.
2081  */
2082 static void setup_msrs(struct vcpu_vmx *vmx)
2083 {
2084         int save_nmsrs, index;
2085
2086         save_nmsrs = 0;
2087 #ifdef CONFIG_X86_64
2088         if (is_long_mode(&vmx->vcpu)) {
2089                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2090                 if (index >= 0)
2091                         move_msr_up(vmx, index, save_nmsrs++);
2092                 index = __find_msr_index(vmx, MSR_LSTAR);
2093                 if (index >= 0)
2094                         move_msr_up(vmx, index, save_nmsrs++);
2095                 index = __find_msr_index(vmx, MSR_CSTAR);
2096                 if (index >= 0)
2097                         move_msr_up(vmx, index, save_nmsrs++);
2098                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2099                 if (index >= 0 && vmx->rdtscp_enabled)
2100                         move_msr_up(vmx, index, save_nmsrs++);
2101                 /*
2102                  * MSR_STAR is only needed on long mode guests, and only
2103                  * if efer.sce is enabled.
2104                  */
2105                 index = __find_msr_index(vmx, MSR_STAR);
2106                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2107                         move_msr_up(vmx, index, save_nmsrs++);
2108         }
2109 #endif
2110         index = __find_msr_index(vmx, MSR_EFER);
2111         if (index >= 0 && update_transition_efer(vmx, index))
2112                 move_msr_up(vmx, index, save_nmsrs++);
2113
2114         vmx->save_nmsrs = save_nmsrs;
2115
2116         if (cpu_has_vmx_msr_bitmap())
2117                 vmx_set_msr_bitmap(&vmx->vcpu);
2118 }
2119
2120 /*
2121  * reads and returns guest's timestamp counter "register"
2122  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2123  */
2124 static u64 guest_read_tsc(void)
2125 {
2126         u64 host_tsc, tsc_offset;
2127
2128         rdtscll(host_tsc);
2129         tsc_offset = vmcs_read64(TSC_OFFSET);
2130         return host_tsc + tsc_offset;
2131 }
2132
2133 /*
2134  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135  * counter, even if a nested guest (L2) is currently running.
2136  */
2137 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2138 {
2139         u64 tsc_offset;
2140
2141         tsc_offset = is_guest_mode(vcpu) ?
2142                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2143                 vmcs_read64(TSC_OFFSET);
2144         return host_tsc + tsc_offset;
2145 }
2146
2147 /*
2148  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2149  * software catchup for faster rates on slower CPUs.
2150  */
2151 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2152 {
2153         if (!scale)
2154                 return;
2155
2156         if (user_tsc_khz > tsc_khz) {
2157                 vcpu->arch.tsc_catchup = 1;
2158                 vcpu->arch.tsc_always_catchup = 1;
2159         } else
2160                 WARN(1, "user requested TSC rate below hardware speed\n");
2161 }
2162
2163 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2164 {
2165         return vmcs_read64(TSC_OFFSET);
2166 }
2167
2168 /*
2169  * writes 'offset' into guest's timestamp counter offset register
2170  */
2171 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2172 {
2173         if (is_guest_mode(vcpu)) {
2174                 /*
2175                  * We're here if L1 chose not to trap WRMSR to TSC. According
2176                  * to the spec, this should set L1's TSC; The offset that L1
2177                  * set for L2 remains unchanged, and still needs to be added
2178                  * to the newly set TSC to get L2's TSC.
2179                  */
2180                 struct vmcs12 *vmcs12;
2181                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2182                 /* recalculate vmcs02.TSC_OFFSET: */
2183                 vmcs12 = get_vmcs12(vcpu);
2184                 vmcs_write64(TSC_OFFSET, offset +
2185                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2186                          vmcs12->tsc_offset : 0));
2187         } else {
2188                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2189                                            vmcs_read64(TSC_OFFSET), offset);
2190                 vmcs_write64(TSC_OFFSET, offset);
2191         }
2192 }
2193
2194 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2195 {
2196         u64 offset = vmcs_read64(TSC_OFFSET);
2197
2198         vmcs_write64(TSC_OFFSET, offset + adjustment);
2199         if (is_guest_mode(vcpu)) {
2200                 /* Even when running L2, the adjustment needs to apply to L1 */
2201                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2202         } else
2203                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2204                                            offset + adjustment);
2205 }
2206
2207 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2208 {
2209         return target_tsc - native_read_tsc();
2210 }
2211
2212 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2213 {
2214         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2215         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2216 }
2217
2218 /*
2219  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221  * all guests if the "nested" module option is off, and can also be disabled
2222  * for a single guest by disabling its VMX cpuid bit.
2223  */
2224 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2225 {
2226         return nested && guest_cpuid_has_vmx(vcpu);
2227 }
2228
2229 /*
2230  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231  * returned for the various VMX controls MSRs when nested VMX is enabled.
2232  * The same values should also be used to verify that vmcs12 control fields are
2233  * valid during nested entry from L1 to L2.
2234  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236  * bit in the high half is on if the corresponding bit in the control field
2237  * may be on. See also vmx_control_verify().
2238  * TODO: allow these variables to be modified (downgraded) by module options
2239  * or other means.
2240  */
2241 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2242 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2243 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2244 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2245 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2246 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2247 static u32 nested_vmx_ept_caps;
2248 static __init void nested_vmx_setup_ctls_msrs(void)
2249 {
2250         /*
2251          * Note that as a general rule, the high half of the MSRs (bits in
2252          * the control fields which may be 1) should be initialized by the
2253          * intersection of the underlying hardware's MSR (i.e., features which
2254          * can be supported) and the list of features we want to expose -
2255          * because they are known to be properly supported in our code.
2256          * Also, usually, the low half of the MSRs (bits which must be 1) can
2257          * be set to 0, meaning that L1 may turn off any of these bits. The
2258          * reason is that if one of these bits is necessary, it will appear
2259          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2260          * fields of vmcs01 and vmcs02, will turn these bits off - and
2261          * nested_vmx_exit_handled() will not pass related exits to L1.
2262          * These rules have exceptions below.
2263          */
2264
2265         /* pin-based controls */
2266         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2267               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2268         /*
2269          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2270          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2271          */
2272         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2273         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2274                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2275         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2276                 PIN_BASED_VMX_PREEMPTION_TIMER;
2277
2278         /*
2279          * Exit controls
2280          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2281          * 17 must be 1.
2282          */
2283         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2284                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2285         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2286         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2287         nested_vmx_exit_ctls_high &=
2288 #ifdef CONFIG_X86_64
2289                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2290 #endif
2291                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2292         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2293                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2294                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2295         if (vmx_mpx_supported())
2296                 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2297
2298         /* entry controls */
2299         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2300                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2301         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2302         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2303         nested_vmx_entry_ctls_high &=
2304 #ifdef CONFIG_X86_64
2305                 VM_ENTRY_IA32E_MODE |
2306 #endif
2307                 VM_ENTRY_LOAD_IA32_PAT;
2308         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2309                                        VM_ENTRY_LOAD_IA32_EFER);
2310         if (vmx_mpx_supported())
2311                 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2312
2313         /* cpu-based controls */
2314         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2315                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2316         nested_vmx_procbased_ctls_low = 0;
2317         nested_vmx_procbased_ctls_high &=
2318                 CPU_BASED_VIRTUAL_INTR_PENDING |
2319                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2320                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2321                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2322                 CPU_BASED_CR3_STORE_EXITING |
2323 #ifdef CONFIG_X86_64
2324                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2325 #endif
2326                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2327                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2328                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2329                 CPU_BASED_PAUSE_EXITING |
2330                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2331         /*
2332          * We can allow some features even when not supported by the
2333          * hardware. For example, L1 can specify an MSR bitmap - and we
2334          * can use it to avoid exits to L1 - even when L0 runs L2
2335          * without MSR bitmaps.
2336          */
2337         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2338
2339         /* secondary cpu-based controls */
2340         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2341                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2342         nested_vmx_secondary_ctls_low = 0;
2343         nested_vmx_secondary_ctls_high &=
2344                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2345                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2346                 SECONDARY_EXEC_WBINVD_EXITING;
2347
2348         if (enable_ept) {
2349                 /* nested EPT: emulate EPT also to L1 */
2350                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2351                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2352                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2353                          VMX_EPT_INVEPT_BIT;
2354                 nested_vmx_ept_caps &= vmx_capability.ept;
2355                 /*
2356                  * Since invept is completely emulated we support both global
2357                  * and context invalidation independent of what host cpu
2358                  * supports
2359                  */
2360                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2361                         VMX_EPT_EXTENT_CONTEXT_BIT;
2362         } else
2363                 nested_vmx_ept_caps = 0;
2364
2365         /* miscellaneous data */
2366         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2367         nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2368         nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2369                 VMX_MISC_ACTIVITY_HLT;
2370         nested_vmx_misc_high = 0;
2371 }
2372
2373 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2374 {
2375         /*
2376          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2377          */
2378         return ((control & high) | low) == control;
2379 }
2380
2381 static inline u64 vmx_control_msr(u32 low, u32 high)
2382 {
2383         return low | ((u64)high << 32);
2384 }
2385
2386 /* Returns 0 on success, non-0 otherwise. */
2387 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2388 {
2389         switch (msr_index) {
2390         case MSR_IA32_VMX_BASIC:
2391                 /*
2392                  * This MSR reports some information about VMX support. We
2393                  * should return information about the VMX we emulate for the
2394                  * guest, and the VMCS structure we give it - not about the
2395                  * VMX support of the underlying hardware.
2396                  */
2397                 *pdata = VMCS12_REVISION |
2398                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2399                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2400                 break;
2401         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2402         case MSR_IA32_VMX_PINBASED_CTLS:
2403                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2404                                         nested_vmx_pinbased_ctls_high);
2405                 break;
2406         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2407         case MSR_IA32_VMX_PROCBASED_CTLS:
2408                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2409                                         nested_vmx_procbased_ctls_high);
2410                 break;
2411         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2412         case MSR_IA32_VMX_EXIT_CTLS:
2413                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2414                                         nested_vmx_exit_ctls_high);
2415                 break;
2416         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2417         case MSR_IA32_VMX_ENTRY_CTLS:
2418                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2419                                         nested_vmx_entry_ctls_high);
2420                 break;
2421         case MSR_IA32_VMX_MISC:
2422                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2423                                          nested_vmx_misc_high);
2424                 break;
2425         /*
2426          * These MSRs specify bits which the guest must keep fixed (on or off)
2427          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2428          * We picked the standard core2 setting.
2429          */
2430 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2431 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2432         case MSR_IA32_VMX_CR0_FIXED0:
2433                 *pdata = VMXON_CR0_ALWAYSON;
2434                 break;
2435         case MSR_IA32_VMX_CR0_FIXED1:
2436                 *pdata = -1ULL;
2437                 break;
2438         case MSR_IA32_VMX_CR4_FIXED0:
2439                 *pdata = VMXON_CR4_ALWAYSON;
2440                 break;
2441         case MSR_IA32_VMX_CR4_FIXED1:
2442                 *pdata = -1ULL;
2443                 break;
2444         case MSR_IA32_VMX_VMCS_ENUM:
2445                 *pdata = 0x1f;
2446                 break;
2447         case MSR_IA32_VMX_PROCBASED_CTLS2:
2448                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2449                                         nested_vmx_secondary_ctls_high);
2450                 break;
2451         case MSR_IA32_VMX_EPT_VPID_CAP:
2452                 /* Currently, no nested vpid support */
2453                 *pdata = nested_vmx_ept_caps;
2454                 break;
2455         default:
2456                 return 1;
2457         }
2458
2459         return 0;
2460 }
2461
2462 /*
2463  * Reads an msr value (of 'msr_index') into 'pdata'.
2464  * Returns 0 on success, non-0 otherwise.
2465  * Assumes vcpu_load() was already called.
2466  */
2467 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2468 {
2469         u64 data;
2470         struct shared_msr_entry *msr;
2471
2472         if (!pdata) {
2473                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2474                 return -EINVAL;
2475         }
2476
2477         switch (msr_index) {
2478 #ifdef CONFIG_X86_64
2479         case MSR_FS_BASE:
2480                 data = vmcs_readl(GUEST_FS_BASE);
2481                 break;
2482         case MSR_GS_BASE:
2483                 data = vmcs_readl(GUEST_GS_BASE);
2484                 break;
2485         case MSR_KERNEL_GS_BASE:
2486                 vmx_load_host_state(to_vmx(vcpu));
2487                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2488                 break;
2489 #endif
2490         case MSR_EFER:
2491                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2492         case MSR_IA32_TSC:
2493                 data = guest_read_tsc();
2494                 break;
2495         case MSR_IA32_SYSENTER_CS:
2496                 data = vmcs_read32(GUEST_SYSENTER_CS);
2497                 break;
2498         case MSR_IA32_SYSENTER_EIP:
2499                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2500                 break;
2501         case MSR_IA32_SYSENTER_ESP:
2502                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2503                 break;
2504         case MSR_IA32_BNDCFGS:
2505                 if (!vmx_mpx_supported())
2506                         return 1;
2507                 data = vmcs_read64(GUEST_BNDCFGS);
2508                 break;
2509         case MSR_IA32_FEATURE_CONTROL:
2510                 if (!nested_vmx_allowed(vcpu))
2511                         return 1;
2512                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2513                 break;
2514         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2515                 if (!nested_vmx_allowed(vcpu))
2516                         return 1;
2517                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2518         case MSR_TSC_AUX:
2519                 if (!to_vmx(vcpu)->rdtscp_enabled)
2520                         return 1;
2521                 /* Otherwise falls through */
2522         default:
2523                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2524                 if (msr) {
2525                         data = msr->data;
2526                         break;
2527                 }
2528                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2529         }
2530
2531         *pdata = data;
2532         return 0;
2533 }
2534
2535 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2536
2537 /*
2538  * Writes msr value into into the appropriate "register".
2539  * Returns 0 on success, non-0 otherwise.
2540  * Assumes vcpu_load() was already called.
2541  */
2542 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2543 {
2544         struct vcpu_vmx *vmx = to_vmx(vcpu);
2545         struct shared_msr_entry *msr;
2546         int ret = 0;
2547         u32 msr_index = msr_info->index;
2548         u64 data = msr_info->data;
2549
2550         switch (msr_index) {
2551         case MSR_EFER:
2552                 ret = kvm_set_msr_common(vcpu, msr_info);
2553                 break;
2554 #ifdef CONFIG_X86_64
2555         case MSR_FS_BASE:
2556                 vmx_segment_cache_clear(vmx);
2557                 vmcs_writel(GUEST_FS_BASE, data);
2558                 break;
2559         case MSR_GS_BASE:
2560                 vmx_segment_cache_clear(vmx);
2561                 vmcs_writel(GUEST_GS_BASE, data);
2562                 break;
2563         case MSR_KERNEL_GS_BASE:
2564                 vmx_load_host_state(vmx);
2565                 vmx->msr_guest_kernel_gs_base = data;
2566                 break;
2567 #endif
2568         case MSR_IA32_SYSENTER_CS:
2569                 vmcs_write32(GUEST_SYSENTER_CS, data);
2570                 break;
2571         case MSR_IA32_SYSENTER_EIP:
2572                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2573                 break;
2574         case MSR_IA32_SYSENTER_ESP:
2575                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2576                 break;
2577         case MSR_IA32_BNDCFGS:
2578                 if (!vmx_mpx_supported())
2579                         return 1;
2580                 vmcs_write64(GUEST_BNDCFGS, data);
2581                 break;
2582         case MSR_IA32_TSC:
2583                 kvm_write_tsc(vcpu, msr_info);
2584                 break;
2585         case MSR_IA32_CR_PAT:
2586                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2587                         vmcs_write64(GUEST_IA32_PAT, data);
2588                         vcpu->arch.pat = data;
2589                         break;
2590                 }
2591                 ret = kvm_set_msr_common(vcpu, msr_info);
2592                 break;
2593         case MSR_IA32_TSC_ADJUST:
2594                 ret = kvm_set_msr_common(vcpu, msr_info);
2595                 break;
2596         case MSR_IA32_FEATURE_CONTROL:
2597                 if (!nested_vmx_allowed(vcpu) ||
2598                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2599                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2600                         return 1;
2601                 vmx->nested.msr_ia32_feature_control = data;
2602                 if (msr_info->host_initiated && data == 0)
2603                         vmx_leave_nested(vcpu);
2604                 break;
2605         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2606                 return 1; /* they are read-only */
2607         case MSR_TSC_AUX:
2608                 if (!vmx->rdtscp_enabled)
2609                         return 1;
2610                 /* Check reserved bit, higher 32 bits should be zero */
2611                 if ((data >> 32) != 0)
2612                         return 1;
2613                 /* Otherwise falls through */
2614         default:
2615                 msr = find_msr_entry(vmx, msr_index);
2616                 if (msr) {
2617                         msr->data = data;
2618                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2619                                 preempt_disable();
2620                                 kvm_set_shared_msr(msr->index, msr->data,
2621                                                    msr->mask);
2622                                 preempt_enable();
2623                         }
2624                         break;
2625                 }
2626                 ret = kvm_set_msr_common(vcpu, msr_info);
2627         }
2628
2629         return ret;
2630 }
2631
2632 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2633 {
2634         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2635         switch (reg) {
2636         case VCPU_REGS_RSP:
2637                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2638                 break;
2639         case VCPU_REGS_RIP:
2640                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2641                 break;
2642         case VCPU_EXREG_PDPTR:
2643                 if (enable_ept)
2644                         ept_save_pdptrs(vcpu);
2645                 break;
2646         default:
2647                 break;
2648         }
2649 }
2650
2651 static __init int cpu_has_kvm_support(void)
2652 {
2653         return cpu_has_vmx();
2654 }
2655
2656 static __init int vmx_disabled_by_bios(void)
2657 {
2658         u64 msr;
2659
2660         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2661         if (msr & FEATURE_CONTROL_LOCKED) {
2662                 /* launched w/ TXT and VMX disabled */
2663                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2664                         && tboot_enabled())
2665                         return 1;
2666                 /* launched w/o TXT and VMX only enabled w/ TXT */
2667                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2668                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2669                         && !tboot_enabled()) {
2670                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2671                                 "activate TXT before enabling KVM\n");
2672                         return 1;
2673                 }
2674                 /* launched w/o TXT and VMX disabled */
2675                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2676                         && !tboot_enabled())
2677                         return 1;
2678         }
2679
2680         return 0;
2681 }
2682
2683 static void kvm_cpu_vmxon(u64 addr)
2684 {
2685         asm volatile (ASM_VMX_VMXON_RAX
2686                         : : "a"(&addr), "m"(addr)
2687                         : "memory", "cc");
2688 }
2689
2690 static int hardware_enable(void *garbage)
2691 {
2692         int cpu = raw_smp_processor_id();
2693         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2694         u64 old, test_bits;
2695
2696         if (read_cr4() & X86_CR4_VMXE)
2697                 return -EBUSY;
2698
2699         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2700
2701         /*
2702          * Now we can enable the vmclear operation in kdump
2703          * since the loaded_vmcss_on_cpu list on this cpu
2704          * has been initialized.
2705          *
2706          * Though the cpu is not in VMX operation now, there
2707          * is no problem to enable the vmclear operation
2708          * for the loaded_vmcss_on_cpu list is empty!
2709          */
2710         crash_enable_local_vmclear(cpu);
2711
2712         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2713
2714         test_bits = FEATURE_CONTROL_LOCKED;
2715         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2716         if (tboot_enabled())
2717                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2718
2719         if ((old & test_bits) != test_bits) {
2720                 /* enable and lock */
2721                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2722         }
2723         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2724
2725         if (vmm_exclusive) {
2726                 kvm_cpu_vmxon(phys_addr);
2727                 ept_sync_global();
2728         }
2729
2730         native_store_gdt(&__get_cpu_var(host_gdt));
2731
2732         return 0;
2733 }
2734
2735 static void vmclear_local_loaded_vmcss(void)
2736 {
2737         int cpu = raw_smp_processor_id();
2738         struct loaded_vmcs *v, *n;
2739
2740         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2741                                  loaded_vmcss_on_cpu_link)
2742                 __loaded_vmcs_clear(v);
2743 }
2744
2745
2746 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2747  * tricks.
2748  */
2749 static void kvm_cpu_vmxoff(void)
2750 {
2751         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2752 }
2753
2754 static void hardware_disable(void *garbage)
2755 {
2756         if (vmm_exclusive) {
2757                 vmclear_local_loaded_vmcss();
2758                 kvm_cpu_vmxoff();
2759         }
2760         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2761 }
2762
2763 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2764                                       u32 msr, u32 *result)
2765 {
2766         u32 vmx_msr_low, vmx_msr_high;
2767         u32 ctl = ctl_min | ctl_opt;
2768
2769         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2770
2771         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2772         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2773
2774         /* Ensure minimum (required) set of control bits are supported. */
2775         if (ctl_min & ~ctl)
2776                 return -EIO;
2777
2778         *result = ctl;
2779         return 0;
2780 }
2781
2782 static __init bool allow_1_setting(u32 msr, u32 ctl)
2783 {
2784         u32 vmx_msr_low, vmx_msr_high;
2785
2786         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2787         return vmx_msr_high & ctl;
2788 }
2789
2790 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2791 {
2792         u32 vmx_msr_low, vmx_msr_high;
2793         u32 min, opt, min2, opt2;
2794         u32 _pin_based_exec_control = 0;
2795         u32 _cpu_based_exec_control = 0;
2796         u32 _cpu_based_2nd_exec_control = 0;
2797         u32 _vmexit_control = 0;
2798         u32 _vmentry_control = 0;
2799
2800         min = CPU_BASED_HLT_EXITING |
2801 #ifdef CONFIG_X86_64
2802               CPU_BASED_CR8_LOAD_EXITING |
2803               CPU_BASED_CR8_STORE_EXITING |
2804 #endif
2805               CPU_BASED_CR3_LOAD_EXITING |
2806               CPU_BASED_CR3_STORE_EXITING |
2807               CPU_BASED_USE_IO_BITMAPS |
2808               CPU_BASED_MOV_DR_EXITING |
2809               CPU_BASED_USE_TSC_OFFSETING |
2810               CPU_BASED_MWAIT_EXITING |
2811               CPU_BASED_MONITOR_EXITING |
2812               CPU_BASED_INVLPG_EXITING |
2813               CPU_BASED_RDPMC_EXITING;
2814
2815         opt = CPU_BASED_TPR_SHADOW |
2816               CPU_BASED_USE_MSR_BITMAPS |
2817               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2818         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2819                                 &_cpu_based_exec_control) < 0)
2820                 return -EIO;
2821 #ifdef CONFIG_X86_64
2822         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2823                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2824                                            ~CPU_BASED_CR8_STORE_EXITING;
2825 #endif
2826         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2827                 min2 = 0;
2828                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2829                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2830                         SECONDARY_EXEC_WBINVD_EXITING |
2831                         SECONDARY_EXEC_ENABLE_VPID |
2832                         SECONDARY_EXEC_ENABLE_EPT |
2833                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2834                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2835                         SECONDARY_EXEC_RDTSCP |
2836                         SECONDARY_EXEC_ENABLE_INVPCID |
2837                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2838                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2839                         SECONDARY_EXEC_SHADOW_VMCS;
2840                 if (adjust_vmx_controls(min2, opt2,
2841                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2842                                         &_cpu_based_2nd_exec_control) < 0)
2843                         return -EIO;
2844         }
2845 #ifndef CONFIG_X86_64
2846         if (!(_cpu_based_2nd_exec_control &
2847                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2848                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2849 #endif
2850
2851         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2852                 _cpu_based_2nd_exec_control &= ~(
2853                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2854                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2855                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2856
2857         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2858                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2859                    enabled */
2860                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2861                                              CPU_BASED_CR3_STORE_EXITING |
2862                                              CPU_BASED_INVLPG_EXITING);
2863                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2864                       vmx_capability.ept, vmx_capability.vpid);
2865         }
2866
2867         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2868 #ifdef CONFIG_X86_64
2869         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2870 #endif
2871         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2872                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2873         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2874                                 &_vmexit_control) < 0)
2875                 return -EIO;
2876
2877         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2878         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2879         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2880                                 &_pin_based_exec_control) < 0)
2881                 return -EIO;
2882
2883         if (!(_cpu_based_2nd_exec_control &
2884                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2885                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2886                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2887
2888         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2889         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2890         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2891                                 &_vmentry_control) < 0)
2892                 return -EIO;
2893
2894         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2895
2896         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2897         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2898                 return -EIO;
2899
2900 #ifdef CONFIG_X86_64
2901         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2902         if (vmx_msr_high & (1u<<16))
2903                 return -EIO;
2904 #endif
2905
2906         /* Require Write-Back (WB) memory type for VMCS accesses. */
2907         if (((vmx_msr_high >> 18) & 15) != 6)
2908                 return -EIO;
2909
2910         vmcs_conf->size = vmx_msr_high & 0x1fff;
2911         vmcs_conf->order = get_order(vmcs_config.size);
2912         vmcs_conf->revision_id = vmx_msr_low;
2913
2914         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2915         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2916         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2917         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2918         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2919
2920         cpu_has_load_ia32_efer =
2921                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2922                                 VM_ENTRY_LOAD_IA32_EFER)
2923                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2924                                    VM_EXIT_LOAD_IA32_EFER);
2925
2926         cpu_has_load_perf_global_ctrl =
2927                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2928                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2929                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2930                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2931
2932         /*
2933          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2934          * but due to arrata below it can't be used. Workaround is to use
2935          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2936          *
2937          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2938          *
2939          * AAK155             (model 26)
2940          * AAP115             (model 30)
2941          * AAT100             (model 37)
2942          * BC86,AAY89,BD102   (model 44)
2943          * BA97               (model 46)
2944          *
2945          */
2946         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2947                 switch (boot_cpu_data.x86_model) {
2948                 case 26:
2949                 case 30:
2950                 case 37:
2951                 case 44:
2952                 case 46:
2953                         cpu_has_load_perf_global_ctrl = false;
2954                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2955                                         "does not work properly. Using workaround\n");
2956                         break;
2957                 default:
2958                         break;
2959                 }
2960         }
2961
2962         return 0;
2963 }
2964
2965 static struct vmcs *alloc_vmcs_cpu(int cpu)
2966 {
2967         int node = cpu_to_node(cpu);
2968         struct page *pages;
2969         struct vmcs *vmcs;
2970
2971         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2972         if (!pages)
2973                 return NULL;
2974         vmcs = page_address(pages);
2975         memset(vmcs, 0, vmcs_config.size);
2976         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2977         return vmcs;
2978 }
2979
2980 static struct vmcs *alloc_vmcs(void)
2981 {
2982         return alloc_vmcs_cpu(raw_smp_processor_id());
2983 }
2984
2985 static void free_vmcs(struct vmcs *vmcs)
2986 {
2987         free_pages((unsigned long)vmcs, vmcs_config.order);
2988 }
2989
2990 /*
2991  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2992  */
2993 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2994 {
2995         if (!loaded_vmcs->vmcs)
2996                 return;
2997         loaded_vmcs_clear(loaded_vmcs);
2998         free_vmcs(loaded_vmcs->vmcs);
2999         loaded_vmcs->vmcs = NULL;
3000 }
3001
3002 static void free_kvm_area(void)
3003 {
3004         int cpu;
3005
3006         for_each_possible_cpu(cpu) {
3007                 free_vmcs(per_cpu(vmxarea, cpu));
3008                 per_cpu(vmxarea, cpu) = NULL;
3009         }
3010 }
3011
3012 static __init int alloc_kvm_area(void)
3013 {
3014         int cpu;
3015
3016         for_each_possible_cpu(cpu) {
3017                 struct vmcs *vmcs;
3018
3019                 vmcs = alloc_vmcs_cpu(cpu);
3020                 if (!vmcs) {
3021                         free_kvm_area();
3022                         return -ENOMEM;
3023                 }
3024
3025                 per_cpu(vmxarea, cpu) = vmcs;
3026         }
3027         return 0;
3028 }
3029
3030 static __init int hardware_setup(void)
3031 {
3032         if (setup_vmcs_config(&vmcs_config) < 0)
3033                 return -EIO;
3034
3035         if (boot_cpu_has(X86_FEATURE_NX))
3036                 kvm_enable_efer_bits(EFER_NX);
3037
3038         if (!cpu_has_vmx_vpid())
3039                 enable_vpid = 0;
3040         if (!cpu_has_vmx_shadow_vmcs())
3041                 enable_shadow_vmcs = 0;
3042
3043         if (!cpu_has_vmx_ept() ||
3044             !cpu_has_vmx_ept_4levels()) {
3045                 enable_ept = 0;
3046                 enable_unrestricted_guest = 0;
3047                 enable_ept_ad_bits = 0;
3048         }
3049
3050         if (!cpu_has_vmx_ept_ad_bits())
3051                 enable_ept_ad_bits = 0;
3052
3053         if (!cpu_has_vmx_unrestricted_guest())
3054                 enable_unrestricted_guest = 0;
3055
3056         if (!cpu_has_vmx_flexpriority())
3057                 flexpriority_enabled = 0;
3058
3059         if (!cpu_has_vmx_tpr_shadow())
3060                 kvm_x86_ops->update_cr8_intercept = NULL;
3061
3062         if (enable_ept && !cpu_has_vmx_ept_2m_page())
3063                 kvm_disable_largepages();
3064
3065         if (!cpu_has_vmx_ple())
3066                 ple_gap = 0;
3067
3068         if (!cpu_has_vmx_apicv())
3069                 enable_apicv = 0;
3070
3071         if (enable_apicv)
3072                 kvm_x86_ops->update_cr8_intercept = NULL;
3073         else {
3074                 kvm_x86_ops->hwapic_irr_update = NULL;
3075                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3076                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3077         }
3078
3079         if (nested)
3080                 nested_vmx_setup_ctls_msrs();
3081
3082         return alloc_kvm_area();
3083 }
3084
3085 static __exit void hardware_unsetup(void)
3086 {
3087         free_kvm_area();
3088 }
3089
3090 static bool emulation_required(struct kvm_vcpu *vcpu)
3091 {
3092         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3093 }
3094
3095 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3096                 struct kvm_segment *save)
3097 {
3098         if (!emulate_invalid_guest_state) {
3099                 /*
3100                  * CS and SS RPL should be equal during guest entry according
3101                  * to VMX spec, but in reality it is not always so. Since vcpu
3102                  * is in the middle of the transition from real mode to
3103                  * protected mode it is safe to assume that RPL 0 is a good
3104                  * default value.
3105                  */
3106                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3107                         save->selector &= ~SELECTOR_RPL_MASK;
3108                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3109                 save->s = 1;
3110         }
3111         vmx_set_segment(vcpu, save, seg);
3112 }
3113
3114 static void enter_pmode(struct kvm_vcpu *vcpu)
3115 {
3116         unsigned long flags;
3117         struct vcpu_vmx *vmx = to_vmx(vcpu);
3118
3119         /*
3120          * Update real mode segment cache. It may be not up-to-date if sement
3121          * register was written while vcpu was in a guest mode.
3122          */
3123         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3124         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3125         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3126         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3127         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3128         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3129
3130         vmx->rmode.vm86_active = 0;
3131
3132         vmx_segment_cache_clear(vmx);
3133
3134         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3135
3136         flags = vmcs_readl(GUEST_RFLAGS);
3137         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3138         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3139         vmcs_writel(GUEST_RFLAGS, flags);
3140
3141         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3142                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3143
3144         update_exception_bitmap(vcpu);
3145
3146         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3147         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3148         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3149         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3150         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3151         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3152
3153         /* CPL is always 0 when CPU enters protected mode */
3154         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3155         vmx->cpl = 0;
3156 }
3157
3158 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3159 {
3160         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3161         struct kvm_segment var = *save;
3162
3163         var.dpl = 0x3;
3164         if (seg == VCPU_SREG_CS)
3165                 var.type = 0x3;
3166
3167         if (!emulate_invalid_guest_state) {
3168                 var.selector = var.base >> 4;
3169                 var.base = var.base & 0xffff0;
3170                 var.limit = 0xffff;
3171                 var.g = 0;
3172                 var.db = 0;
3173                 var.present = 1;
3174                 var.s = 1;
3175                 var.l = 0;
3176                 var.unusable = 0;
3177                 var.type = 0x3;
3178                 var.avl = 0;
3179                 if (save->base & 0xf)
3180                         printk_once(KERN_WARNING "kvm: segment base is not "
3181                                         "paragraph aligned when entering "
3182                                         "protected mode (seg=%d)", seg);
3183         }
3184
3185         vmcs_write16(sf->selector, var.selector);
3186         vmcs_write32(sf->base, var.base);
3187         vmcs_write32(sf->limit, var.limit);
3188         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3189 }
3190
3191 static void enter_rmode(struct kvm_vcpu *vcpu)
3192 {
3193         unsigned long flags;
3194         struct vcpu_vmx *vmx = to_vmx(vcpu);
3195
3196         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3197         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3198         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3199         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3200         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3201         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3202         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3203
3204         vmx->rmode.vm86_active = 1;
3205
3206         /*
3207          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3208          * vcpu. Warn the user that an update is overdue.
3209          */
3210         if (!vcpu->kvm->arch.tss_addr)
3211                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3212                              "called before entering vcpu\n");
3213
3214         vmx_segment_cache_clear(vmx);
3215
3216         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3217         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3218         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3219
3220         flags = vmcs_readl(GUEST_RFLAGS);
3221         vmx->rmode.save_rflags = flags;
3222
3223         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3224
3225         vmcs_writel(GUEST_RFLAGS, flags);
3226         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3227         update_exception_bitmap(vcpu);
3228
3229         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3230         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3231         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3232         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3233         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3234         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3235
3236         kvm_mmu_reset_context(vcpu);
3237 }
3238
3239 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3240 {
3241         struct vcpu_vmx *vmx = to_vmx(vcpu);
3242         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3243
3244         if (!msr)
3245                 return;
3246
3247         /*
3248          * Force kernel_gs_base reloading before EFER changes, as control
3249          * of this msr depends on is_long_mode().
3250          */
3251         vmx_load_host_state(to_vmx(vcpu));
3252         vcpu->arch.efer = efer;
3253         if (efer & EFER_LMA) {
3254                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3255                 msr->data = efer;
3256         } else {
3257                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3258
3259                 msr->data = efer & ~EFER_LME;
3260         }
3261         setup_msrs(vmx);
3262 }
3263
3264 #ifdef CONFIG_X86_64
3265
3266 static void enter_lmode(struct kvm_vcpu *vcpu)
3267 {
3268         u32 guest_tr_ar;
3269
3270         vmx_segment_cache_clear(to_vmx(vcpu));
3271
3272         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3273         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3274                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3275                                      __func__);
3276                 vmcs_write32(GUEST_TR_AR_BYTES,
3277                              (guest_tr_ar & ~AR_TYPE_MASK)
3278                              | AR_TYPE_BUSY_64_TSS);
3279         }
3280         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3281 }
3282
3283 static void exit_lmode(struct kvm_vcpu *vcpu)
3284 {
3285         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3286         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3287 }
3288
3289 #endif
3290
3291 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3292 {
3293         vpid_sync_context(to_vmx(vcpu));
3294         if (enable_ept) {
3295                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3296                         return;
3297                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3298         }
3299 }
3300
3301 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3302 {
3303         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3304
3305         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3306         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3307 }
3308
3309 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3310 {
3311         if (enable_ept && is_paging(vcpu))
3312                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3313         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3314 }
3315
3316 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3317 {
3318         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3319
3320         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3321         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3322 }
3323
3324 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3325 {
3326         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3327
3328         if (!test_bit(VCPU_EXREG_PDPTR,
3329                       (unsigned long *)&vcpu->arch.regs_dirty))
3330                 return;
3331
3332         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3333                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3334                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3335                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3336                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3337         }
3338 }
3339
3340 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3341 {
3342         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3343
3344         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3345                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3346                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3347                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3348                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3349         }
3350
3351         __set_bit(VCPU_EXREG_PDPTR,
3352                   (unsigned long *)&vcpu->arch.regs_avail);
3353         __set_bit(VCPU_EXREG_PDPTR,
3354                   (unsigned long *)&vcpu->arch.regs_dirty);
3355 }
3356
3357 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3358
3359 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3360                                         unsigned long cr0,
3361                                         struct kvm_vcpu *vcpu)
3362 {
3363         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3364                 vmx_decache_cr3(vcpu);
3365         if (!(cr0 & X86_CR0_PG)) {
3366                 /* From paging/starting to nonpaging */
3367                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3368                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3369                              (CPU_BASED_CR3_LOAD_EXITING |
3370                               CPU_BASED_CR3_STORE_EXITING));
3371                 vcpu->arch.cr0 = cr0;
3372                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3373         } else if (!is_paging(vcpu)) {
3374                 /* From nonpaging to paging */
3375                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3376                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3377                              ~(CPU_BASED_CR3_LOAD_EXITING |
3378                                CPU_BASED_CR3_STORE_EXITING));
3379                 vcpu->arch.cr0 = cr0;
3380                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3381         }
3382
3383         if (!(cr0 & X86_CR0_WP))
3384                 *hw_cr0 &= ~X86_CR0_WP;
3385 }
3386
3387 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3388 {
3389         struct vcpu_vmx *vmx = to_vmx(vcpu);
3390         unsigned long hw_cr0;
3391
3392         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3393         if (enable_unrestricted_guest)
3394                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3395         else {
3396                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3397
3398                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3399                         enter_pmode(vcpu);
3400
3401                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3402                         enter_rmode(vcpu);
3403         }
3404
3405 #ifdef CONFIG_X86_64
3406         if (vcpu->arch.efer & EFER_LME) {
3407                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3408                         enter_lmode(vcpu);
3409                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3410                         exit_lmode(vcpu);
3411         }
3412 #endif
3413
3414         if (enable_ept)
3415                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3416
3417         if (!vcpu->fpu_active)
3418                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3419
3420         vmcs_writel(CR0_READ_SHADOW, cr0);
3421         vmcs_writel(GUEST_CR0, hw_cr0);
3422         vcpu->arch.cr0 = cr0;
3423
3424         /* depends on vcpu->arch.cr0 to be set to a new value */
3425         vmx->emulation_required = emulation_required(vcpu);
3426 }
3427
3428 static u64 construct_eptp(unsigned long root_hpa)
3429 {
3430         u64 eptp;
3431
3432         /* TODO write the value reading from MSR */
3433         eptp = VMX_EPT_DEFAULT_MT |
3434                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3435         if (enable_ept_ad_bits)
3436                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3437         eptp |= (root_hpa & PAGE_MASK);
3438
3439         return eptp;
3440 }
3441
3442 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3443 {
3444         unsigned long guest_cr3;
3445         u64 eptp;
3446
3447         guest_cr3 = cr3;
3448         if (enable_ept) {
3449                 eptp = construct_eptp(cr3);
3450                 vmcs_write64(EPT_POINTER, eptp);
3451                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3452                         guest_cr3 = kvm_read_cr3(vcpu);
3453                 else
3454                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3455                 ept_load_pdptrs(vcpu);
3456         }
3457
3458         vmx_flush_tlb(vcpu);
3459         vmcs_writel(GUEST_CR3, guest_cr3);
3460 }
3461
3462 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3463 {
3464         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3465                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3466
3467         if (cr4 & X86_CR4_VMXE) {
3468                 /*
3469                  * To use VMXON (and later other VMX instructions), a guest
3470                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3471                  * So basically the check on whether to allow nested VMX
3472                  * is here.
3473                  */
3474                 if (!nested_vmx_allowed(vcpu))
3475                         return 1;
3476         }
3477         if (to_vmx(vcpu)->nested.vmxon &&
3478             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3479                 return 1;
3480
3481         vcpu->arch.cr4 = cr4;
3482         if (enable_ept) {
3483                 if (!is_paging(vcpu)) {
3484                         hw_cr4 &= ~X86_CR4_PAE;
3485                         hw_cr4 |= X86_CR4_PSE;
3486                         /*
3487                          * SMEP is disabled if CPU is in non-paging mode in
3488                          * hardware. However KVM always uses paging mode to
3489                          * emulate guest non-paging mode with TDP.
3490                          * To emulate this behavior, SMEP needs to be manually
3491                          * disabled when guest switches to non-paging mode.
3492                          */
3493                         hw_cr4 &= ~X86_CR4_SMEP;
3494                 } else if (!(cr4 & X86_CR4_PAE)) {
3495                         hw_cr4 &= ~X86_CR4_PAE;
3496                 }
3497         }
3498
3499         vmcs_writel(CR4_READ_SHADOW, cr4);
3500         vmcs_writel(GUEST_CR4, hw_cr4);
3501         return 0;
3502 }
3503
3504 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3505                             struct kvm_segment *var, int seg)
3506 {
3507         struct vcpu_vmx *vmx = to_vmx(vcpu);
3508         u32 ar;
3509
3510         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3511                 *var = vmx->rmode.segs[seg];
3512                 if (seg == VCPU_SREG_TR
3513                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3514                         return;
3515                 var->base = vmx_read_guest_seg_base(vmx, seg);
3516                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3517                 return;
3518         }
3519         var->base = vmx_read_guest_seg_base(vmx, seg);
3520         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3521         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3522         ar = vmx_read_guest_seg_ar(vmx, seg);
3523         var->unusable = (ar >> 16) & 1;
3524         var->type = ar & 15;
3525         var->s = (ar >> 4) & 1;
3526         var->dpl = (ar >> 5) & 3;
3527         /*
3528          * Some userspaces do not preserve unusable property. Since usable
3529          * segment has to be present according to VMX spec we can use present
3530          * property to amend userspace bug by making unusable segment always
3531          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3532          * segment as unusable.
3533          */
3534         var->present = !var->unusable;
3535         var->avl = (ar >> 12) & 1;
3536         var->l = (ar >> 13) & 1;
3537         var->db = (ar >> 14) & 1;
3538         var->g = (ar >> 15) & 1;
3539 }
3540
3541 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3542 {
3543         struct kvm_segment s;
3544
3545         if (to_vmx(vcpu)->rmode.vm86_active) {
3546                 vmx_get_segment(vcpu, &s, seg);
3547                 return s.base;
3548         }
3549         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3550 }
3551
3552 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3553 {
3554         struct vcpu_vmx *vmx = to_vmx(vcpu);
3555
3556         if (!is_protmode(vcpu))
3557                 return 0;
3558
3559         if (!is_long_mode(vcpu)
3560             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3561                 return 3;
3562
3563         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3564                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3565                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3566         }
3567
3568         return vmx->cpl;
3569 }
3570
3571
3572 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3573 {
3574         u32 ar;
3575
3576         if (var->unusable || !var->present)
3577                 ar = 1 << 16;
3578         else {
3579                 ar = var->type & 15;
3580                 ar |= (var->s & 1) << 4;
3581                 ar |= (var->dpl & 3) << 5;
3582                 ar |= (var->present & 1) << 7;
3583                 ar |= (var->avl & 1) << 12;
3584                 ar |= (var->l & 1) << 13;
3585                 ar |= (var->db & 1) << 14;
3586                 ar |= (var->g & 1) << 15;
3587         }
3588
3589         return ar;
3590 }
3591
3592 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3593                             struct kvm_segment *var, int seg)
3594 {
3595         struct vcpu_vmx *vmx = to_vmx(vcpu);
3596         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3597
3598         vmx_segment_cache_clear(vmx);
3599         if (seg == VCPU_SREG_CS)
3600                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3601
3602         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3603                 vmx->rmode.segs[seg] = *var;
3604                 if (seg == VCPU_SREG_TR)
3605                         vmcs_write16(sf->selector, var->selector);
3606                 else if (var->s)
3607                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3608                 goto out;
3609         }
3610
3611         vmcs_writel(sf->base, var->base);
3612         vmcs_write32(sf->limit, var->limit);
3613         vmcs_write16(sf->selector, var->selector);
3614
3615         /*
3616          *   Fix the "Accessed" bit in AR field of segment registers for older
3617          * qemu binaries.
3618          *   IA32 arch specifies that at the time of processor reset the
3619          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3620          * is setting it to 0 in the userland code. This causes invalid guest
3621          * state vmexit when "unrestricted guest" mode is turned on.
3622          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3623          * tree. Newer qemu binaries with that qemu fix would not need this
3624          * kvm hack.
3625          */
3626         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3627                 var->type |= 0x1; /* Accessed */
3628
3629         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3630
3631 out:
3632         vmx->emulation_required |= emulation_required(vcpu);
3633 }
3634
3635 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3636 {
3637         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3638
3639         *db = (ar >> 14) & 1;
3640         *l = (ar >> 13) & 1;
3641 }
3642
3643 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3644 {
3645         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3646         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3647 }
3648
3649 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3650 {
3651         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3652         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3653 }
3654
3655 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3656 {
3657         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3658         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3659 }
3660
3661 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3662 {
3663         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3664         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3665 }
3666
3667 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3668 {
3669         struct kvm_segment var;
3670         u32 ar;
3671
3672         vmx_get_segment(vcpu, &var, seg);
3673         var.dpl = 0x3;
3674         if (seg == VCPU_SREG_CS)
3675                 var.type = 0x3;
3676         ar = vmx_segment_access_rights(&var);
3677
3678         if (var.base != (var.selector << 4))
3679                 return false;
3680         if (var.limit != 0xffff)
3681                 return false;
3682         if (ar != 0xf3)
3683                 return false;
3684
3685         return true;
3686 }
3687
3688 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3689 {
3690         struct kvm_segment cs;
3691         unsigned int cs_rpl;
3692
3693         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3694         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3695
3696         if (cs.unusable)
3697                 return false;
3698         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3699                 return false;
3700         if (!cs.s)
3701                 return false;
3702         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3703                 if (cs.dpl > cs_rpl)
3704                         return false;
3705         } else {
3706                 if (cs.dpl != cs_rpl)
3707                         return false;
3708         }
3709         if (!cs.present)
3710                 return false;
3711
3712         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3713         return true;
3714 }
3715
3716 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3717 {
3718         struct kvm_segment ss;
3719         unsigned int ss_rpl;
3720
3721         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3722         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3723
3724         if (ss.unusable)
3725                 return true;
3726         if (ss.type != 3 && ss.type != 7)
3727                 return false;
3728         if (!ss.s)
3729                 return false;
3730         if (ss.dpl != ss_rpl) /* DPL != RPL */
3731                 return false;
3732         if (!ss.present)
3733                 return false;
3734
3735         return true;
3736 }
3737
3738 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3739 {
3740         struct kvm_segment var;
3741         unsigned int rpl;
3742
3743         vmx_get_segment(vcpu, &var, seg);
3744         rpl = var.selector & SELECTOR_RPL_MASK;
3745
3746         if (var.unusable)
3747                 return true;
3748         if (!var.s)
3749                 return false;
3750         if (!var.present)
3751                 return false;
3752         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3753                 if (var.dpl < rpl) /* DPL < RPL */
3754                         return false;
3755         }
3756
3757         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3758          * rights flags
3759          */
3760         return true;
3761 }
3762
3763 static bool tr_valid(struct kvm_vcpu *vcpu)
3764 {
3765         struct kvm_segment tr;
3766
3767         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3768
3769         if (tr.unusable)
3770                 return false;
3771         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3772                 return false;
3773         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3774                 return false;
3775         if (!tr.present)
3776                 return false;
3777
3778         return true;
3779 }
3780
3781 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3782 {
3783         struct kvm_segment ldtr;
3784
3785         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3786
3787         if (ldtr.unusable)
3788                 return true;
3789         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3790                 return false;
3791         if (ldtr.type != 2)
3792                 return false;
3793         if (!ldtr.present)
3794                 return false;
3795
3796         return true;
3797 }
3798
3799 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3800 {
3801         struct kvm_segment cs, ss;
3802
3803         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3804         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3805
3806         return ((cs.selector & SELECTOR_RPL_MASK) ==
3807                  (ss.selector & SELECTOR_RPL_MASK));
3808 }
3809
3810 /*
3811  * Check if guest state is valid. Returns true if valid, false if
3812  * not.
3813  * We assume that registers are always usable
3814  */
3815 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3816 {
3817         if (enable_unrestricted_guest)
3818                 return true;
3819
3820         /* real mode guest state checks */
3821         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3822                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3823                         return false;
3824                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3825                         return false;
3826                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3827                         return false;
3828                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3829                         return false;
3830                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3831                         return false;
3832                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3833                         return false;
3834         } else {
3835         /* protected mode guest state checks */
3836                 if (!cs_ss_rpl_check(vcpu))
3837                         return false;
3838                 if (!code_segment_valid(vcpu))
3839                         return false;
3840                 if (!stack_segment_valid(vcpu))
3841                         return false;
3842                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3843                         return false;
3844                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3845                         return false;
3846                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3847                         return false;
3848                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3849                         return false;
3850                 if (!tr_valid(vcpu))
3851                         return false;
3852                 if (!ldtr_valid(vcpu))
3853                         return false;
3854         }
3855         /* TODO:
3856          * - Add checks on RIP
3857          * - Add checks on RFLAGS
3858          */
3859
3860         return true;
3861 }
3862
3863 static int init_rmode_tss(struct kvm *kvm)
3864 {
3865         gfn_t fn;
3866         u16 data = 0;
3867         int r, idx, ret = 0;
3868
3869         idx = srcu_read_lock(&kvm->srcu);
3870         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3871         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3872         if (r < 0)
3873                 goto out;
3874         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3875         r = kvm_write_guest_page(kvm, fn++, &data,
3876                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3877         if (r < 0)
3878                 goto out;
3879         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3880         if (r < 0)
3881                 goto out;
3882         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3883         if (r < 0)
3884                 goto out;
3885         data = ~0;
3886         r = kvm_write_guest_page(kvm, fn, &data,
3887                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3888                                  sizeof(u8));
3889         if (r < 0)
3890                 goto out;
3891
3892         ret = 1;
3893 out:
3894         srcu_read_unlock(&kvm->srcu, idx);
3895         return ret;
3896 }
3897
3898 static int init_rmode_identity_map(struct kvm *kvm)
3899 {
3900         int i, idx, r, ret;
3901         pfn_t identity_map_pfn;
3902         u32 tmp;
3903
3904         if (!enable_ept)
3905                 return 1;
3906         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3907                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3908                         "haven't been allocated!\n");
3909                 return 0;
3910         }
3911         if (likely(kvm->arch.ept_identity_pagetable_done))
3912                 return 1;
3913         ret = 0;
3914         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3915         idx = srcu_read_lock(&kvm->srcu);
3916         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3917         if (r < 0)
3918                 goto out;
3919         /* Set up identity-mapping pagetable for EPT in real mode */
3920         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3921                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3922                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3923                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3924                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3925                 if (r < 0)
3926                         goto out;
3927         }
3928         kvm->arch.ept_identity_pagetable_done = true;
3929         ret = 1;
3930 out:
3931         srcu_read_unlock(&kvm->srcu, idx);
3932         return ret;
3933 }
3934
3935 static void seg_setup(int seg)
3936 {
3937         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3938         unsigned int ar;
3939
3940         vmcs_write16(sf->selector, 0);
3941         vmcs_writel(sf->base, 0);
3942         vmcs_write32(sf->limit, 0xffff);
3943         ar = 0x93;
3944         if (seg == VCPU_SREG_CS)
3945                 ar |= 0x08; /* code segment */
3946
3947         vmcs_write32(sf->ar_bytes, ar);
3948 }
3949
3950 static int alloc_apic_access_page(struct kvm *kvm)
3951 {
3952         struct page *page;
3953         struct kvm_userspace_memory_region kvm_userspace_mem;
3954         int r = 0;
3955
3956         mutex_lock(&kvm->slots_lock);
3957         if (kvm->arch.apic_access_page)
3958                 goto out;
3959         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3960         kvm_userspace_mem.flags = 0;
3961         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3962         kvm_userspace_mem.memory_size = PAGE_SIZE;
3963         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3964         if (r)
3965                 goto out;
3966
3967         page = gfn_to_page(kvm, 0xfee00);
3968         if (is_error_page(page)) {
3969                 r = -EFAULT;
3970                 goto out;
3971         }
3972
3973         kvm->arch.apic_access_page = page;
3974 out:
3975         mutex_unlock(&kvm->slots_lock);
3976         return r;
3977 }
3978
3979 static int alloc_identity_pagetable(struct kvm *kvm)
3980 {
3981         struct page *page;
3982         struct kvm_userspace_memory_region kvm_userspace_mem;
3983         int r = 0;
3984
3985         mutex_lock(&kvm->slots_lock);
3986         if (kvm->arch.ept_identity_pagetable)
3987                 goto out;
3988         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3989         kvm_userspace_mem.flags = 0;
3990         kvm_userspace_mem.guest_phys_addr =
3991                 kvm->arch.ept_identity_map_addr;
3992         kvm_userspace_mem.memory_size = PAGE_SIZE;
3993         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3994         if (r)
3995                 goto out;
3996
3997         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3998         if (is_error_page(page)) {
3999                 r = -EFAULT;
4000                 goto out;
4001         }
4002
4003         kvm->arch.ept_identity_pagetable = page;
4004 out:
4005         mutex_unlock(&kvm->slots_lock);
4006         return r;
4007 }
4008
4009 static void allocate_vpid(struct vcpu_vmx *vmx)
4010 {
4011         int vpid;
4012
4013         vmx->vpid = 0;
4014         if (!enable_vpid)
4015                 return;
4016         spin_lock(&vmx_vpid_lock);
4017         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4018         if (vpid < VMX_NR_VPIDS) {
4019                 vmx->vpid = vpid;
4020                 __set_bit(vpid, vmx_vpid_bitmap);
4021         }
4022         spin_unlock(&vmx_vpid_lock);
4023 }
4024
4025 static void free_vpid(struct vcpu_vmx *vmx)
4026 {
4027         if (!enable_vpid)
4028                 return;
4029         spin_lock(&vmx_vpid_lock);
4030         if (vmx->vpid != 0)
4031                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4032         spin_unlock(&vmx_vpid_lock);
4033 }
4034
4035 #define MSR_TYPE_R      1
4036 #define MSR_TYPE_W      2
4037 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4038                                                 u32 msr, int type)
4039 {
4040         int f = sizeof(unsigned long);
4041
4042         if (!cpu_has_vmx_msr_bitmap())
4043                 return;
4044
4045         /*
4046          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4047          * have the write-low and read-high bitmap offsets the wrong way round.
4048          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4049          */
4050         if (msr <= 0x1fff) {
4051                 if (type & MSR_TYPE_R)
4052                         /* read-low */
4053                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4054
4055                 if (type & MSR_TYPE_W)
4056                         /* write-low */
4057                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4058
4059         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4060                 msr &= 0x1fff;
4061                 if (type & MSR_TYPE_R)
4062                         /* read-high */
4063                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4064
4065                 if (type & MSR_TYPE_W)
4066                         /* write-high */
4067                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4068
4069         }
4070 }
4071
4072 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4073                                                 u32 msr, int type)
4074 {
4075         int f = sizeof(unsigned long);
4076
4077         if (!cpu_has_vmx_msr_bitmap())
4078                 return;
4079
4080         /*
4081          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4082          * have the write-low and read-high bitmap offsets the wrong way round.
4083          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4084          */
4085         if (msr <= 0x1fff) {
4086                 if (type & MSR_TYPE_R)
4087                         /* read-low */
4088                         __set_bit(msr, msr_bitmap + 0x000 / f);
4089
4090                 if (type & MSR_TYPE_W)
4091                         /* write-low */
4092                         __set_bit(msr, msr_bitmap + 0x800 / f);
4093
4094         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4095                 msr &= 0x1fff;
4096                 if (type & MSR_TYPE_R)
4097                         /* read-high */
4098                         __set_bit(msr, msr_bitmap + 0x400 / f);
4099
4100                 if (type & MSR_TYPE_W)
4101                         /* write-high */
4102                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4103
4104         }
4105 }
4106
4107 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4108 {
4109         if (!longmode_only)
4110                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4111                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4112         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4113                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4114 }
4115
4116 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4117 {
4118         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4119                         msr, MSR_TYPE_R);
4120         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4121                         msr, MSR_TYPE_R);
4122 }
4123
4124 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4125 {
4126         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4127                         msr, MSR_TYPE_R);
4128         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4129                         msr, MSR_TYPE_R);
4130 }
4131
4132 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4133 {
4134         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4135                         msr, MSR_TYPE_W);
4136         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4137                         msr, MSR_TYPE_W);
4138 }
4139
4140 static int vmx_vm_has_apicv(struct kvm *kvm)
4141 {
4142         return enable_apicv && irqchip_in_kernel(kvm);
4143 }
4144
4145 /*
4146  * Send interrupt to vcpu via posted interrupt way.
4147  * 1. If target vcpu is running(non-root mode), send posted interrupt
4148  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4149  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4150  * interrupt from PIR in next vmentry.
4151  */
4152 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4153 {
4154         struct vcpu_vmx *vmx = to_vmx(vcpu);
4155         int r;
4156
4157         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4158                 return;
4159
4160         r = pi_test_and_set_on(&vmx->pi_desc);
4161         kvm_make_request(KVM_REQ_EVENT, vcpu);
4162 #ifdef CONFIG_SMP
4163         if (!r && (vcpu->mode == IN_GUEST_MODE))
4164                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4165                                 POSTED_INTR_VECTOR);
4166         else
4167 #endif
4168                 kvm_vcpu_kick(vcpu);
4169 }
4170
4171 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4172 {
4173         struct vcpu_vmx *vmx = to_vmx(vcpu);
4174
4175         if (!pi_test_and_clear_on(&vmx->pi_desc))
4176                 return;
4177
4178         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4179 }
4180
4181 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4182 {
4183         return;
4184 }
4185
4186 /*
4187  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4188  * will not change in the lifetime of the guest.
4189  * Note that host-state that does change is set elsewhere. E.g., host-state
4190  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4191  */
4192 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4193 {
4194         u32 low32, high32;
4195         unsigned long tmpl;
4196         struct desc_ptr dt;
4197
4198         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4199         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4200         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4201
4202         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4203 #ifdef CONFIG_X86_64
4204         /*
4205          * Load null selectors, so we can avoid reloading them in
4206          * __vmx_load_host_state(), in case userspace uses the null selectors
4207          * too (the expected case).
4208          */
4209         vmcs_write16(HOST_DS_SELECTOR, 0);
4210         vmcs_write16(HOST_ES_SELECTOR, 0);
4211 #else
4212         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4213         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4214 #endif
4215         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4216         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4217
4218         native_store_idt(&dt);
4219         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4220         vmx->host_idt_base = dt.address;
4221
4222         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4223
4224         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4225         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4226         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4227         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4228
4229         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4230                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4231                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4232         }
4233 }
4234
4235 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4236 {
4237         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4238         if (enable_ept)
4239                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4240         if (is_guest_mode(&vmx->vcpu))
4241                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4242                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4243         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4244 }
4245
4246 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4247 {
4248         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4249
4250         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4251                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4252         return pin_based_exec_ctrl;
4253 }
4254
4255 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4256 {
4257         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4258
4259         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4260                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4261
4262         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4263                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4264 #ifdef CONFIG_X86_64
4265                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4266                                 CPU_BASED_CR8_LOAD_EXITING;
4267 #endif
4268         }
4269         if (!enable_ept)
4270                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4271                                 CPU_BASED_CR3_LOAD_EXITING  |
4272                                 CPU_BASED_INVLPG_EXITING;
4273         return exec_control;
4274 }
4275
4276 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4277 {
4278         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4279         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4280                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4281         if (vmx->vpid == 0)
4282                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4283         if (!enable_ept) {
4284                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4285                 enable_unrestricted_guest = 0;
4286                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4287                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4288         }
4289         if (!enable_unrestricted_guest)
4290                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4291         if (!ple_gap)
4292                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4293         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4294                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4295                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4296         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4297         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4298            (handle_vmptrld).
4299            We can NOT enable shadow_vmcs here because we don't have yet
4300            a current VMCS12
4301         */
4302         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4303         return exec_control;
4304 }
4305
4306 static void ept_set_mmio_spte_mask(void)
4307 {
4308         /*
4309          * EPT Misconfigurations can be generated if the value of bits 2:0
4310          * of an EPT paging-structure entry is 110b (write/execute).
4311          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4312          * spte.
4313          */
4314         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4315 }
4316
4317 /*
4318  * Sets up the vmcs for emulated real mode.
4319  */
4320 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4321 {
4322 #ifdef CONFIG_X86_64
4323         unsigned long a;
4324 #endif
4325         int i;
4326
4327         /* I/O */
4328         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4329         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4330
4331         if (enable_shadow_vmcs) {
4332                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4333                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4334         }
4335         if (cpu_has_vmx_msr_bitmap())
4336                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4337
4338         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4339
4340         /* Control */
4341         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4342
4343         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4344
4345         if (cpu_has_secondary_exec_ctrls()) {
4346                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4347                                 vmx_secondary_exec_control(vmx));
4348         }
4349
4350         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4351                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4352                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4353                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4354                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4355
4356                 vmcs_write16(GUEST_INTR_STATUS, 0);
4357
4358                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4359                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4360         }
4361
4362         if (ple_gap) {
4363                 vmcs_write32(PLE_GAP, ple_gap);
4364                 vmcs_write32(PLE_WINDOW, ple_window);
4365         }
4366
4367         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4368         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4369         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4370
4371         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4372         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4373         vmx_set_constant_host_state(vmx);
4374 #ifdef CONFIG_X86_64
4375         rdmsrl(MSR_FS_BASE, a);
4376         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4377         rdmsrl(MSR_GS_BASE, a);
4378         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4379 #else
4380         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4381         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4382 #endif
4383
4384         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4385         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4386         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4387         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4388         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4389
4390         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4391                 u32 msr_low, msr_high;
4392                 u64 host_pat;
4393                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4394                 host_pat = msr_low | ((u64) msr_high << 32);
4395                 /* Write the default value follow host pat */
4396                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4397                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4398                 vmx->vcpu.arch.pat = host_pat;
4399         }
4400
4401         for (i = 0; i < NR_VMX_MSR; ++i) {
4402                 u32 index = vmx_msr_index[i];
4403                 u32 data_low, data_high;
4404                 int j = vmx->nmsrs;
4405
4406                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4407                         continue;
4408                 if (wrmsr_safe(index, data_low, data_high) < 0)
4409                         continue;
4410                 vmx->guest_msrs[j].index = i;
4411                 vmx->guest_msrs[j].data = 0;
4412                 vmx->guest_msrs[j].mask = -1ull;
4413                 ++vmx->nmsrs;
4414         }
4415
4416
4417         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4418
4419         /* 22.2.1, 20.8.1 */
4420         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4421
4422         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4423         set_cr4_guest_host_mask(vmx);
4424
4425         return 0;
4426 }
4427
4428 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4429 {
4430         struct vcpu_vmx *vmx = to_vmx(vcpu);
4431         struct msr_data apic_base_msr;
4432
4433         vmx->rmode.vm86_active = 0;
4434
4435         vmx->soft_vnmi_blocked = 0;
4436
4437         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4438         kvm_set_cr8(&vmx->vcpu, 0);
4439         apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4440         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4441                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4442         apic_base_msr.host_initiated = true;
4443         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4444
4445         vmx_segment_cache_clear(vmx);
4446
4447         seg_setup(VCPU_SREG_CS);
4448         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4449         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4450
4451         seg_setup(VCPU_SREG_DS);
4452         seg_setup(VCPU_SREG_ES);
4453         seg_setup(VCPU_SREG_FS);
4454         seg_setup(VCPU_SREG_GS);
4455         seg_setup(VCPU_SREG_SS);
4456
4457         vmcs_write16(GUEST_TR_SELECTOR, 0);
4458         vmcs_writel(GUEST_TR_BASE, 0);
4459         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4460         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4461
4462         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4463         vmcs_writel(GUEST_LDTR_BASE, 0);
4464         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4465         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4466
4467         vmcs_write32(GUEST_SYSENTER_CS, 0);
4468         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4469         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4470
4471         vmcs_writel(GUEST_RFLAGS, 0x02);
4472         kvm_rip_write(vcpu, 0xfff0);
4473
4474         vmcs_writel(GUEST_GDTR_BASE, 0);
4475         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4476
4477         vmcs_writel(GUEST_IDTR_BASE, 0);
4478         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4479
4480         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4481         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4482         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4483
4484         /* Special registers */
4485         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4486
4487         setup_msrs(vmx);
4488
4489         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4490
4491         if (cpu_has_vmx_tpr_shadow()) {
4492                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4493                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4494                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4495                                      __pa(vmx->vcpu.arch.apic->regs));
4496                 vmcs_write32(TPR_THRESHOLD, 0);
4497         }
4498
4499         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4500                 vmcs_write64(APIC_ACCESS_ADDR,
4501                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4502
4503         if (vmx_vm_has_apicv(vcpu->kvm))
4504                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4505
4506         if (vmx->vpid != 0)
4507                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4508
4509         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4510         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4511         vmx_set_cr4(&vmx->vcpu, 0);
4512         vmx_set_efer(&vmx->vcpu, 0);
4513         vmx_fpu_activate(&vmx->vcpu);
4514         update_exception_bitmap(&vmx->vcpu);
4515
4516         vpid_sync_context(vmx);
4517 }
4518
4519 /*
4520  * In nested virtualization, check if L1 asked to exit on external interrupts.
4521  * For most existing hypervisors, this will always return true.
4522  */
4523 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4524 {
4525         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4526                 PIN_BASED_EXT_INTR_MASK;
4527 }
4528
4529 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4530 {
4531         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4532                 PIN_BASED_NMI_EXITING;
4533 }
4534
4535 static void enable_irq_window(struct kvm_vcpu *vcpu)
4536 {
4537         u32 cpu_based_vm_exec_control;
4538
4539         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4540         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4541         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4542 }
4543
4544 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4545 {
4546         u32 cpu_based_vm_exec_control;
4547
4548         if (!cpu_has_virtual_nmis() ||
4549             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4550                 enable_irq_window(vcpu);
4551                 return;
4552         }
4553
4554         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4555         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4556         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4557 }
4558
4559 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4560 {
4561         struct vcpu_vmx *vmx = to_vmx(vcpu);
4562         uint32_t intr;
4563         int irq = vcpu->arch.interrupt.nr;
4564
4565         trace_kvm_inj_virq(irq);
4566
4567         ++vcpu->stat.irq_injections;
4568         if (vmx->rmode.vm86_active) {
4569                 int inc_eip = 0;
4570                 if (vcpu->arch.interrupt.soft)
4571                         inc_eip = vcpu->arch.event_exit_inst_len;
4572                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4573                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4574                 return;
4575         }
4576         intr = irq | INTR_INFO_VALID_MASK;
4577         if (vcpu->arch.interrupt.soft) {
4578                 intr |= INTR_TYPE_SOFT_INTR;
4579                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4580                              vmx->vcpu.arch.event_exit_inst_len);
4581         } else
4582                 intr |= INTR_TYPE_EXT_INTR;
4583         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4584 }
4585
4586 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4587 {
4588         struct vcpu_vmx *vmx = to_vmx(vcpu);
4589
4590         if (is_guest_mode(vcpu))
4591                 return;
4592
4593         if (!cpu_has_virtual_nmis()) {
4594                 /*
4595                  * Tracking the NMI-blocked state in software is built upon
4596                  * finding the next open IRQ window. This, in turn, depends on
4597                  * well-behaving guests: They have to keep IRQs disabled at
4598                  * least as long as the NMI handler runs. Otherwise we may
4599                  * cause NMI nesting, maybe breaking the guest. But as this is
4600                  * highly unlikely, we can live with the residual risk.
4601                  */
4602                 vmx->soft_vnmi_blocked = 1;
4603                 vmx->vnmi_blocked_time = 0;
4604         }
4605
4606         ++vcpu->stat.nmi_injections;
4607         vmx->nmi_known_unmasked = false;
4608         if (vmx->rmode.vm86_active) {
4609                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4610                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4611                 return;
4612         }
4613         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4614                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4615 }
4616
4617 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4618 {
4619         if (!cpu_has_virtual_nmis())
4620                 return to_vmx(vcpu)->soft_vnmi_blocked;
4621         if (to_vmx(vcpu)->nmi_known_unmasked)
4622                 return false;
4623         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4624 }
4625
4626 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4627 {
4628         struct vcpu_vmx *vmx = to_vmx(vcpu);
4629
4630         if (!cpu_has_virtual_nmis()) {
4631                 if (vmx->soft_vnmi_blocked != masked) {
4632                         vmx->soft_vnmi_blocked = masked;
4633                         vmx->vnmi_blocked_time = 0;
4634                 }
4635         } else {
4636                 vmx->nmi_known_unmasked = !masked;
4637                 if (masked)
4638                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4639                                       GUEST_INTR_STATE_NMI);
4640                 else
4641                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4642                                         GUEST_INTR_STATE_NMI);
4643         }
4644 }
4645
4646 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4647 {
4648         if (to_vmx(vcpu)->nested.nested_run_pending)
4649                 return 0;
4650
4651         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4652                 return 0;
4653
4654         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4655                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4656                    | GUEST_INTR_STATE_NMI));
4657 }
4658
4659 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4660 {
4661         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4662                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4663                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4664                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4665 }
4666
4667 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4668 {
4669         int ret;
4670         struct kvm_userspace_memory_region tss_mem = {
4671                 .slot = TSS_PRIVATE_MEMSLOT,
4672                 .guest_phys_addr = addr,
4673                 .memory_size = PAGE_SIZE * 3,
4674                 .flags = 0,
4675         };
4676
4677         ret = kvm_set_memory_region(kvm, &tss_mem);
4678         if (ret)
4679                 return ret;
4680         kvm->arch.tss_addr = addr;
4681         if (!init_rmode_tss(kvm))
4682                 return  -ENOMEM;
4683
4684         return 0;
4685 }
4686
4687 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4688 {
4689         switch (vec) {
4690         case BP_VECTOR:
4691                 /*
4692                  * Update instruction length as we may reinject the exception
4693                  * from user space while in guest debugging mode.
4694                  */
4695                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4696                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4697                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4698                         return false;
4699                 /* fall through */
4700         case DB_VECTOR:
4701                 if (vcpu->guest_debug &
4702                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4703                         return false;
4704                 /* fall through */
4705         case DE_VECTOR:
4706         case OF_VECTOR:
4707         case BR_VECTOR:
4708         case UD_VECTOR:
4709         case DF_VECTOR:
4710         case SS_VECTOR:
4711         case GP_VECTOR:
4712         case MF_VECTOR:
4713                 return true;
4714         break;
4715         }
4716         return false;
4717 }
4718
4719 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4720                                   int vec, u32 err_code)
4721 {
4722         /*
4723          * Instruction with address size override prefix opcode 0x67
4724          * Cause the #SS fault with 0 error code in VM86 mode.
4725          */
4726         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4727                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4728                         if (vcpu->arch.halt_request) {
4729                                 vcpu->arch.halt_request = 0;
4730                                 return kvm_emulate_halt(vcpu);
4731                         }
4732                         return 1;
4733                 }
4734                 return 0;
4735         }
4736
4737         /*
4738          * Forward all other exceptions that are valid in real mode.
4739          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4740          *        the required debugging infrastructure rework.
4741          */
4742         kvm_queue_exception(vcpu, vec);
4743         return 1;
4744 }
4745
4746 /*
4747  * Trigger machine check on the host. We assume all the MSRs are already set up
4748  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4749  * We pass a fake environment to the machine check handler because we want
4750  * the guest to be always treated like user space, no matter what context
4751  * it used internally.
4752  */
4753 static void kvm_machine_check(void)
4754 {
4755 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4756         struct pt_regs regs = {
4757                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4758                 .flags = X86_EFLAGS_IF,
4759         };
4760
4761         do_machine_check(&regs, 0);
4762 #endif
4763 }
4764
4765 static int handle_machine_check(struct kvm_vcpu *vcpu)
4766 {
4767         /* already handled by vcpu_run */
4768         return 1;
4769 }
4770
4771 static int handle_exception(struct kvm_vcpu *vcpu)
4772 {
4773         struct vcpu_vmx *vmx = to_vmx(vcpu);
4774         struct kvm_run *kvm_run = vcpu->run;
4775         u32 intr_info, ex_no, error_code;
4776         unsigned long cr2, rip, dr6;
4777         u32 vect_info;
4778         enum emulation_result er;
4779
4780         vect_info = vmx->idt_vectoring_info;
4781         intr_info = vmx->exit_intr_info;
4782
4783         if (is_machine_check(intr_info))
4784                 return handle_machine_check(vcpu);
4785
4786         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4787                 return 1;  /* already handled by vmx_vcpu_run() */
4788
4789         if (is_no_device(intr_info)) {
4790                 vmx_fpu_activate(vcpu);
4791                 return 1;
4792         }
4793
4794         if (is_invalid_opcode(intr_info)) {
4795                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4796                 if (er != EMULATE_DONE)
4797                         kvm_queue_exception(vcpu, UD_VECTOR);
4798                 return 1;
4799         }
4800
4801         error_code = 0;
4802         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4803                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4804
4805         /*
4806          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4807          * MMIO, it is better to report an internal error.
4808          * See the comments in vmx_handle_exit.
4809          */
4810         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4811             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4812                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4813                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4814                 vcpu->run->internal.ndata = 2;
4815                 vcpu->run->internal.data[0] = vect_info;
4816                 vcpu->run->internal.data[1] = intr_info;
4817                 return 0;
4818         }
4819
4820         if (is_page_fault(intr_info)) {
4821                 /* EPT won't cause page fault directly */
4822                 BUG_ON(enable_ept);
4823                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4824                 trace_kvm_page_fault(cr2, error_code);
4825
4826                 if (kvm_event_needs_reinjection(vcpu))
4827                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4828                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4829         }
4830
4831         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4832
4833         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4834                 return handle_rmode_exception(vcpu, ex_no, error_code);
4835
4836         switch (ex_no) {
4837         case DB_VECTOR:
4838                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4839                 if (!(vcpu->guest_debug &
4840                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4841                         vcpu->arch.dr6 &= ~15;
4842                         vcpu->arch.dr6 |= dr6;
4843                         kvm_queue_exception(vcpu, DB_VECTOR);
4844                         return 1;
4845                 }
4846                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4847                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4848                 /* fall through */
4849         case BP_VECTOR:
4850                 /*
4851                  * Update instruction length as we may reinject #BP from
4852                  * user space while in guest debugging mode. Reading it for
4853                  * #DB as well causes no harm, it is not used in that case.
4854                  */
4855                 vmx->vcpu.arch.event_exit_inst_len =
4856                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4857                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4858                 rip = kvm_rip_read(vcpu);
4859                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4860                 kvm_run->debug.arch.exception = ex_no;
4861                 break;
4862         default:
4863                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4864                 kvm_run->ex.exception = ex_no;
4865                 kvm_run->ex.error_code = error_code;
4866                 break;
4867         }
4868         return 0;
4869 }
4870
4871 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4872 {
4873         ++vcpu->stat.irq_exits;
4874         return 1;
4875 }
4876
4877 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4878 {
4879         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4880         return 0;
4881 }
4882
4883 static int handle_io(struct kvm_vcpu *vcpu)
4884 {
4885         unsigned long exit_qualification;
4886         int size, in, string;
4887         unsigned port;
4888
4889         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4890         string = (exit_qualification & 16) != 0;
4891         in = (exit_qualification & 8) != 0;
4892
4893         ++vcpu->stat.io_exits;
4894
4895         if (string || in)
4896                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4897
4898         port = exit_qualification >> 16;
4899         size = (exit_qualification & 7) + 1;
4900         skip_emulated_instruction(vcpu);
4901
4902         return kvm_fast_pio_out(vcpu, size, port);
4903 }
4904
4905 static void
4906 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4907 {
4908         /*
4909          * Patch in the VMCALL instruction:
4910          */
4911         hypercall[0] = 0x0f;
4912         hypercall[1] = 0x01;
4913         hypercall[2] = 0xc1;
4914 }
4915
4916 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4917 {
4918         unsigned long always_on = VMXON_CR0_ALWAYSON;
4919
4920         if (nested_vmx_secondary_ctls_high &
4921                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4922             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4923                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4924         return (val & always_on) == always_on;
4925 }
4926
4927 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4928 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4929 {
4930         if (is_guest_mode(vcpu)) {
4931                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4932                 unsigned long orig_val = val;
4933
4934                 /*
4935                  * We get here when L2 changed cr0 in a way that did not change
4936                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4937                  * but did change L0 shadowed bits. So we first calculate the
4938                  * effective cr0 value that L1 would like to write into the
4939                  * hardware. It consists of the L2-owned bits from the new
4940                  * value combined with the L1-owned bits from L1's guest_cr0.
4941                  */
4942                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4943                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4944
4945                 if (!nested_cr0_valid(vmcs12, val))
4946                         return 1;
4947
4948                 if (kvm_set_cr0(vcpu, val))
4949                         return 1;
4950                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4951                 return 0;
4952         } else {
4953                 if (to_vmx(vcpu)->nested.vmxon &&
4954                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4955                         return 1;
4956                 return kvm_set_cr0(vcpu, val);
4957         }
4958 }
4959
4960 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4961 {
4962         if (is_guest_mode(vcpu)) {
4963                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4964                 unsigned long orig_val = val;
4965
4966                 /* analogously to handle_set_cr0 */
4967                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4968                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4969                 if (kvm_set_cr4(vcpu, val))
4970                         return 1;
4971                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4972                 return 0;
4973         } else
4974                 return kvm_set_cr4(vcpu, val);
4975 }
4976
4977 /* called to set cr0 as approriate for clts instruction exit. */
4978 static void handle_clts(struct kvm_vcpu *vcpu)
4979 {
4980         if (is_guest_mode(vcpu)) {
4981                 /*
4982                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4983                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4984                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4985                  */
4986                 vmcs_writel(CR0_READ_SHADOW,
4987                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4988                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4989         } else
4990                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4991 }
4992
4993 static int handle_cr(struct kvm_vcpu *vcpu)
4994 {
4995         unsigned long exit_qualification, val;
4996         int cr;
4997         int reg;
4998         int err;
4999
5000         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5001         cr = exit_qualification & 15;
5002         reg = (exit_qualification >> 8) & 15;
5003         switch ((exit_qualification >> 4) & 3) {
5004         case 0: /* mov to cr */
5005                 val = kvm_register_read(vcpu, reg);
5006                 trace_kvm_cr_write(cr, val);
5007                 switch (cr) {
5008                 case 0:
5009                         err = handle_set_cr0(vcpu, val);
5010                         kvm_complete_insn_gp(vcpu, err);
5011                         return 1;
5012                 case 3:
5013                         err = kvm_set_cr3(vcpu, val);
5014                         kvm_complete_insn_gp(vcpu, err);
5015                         return 1;
5016                 case 4:
5017                         err = handle_set_cr4(vcpu, val);
5018                         kvm_complete_insn_gp(vcpu, err);
5019                         return 1;
5020                 case 8: {
5021                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5022                                 u8 cr8 = kvm_register_read(vcpu, reg);
5023                                 err = kvm_set_cr8(vcpu, cr8);
5024                                 kvm_complete_insn_gp(vcpu, err);
5025                                 if (irqchip_in_kernel(vcpu->kvm))
5026                                         return 1;
5027                                 if (cr8_prev <= cr8)
5028                                         return 1;
5029                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5030                                 return 0;
5031                         }
5032                 }
5033                 break;
5034         case 2: /* clts */
5035                 handle_clts(vcpu);
5036                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5037                 skip_emulated_instruction(vcpu);
5038                 vmx_fpu_activate(vcpu);
5039                 return 1;
5040         case 1: /*mov from cr*/
5041                 switch (cr) {
5042                 case 3:
5043                         val = kvm_read_cr3(vcpu);
5044                         kvm_register_write(vcpu, reg, val);
5045                         trace_kvm_cr_read(cr, val);
5046                         skip_emulated_instruction(vcpu);
5047                         return 1;
5048                 case 8:
5049                         val = kvm_get_cr8(vcpu);
5050                         kvm_register_write(vcpu, reg, val);
5051                         trace_kvm_cr_read(cr, val);
5052                         skip_emulated_instruction(vcpu);
5053                         return 1;
5054                 }
5055                 break;
5056         case 3: /* lmsw */
5057                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5058                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5059                 kvm_lmsw(vcpu, val);
5060
5061                 skip_emulated_instruction(vcpu);
5062                 return 1;
5063         default:
5064                 break;
5065         }
5066         vcpu->run->exit_reason = 0;
5067         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5068                (int)(exit_qualification >> 4) & 3, cr);
5069         return 0;
5070 }
5071
5072 static int handle_dr(struct kvm_vcpu *vcpu)
5073 {
5074         unsigned long exit_qualification;
5075         int dr, reg;
5076
5077         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5078         if (!kvm_require_cpl(vcpu, 0))
5079                 return 1;
5080         dr = vmcs_readl(GUEST_DR7);
5081         if (dr & DR7_GD) {
5082                 /*
5083                  * As the vm-exit takes precedence over the debug trap, we
5084                  * need to emulate the latter, either for the host or the
5085                  * guest debugging itself.
5086                  */
5087                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5088                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5089                         vcpu->run->debug.arch.dr7 = dr;
5090                         vcpu->run->debug.arch.pc =
5091                                 vmcs_readl(GUEST_CS_BASE) +
5092                                 vmcs_readl(GUEST_RIP);
5093                         vcpu->run->debug.arch.exception = DB_VECTOR;
5094                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5095                         return 0;
5096                 } else {
5097                         vcpu->arch.dr7 &= ~DR7_GD;
5098                         vcpu->arch.dr6 |= DR6_BD;
5099                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5100                         kvm_queue_exception(vcpu, DB_VECTOR);
5101                         return 1;
5102                 }
5103         }
5104
5105         if (vcpu->guest_debug == 0) {
5106                 u32 cpu_based_vm_exec_control;
5107
5108                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5109                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5110                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5111
5112                 /*
5113                  * No more DR vmexits; force a reload of the debug registers
5114                  * and reenter on this instruction.  The next vmexit will
5115                  * retrieve the full state of the debug registers.
5116                  */
5117                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5118                 return 1;
5119         }
5120
5121         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5122         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5123         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5124         if (exit_qualification & TYPE_MOV_FROM_DR) {
5125                 unsigned long val;
5126
5127                 if (kvm_get_dr(vcpu, dr, &val))
5128                         return 1;
5129                 kvm_register_write(vcpu, reg, val);
5130         } else
5131                 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5132                         return 1;
5133
5134         skip_emulated_instruction(vcpu);
5135         return 1;
5136 }
5137
5138 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5139 {
5140         return vcpu->arch.dr6;
5141 }
5142
5143 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5144 {
5145 }
5146
5147 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5148 {
5149         u32 cpu_based_vm_exec_control;
5150
5151         get_debugreg(vcpu->arch.db[0], 0);
5152         get_debugreg(vcpu->arch.db[1], 1);
5153         get_debugreg(vcpu->arch.db[2], 2);
5154         get_debugreg(vcpu->arch.db[3], 3);
5155         get_debugreg(vcpu->arch.dr6, 6);
5156         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5157
5158         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5159
5160         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5161         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5162         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5163 }
5164
5165 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5166 {
5167         vmcs_writel(GUEST_DR7, val);
5168 }
5169
5170 static int handle_cpuid(struct kvm_vcpu *vcpu)
5171 {
5172         kvm_emulate_cpuid(vcpu);
5173         return 1;
5174 }
5175
5176 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5177 {
5178         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5179         u64 data;
5180
5181         if (vmx_get_msr(vcpu, ecx, &data)) {
5182                 trace_kvm_msr_read_ex(ecx);
5183                 kvm_inject_gp(vcpu, 0);
5184                 return 1;
5185         }
5186
5187         trace_kvm_msr_read(ecx, data);
5188
5189         /* FIXME: handling of bits 32:63 of rax, rdx */
5190         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5191         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5192         skip_emulated_instruction(vcpu);
5193         return 1;
5194 }
5195
5196 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5197 {
5198         struct msr_data msr;
5199         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5200         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5201                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5202
5203         msr.data = data;
5204         msr.index = ecx;
5205         msr.host_initiated = false;
5206         if (vmx_set_msr(vcpu, &msr) != 0) {
5207                 trace_kvm_msr_write_ex(ecx, data);
5208                 kvm_inject_gp(vcpu, 0);
5209                 return 1;
5210         }
5211
5212         trace_kvm_msr_write(ecx, data);
5213         skip_emulated_instruction(vcpu);
5214         return 1;
5215 }
5216
5217 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5218 {
5219         kvm_make_request(KVM_REQ_EVENT, vcpu);
5220         return 1;
5221 }
5222
5223 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5224 {
5225         u32 cpu_based_vm_exec_control;
5226
5227         /* clear pending irq */
5228         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5229         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5230         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5231
5232         kvm_make_request(KVM_REQ_EVENT, vcpu);
5233
5234         ++vcpu->stat.irq_window_exits;
5235
5236         /*
5237          * If the user space waits to inject interrupts, exit as soon as
5238          * possible
5239          */
5240         if (!irqchip_in_kernel(vcpu->kvm) &&
5241             vcpu->run->request_interrupt_window &&
5242             !kvm_cpu_has_interrupt(vcpu)) {
5243                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5244                 return 0;
5245         }
5246         return 1;
5247 }
5248
5249 static int handle_halt(struct kvm_vcpu *vcpu)
5250 {
5251         skip_emulated_instruction(vcpu);
5252         return kvm_emulate_halt(vcpu);
5253 }
5254
5255 static int handle_vmcall(struct kvm_vcpu *vcpu)
5256 {
5257         skip_emulated_instruction(vcpu);
5258         kvm_emulate_hypercall(vcpu);
5259         return 1;
5260 }
5261
5262 static int handle_invd(struct kvm_vcpu *vcpu)
5263 {
5264         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5265 }
5266
5267 static int handle_invlpg(struct kvm_vcpu *vcpu)
5268 {
5269         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5270
5271         kvm_mmu_invlpg(vcpu, exit_qualification);
5272         skip_emulated_instruction(vcpu);
5273         return 1;
5274 }
5275
5276 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5277 {
5278         int err;
5279
5280         err = kvm_rdpmc(vcpu);
5281         kvm_complete_insn_gp(vcpu, err);
5282
5283         return 1;
5284 }
5285
5286 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5287 {
5288         skip_emulated_instruction(vcpu);
5289         kvm_emulate_wbinvd(vcpu);
5290         return 1;
5291 }
5292
5293 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5294 {
5295         u64 new_bv = kvm_read_edx_eax(vcpu);
5296         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5297
5298         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5299                 skip_emulated_instruction(vcpu);
5300         return 1;
5301 }
5302
5303 static int handle_apic_access(struct kvm_vcpu *vcpu)
5304 {
5305         if (likely(fasteoi)) {
5306                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5307                 int access_type, offset;
5308
5309                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5310                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5311                 /*
5312                  * Sane guest uses MOV to write EOI, with written value
5313                  * not cared. So make a short-circuit here by avoiding
5314                  * heavy instruction emulation.
5315                  */
5316                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5317                     (offset == APIC_EOI)) {
5318                         kvm_lapic_set_eoi(vcpu);
5319                         skip_emulated_instruction(vcpu);
5320                         return 1;
5321                 }
5322         }
5323         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5324 }
5325
5326 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5327 {
5328         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5329         int vector = exit_qualification & 0xff;
5330
5331         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5332         kvm_apic_set_eoi_accelerated(vcpu, vector);
5333         return 1;
5334 }
5335
5336 static int handle_apic_write(struct kvm_vcpu *vcpu)
5337 {
5338         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5339         u32 offset = exit_qualification & 0xfff;
5340
5341         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5342         kvm_apic_write_nodecode(vcpu, offset);
5343         return 1;
5344 }
5345
5346 static int handle_task_switch(struct kvm_vcpu *vcpu)
5347 {
5348         struct vcpu_vmx *vmx = to_vmx(vcpu);
5349         unsigned long exit_qualification;
5350         bool has_error_code = false;
5351         u32 error_code = 0;
5352         u16 tss_selector;
5353         int reason, type, idt_v, idt_index;
5354
5355         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5356         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5357         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5358
5359         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5360
5361         reason = (u32)exit_qualification >> 30;
5362         if (reason == TASK_SWITCH_GATE && idt_v) {
5363                 switch (type) {
5364                 case INTR_TYPE_NMI_INTR:
5365                         vcpu->arch.nmi_injected = false;
5366                         vmx_set_nmi_mask(vcpu, true);
5367                         break;
5368                 case INTR_TYPE_EXT_INTR:
5369                 case INTR_TYPE_SOFT_INTR:
5370                         kvm_clear_interrupt_queue(vcpu);
5371                         break;
5372                 case INTR_TYPE_HARD_EXCEPTION:
5373                         if (vmx->idt_vectoring_info &
5374                             VECTORING_INFO_DELIVER_CODE_MASK) {
5375                                 has_error_code = true;
5376                                 error_code =
5377                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5378                         }
5379                         /* fall through */
5380                 case INTR_TYPE_SOFT_EXCEPTION:
5381                         kvm_clear_exception_queue(vcpu);
5382                         break;
5383                 default:
5384                         break;
5385                 }
5386         }
5387         tss_selector = exit_qualification;
5388
5389         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5390                        type != INTR_TYPE_EXT_INTR &&
5391                        type != INTR_TYPE_NMI_INTR))
5392                 skip_emulated_instruction(vcpu);
5393
5394         if (kvm_task_switch(vcpu, tss_selector,
5395                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5396                             has_error_code, error_code) == EMULATE_FAIL) {
5397                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5398                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5399                 vcpu->run->internal.ndata = 0;
5400                 return 0;
5401         }
5402
5403         /* clear all local breakpoint enable flags */
5404         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5405
5406         /*
5407          * TODO: What about debug traps on tss switch?
5408          *       Are we supposed to inject them and update dr6?
5409          */
5410
5411         return 1;
5412 }
5413
5414 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5415 {
5416         unsigned long exit_qualification;
5417         gpa_t gpa;
5418         u32 error_code;
5419         int gla_validity;
5420
5421         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5422
5423         gla_validity = (exit_qualification >> 7) & 0x3;
5424         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5425                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5426                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5427                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5428                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5429                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5430                         (long unsigned int)exit_qualification);
5431                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5432                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5433                 return 0;
5434         }
5435
5436         /*
5437          * EPT violation happened while executing iret from NMI,
5438          * "blocked by NMI" bit has to be set before next VM entry.
5439          * There are errata that may cause this bit to not be set:
5440          * AAK134, BY25.
5441          */
5442         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5443                         cpu_has_virtual_nmis() &&
5444                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5445                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5446
5447         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5448         trace_kvm_page_fault(gpa, exit_qualification);
5449
5450         /* It is a write fault? */
5451         error_code = exit_qualification & (1U << 1);
5452         /* It is a fetch fault? */
5453         error_code |= (exit_qualification & (1U << 2)) << 2;
5454         /* ept page table is present? */
5455         error_code |= (exit_qualification >> 3) & 0x1;
5456
5457         vcpu->arch.exit_qualification = exit_qualification;
5458
5459         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5460 }
5461
5462 static u64 ept_rsvd_mask(u64 spte, int level)
5463 {
5464         int i;
5465         u64 mask = 0;
5466
5467         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5468                 mask |= (1ULL << i);
5469
5470         if (level > 2)
5471                 /* bits 7:3 reserved */
5472                 mask |= 0xf8;
5473         else if (level == 2) {
5474                 if (spte & (1ULL << 7))
5475                         /* 2MB ref, bits 20:12 reserved */
5476                         mask |= 0x1ff000;
5477                 else
5478                         /* bits 6:3 reserved */
5479                         mask |= 0x78;
5480         }
5481
5482         return mask;
5483 }
5484
5485 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5486                                        int level)
5487 {
5488         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5489
5490         /* 010b (write-only) */
5491         WARN_ON((spte & 0x7) == 0x2);
5492
5493         /* 110b (write/execute) */
5494         WARN_ON((spte & 0x7) == 0x6);
5495
5496         /* 100b (execute-only) and value not supported by logical processor */
5497         if (!cpu_has_vmx_ept_execute_only())
5498                 WARN_ON((spte & 0x7) == 0x4);
5499
5500         /* not 000b */
5501         if ((spte & 0x7)) {
5502                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5503
5504                 if (rsvd_bits != 0) {
5505                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5506                                          __func__, rsvd_bits);
5507                         WARN_ON(1);
5508                 }
5509
5510                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5511                         u64 ept_mem_type = (spte & 0x38) >> 3;
5512
5513                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5514                             ept_mem_type == 7) {
5515                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5516                                                 __func__, ept_mem_type);
5517                                 WARN_ON(1);
5518                         }
5519                 }
5520         }
5521 }
5522
5523 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5524 {
5525         u64 sptes[4];
5526         int nr_sptes, i, ret;
5527         gpa_t gpa;
5528
5529         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5530
5531         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5532         if (likely(ret == RET_MMIO_PF_EMULATE))
5533                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5534                                               EMULATE_DONE;
5535
5536         if (unlikely(ret == RET_MMIO_PF_INVALID))
5537                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5538
5539         if (unlikely(ret == RET_MMIO_PF_RETRY))
5540                 return 1;
5541
5542         /* It is the real ept misconfig */
5543         printk(KERN_ERR "EPT: Misconfiguration.\n");
5544         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5545
5546         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5547
5548         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5549                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5550
5551         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5552         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5553
5554         return 0;
5555 }
5556
5557 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5558 {
5559         u32 cpu_based_vm_exec_control;
5560
5561         /* clear pending NMI */
5562         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5563         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5564         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5565         ++vcpu->stat.nmi_window_exits;
5566         kvm_make_request(KVM_REQ_EVENT, vcpu);
5567
5568         return 1;
5569 }
5570
5571 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5572 {
5573         struct vcpu_vmx *vmx = to_vmx(vcpu);
5574         enum emulation_result err = EMULATE_DONE;
5575         int ret = 1;
5576         u32 cpu_exec_ctrl;
5577         bool intr_window_requested;
5578         unsigned count = 130;
5579
5580         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5581         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5582
5583         while (!guest_state_valid(vcpu) && count-- != 0) {
5584                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5585                         return handle_interrupt_window(&vmx->vcpu);
5586
5587                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5588                         return 1;
5589
5590                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5591
5592                 if (err == EMULATE_USER_EXIT) {
5593                         ++vcpu->stat.mmio_exits;
5594                         ret = 0;
5595                         goto out;
5596                 }
5597
5598                 if (err != EMULATE_DONE) {
5599                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5600                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5601                         vcpu->run->internal.ndata = 0;
5602                         return 0;
5603                 }
5604
5605                 if (vcpu->arch.halt_request) {
5606                         vcpu->arch.halt_request = 0;
5607                         ret = kvm_emulate_halt(vcpu);
5608                         goto out;
5609                 }
5610
5611                 if (signal_pending(current))
5612                         goto out;
5613                 if (need_resched())
5614                         schedule();
5615         }
5616
5617         vmx->emulation_required = emulation_required(vcpu);
5618 out:
5619         return ret;
5620 }
5621
5622 /*
5623  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5624  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5625  */
5626 static int handle_pause(struct kvm_vcpu *vcpu)
5627 {
5628         skip_emulated_instruction(vcpu);
5629         kvm_vcpu_on_spin(vcpu);
5630
5631         return 1;
5632 }
5633
5634 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5635 {
5636         kvm_queue_exception(vcpu, UD_VECTOR);
5637         return 1;
5638 }
5639
5640 /*
5641  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5642  * We could reuse a single VMCS for all the L2 guests, but we also want the
5643  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5644  * allows keeping them loaded on the processor, and in the future will allow
5645  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5646  * every entry if they never change.
5647  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5648  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5649  *
5650  * The following functions allocate and free a vmcs02 in this pool.
5651  */
5652
5653 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5654 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5655 {
5656         struct vmcs02_list *item;
5657         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5658                 if (item->vmptr == vmx->nested.current_vmptr) {
5659                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5660                         return &item->vmcs02;
5661                 }
5662
5663         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5664                 /* Recycle the least recently used VMCS. */
5665                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5666                         struct vmcs02_list, list);
5667                 item->vmptr = vmx->nested.current_vmptr;
5668                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5669                 return &item->vmcs02;
5670         }
5671
5672         /* Create a new VMCS */
5673         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5674         if (!item)
5675                 return NULL;
5676         item->vmcs02.vmcs = alloc_vmcs();
5677         if (!item->vmcs02.vmcs) {
5678                 kfree(item);
5679                 return NULL;
5680         }
5681         loaded_vmcs_init(&item->vmcs02);
5682         item->vmptr = vmx->nested.current_vmptr;
5683         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5684         vmx->nested.vmcs02_num++;
5685         return &item->vmcs02;
5686 }
5687
5688 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5689 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5690 {
5691         struct vmcs02_list *item;
5692         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5693                 if (item->vmptr == vmptr) {
5694                         free_loaded_vmcs(&item->vmcs02);
5695                         list_del(&item->list);
5696                         kfree(item);
5697                         vmx->nested.vmcs02_num--;
5698                         return;
5699                 }
5700 }
5701
5702 /*
5703  * Free all VMCSs saved for this vcpu, except the one pointed by
5704  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5705  * currently used, if running L2), and vmcs01 when running L2.
5706  */
5707 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5708 {
5709         struct vmcs02_list *item, *n;
5710         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5711                 if (vmx->loaded_vmcs != &item->vmcs02)
5712                         free_loaded_vmcs(&item->vmcs02);
5713                 list_del(&item->list);
5714                 kfree(item);
5715         }
5716         vmx->nested.vmcs02_num = 0;
5717
5718         if (vmx->loaded_vmcs != &vmx->vmcs01)
5719                 free_loaded_vmcs(&vmx->vmcs01);
5720 }
5721
5722 /*
5723  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5724  * set the success or error code of an emulated VMX instruction, as specified
5725  * by Vol 2B, VMX Instruction Reference, "Conventions".
5726  */
5727 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5728 {
5729         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5730                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5731                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5732 }
5733
5734 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5735 {
5736         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5737                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5738                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5739                         | X86_EFLAGS_CF);
5740 }
5741
5742 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5743                                         u32 vm_instruction_error)
5744 {
5745         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5746                 /*
5747                  * failValid writes the error number to the current VMCS, which
5748                  * can't be done there isn't a current VMCS.
5749                  */
5750                 nested_vmx_failInvalid(vcpu);
5751                 return;
5752         }
5753         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5754                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5755                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5756                         | X86_EFLAGS_ZF);
5757         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5758         /*
5759          * We don't need to force a shadow sync because
5760          * VM_INSTRUCTION_ERROR is not shadowed
5761          */
5762 }
5763
5764 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5765 {
5766         struct vcpu_vmx *vmx =
5767                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5768
5769         vmx->nested.preemption_timer_expired = true;
5770         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5771         kvm_vcpu_kick(&vmx->vcpu);
5772
5773         return HRTIMER_NORESTART;
5774 }
5775
5776 /*
5777  * Emulate the VMXON instruction.
5778  * Currently, we just remember that VMX is active, and do not save or even
5779  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5780  * do not currently need to store anything in that guest-allocated memory
5781  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5782  * argument is different from the VMXON pointer (which the spec says they do).
5783  */
5784 static int handle_vmon(struct kvm_vcpu *vcpu)
5785 {
5786         struct kvm_segment cs;
5787         struct vcpu_vmx *vmx = to_vmx(vcpu);
5788         struct vmcs *shadow_vmcs;
5789         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5790                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5791
5792         /* The Intel VMX Instruction Reference lists a bunch of bits that
5793          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5794          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5795          * Otherwise, we should fail with #UD. We test these now:
5796          */
5797         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5798             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5799             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5800                 kvm_queue_exception(vcpu, UD_VECTOR);
5801                 return 1;
5802         }
5803
5804         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5805         if (is_long_mode(vcpu) && !cs.l) {
5806                 kvm_queue_exception(vcpu, UD_VECTOR);
5807                 return 1;
5808         }
5809
5810         if (vmx_get_cpl(vcpu)) {
5811                 kvm_inject_gp(vcpu, 0);
5812                 return 1;
5813         }
5814         if (vmx->nested.vmxon) {
5815                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5816                 skip_emulated_instruction(vcpu);
5817                 return 1;
5818         }
5819
5820         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5821                         != VMXON_NEEDED_FEATURES) {
5822                 kvm_inject_gp(vcpu, 0);
5823                 return 1;
5824         }
5825
5826         if (enable_shadow_vmcs) {
5827                 shadow_vmcs = alloc_vmcs();
5828                 if (!shadow_vmcs)
5829                         return -ENOMEM;
5830                 /* mark vmcs as shadow */
5831                 shadow_vmcs->revision_id |= (1u << 31);
5832                 /* init shadow vmcs */
5833                 vmcs_clear(shadow_vmcs);
5834                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5835         }
5836
5837         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5838         vmx->nested.vmcs02_num = 0;
5839
5840         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5841                      HRTIMER_MODE_REL);
5842         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5843
5844         vmx->nested.vmxon = true;
5845
5846         skip_emulated_instruction(vcpu);
5847         nested_vmx_succeed(vcpu);
5848         return 1;
5849 }
5850
5851 /*
5852  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5853  * for running VMX instructions (except VMXON, whose prerequisites are
5854  * slightly different). It also specifies what exception to inject otherwise.
5855  */
5856 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5857 {
5858         struct kvm_segment cs;
5859         struct vcpu_vmx *vmx = to_vmx(vcpu);
5860
5861         if (!vmx->nested.vmxon) {
5862                 kvm_queue_exception(vcpu, UD_VECTOR);
5863                 return 0;
5864         }
5865
5866         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5867         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5868             (is_long_mode(vcpu) && !cs.l)) {
5869                 kvm_queue_exception(vcpu, UD_VECTOR);
5870                 return 0;
5871         }
5872
5873         if (vmx_get_cpl(vcpu)) {
5874                 kvm_inject_gp(vcpu, 0);
5875                 return 0;
5876         }
5877
5878         return 1;
5879 }
5880
5881 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5882 {
5883         u32 exec_control;
5884         if (enable_shadow_vmcs) {
5885                 if (vmx->nested.current_vmcs12 != NULL) {
5886                         /* copy to memory all shadowed fields in case
5887                            they were modified */
5888                         copy_shadow_to_vmcs12(vmx);
5889                         vmx->nested.sync_shadow_vmcs = false;
5890                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5891                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5892                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5893                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5894                 }
5895         }
5896         kunmap(vmx->nested.current_vmcs12_page);
5897         nested_release_page(vmx->nested.current_vmcs12_page);
5898 }
5899
5900 /*
5901  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5902  * just stops using VMX.
5903  */
5904 static void free_nested(struct vcpu_vmx *vmx)
5905 {
5906         if (!vmx->nested.vmxon)
5907                 return;
5908         vmx->nested.vmxon = false;
5909         if (vmx->nested.current_vmptr != -1ull) {
5910                 nested_release_vmcs12(vmx);
5911                 vmx->nested.current_vmptr = -1ull;
5912                 vmx->nested.current_vmcs12 = NULL;
5913         }
5914         if (enable_shadow_vmcs)
5915                 free_vmcs(vmx->nested.current_shadow_vmcs);
5916         /* Unpin physical memory we referred to in current vmcs02 */
5917         if (vmx->nested.apic_access_page) {
5918                 nested_release_page(vmx->nested.apic_access_page);
5919                 vmx->nested.apic_access_page = 0;
5920         }
5921
5922         nested_free_all_saved_vmcss(vmx);
5923 }
5924
5925 /* Emulate the VMXOFF instruction */
5926 static int handle_vmoff(struct kvm_vcpu *vcpu)
5927 {
5928         if (!nested_vmx_check_permission(vcpu))
5929                 return 1;
5930         free_nested(to_vmx(vcpu));
5931         skip_emulated_instruction(vcpu);
5932         nested_vmx_succeed(vcpu);
5933         return 1;
5934 }
5935
5936 /*
5937  * Decode the memory-address operand of a vmx instruction, as recorded on an
5938  * exit caused by such an instruction (run by a guest hypervisor).
5939  * On success, returns 0. When the operand is invalid, returns 1 and throws
5940  * #UD or #GP.
5941  */
5942 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5943                                  unsigned long exit_qualification,
5944                                  u32 vmx_instruction_info, gva_t *ret)
5945 {
5946         /*
5947          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5948          * Execution", on an exit, vmx_instruction_info holds most of the
5949          * addressing components of the operand. Only the displacement part
5950          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5951          * For how an actual address is calculated from all these components,
5952          * refer to Vol. 1, "Operand Addressing".
5953          */
5954         int  scaling = vmx_instruction_info & 3;
5955         int  addr_size = (vmx_instruction_info >> 7) & 7;
5956         bool is_reg = vmx_instruction_info & (1u << 10);
5957         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5958         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5959         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5960         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5961         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5962
5963         if (is_reg) {
5964                 kvm_queue_exception(vcpu, UD_VECTOR);
5965                 return 1;
5966         }
5967
5968         /* Addr = segment_base + offset */
5969         /* offset = base + [index * scale] + displacement */
5970         *ret = vmx_get_segment_base(vcpu, seg_reg);
5971         if (base_is_valid)
5972                 *ret += kvm_register_read(vcpu, base_reg);
5973         if (index_is_valid)
5974                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5975         *ret += exit_qualification; /* holds the displacement */
5976
5977         if (addr_size == 1) /* 32 bit */
5978                 *ret &= 0xffffffff;
5979
5980         /*
5981          * TODO: throw #GP (and return 1) in various cases that the VM*
5982          * instructions require it - e.g., offset beyond segment limit,
5983          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5984          * address, and so on. Currently these are not checked.
5985          */
5986         return 0;
5987 }
5988
5989 /* Emulate the VMCLEAR instruction */
5990 static int handle_vmclear(struct kvm_vcpu *vcpu)
5991 {
5992         struct vcpu_vmx *vmx = to_vmx(vcpu);
5993         gva_t gva;
5994         gpa_t vmptr;
5995         struct vmcs12 *vmcs12;
5996         struct page *page;
5997         struct x86_exception e;
5998
5999         if (!nested_vmx_check_permission(vcpu))
6000                 return 1;
6001
6002         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6003                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6004                 return 1;
6005
6006         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6007                                 sizeof(vmptr), &e)) {
6008                 kvm_inject_page_fault(vcpu, &e);
6009                 return 1;
6010         }
6011
6012         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6013                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
6014                 skip_emulated_instruction(vcpu);
6015                 return 1;
6016         }
6017
6018         if (vmptr == vmx->nested.current_vmptr) {
6019                 nested_release_vmcs12(vmx);
6020                 vmx->nested.current_vmptr = -1ull;
6021                 vmx->nested.current_vmcs12 = NULL;
6022         }
6023
6024         page = nested_get_page(vcpu, vmptr);
6025         if (page == NULL) {
6026                 /*
6027                  * For accurate processor emulation, VMCLEAR beyond available
6028                  * physical memory should do nothing at all. However, it is
6029                  * possible that a nested vmx bug, not a guest hypervisor bug,
6030                  * resulted in this case, so let's shut down before doing any
6031                  * more damage:
6032                  */
6033                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6034                 return 1;
6035         }
6036         vmcs12 = kmap(page);
6037         vmcs12->launch_state = 0;
6038         kunmap(page);
6039         nested_release_page(page);
6040
6041         nested_free_vmcs02(vmx, vmptr);
6042
6043         skip_emulated_instruction(vcpu);
6044         nested_vmx_succeed(vcpu);
6045         return 1;
6046 }
6047
6048 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6049
6050 /* Emulate the VMLAUNCH instruction */
6051 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6052 {
6053         return nested_vmx_run(vcpu, true);
6054 }
6055
6056 /* Emulate the VMRESUME instruction */
6057 static int handle_vmresume(struct kvm_vcpu *vcpu)
6058 {
6059
6060         return nested_vmx_run(vcpu, false);
6061 }
6062
6063 enum vmcs_field_type {
6064         VMCS_FIELD_TYPE_U16 = 0,
6065         VMCS_FIELD_TYPE_U64 = 1,
6066         VMCS_FIELD_TYPE_U32 = 2,
6067         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6068 };
6069
6070 static inline int vmcs_field_type(unsigned long field)
6071 {
6072         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6073                 return VMCS_FIELD_TYPE_U32;
6074         return (field >> 13) & 0x3 ;
6075 }
6076
6077 static inline int vmcs_field_readonly(unsigned long field)
6078 {
6079         return (((field >> 10) & 0x3) == 1);
6080 }
6081
6082 /*
6083  * Read a vmcs12 field. Since these can have varying lengths and we return
6084  * one type, we chose the biggest type (u64) and zero-extend the return value
6085  * to that size. Note that the caller, handle_vmread, might need to use only
6086  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6087  * 64-bit fields are to be returned).
6088  */
6089 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6090                                         unsigned long field, u64 *ret)
6091 {
6092         short offset = vmcs_field_to_offset(field);
6093         char *p;
6094
6095         if (offset < 0)
6096                 return 0;
6097
6098         p = ((char *)(get_vmcs12(vcpu))) + offset;
6099
6100         switch (vmcs_field_type(field)) {
6101         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6102                 *ret = *((natural_width *)p);
6103                 return 1;
6104         case VMCS_FIELD_TYPE_U16:
6105                 *ret = *((u16 *)p);
6106                 return 1;
6107         case VMCS_FIELD_TYPE_U32:
6108                 *ret = *((u32 *)p);
6109                 return 1;
6110         case VMCS_FIELD_TYPE_U64:
6111                 *ret = *((u64 *)p);
6112                 return 1;
6113         default:
6114                 return 0; /* can never happen. */
6115         }
6116 }
6117
6118
6119 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6120                                     unsigned long field, u64 field_value){
6121         short offset = vmcs_field_to_offset(field);
6122         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6123         if (offset < 0)
6124                 return false;
6125
6126         switch (vmcs_field_type(field)) {
6127         case VMCS_FIELD_TYPE_U16:
6128                 *(u16 *)p = field_value;
6129                 return true;
6130         case VMCS_FIELD_TYPE_U32:
6131                 *(u32 *)p = field_value;
6132                 return true;
6133         case VMCS_FIELD_TYPE_U64:
6134                 *(u64 *)p = field_value;
6135                 return true;
6136         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6137                 *(natural_width *)p = field_value;
6138                 return true;
6139         default:
6140                 return false; /* can never happen. */
6141         }
6142
6143 }
6144
6145 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6146 {
6147         int i;
6148         unsigned long field;
6149         u64 field_value;
6150         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6151         const unsigned long *fields = shadow_read_write_fields;
6152         const int num_fields = max_shadow_read_write_fields;
6153
6154         vmcs_load(shadow_vmcs);
6155
6156         for (i = 0; i < num_fields; i++) {
6157                 field = fields[i];
6158                 switch (vmcs_field_type(field)) {
6159                 case VMCS_FIELD_TYPE_U16:
6160                         field_value = vmcs_read16(field);
6161                         break;
6162                 case VMCS_FIELD_TYPE_U32:
6163                         field_value = vmcs_read32(field);
6164                         break;
6165                 case VMCS_FIELD_TYPE_U64:
6166                         field_value = vmcs_read64(field);
6167                         break;
6168                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6169                         field_value = vmcs_readl(field);
6170                         break;
6171                 }
6172                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6173         }
6174
6175         vmcs_clear(shadow_vmcs);
6176         vmcs_load(vmx->loaded_vmcs->vmcs);
6177 }
6178
6179 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6180 {
6181         const unsigned long *fields[] = {
6182                 shadow_read_write_fields,
6183                 shadow_read_only_fields
6184         };
6185         const int max_fields[] = {
6186                 max_shadow_read_write_fields,
6187                 max_shadow_read_only_fields
6188         };
6189         int i, q;
6190         unsigned long field;
6191         u64 field_value = 0;
6192         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6193
6194         vmcs_load(shadow_vmcs);
6195
6196         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6197                 for (i = 0; i < max_fields[q]; i++) {
6198                         field = fields[q][i];
6199                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6200
6201                         switch (vmcs_field_type(field)) {
6202                         case VMCS_FIELD_TYPE_U16:
6203                                 vmcs_write16(field, (u16)field_value);
6204                                 break;
6205                         case VMCS_FIELD_TYPE_U32:
6206                                 vmcs_write32(field, (u32)field_value);
6207                                 break;
6208                         case VMCS_FIELD_TYPE_U64:
6209                                 vmcs_write64(field, (u64)field_value);
6210                                 break;
6211                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6212                                 vmcs_writel(field, (long)field_value);
6213                                 break;
6214                         }
6215                 }
6216         }
6217
6218         vmcs_clear(shadow_vmcs);
6219         vmcs_load(vmx->loaded_vmcs->vmcs);
6220 }
6221
6222 /*
6223  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6224  * used before) all generate the same failure when it is missing.
6225  */
6226 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6227 {
6228         struct vcpu_vmx *vmx = to_vmx(vcpu);
6229         if (vmx->nested.current_vmptr == -1ull) {
6230                 nested_vmx_failInvalid(vcpu);
6231                 skip_emulated_instruction(vcpu);
6232                 return 0;
6233         }
6234         return 1;
6235 }
6236
6237 static int handle_vmread(struct kvm_vcpu *vcpu)
6238 {
6239         unsigned long field;
6240         u64 field_value;
6241         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6242         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6243         gva_t gva = 0;
6244
6245         if (!nested_vmx_check_permission(vcpu) ||
6246             !nested_vmx_check_vmcs12(vcpu))
6247                 return 1;
6248
6249         /* Decode instruction info and find the field to read */
6250         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6251         /* Read the field, zero-extended to a u64 field_value */
6252         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6253                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6254                 skip_emulated_instruction(vcpu);
6255                 return 1;
6256         }
6257         /*
6258          * Now copy part of this value to register or memory, as requested.
6259          * Note that the number of bits actually copied is 32 or 64 depending
6260          * on the guest's mode (32 or 64 bit), not on the given field's length.
6261          */
6262         if (vmx_instruction_info & (1u << 10)) {
6263                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6264                         field_value);
6265         } else {
6266                 if (get_vmx_mem_address(vcpu, exit_qualification,
6267                                 vmx_instruction_info, &gva))
6268                         return 1;
6269                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6270                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6271                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6272         }
6273
6274         nested_vmx_succeed(vcpu);
6275         skip_emulated_instruction(vcpu);
6276         return 1;
6277 }
6278
6279
6280 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6281 {
6282         unsigned long field;
6283         gva_t gva;
6284         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6285         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6286         /* The value to write might be 32 or 64 bits, depending on L1's long
6287          * mode, and eventually we need to write that into a field of several
6288          * possible lengths. The code below first zero-extends the value to 64
6289          * bit (field_value), and then copies only the approriate number of
6290          * bits into the vmcs12 field.
6291          */
6292         u64 field_value = 0;
6293         struct x86_exception e;
6294
6295         if (!nested_vmx_check_permission(vcpu) ||
6296             !nested_vmx_check_vmcs12(vcpu))
6297                 return 1;
6298
6299         if (vmx_instruction_info & (1u << 10))
6300                 field_value = kvm_register_read(vcpu,
6301                         (((vmx_instruction_info) >> 3) & 0xf));
6302         else {
6303                 if (get_vmx_mem_address(vcpu, exit_qualification,
6304                                 vmx_instruction_info, &gva))
6305                         return 1;
6306                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6307                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6308                         kvm_inject_page_fault(vcpu, &e);
6309                         return 1;
6310                 }
6311         }
6312
6313
6314         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6315         if (vmcs_field_readonly(field)) {
6316                 nested_vmx_failValid(vcpu,
6317                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6318                 skip_emulated_instruction(vcpu);
6319                 return 1;
6320         }
6321
6322         if (!vmcs12_write_any(vcpu, field, field_value)) {
6323                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6324                 skip_emulated_instruction(vcpu);
6325                 return 1;
6326         }
6327
6328         nested_vmx_succeed(vcpu);
6329         skip_emulated_instruction(vcpu);
6330         return 1;
6331 }
6332
6333 /* Emulate the VMPTRLD instruction */
6334 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6335 {
6336         struct vcpu_vmx *vmx = to_vmx(vcpu);
6337         gva_t gva;
6338         gpa_t vmptr;
6339         struct x86_exception e;
6340         u32 exec_control;
6341
6342         if (!nested_vmx_check_permission(vcpu))
6343                 return 1;
6344
6345         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6346                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6347                 return 1;
6348
6349         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6350                                 sizeof(vmptr), &e)) {
6351                 kvm_inject_page_fault(vcpu, &e);
6352                 return 1;
6353         }
6354
6355         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6356                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6357                 skip_emulated_instruction(vcpu);
6358                 return 1;
6359         }
6360
6361         if (vmx->nested.current_vmptr != vmptr) {
6362                 struct vmcs12 *new_vmcs12;
6363                 struct page *page;
6364                 page = nested_get_page(vcpu, vmptr);
6365                 if (page == NULL) {
6366                         nested_vmx_failInvalid(vcpu);
6367                         skip_emulated_instruction(vcpu);
6368                         return 1;
6369                 }
6370                 new_vmcs12 = kmap(page);
6371                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6372                         kunmap(page);
6373                         nested_release_page_clean(page);
6374                         nested_vmx_failValid(vcpu,
6375                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6376                         skip_emulated_instruction(vcpu);
6377                         return 1;
6378                 }
6379                 if (vmx->nested.current_vmptr != -1ull)
6380                         nested_release_vmcs12(vmx);
6381
6382                 vmx->nested.current_vmptr = vmptr;
6383                 vmx->nested.current_vmcs12 = new_vmcs12;
6384                 vmx->nested.current_vmcs12_page = page;
6385                 if (enable_shadow_vmcs) {
6386                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6387                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6388                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6389                         vmcs_write64(VMCS_LINK_POINTER,
6390                                      __pa(vmx->nested.current_shadow_vmcs));
6391                         vmx->nested.sync_shadow_vmcs = true;
6392                 }
6393         }
6394
6395         nested_vmx_succeed(vcpu);
6396         skip_emulated_instruction(vcpu);
6397         return 1;
6398 }
6399
6400 /* Emulate the VMPTRST instruction */
6401 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6402 {
6403         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6404         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6405         gva_t vmcs_gva;
6406         struct x86_exception e;
6407
6408         if (!nested_vmx_check_permission(vcpu))
6409                 return 1;
6410
6411         if (get_vmx_mem_address(vcpu, exit_qualification,
6412                         vmx_instruction_info, &vmcs_gva))
6413                 return 1;
6414         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6415         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6416                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6417                                  sizeof(u64), &e)) {
6418                 kvm_inject_page_fault(vcpu, &e);
6419                 return 1;
6420         }
6421         nested_vmx_succeed(vcpu);
6422         skip_emulated_instruction(vcpu);
6423         return 1;
6424 }
6425
6426 /* Emulate the INVEPT instruction */
6427 static int handle_invept(struct kvm_vcpu *vcpu)
6428 {
6429         u32 vmx_instruction_info, types;
6430         unsigned long type;
6431         gva_t gva;
6432         struct x86_exception e;
6433         struct {
6434                 u64 eptp, gpa;
6435         } operand;
6436         u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6437
6438         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6439             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6440                 kvm_queue_exception(vcpu, UD_VECTOR);
6441                 return 1;
6442         }
6443
6444         if (!nested_vmx_check_permission(vcpu))
6445                 return 1;
6446
6447         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6448                 kvm_queue_exception(vcpu, UD_VECTOR);
6449                 return 1;
6450         }
6451
6452         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6453         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6454
6455         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6456
6457         if (!(types & (1UL << type))) {
6458                 nested_vmx_failValid(vcpu,
6459                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6460                 return 1;
6461         }
6462
6463         /* According to the Intel VMX instruction reference, the memory
6464          * operand is read even if it isn't needed (e.g., for type==global)
6465          */
6466         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6467                         vmx_instruction_info, &gva))
6468                 return 1;
6469         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6470                                 sizeof(operand), &e)) {
6471                 kvm_inject_page_fault(vcpu, &e);
6472                 return 1;
6473         }
6474
6475         switch (type) {
6476         case VMX_EPT_EXTENT_CONTEXT:
6477                 if ((operand.eptp & eptp_mask) !=
6478                                 (nested_ept_get_cr3(vcpu) & eptp_mask))
6479                         break;
6480         case VMX_EPT_EXTENT_GLOBAL:
6481                 kvm_mmu_sync_roots(vcpu);
6482                 kvm_mmu_flush_tlb(vcpu);
6483                 nested_vmx_succeed(vcpu);
6484                 break;
6485         default:
6486                 BUG_ON(1);
6487                 break;
6488         }
6489
6490         skip_emulated_instruction(vcpu);
6491         return 1;
6492 }
6493
6494 /*
6495  * The exit handlers return 1 if the exit was handled fully and guest execution
6496  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6497  * to be done to userspace and return 0.
6498  */
6499 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6500         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6501         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6502         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6503         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6504         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6505         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6506         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6507         [EXIT_REASON_CPUID]                   = handle_cpuid,
6508         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6509         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6510         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6511         [EXIT_REASON_HLT]                     = handle_halt,
6512         [EXIT_REASON_INVD]                    = handle_invd,
6513         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6514         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6515         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6516         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6517         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6518         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6519         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6520         [EXIT_REASON_VMREAD]                  = handle_vmread,
6521         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6522         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6523         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6524         [EXIT_REASON_VMON]                    = handle_vmon,
6525         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6526         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6527         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6528         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6529         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6530         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6531         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6532         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6533         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6534         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6535         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6536         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6537         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6538         [EXIT_REASON_INVEPT]                  = handle_invept,
6539 };
6540
6541 static const int kvm_vmx_max_exit_handlers =
6542         ARRAY_SIZE(kvm_vmx_exit_handlers);
6543
6544 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6545                                        struct vmcs12 *vmcs12)
6546 {
6547         unsigned long exit_qualification;
6548         gpa_t bitmap, last_bitmap;
6549         unsigned int port;
6550         int size;
6551         u8 b;
6552
6553         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6554                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6555
6556         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6557
6558         port = exit_qualification >> 16;
6559         size = (exit_qualification & 7) + 1;
6560
6561         last_bitmap = (gpa_t)-1;
6562         b = -1;
6563
6564         while (size > 0) {
6565                 if (port < 0x8000)
6566                         bitmap = vmcs12->io_bitmap_a;
6567                 else if (port < 0x10000)
6568                         bitmap = vmcs12->io_bitmap_b;
6569                 else
6570                         return 1;
6571                 bitmap += (port & 0x7fff) / 8;
6572
6573                 if (last_bitmap != bitmap)
6574                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6575                                 return 1;
6576                 if (b & (1 << (port & 7)))
6577                         return 1;
6578
6579                 port++;
6580                 size--;
6581                 last_bitmap = bitmap;
6582         }
6583
6584         return 0;
6585 }
6586
6587 /*
6588  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6589  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6590  * disinterest in the current event (read or write a specific MSR) by using an
6591  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6592  */
6593 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6594         struct vmcs12 *vmcs12, u32 exit_reason)
6595 {
6596         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6597         gpa_t bitmap;
6598
6599         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6600                 return 1;
6601
6602         /*
6603          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6604          * for the four combinations of read/write and low/high MSR numbers.
6605          * First we need to figure out which of the four to use:
6606          */
6607         bitmap = vmcs12->msr_bitmap;
6608         if (exit_reason == EXIT_REASON_MSR_WRITE)
6609                 bitmap += 2048;
6610         if (msr_index >= 0xc0000000) {
6611                 msr_index -= 0xc0000000;
6612                 bitmap += 1024;
6613         }
6614
6615         /* Then read the msr_index'th bit from this bitmap: */
6616         if (msr_index < 1024*8) {
6617                 unsigned char b;
6618                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6619                         return 1;
6620                 return 1 & (b >> (msr_index & 7));
6621         } else
6622                 return 1; /* let L1 handle the wrong parameter */
6623 }
6624
6625 /*
6626  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6627  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6628  * intercept (via guest_host_mask etc.) the current event.
6629  */
6630 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6631         struct vmcs12 *vmcs12)
6632 {
6633         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6634         int cr = exit_qualification & 15;
6635         int reg = (exit_qualification >> 8) & 15;
6636         unsigned long val = kvm_register_read(vcpu, reg);
6637
6638         switch ((exit_qualification >> 4) & 3) {
6639         case 0: /* mov to cr */
6640                 switch (cr) {
6641                 case 0:
6642                         if (vmcs12->cr0_guest_host_mask &
6643                             (val ^ vmcs12->cr0_read_shadow))
6644                                 return 1;
6645                         break;
6646                 case 3:
6647                         if ((vmcs12->cr3_target_count >= 1 &&
6648                                         vmcs12->cr3_target_value0 == val) ||
6649                                 (vmcs12->cr3_target_count >= 2 &&
6650                                         vmcs12->cr3_target_value1 == val) ||
6651                                 (vmcs12->cr3_target_count >= 3 &&
6652                                         vmcs12->cr3_target_value2 == val) ||
6653                                 (vmcs12->cr3_target_count >= 4 &&
6654                                         vmcs12->cr3_target_value3 == val))
6655                                 return 0;
6656                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6657                                 return 1;
6658                         break;
6659                 case 4:
6660                         if (vmcs12->cr4_guest_host_mask &
6661                             (vmcs12->cr4_read_shadow ^ val))
6662                                 return 1;
6663                         break;
6664                 case 8:
6665                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6666                                 return 1;
6667                         break;
6668                 }
6669                 break;
6670         case 2: /* clts */
6671                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6672                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6673                         return 1;
6674                 break;
6675         case 1: /* mov from cr */
6676                 switch (cr) {
6677                 case 3:
6678                         if (vmcs12->cpu_based_vm_exec_control &
6679                             CPU_BASED_CR3_STORE_EXITING)
6680                                 return 1;
6681                         break;
6682                 case 8:
6683                         if (vmcs12->cpu_based_vm_exec_control &
6684                             CPU_BASED_CR8_STORE_EXITING)
6685                                 return 1;
6686                         break;
6687                 }
6688                 break;
6689         case 3: /* lmsw */
6690                 /*
6691                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6692                  * cr0. Other attempted changes are ignored, with no exit.
6693                  */
6694                 if (vmcs12->cr0_guest_host_mask & 0xe &
6695                     (val ^ vmcs12->cr0_read_shadow))
6696                         return 1;
6697                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6698                     !(vmcs12->cr0_read_shadow & 0x1) &&
6699                     (val & 0x1))
6700                         return 1;
6701                 break;
6702         }
6703         return 0;
6704 }
6705
6706 /*
6707  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6708  * should handle it ourselves in L0 (and then continue L2). Only call this
6709  * when in is_guest_mode (L2).
6710  */
6711 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6712 {
6713         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6714         struct vcpu_vmx *vmx = to_vmx(vcpu);
6715         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6716         u32 exit_reason = vmx->exit_reason;
6717
6718         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6719                                 vmcs_readl(EXIT_QUALIFICATION),
6720                                 vmx->idt_vectoring_info,
6721                                 intr_info,
6722                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6723                                 KVM_ISA_VMX);
6724
6725         if (vmx->nested.nested_run_pending)
6726                 return 0;
6727
6728         if (unlikely(vmx->fail)) {
6729                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6730                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6731                 return 1;
6732         }
6733
6734         switch (exit_reason) {
6735         case EXIT_REASON_EXCEPTION_NMI:
6736                 if (!is_exception(intr_info))
6737                         return 0;
6738                 else if (is_page_fault(intr_info))
6739                         return enable_ept;
6740                 else if (is_no_device(intr_info) &&
6741                          !(vmcs12->guest_cr0 & X86_CR0_TS))
6742                         return 0;
6743                 return vmcs12->exception_bitmap &
6744                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6745         case EXIT_REASON_EXTERNAL_INTERRUPT:
6746                 return 0;
6747         case EXIT_REASON_TRIPLE_FAULT:
6748                 return 1;
6749         case EXIT_REASON_PENDING_INTERRUPT:
6750                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6751         case EXIT_REASON_NMI_WINDOW:
6752                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6753         case EXIT_REASON_TASK_SWITCH:
6754                 return 1;
6755         case EXIT_REASON_CPUID:
6756                 return 1;
6757         case EXIT_REASON_HLT:
6758                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6759         case EXIT_REASON_INVD:
6760                 return 1;
6761         case EXIT_REASON_INVLPG:
6762                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6763         case EXIT_REASON_RDPMC:
6764                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6765         case EXIT_REASON_RDTSC:
6766                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6767         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6768         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6769         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6770         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6771         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6772         case EXIT_REASON_INVEPT:
6773                 /*
6774                  * VMX instructions trap unconditionally. This allows L1 to
6775                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6776                  */
6777                 return 1;
6778         case EXIT_REASON_CR_ACCESS:
6779                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6780         case EXIT_REASON_DR_ACCESS:
6781                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6782         case EXIT_REASON_IO_INSTRUCTION:
6783                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6784         case EXIT_REASON_MSR_READ:
6785         case EXIT_REASON_MSR_WRITE:
6786                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6787         case EXIT_REASON_INVALID_STATE:
6788                 return 1;
6789         case EXIT_REASON_MWAIT_INSTRUCTION:
6790                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6791         case EXIT_REASON_MONITOR_INSTRUCTION:
6792                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6793         case EXIT_REASON_PAUSE_INSTRUCTION:
6794                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6795                         nested_cpu_has2(vmcs12,
6796                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6797         case EXIT_REASON_MCE_DURING_VMENTRY:
6798                 return 0;
6799         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6800                 return 1;
6801         case EXIT_REASON_APIC_ACCESS:
6802                 return nested_cpu_has2(vmcs12,
6803                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6804         case EXIT_REASON_EPT_VIOLATION:
6805                 /*
6806                  * L0 always deals with the EPT violation. If nested EPT is
6807                  * used, and the nested mmu code discovers that the address is
6808                  * missing in the guest EPT table (EPT12), the EPT violation
6809                  * will be injected with nested_ept_inject_page_fault()
6810                  */
6811                 return 0;
6812         case EXIT_REASON_EPT_MISCONFIG:
6813                 /*
6814                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6815                  * table (shadow on EPT) or a merged EPT table that L0 built
6816                  * (EPT on EPT). So any problems with the structure of the
6817                  * table is L0's fault.
6818                  */
6819                 return 0;
6820         case EXIT_REASON_WBINVD:
6821                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6822         case EXIT_REASON_XSETBV:
6823                 return 1;
6824         default:
6825                 return 1;
6826         }
6827 }
6828
6829 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6830 {
6831         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6832         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6833 }
6834
6835 /*
6836  * The guest has exited.  See if we can fix it or if we need userspace
6837  * assistance.
6838  */
6839 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6840 {
6841         struct vcpu_vmx *vmx = to_vmx(vcpu);
6842         u32 exit_reason = vmx->exit_reason;
6843         u32 vectoring_info = vmx->idt_vectoring_info;
6844
6845         /* If guest state is invalid, start emulating */
6846         if (vmx->emulation_required)
6847                 return handle_invalid_guest_state(vcpu);
6848
6849         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6850                 nested_vmx_vmexit(vcpu, exit_reason,
6851                                   vmcs_read32(VM_EXIT_INTR_INFO),
6852                                   vmcs_readl(EXIT_QUALIFICATION));
6853                 return 1;
6854         }
6855
6856         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6857                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6858                 vcpu->run->fail_entry.hardware_entry_failure_reason
6859                         = exit_reason;
6860                 return 0;
6861         }
6862
6863         if (unlikely(vmx->fail)) {
6864                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6865                 vcpu->run->fail_entry.hardware_entry_failure_reason
6866                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6867                 return 0;
6868         }
6869
6870         /*
6871          * Note:
6872          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6873          * delivery event since it indicates guest is accessing MMIO.
6874          * The vm-exit can be triggered again after return to guest that
6875          * will cause infinite loop.
6876          */
6877         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6878                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6879                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6880                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6881                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6882                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6883                 vcpu->run->internal.ndata = 2;
6884                 vcpu->run->internal.data[0] = vectoring_info;
6885                 vcpu->run->internal.data[1] = exit_reason;
6886                 return 0;
6887         }
6888
6889         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6890             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6891                                         get_vmcs12(vcpu))))) {
6892                 if (vmx_interrupt_allowed(vcpu)) {
6893                         vmx->soft_vnmi_blocked = 0;
6894                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6895                            vcpu->arch.nmi_pending) {
6896                         /*
6897                          * This CPU don't support us in finding the end of an
6898                          * NMI-blocked window if the guest runs with IRQs
6899                          * disabled. So we pull the trigger after 1 s of
6900                          * futile waiting, but inform the user about this.
6901                          */
6902                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6903                                "state on VCPU %d after 1 s timeout\n",
6904                                __func__, vcpu->vcpu_id);
6905                         vmx->soft_vnmi_blocked = 0;
6906                 }
6907         }
6908
6909         if (exit_reason < kvm_vmx_max_exit_handlers
6910             && kvm_vmx_exit_handlers[exit_reason])
6911                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6912         else {
6913                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6914                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6915         }
6916         return 0;
6917 }
6918
6919 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6920 {
6921         if (irr == -1 || tpr < irr) {
6922                 vmcs_write32(TPR_THRESHOLD, 0);
6923                 return;
6924         }
6925
6926         vmcs_write32(TPR_THRESHOLD, irr);
6927 }
6928
6929 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6930 {
6931         u32 sec_exec_control;
6932
6933         /*
6934          * There is not point to enable virtualize x2apic without enable
6935          * apicv
6936          */
6937         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6938                                 !vmx_vm_has_apicv(vcpu->kvm))
6939                 return;
6940
6941         if (!vm_need_tpr_shadow(vcpu->kvm))
6942                 return;
6943
6944         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6945
6946         if (set) {
6947                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6948                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6949         } else {
6950                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6951                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6952         }
6953         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6954
6955         vmx_set_msr_bitmap(vcpu);
6956 }
6957
6958 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6959 {
6960         u16 status;
6961         u8 old;
6962
6963         if (!vmx_vm_has_apicv(kvm))
6964                 return;
6965
6966         if (isr == -1)
6967                 isr = 0;
6968
6969         status = vmcs_read16(GUEST_INTR_STATUS);
6970         old = status >> 8;
6971         if (isr != old) {
6972                 status &= 0xff;
6973                 status |= isr << 8;
6974                 vmcs_write16(GUEST_INTR_STATUS, status);
6975         }
6976 }
6977
6978 static void vmx_set_rvi(int vector)
6979 {
6980         u16 status;
6981         u8 old;
6982
6983         status = vmcs_read16(GUEST_INTR_STATUS);
6984         old = (u8)status & 0xff;
6985         if ((u8)vector != old) {
6986                 status &= ~0xff;
6987                 status |= (u8)vector;
6988                 vmcs_write16(GUEST_INTR_STATUS, status);
6989         }
6990 }
6991
6992 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6993 {
6994         if (max_irr == -1)
6995                 return;
6996
6997         vmx_set_rvi(max_irr);
6998 }
6999
7000 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7001 {
7002         if (!vmx_vm_has_apicv(vcpu->kvm))
7003                 return;
7004
7005         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7006         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7007         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7008         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7009 }
7010
7011 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7012 {
7013         u32 exit_intr_info;
7014
7015         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7016               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7017                 return;
7018
7019         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7020         exit_intr_info = vmx->exit_intr_info;
7021
7022         /* Handle machine checks before interrupts are enabled */
7023         if (is_machine_check(exit_intr_info))
7024                 kvm_machine_check();
7025
7026         /* We need to handle NMIs before interrupts are enabled */
7027         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7028             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7029                 kvm_before_handle_nmi(&vmx->vcpu);
7030                 asm("int $2");
7031                 kvm_after_handle_nmi(&vmx->vcpu);
7032         }
7033 }
7034
7035 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7036 {
7037         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7038
7039         /*
7040          * If external interrupt exists, IF bit is set in rflags/eflags on the
7041          * interrupt stack frame, and interrupt will be enabled on a return
7042          * from interrupt handler.
7043          */
7044         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7045                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7046                 unsigned int vector;
7047                 unsigned long entry;
7048                 gate_desc *desc;
7049                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7050 #ifdef CONFIG_X86_64
7051                 unsigned long tmp;
7052 #endif
7053
7054                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7055                 desc = (gate_desc *)vmx->host_idt_base + vector;
7056                 entry = gate_offset(*desc);
7057                 asm volatile(
7058 #ifdef CONFIG_X86_64
7059                         "mov %%" _ASM_SP ", %[sp]\n\t"
7060                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7061                         "push $%c[ss]\n\t"
7062                         "push %[sp]\n\t"
7063 #endif
7064                         "pushf\n\t"
7065                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7066                         __ASM_SIZE(push) " $%c[cs]\n\t"
7067                         "call *%[entry]\n\t"
7068                         :
7069 #ifdef CONFIG_X86_64
7070                         [sp]"=&r"(tmp)
7071 #endif
7072                         :
7073                         [entry]"r"(entry),
7074                         [ss]"i"(__KERNEL_DS),
7075                         [cs]"i"(__KERNEL_CS)
7076                         );
7077         } else
7078                 local_irq_enable();
7079 }
7080
7081 static bool vmx_mpx_supported(void)
7082 {
7083         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7084                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7085 }
7086
7087 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7088 {
7089         u32 exit_intr_info;
7090         bool unblock_nmi;
7091         u8 vector;
7092         bool idtv_info_valid;
7093
7094         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7095
7096         if (cpu_has_virtual_nmis()) {
7097                 if (vmx->nmi_known_unmasked)
7098                         return;
7099                 /*
7100                  * Can't use vmx->exit_intr_info since we're not sure what
7101                  * the exit reason is.
7102                  */
7103                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7104                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7105                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7106                 /*
7107                  * SDM 3: 27.7.1.2 (September 2008)
7108                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7109                  * a guest IRET fault.
7110                  * SDM 3: 23.2.2 (September 2008)
7111                  * Bit 12 is undefined in any of the following cases:
7112                  *  If the VM exit sets the valid bit in the IDT-vectoring
7113                  *   information field.
7114                  *  If the VM exit is due to a double fault.
7115                  */
7116                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7117                     vector != DF_VECTOR && !idtv_info_valid)
7118                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7119                                       GUEST_INTR_STATE_NMI);
7120                 else
7121                         vmx->nmi_known_unmasked =
7122                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7123                                   & GUEST_INTR_STATE_NMI);
7124         } else if (unlikely(vmx->soft_vnmi_blocked))
7125                 vmx->vnmi_blocked_time +=
7126                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7127 }
7128
7129 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7130                                       u32 idt_vectoring_info,
7131                                       int instr_len_field,
7132                                       int error_code_field)
7133 {
7134         u8 vector;
7135         int type;
7136         bool idtv_info_valid;
7137
7138         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7139
7140         vcpu->arch.nmi_injected = false;
7141         kvm_clear_exception_queue(vcpu);
7142         kvm_clear_interrupt_queue(vcpu);
7143
7144         if (!idtv_info_valid)
7145                 return;
7146
7147         kvm_make_request(KVM_REQ_EVENT, vcpu);
7148
7149         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7150         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7151
7152         switch (type) {
7153         case INTR_TYPE_NMI_INTR:
7154                 vcpu->arch.nmi_injected = true;
7155                 /*
7156                  * SDM 3: 27.7.1.2 (September 2008)
7157                  * Clear bit "block by NMI" before VM entry if a NMI
7158                  * delivery faulted.
7159                  */
7160                 vmx_set_nmi_mask(vcpu, false);
7161                 break;
7162         case INTR_TYPE_SOFT_EXCEPTION:
7163                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7164                 /* fall through */
7165         case INTR_TYPE_HARD_EXCEPTION:
7166                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7167                         u32 err = vmcs_read32(error_code_field);
7168                         kvm_requeue_exception_e(vcpu, vector, err);
7169                 } else
7170                         kvm_requeue_exception(vcpu, vector);
7171                 break;
7172         case INTR_TYPE_SOFT_INTR:
7173                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7174                 /* fall through */
7175         case INTR_TYPE_EXT_INTR:
7176                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7177                 break;
7178         default:
7179                 break;
7180         }
7181 }
7182
7183 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7184 {
7185         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7186                                   VM_EXIT_INSTRUCTION_LEN,
7187                                   IDT_VECTORING_ERROR_CODE);
7188 }
7189
7190 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7191 {
7192         __vmx_complete_interrupts(vcpu,
7193                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7194                                   VM_ENTRY_INSTRUCTION_LEN,
7195                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7196
7197         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7198 }
7199
7200 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7201 {
7202         int i, nr_msrs;
7203         struct perf_guest_switch_msr *msrs;
7204
7205         msrs = perf_guest_get_msrs(&nr_msrs);
7206
7207         if (!msrs)
7208                 return;
7209
7210         for (i = 0; i < nr_msrs; i++)
7211                 if (msrs[i].host == msrs[i].guest)
7212                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7213                 else
7214                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7215                                         msrs[i].host);
7216 }
7217
7218 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7219 {
7220         struct vcpu_vmx *vmx = to_vmx(vcpu);
7221         unsigned long debugctlmsr;
7222
7223         /* Record the guest's net vcpu time for enforced NMI injections. */
7224         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7225                 vmx->entry_time = ktime_get();
7226
7227         /* Don't enter VMX if guest state is invalid, let the exit handler
7228            start emulation until we arrive back to a valid state */
7229         if (vmx->emulation_required)
7230                 return;
7231
7232         if (vmx->nested.sync_shadow_vmcs) {
7233                 copy_vmcs12_to_shadow(vmx);
7234                 vmx->nested.sync_shadow_vmcs = false;
7235         }
7236
7237         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7238                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7239         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7240                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7241
7242         /* When single-stepping over STI and MOV SS, we must clear the
7243          * corresponding interruptibility bits in the guest state. Otherwise
7244          * vmentry fails as it then expects bit 14 (BS) in pending debug
7245          * exceptions being set, but that's not correct for the guest debugging
7246          * case. */
7247         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7248                 vmx_set_interrupt_shadow(vcpu, 0);
7249
7250         atomic_switch_perf_msrs(vmx);
7251         debugctlmsr = get_debugctlmsr();
7252
7253         vmx->__launched = vmx->loaded_vmcs->launched;
7254         asm(
7255                 /* Store host registers */
7256                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7257                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7258                 "push %%" _ASM_CX " \n\t"
7259                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7260                 "je 1f \n\t"
7261                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7262                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7263                 "1: \n\t"
7264                 /* Reload cr2 if changed */
7265                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7266                 "mov %%cr2, %%" _ASM_DX " \n\t"
7267                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7268                 "je 2f \n\t"
7269                 "mov %%" _ASM_AX", %%cr2 \n\t"
7270                 "2: \n\t"
7271                 /* Check if vmlaunch of vmresume is needed */
7272                 "cmpl $0, %c[launched](%0) \n\t"
7273                 /* Load guest registers.  Don't clobber flags. */
7274                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7275                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7276                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7277                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7278                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7279                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7280 #ifdef CONFIG_X86_64
7281                 "mov %c[r8](%0),  %%r8  \n\t"
7282                 "mov %c[r9](%0),  %%r9  \n\t"
7283                 "mov %c[r10](%0), %%r10 \n\t"
7284                 "mov %c[r11](%0), %%r11 \n\t"
7285                 "mov %c[r12](%0), %%r12 \n\t"
7286                 "mov %c[r13](%0), %%r13 \n\t"
7287                 "mov %c[r14](%0), %%r14 \n\t"
7288                 "mov %c[r15](%0), %%r15 \n\t"
7289 #endif
7290                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7291
7292                 /* Enter guest mode */
7293                 "jne 1f \n\t"
7294                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7295                 "jmp 2f \n\t"
7296                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7297                 "2: "
7298                 /* Save guest registers, load host registers, keep flags */
7299                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7300                 "pop %0 \n\t"
7301                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7302                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7303                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7304                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7305                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7306                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7307                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7308 #ifdef CONFIG_X86_64
7309                 "mov %%r8,  %c[r8](%0) \n\t"
7310                 "mov %%r9,  %c[r9](%0) \n\t"
7311                 "mov %%r10, %c[r10](%0) \n\t"
7312                 "mov %%r11, %c[r11](%0) \n\t"
7313                 "mov %%r12, %c[r12](%0) \n\t"
7314                 "mov %%r13, %c[r13](%0) \n\t"
7315                 "mov %%r14, %c[r14](%0) \n\t"
7316                 "mov %%r15, %c[r15](%0) \n\t"
7317 #endif
7318                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7319                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7320
7321                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7322                 "setbe %c[fail](%0) \n\t"
7323                 ".pushsection .rodata \n\t"
7324                 ".global vmx_return \n\t"
7325                 "vmx_return: " _ASM_PTR " 2b \n\t"
7326                 ".popsection"
7327               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7328                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7329                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7330                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7331                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7332                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7333                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7334                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7335                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7336                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7337                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7338 #ifdef CONFIG_X86_64
7339                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7340                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7341                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7342                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7343                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7344                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7345                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7346                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7347 #endif
7348                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7349                 [wordsize]"i"(sizeof(ulong))
7350               : "cc", "memory"
7351 #ifdef CONFIG_X86_64
7352                 , "rax", "rbx", "rdi", "rsi"
7353                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7354 #else
7355                 , "eax", "ebx", "edi", "esi"
7356 #endif
7357               );
7358
7359         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7360         if (debugctlmsr)
7361                 update_debugctlmsr(debugctlmsr);
7362
7363 #ifndef CONFIG_X86_64
7364         /*
7365          * The sysexit path does not restore ds/es, so we must set them to
7366          * a reasonable value ourselves.
7367          *
7368          * We can't defer this to vmx_load_host_state() since that function
7369          * may be executed in interrupt context, which saves and restore segments
7370          * around it, nullifying its effect.
7371          */
7372         loadsegment(ds, __USER_DS);
7373         loadsegment(es, __USER_DS);
7374 #endif
7375
7376         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7377                                   | (1 << VCPU_EXREG_RFLAGS)
7378                                   | (1 << VCPU_EXREG_CPL)
7379                                   | (1 << VCPU_EXREG_PDPTR)
7380                                   | (1 << VCPU_EXREG_SEGMENTS)
7381                                   | (1 << VCPU_EXREG_CR3));
7382         vcpu->arch.regs_dirty = 0;
7383
7384         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7385
7386         vmx->loaded_vmcs->launched = 1;
7387
7388         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7389         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7390
7391         /*
7392          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7393          * we did not inject a still-pending event to L1 now because of
7394          * nested_run_pending, we need to re-enable this bit.
7395          */
7396         if (vmx->nested.nested_run_pending)
7397                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7398
7399         vmx->nested.nested_run_pending = 0;
7400
7401         vmx_complete_atomic_exit(vmx);
7402         vmx_recover_nmi_blocking(vmx);
7403         vmx_complete_interrupts(vmx);
7404 }
7405
7406 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7407 {
7408         struct vcpu_vmx *vmx = to_vmx(vcpu);
7409
7410         free_vpid(vmx);
7411         free_loaded_vmcs(vmx->loaded_vmcs);
7412         free_nested(vmx);
7413         kfree(vmx->guest_msrs);
7414         kvm_vcpu_uninit(vcpu);
7415         kmem_cache_free(kvm_vcpu_cache, vmx);
7416 }
7417
7418 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7419 {
7420         int err;
7421         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7422         int cpu;
7423
7424         if (!vmx)
7425                 return ERR_PTR(-ENOMEM);
7426
7427         allocate_vpid(vmx);
7428
7429         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7430         if (err)
7431                 goto free_vcpu;
7432
7433         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7434         err = -ENOMEM;
7435         if (!vmx->guest_msrs) {
7436                 goto uninit_vcpu;
7437         }
7438
7439         vmx->loaded_vmcs = &vmx->vmcs01;
7440         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7441         if (!vmx->loaded_vmcs->vmcs)
7442                 goto free_msrs;
7443         if (!vmm_exclusive)
7444                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7445         loaded_vmcs_init(vmx->loaded_vmcs);
7446         if (!vmm_exclusive)
7447                 kvm_cpu_vmxoff();
7448
7449         cpu = get_cpu();
7450         vmx_vcpu_load(&vmx->vcpu, cpu);
7451         vmx->vcpu.cpu = cpu;
7452         err = vmx_vcpu_setup(vmx);
7453         vmx_vcpu_put(&vmx->vcpu);
7454         put_cpu();
7455         if (err)
7456                 goto free_vmcs;
7457         if (vm_need_virtualize_apic_accesses(kvm)) {
7458                 err = alloc_apic_access_page(kvm);
7459                 if (err)
7460                         goto free_vmcs;
7461         }
7462
7463         if (enable_ept) {
7464                 if (!kvm->arch.ept_identity_map_addr)
7465                         kvm->arch.ept_identity_map_addr =
7466                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7467                 err = -ENOMEM;
7468                 if (alloc_identity_pagetable(kvm) != 0)
7469                         goto free_vmcs;
7470                 if (!init_rmode_identity_map(kvm))
7471                         goto free_vmcs;
7472         }
7473
7474         vmx->nested.current_vmptr = -1ull;
7475         vmx->nested.current_vmcs12 = NULL;
7476
7477         return &vmx->vcpu;
7478
7479 free_vmcs:
7480         free_loaded_vmcs(vmx->loaded_vmcs);
7481 free_msrs:
7482         kfree(vmx->guest_msrs);
7483 uninit_vcpu:
7484         kvm_vcpu_uninit(&vmx->vcpu);
7485 free_vcpu:
7486         free_vpid(vmx);
7487         kmem_cache_free(kvm_vcpu_cache, vmx);
7488         return ERR_PTR(err);
7489 }
7490
7491 static void __init vmx_check_processor_compat(void *rtn)
7492 {
7493         struct vmcs_config vmcs_conf;
7494
7495         *(int *)rtn = 0;
7496         if (setup_vmcs_config(&vmcs_conf) < 0)
7497                 *(int *)rtn = -EIO;
7498         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7499                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7500                                 smp_processor_id());
7501                 *(int *)rtn = -EIO;
7502         }
7503 }
7504
7505 static int get_ept_level(void)
7506 {
7507         return VMX_EPT_DEFAULT_GAW + 1;
7508 }
7509
7510 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7511 {
7512         u64 ret;
7513
7514         /* For VT-d and EPT combination
7515          * 1. MMIO: always map as UC
7516          * 2. EPT with VT-d:
7517          *   a. VT-d without snooping control feature: can't guarantee the
7518          *      result, try to trust guest.
7519          *   b. VT-d with snooping control feature: snooping control feature of
7520          *      VT-d engine can guarantee the cache correctness. Just set it
7521          *      to WB to keep consistent with host. So the same as item 3.
7522          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7523          *    consistent with host MTRR
7524          */
7525         if (is_mmio)
7526                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7527         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
7528                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7529                       VMX_EPT_MT_EPTE_SHIFT;
7530         else
7531                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7532                         | VMX_EPT_IPAT_BIT;
7533
7534         return ret;
7535 }
7536
7537 static int vmx_get_lpage_level(void)
7538 {
7539         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7540                 return PT_DIRECTORY_LEVEL;
7541         else
7542                 /* For shadow and EPT supported 1GB page */
7543                 return PT_PDPE_LEVEL;
7544 }
7545
7546 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7547 {
7548         struct kvm_cpuid_entry2 *best;
7549         struct vcpu_vmx *vmx = to_vmx(vcpu);
7550         u32 exec_control;
7551
7552         vmx->rdtscp_enabled = false;
7553         if (vmx_rdtscp_supported()) {
7554                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7555                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7556                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7557                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7558                                 vmx->rdtscp_enabled = true;
7559                         else {
7560                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7561                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7562                                                 exec_control);
7563                         }
7564                 }
7565         }
7566
7567         /* Exposing INVPCID only when PCID is exposed */
7568         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7569         if (vmx_invpcid_supported() &&
7570             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7571             guest_cpuid_has_pcid(vcpu)) {
7572                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7573                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7574                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7575                              exec_control);
7576         } else {
7577                 if (cpu_has_secondary_exec_ctrls()) {
7578                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7579                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7580                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7581                                      exec_control);
7582                 }
7583                 if (best)
7584                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7585         }
7586 }
7587
7588 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7589 {
7590         if (func == 1 && nested)
7591                 entry->ecx |= bit(X86_FEATURE_VMX);
7592 }
7593
7594 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7595                 struct x86_exception *fault)
7596 {
7597         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7598         u32 exit_reason;
7599
7600         if (fault->error_code & PFERR_RSVD_MASK)
7601                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
7602         else
7603                 exit_reason = EXIT_REASON_EPT_VIOLATION;
7604         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
7605         vmcs12->guest_physical_address = fault->address;
7606 }
7607
7608 /* Callbacks for nested_ept_init_mmu_context: */
7609
7610 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7611 {
7612         /* return the page table to be shadowed - in our case, EPT12 */
7613         return get_vmcs12(vcpu)->ept_pointer;
7614 }
7615
7616 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7617 {
7618         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7619                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7620
7621         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7622         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7623         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7624
7625         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7626 }
7627
7628 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7629 {
7630         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7631 }
7632
7633 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7634                 struct x86_exception *fault)
7635 {
7636         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7637
7638         WARN_ON(!is_guest_mode(vcpu));
7639
7640         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7641         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7642                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7643                                   vmcs_read32(VM_EXIT_INTR_INFO),
7644                                   vmcs_readl(EXIT_QUALIFICATION));
7645         else
7646                 kvm_inject_page_fault(vcpu, fault);
7647 }
7648
7649 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7650 {
7651         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7652         struct vcpu_vmx *vmx = to_vmx(vcpu);
7653
7654         if (vcpu->arch.virtual_tsc_khz == 0)
7655                 return;
7656
7657         /* Make sure short timeouts reliably trigger an immediate vmexit.
7658          * hrtimer_start does not guarantee this. */
7659         if (preemption_timeout <= 1) {
7660                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7661                 return;
7662         }
7663
7664         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7665         preemption_timeout *= 1000000;
7666         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7667         hrtimer_start(&vmx->nested.preemption_timer,
7668                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7669 }
7670
7671 /*
7672  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7673  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7674  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7675  * guest in a way that will both be appropriate to L1's requests, and our
7676  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7677  * function also has additional necessary side-effects, like setting various
7678  * vcpu->arch fields.
7679  */
7680 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7681 {
7682         struct vcpu_vmx *vmx = to_vmx(vcpu);
7683         u32 exec_control;
7684
7685         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7686         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7687         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7688         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7689         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7690         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7691         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7692         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7693         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7694         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7695         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7696         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7697         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7698         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7699         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7700         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7701         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7702         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7703         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7704         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7705         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7706         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7707         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7708         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7709         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7710         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7711         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7712         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7713         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7714         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7715         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7716         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7717         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7718         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7719         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7720         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7721
7722         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7723         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7724                 vmcs12->vm_entry_intr_info_field);
7725         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7726                 vmcs12->vm_entry_exception_error_code);
7727         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7728                 vmcs12->vm_entry_instruction_len);
7729         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7730                 vmcs12->guest_interruptibility_info);
7731         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7732         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7733         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7734         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7735                 vmcs12->guest_pending_dbg_exceptions);
7736         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7737         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7738
7739         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7740
7741         exec_control = vmcs12->pin_based_vm_exec_control;
7742         exec_control |= vmcs_config.pin_based_exec_ctrl;
7743         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7744         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
7745
7746         vmx->nested.preemption_timer_expired = false;
7747         if (nested_cpu_has_preemption_timer(vmcs12))
7748                 vmx_start_preemption_timer(vcpu);
7749
7750         /*
7751          * Whether page-faults are trapped is determined by a combination of
7752          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7753          * If enable_ept, L0 doesn't care about page faults and we should
7754          * set all of these to L1's desires. However, if !enable_ept, L0 does
7755          * care about (at least some) page faults, and because it is not easy
7756          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7757          * to exit on each and every L2 page fault. This is done by setting
7758          * MASK=MATCH=0 and (see below) EB.PF=1.
7759          * Note that below we don't need special code to set EB.PF beyond the
7760          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7761          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7762          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7763          *
7764          * A problem with this approach (when !enable_ept) is that L1 may be
7765          * injected with more page faults than it asked for. This could have
7766          * caused problems, but in practice existing hypervisors don't care.
7767          * To fix this, we will need to emulate the PFEC checking (on the L1
7768          * page tables), using walk_addr(), when injecting PFs to L1.
7769          */
7770         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7771                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7772         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7773                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7774
7775         if (cpu_has_secondary_exec_ctrls()) {
7776                 exec_control = vmx_secondary_exec_control(vmx);
7777                 if (!vmx->rdtscp_enabled)
7778                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7779                 /* Take the following fields only from vmcs12 */
7780                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7781                 if (nested_cpu_has(vmcs12,
7782                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7783                         exec_control |= vmcs12->secondary_vm_exec_control;
7784
7785                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7786                         /*
7787                          * Translate L1 physical address to host physical
7788                          * address for vmcs02. Keep the page pinned, so this
7789                          * physical address remains valid. We keep a reference
7790                          * to it so we can release it later.
7791                          */
7792                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7793                                 nested_release_page(vmx->nested.apic_access_page);
7794                         vmx->nested.apic_access_page =
7795                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7796                         /*
7797                          * If translation failed, no matter: This feature asks
7798                          * to exit when accessing the given address, and if it
7799                          * can never be accessed, this feature won't do
7800                          * anything anyway.
7801                          */
7802                         if (!vmx->nested.apic_access_page)
7803                                 exec_control &=
7804                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7805                         else
7806                                 vmcs_write64(APIC_ACCESS_ADDR,
7807                                   page_to_phys(vmx->nested.apic_access_page));
7808                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7809                         exec_control |=
7810                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7811                         vmcs_write64(APIC_ACCESS_ADDR,
7812                                 page_to_phys(vcpu->kvm->arch.apic_access_page));
7813                 }
7814
7815                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7816         }
7817
7818
7819         /*
7820          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7821          * Some constant fields are set here by vmx_set_constant_host_state().
7822          * Other fields are different per CPU, and will be set later when
7823          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7824          */
7825         vmx_set_constant_host_state(vmx);
7826
7827         /*
7828          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7829          * entry, but only if the current (host) sp changed from the value
7830          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7831          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7832          * here we just force the write to happen on entry.
7833          */
7834         vmx->host_rsp = 0;
7835
7836         exec_control = vmx_exec_control(vmx); /* L0's desires */
7837         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7838         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7839         exec_control &= ~CPU_BASED_TPR_SHADOW;
7840         exec_control |= vmcs12->cpu_based_vm_exec_control;
7841         /*
7842          * Merging of IO and MSR bitmaps not currently supported.
7843          * Rather, exit every time.
7844          */
7845         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7846         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7847         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7848
7849         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7850
7851         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7852          * bitwise-or of what L1 wants to trap for L2, and what we want to
7853          * trap. Note that CR0.TS also needs updating - we do this later.
7854          */
7855         update_exception_bitmap(vcpu);
7856         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7857         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7858
7859         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7860          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7861          * bits are further modified by vmx_set_efer() below.
7862          */
7863         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7864
7865         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7866          * emulated by vmx_set_efer(), below.
7867          */
7868         vm_entry_controls_init(vmx,
7869                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7870                         ~VM_ENTRY_IA32E_MODE) |
7871                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7872
7873         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7874                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7875                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7876         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7877                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7878
7879
7880         set_cr4_guest_host_mask(vmx);
7881
7882         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
7883                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
7884
7885         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7886                 vmcs_write64(TSC_OFFSET,
7887                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7888         else
7889                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7890
7891         if (enable_vpid) {
7892                 /*
7893                  * Trivially support vpid by letting L2s share their parent
7894                  * L1's vpid. TODO: move to a more elaborate solution, giving
7895                  * each L2 its own vpid and exposing the vpid feature to L1.
7896                  */
7897                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7898                 vmx_flush_tlb(vcpu);
7899         }
7900
7901         if (nested_cpu_has_ept(vmcs12)) {
7902                 kvm_mmu_unload(vcpu);
7903                 nested_ept_init_mmu_context(vcpu);
7904         }
7905
7906         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7907                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7908         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7909                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7910         else
7911                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7912         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7913         vmx_set_efer(vcpu, vcpu->arch.efer);
7914
7915         /*
7916          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7917          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7918          * The CR0_READ_SHADOW is what L2 should have expected to read given
7919          * the specifications by L1; It's not enough to take
7920          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7921          * have more bits than L1 expected.
7922          */
7923         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7924         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7925
7926         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7927         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7928
7929         /* shadow page tables on either EPT or shadow page tables */
7930         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7931         kvm_mmu_reset_context(vcpu);
7932
7933         if (!enable_ept)
7934                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7935
7936         /*
7937          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7938          */
7939         if (enable_ept) {
7940                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7941                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7942                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7943                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7944         }
7945
7946         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7947         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7948 }
7949
7950 /*
7951  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7952  * for running an L2 nested guest.
7953  */
7954 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7955 {
7956         struct vmcs12 *vmcs12;
7957         struct vcpu_vmx *vmx = to_vmx(vcpu);
7958         int cpu;
7959         struct loaded_vmcs *vmcs02;
7960         bool ia32e;
7961
7962         if (!nested_vmx_check_permission(vcpu) ||
7963             !nested_vmx_check_vmcs12(vcpu))
7964                 return 1;
7965
7966         skip_emulated_instruction(vcpu);
7967         vmcs12 = get_vmcs12(vcpu);
7968
7969         if (enable_shadow_vmcs)
7970                 copy_shadow_to_vmcs12(vmx);
7971
7972         /*
7973          * The nested entry process starts with enforcing various prerequisites
7974          * on vmcs12 as required by the Intel SDM, and act appropriately when
7975          * they fail: As the SDM explains, some conditions should cause the
7976          * instruction to fail, while others will cause the instruction to seem
7977          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7978          * To speed up the normal (success) code path, we should avoid checking
7979          * for misconfigurations which will anyway be caught by the processor
7980          * when using the merged vmcs02.
7981          */
7982         if (vmcs12->launch_state == launch) {
7983                 nested_vmx_failValid(vcpu,
7984                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7985                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7986                 return 1;
7987         }
7988
7989         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7990             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
7991                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7992                 return 1;
7993         }
7994
7995         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7996                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7997                 /*TODO: Also verify bits beyond physical address width are 0*/
7998                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7999                 return 1;
8000         }
8001
8002         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
8003                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
8004                 /*TODO: Also verify bits beyond physical address width are 0*/
8005                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8006                 return 1;
8007         }
8008
8009         if (vmcs12->vm_entry_msr_load_count > 0 ||
8010             vmcs12->vm_exit_msr_load_count > 0 ||
8011             vmcs12->vm_exit_msr_store_count > 0) {
8012                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8013                                     __func__);
8014                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8015                 return 1;
8016         }
8017
8018         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8019               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8020             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8021               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8022             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8023               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8024             !vmx_control_verify(vmcs12->vm_exit_controls,
8025               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8026             !vmx_control_verify(vmcs12->vm_entry_controls,
8027               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8028         {
8029                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8030                 return 1;
8031         }
8032
8033         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8034             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8035                 nested_vmx_failValid(vcpu,
8036                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8037                 return 1;
8038         }
8039
8040         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8041             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8042                 nested_vmx_entry_failure(vcpu, vmcs12,
8043                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8044                 return 1;
8045         }
8046         if (vmcs12->vmcs_link_pointer != -1ull) {
8047                 nested_vmx_entry_failure(vcpu, vmcs12,
8048                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8049                 return 1;
8050         }
8051
8052         /*
8053          * If the load IA32_EFER VM-entry control is 1, the following checks
8054          * are performed on the field for the IA32_EFER MSR:
8055          * - Bits reserved in the IA32_EFER MSR must be 0.
8056          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8057          *   the IA-32e mode guest VM-exit control. It must also be identical
8058          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8059          *   CR0.PG) is 1.
8060          */
8061         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8062                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8063                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8064                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8065                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8066                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8067                         nested_vmx_entry_failure(vcpu, vmcs12,
8068                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8069                         return 1;
8070                 }
8071         }
8072
8073         /*
8074          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8075          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8076          * the values of the LMA and LME bits in the field must each be that of
8077          * the host address-space size VM-exit control.
8078          */
8079         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8080                 ia32e = (vmcs12->vm_exit_controls &
8081                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8082                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8083                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8084                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8085                         nested_vmx_entry_failure(vcpu, vmcs12,
8086                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8087                         return 1;
8088                 }
8089         }
8090
8091         /*
8092          * We're finally done with prerequisite checking, and can start with
8093          * the nested entry.
8094          */
8095
8096         vmcs02 = nested_get_current_vmcs02(vmx);
8097         if (!vmcs02)
8098                 return -ENOMEM;
8099
8100         enter_guest_mode(vcpu);
8101
8102         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8103
8104         cpu = get_cpu();
8105         vmx->loaded_vmcs = vmcs02;
8106         vmx_vcpu_put(vcpu);
8107         vmx_vcpu_load(vcpu, cpu);
8108         vcpu->cpu = cpu;
8109         put_cpu();
8110
8111         vmx_segment_cache_clear(vmx);
8112
8113         vmcs12->launch_state = 1;
8114
8115         prepare_vmcs02(vcpu, vmcs12);
8116
8117         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8118                 return kvm_emulate_halt(vcpu);
8119
8120         vmx->nested.nested_run_pending = 1;
8121
8122         /*
8123          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8124          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8125          * returned as far as L1 is concerned. It will only return (and set
8126          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8127          */
8128         return 1;
8129 }
8130
8131 /*
8132  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8133  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8134  * This function returns the new value we should put in vmcs12.guest_cr0.
8135  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8136  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8137  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8138  *     didn't trap the bit, because if L1 did, so would L0).
8139  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8140  *     been modified by L2, and L1 knows it. So just leave the old value of
8141  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8142  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8143  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8144  *     changed these bits, and therefore they need to be updated, but L0
8145  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8146  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8147  */
8148 static inline unsigned long
8149 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8150 {
8151         return
8152         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8153         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8154         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8155                         vcpu->arch.cr0_guest_owned_bits));
8156 }
8157
8158 static inline unsigned long
8159 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8160 {
8161         return
8162         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8163         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8164         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8165                         vcpu->arch.cr4_guest_owned_bits));
8166 }
8167
8168 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8169                                        struct vmcs12 *vmcs12)
8170 {
8171         u32 idt_vectoring;
8172         unsigned int nr;
8173
8174         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8175                 nr = vcpu->arch.exception.nr;
8176                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8177
8178                 if (kvm_exception_is_soft(nr)) {
8179                         vmcs12->vm_exit_instruction_len =
8180                                 vcpu->arch.event_exit_inst_len;
8181                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8182                 } else
8183                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8184
8185                 if (vcpu->arch.exception.has_error_code) {
8186                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8187                         vmcs12->idt_vectoring_error_code =
8188                                 vcpu->arch.exception.error_code;
8189                 }
8190
8191                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8192         } else if (vcpu->arch.nmi_injected) {
8193                 vmcs12->idt_vectoring_info_field =
8194                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8195         } else if (vcpu->arch.interrupt.pending) {
8196                 nr = vcpu->arch.interrupt.nr;
8197                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8198
8199                 if (vcpu->arch.interrupt.soft) {
8200                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8201                         vmcs12->vm_entry_instruction_len =
8202                                 vcpu->arch.event_exit_inst_len;
8203                 } else
8204                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8205
8206                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8207         }
8208 }
8209
8210 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8211 {
8212         struct vcpu_vmx *vmx = to_vmx(vcpu);
8213
8214         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8215             vmx->nested.preemption_timer_expired) {
8216                 if (vmx->nested.nested_run_pending)
8217                         return -EBUSY;
8218                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8219                 return 0;
8220         }
8221
8222         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8223                 if (vmx->nested.nested_run_pending ||
8224                     vcpu->arch.interrupt.pending)
8225                         return -EBUSY;
8226                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8227                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
8228                                   INTR_INFO_VALID_MASK, 0);
8229                 /*
8230                  * The NMI-triggered VM exit counts as injection:
8231                  * clear this one and block further NMIs.
8232                  */
8233                 vcpu->arch.nmi_pending = 0;
8234                 vmx_set_nmi_mask(vcpu, true);
8235                 return 0;
8236         }
8237
8238         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8239             nested_exit_on_intr(vcpu)) {
8240                 if (vmx->nested.nested_run_pending)
8241                         return -EBUSY;
8242                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8243         }
8244
8245         return 0;
8246 }
8247
8248 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8249 {
8250         ktime_t remaining =
8251                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8252         u64 value;
8253
8254         if (ktime_to_ns(remaining) <= 0)
8255                 return 0;
8256
8257         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8258         do_div(value, 1000000);
8259         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8260 }
8261
8262 /*
8263  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8264  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8265  * and this function updates it to reflect the changes to the guest state while
8266  * L2 was running (and perhaps made some exits which were handled directly by L0
8267  * without going back to L1), and to reflect the exit reason.
8268  * Note that we do not have to copy here all VMCS fields, just those that
8269  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8270  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8271  * which already writes to vmcs12 directly.
8272  */
8273 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8274                            u32 exit_reason, u32 exit_intr_info,
8275                            unsigned long exit_qualification)
8276 {
8277         /* update guest state fields: */
8278         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8279         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8280
8281         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8282         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8283         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8284         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8285
8286         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8287         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8288         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8289         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8290         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8291         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8292         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8293         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8294         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8295         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8296         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8297         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8298         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8299         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8300         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8301         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8302         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8303         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8304         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8305         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8306         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8307         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8308         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8309         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8310         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8311         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8312         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8313         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8314         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8315         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8316         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8317         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8318         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8319         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8320         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8321         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8322
8323         vmcs12->guest_interruptibility_info =
8324                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8325         vmcs12->guest_pending_dbg_exceptions =
8326                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8327         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8328                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8329         else
8330                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8331
8332         if (nested_cpu_has_preemption_timer(vmcs12)) {
8333                 if (vmcs12->vm_exit_controls &
8334                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8335                         vmcs12->vmx_preemption_timer_value =
8336                                 vmx_get_preemption_timer_value(vcpu);
8337                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8338         }
8339
8340         /*
8341          * In some cases (usually, nested EPT), L2 is allowed to change its
8342          * own CR3 without exiting. If it has changed it, we must keep it.
8343          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8344          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8345          *
8346          * Additionally, restore L2's PDPTR to vmcs12.
8347          */
8348         if (enable_ept) {
8349                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8350                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8351                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8352                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8353                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8354         }
8355
8356         vmcs12->vm_entry_controls =
8357                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8358                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8359
8360         /* TODO: These cannot have changed unless we have MSR bitmaps and
8361          * the relevant bit asks not to trap the change */
8362         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8363         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8364                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8365         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8366                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8367         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8368         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8369         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8370         if (vmx_mpx_supported())
8371                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8372
8373         /* update exit information fields: */
8374
8375         vmcs12->vm_exit_reason = exit_reason;
8376         vmcs12->exit_qualification = exit_qualification;
8377
8378         vmcs12->vm_exit_intr_info = exit_intr_info;
8379         if ((vmcs12->vm_exit_intr_info &
8380              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8381             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8382                 vmcs12->vm_exit_intr_error_code =
8383                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8384         vmcs12->idt_vectoring_info_field = 0;
8385         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8386         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8387
8388         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8389                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8390                  * instead of reading the real value. */
8391                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8392
8393                 /*
8394                  * Transfer the event that L0 or L1 may wanted to inject into
8395                  * L2 to IDT_VECTORING_INFO_FIELD.
8396                  */
8397                 vmcs12_save_pending_event(vcpu, vmcs12);
8398         }
8399
8400         /*
8401          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8402          * preserved above and would only end up incorrectly in L1.
8403          */
8404         vcpu->arch.nmi_injected = false;
8405         kvm_clear_exception_queue(vcpu);
8406         kvm_clear_interrupt_queue(vcpu);
8407 }
8408
8409 /*
8410  * A part of what we need to when the nested L2 guest exits and we want to
8411  * run its L1 parent, is to reset L1's guest state to the host state specified
8412  * in vmcs12.
8413  * This function is to be called not only on normal nested exit, but also on
8414  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8415  * Failures During or After Loading Guest State").
8416  * This function should be called when the active VMCS is L1's (vmcs01).
8417  */
8418 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8419                                    struct vmcs12 *vmcs12)
8420 {
8421         struct kvm_segment seg;
8422
8423         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8424                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8425         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8426                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8427         else
8428                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8429         vmx_set_efer(vcpu, vcpu->arch.efer);
8430
8431         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8432         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8433         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8434         /*
8435          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8436          * actually changed, because it depends on the current state of
8437          * fpu_active (which may have changed).
8438          * Note that vmx_set_cr0 refers to efer set above.
8439          */
8440         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8441         /*
8442          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8443          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8444          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8445          */
8446         update_exception_bitmap(vcpu);
8447         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8448         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8449
8450         /*
8451          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8452          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8453          */
8454         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8455         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8456
8457         nested_ept_uninit_mmu_context(vcpu);
8458
8459         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8460         kvm_mmu_reset_context(vcpu);
8461
8462         if (!enable_ept)
8463                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8464
8465         if (enable_vpid) {
8466                 /*
8467                  * Trivially support vpid by letting L2s share their parent
8468                  * L1's vpid. TODO: move to a more elaborate solution, giving
8469                  * each L2 its own vpid and exposing the vpid feature to L1.
8470                  */
8471                 vmx_flush_tlb(vcpu);
8472         }
8473
8474
8475         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8476         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8477         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8478         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8479         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8480
8481         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
8482         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8483                 vmcs_write64(GUEST_BNDCFGS, 0);
8484
8485         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8486                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8487                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8488         }
8489         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8490                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8491                         vmcs12->host_ia32_perf_global_ctrl);
8492
8493         /* Set L1 segment info according to Intel SDM
8494             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8495         seg = (struct kvm_segment) {
8496                 .base = 0,
8497                 .limit = 0xFFFFFFFF,
8498                 .selector = vmcs12->host_cs_selector,
8499                 .type = 11,
8500                 .present = 1,
8501                 .s = 1,
8502                 .g = 1
8503         };
8504         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8505                 seg.l = 1;
8506         else
8507                 seg.db = 1;
8508         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8509         seg = (struct kvm_segment) {
8510                 .base = 0,
8511                 .limit = 0xFFFFFFFF,
8512                 .type = 3,
8513                 .present = 1,
8514                 .s = 1,
8515                 .db = 1,
8516                 .g = 1
8517         };
8518         seg.selector = vmcs12->host_ds_selector;
8519         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8520         seg.selector = vmcs12->host_es_selector;
8521         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8522         seg.selector = vmcs12->host_ss_selector;
8523         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8524         seg.selector = vmcs12->host_fs_selector;
8525         seg.base = vmcs12->host_fs_base;
8526         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8527         seg.selector = vmcs12->host_gs_selector;
8528         seg.base = vmcs12->host_gs_base;
8529         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8530         seg = (struct kvm_segment) {
8531                 .base = vmcs12->host_tr_base,
8532                 .limit = 0x67,
8533                 .selector = vmcs12->host_tr_selector,
8534                 .type = 11,
8535                 .present = 1
8536         };
8537         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8538
8539         kvm_set_dr(vcpu, 7, 0x400);
8540         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8541 }
8542
8543 /*
8544  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8545  * and modify vmcs12 to make it see what it would expect to see there if
8546  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8547  */
8548 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8549                               u32 exit_intr_info,
8550                               unsigned long exit_qualification)
8551 {
8552         struct vcpu_vmx *vmx = to_vmx(vcpu);
8553         int cpu;
8554         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8555
8556         /* trying to cancel vmlaunch/vmresume is a bug */
8557         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8558
8559         leave_guest_mode(vcpu);
8560         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8561                        exit_qualification);
8562
8563         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8564                                        vmcs12->exit_qualification,
8565                                        vmcs12->idt_vectoring_info_field,
8566                                        vmcs12->vm_exit_intr_info,
8567                                        vmcs12->vm_exit_intr_error_code,
8568                                        KVM_ISA_VMX);
8569
8570         cpu = get_cpu();
8571         vmx->loaded_vmcs = &vmx->vmcs01;
8572         vmx_vcpu_put(vcpu);
8573         vmx_vcpu_load(vcpu, cpu);
8574         vcpu->cpu = cpu;
8575         put_cpu();
8576
8577         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8578         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
8579         vmx_segment_cache_clear(vmx);
8580
8581         /* if no vmcs02 cache requested, remove the one we used */
8582         if (VMCS02_POOL_SIZE == 0)
8583                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8584
8585         load_vmcs12_host_state(vcpu, vmcs12);
8586
8587         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8588         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8589
8590         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8591         vmx->host_rsp = 0;
8592
8593         /* Unpin physical memory we referred to in vmcs02 */
8594         if (vmx->nested.apic_access_page) {
8595                 nested_release_page(vmx->nested.apic_access_page);
8596                 vmx->nested.apic_access_page = 0;
8597         }
8598
8599         /*
8600          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8601          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8602          * success or failure flag accordingly.
8603          */
8604         if (unlikely(vmx->fail)) {
8605                 vmx->fail = 0;
8606                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8607         } else
8608                 nested_vmx_succeed(vcpu);
8609         if (enable_shadow_vmcs)
8610                 vmx->nested.sync_shadow_vmcs = true;
8611
8612         /* in case we halted in L2 */
8613         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8614 }
8615
8616 /*
8617  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8618  */
8619 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8620 {
8621         if (is_guest_mode(vcpu))
8622                 nested_vmx_vmexit(vcpu, -1, 0, 0);
8623         free_nested(to_vmx(vcpu));
8624 }
8625
8626 /*
8627  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8628  * 23.7 "VM-entry failures during or after loading guest state" (this also
8629  * lists the acceptable exit-reason and exit-qualification parameters).
8630  * It should only be called before L2 actually succeeded to run, and when
8631  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8632  */
8633 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8634                         struct vmcs12 *vmcs12,
8635                         u32 reason, unsigned long qualification)
8636 {
8637         load_vmcs12_host_state(vcpu, vmcs12);
8638         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8639         vmcs12->exit_qualification = qualification;
8640         nested_vmx_succeed(vcpu);
8641         if (enable_shadow_vmcs)
8642                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8643 }
8644
8645 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8646                                struct x86_instruction_info *info,
8647                                enum x86_intercept_stage stage)
8648 {
8649         return X86EMUL_CONTINUE;
8650 }
8651
8652 static struct kvm_x86_ops vmx_x86_ops = {
8653         .cpu_has_kvm_support = cpu_has_kvm_support,
8654         .disabled_by_bios = vmx_disabled_by_bios,
8655         .hardware_setup = hardware_setup,
8656         .hardware_unsetup = hardware_unsetup,
8657         .check_processor_compatibility = vmx_check_processor_compat,
8658         .hardware_enable = hardware_enable,
8659         .hardware_disable = hardware_disable,
8660         .cpu_has_accelerated_tpr = report_flexpriority,
8661
8662         .vcpu_create = vmx_create_vcpu,
8663         .vcpu_free = vmx_free_vcpu,
8664         .vcpu_reset = vmx_vcpu_reset,
8665
8666         .prepare_guest_switch = vmx_save_host_state,
8667         .vcpu_load = vmx_vcpu_load,
8668         .vcpu_put = vmx_vcpu_put,
8669
8670         .update_db_bp_intercept = update_exception_bitmap,
8671         .get_msr = vmx_get_msr,
8672         .set_msr = vmx_set_msr,
8673         .get_segment_base = vmx_get_segment_base,
8674         .get_segment = vmx_get_segment,
8675         .set_segment = vmx_set_segment,
8676         .get_cpl = vmx_get_cpl,
8677         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8678         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8679         .decache_cr3 = vmx_decache_cr3,
8680         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8681         .set_cr0 = vmx_set_cr0,
8682         .set_cr3 = vmx_set_cr3,
8683         .set_cr4 = vmx_set_cr4,
8684         .set_efer = vmx_set_efer,
8685         .get_idt = vmx_get_idt,
8686         .set_idt = vmx_set_idt,
8687         .get_gdt = vmx_get_gdt,
8688         .set_gdt = vmx_set_gdt,
8689         .get_dr6 = vmx_get_dr6,
8690         .set_dr6 = vmx_set_dr6,
8691         .set_dr7 = vmx_set_dr7,
8692         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
8693         .cache_reg = vmx_cache_reg,
8694         .get_rflags = vmx_get_rflags,
8695         .set_rflags = vmx_set_rflags,
8696         .fpu_activate = vmx_fpu_activate,
8697         .fpu_deactivate = vmx_fpu_deactivate,
8698
8699         .tlb_flush = vmx_flush_tlb,
8700
8701         .run = vmx_vcpu_run,
8702         .handle_exit = vmx_handle_exit,
8703         .skip_emulated_instruction = skip_emulated_instruction,
8704         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8705         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8706         .patch_hypercall = vmx_patch_hypercall,
8707         .set_irq = vmx_inject_irq,
8708         .set_nmi = vmx_inject_nmi,
8709         .queue_exception = vmx_queue_exception,
8710         .cancel_injection = vmx_cancel_injection,
8711         .interrupt_allowed = vmx_interrupt_allowed,
8712         .nmi_allowed = vmx_nmi_allowed,
8713         .get_nmi_mask = vmx_get_nmi_mask,
8714         .set_nmi_mask = vmx_set_nmi_mask,
8715         .enable_nmi_window = enable_nmi_window,
8716         .enable_irq_window = enable_irq_window,
8717         .update_cr8_intercept = update_cr8_intercept,
8718         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8719         .vm_has_apicv = vmx_vm_has_apicv,
8720         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8721         .hwapic_irr_update = vmx_hwapic_irr_update,
8722         .hwapic_isr_update = vmx_hwapic_isr_update,
8723         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8724         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8725
8726         .set_tss_addr = vmx_set_tss_addr,
8727         .get_tdp_level = get_ept_level,
8728         .get_mt_mask = vmx_get_mt_mask,
8729
8730         .get_exit_info = vmx_get_exit_info,
8731
8732         .get_lpage_level = vmx_get_lpage_level,
8733
8734         .cpuid_update = vmx_cpuid_update,
8735
8736         .rdtscp_supported = vmx_rdtscp_supported,
8737         .invpcid_supported = vmx_invpcid_supported,
8738
8739         .set_supported_cpuid = vmx_set_supported_cpuid,
8740
8741         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8742
8743         .set_tsc_khz = vmx_set_tsc_khz,
8744         .read_tsc_offset = vmx_read_tsc_offset,
8745         .write_tsc_offset = vmx_write_tsc_offset,
8746         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8747         .compute_tsc_offset = vmx_compute_tsc_offset,
8748         .read_l1_tsc = vmx_read_l1_tsc,
8749
8750         .set_tdp_cr3 = vmx_set_cr3,
8751
8752         .check_intercept = vmx_check_intercept,
8753         .handle_external_intr = vmx_handle_external_intr,
8754         .mpx_supported = vmx_mpx_supported,
8755
8756         .check_nested_events = vmx_check_nested_events,
8757 };
8758
8759 static int __init vmx_init(void)
8760 {
8761         int r, i, msr;
8762
8763         rdmsrl_safe(MSR_EFER, &host_efer);
8764
8765         for (i = 0; i < NR_VMX_MSR; ++i)
8766                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8767
8768         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8769         if (!vmx_io_bitmap_a)
8770                 return -ENOMEM;
8771
8772         r = -ENOMEM;
8773
8774         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8775         if (!vmx_io_bitmap_b)
8776                 goto out;
8777
8778         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8779         if (!vmx_msr_bitmap_legacy)
8780                 goto out1;
8781
8782         vmx_msr_bitmap_legacy_x2apic =
8783                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8784         if (!vmx_msr_bitmap_legacy_x2apic)
8785                 goto out2;
8786
8787         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8788         if (!vmx_msr_bitmap_longmode)
8789                 goto out3;
8790
8791         vmx_msr_bitmap_longmode_x2apic =
8792                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8793         if (!vmx_msr_bitmap_longmode_x2apic)
8794                 goto out4;
8795         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8796         if (!vmx_vmread_bitmap)
8797                 goto out5;
8798
8799         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8800         if (!vmx_vmwrite_bitmap)
8801                 goto out6;
8802
8803         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8804         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8805         /* shadowed read/write fields */
8806         for (i = 0; i < max_shadow_read_write_fields; i++) {
8807                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8808                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8809         }
8810         /* shadowed read only fields */
8811         for (i = 0; i < max_shadow_read_only_fields; i++)
8812                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8813
8814         /*
8815          * Allow direct access to the PC debug port (it is often used for I/O
8816          * delays, but the vmexits simply slow things down).
8817          */
8818         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8819         clear_bit(0x80, vmx_io_bitmap_a);
8820
8821         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8822
8823         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8824         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8825
8826         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8827
8828         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8829                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8830         if (r)
8831                 goto out7;
8832
8833 #ifdef CONFIG_KEXEC
8834         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8835                            crash_vmclear_local_loaded_vmcss);
8836 #endif
8837
8838         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8839         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8840         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8841         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8842         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8843         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8844         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8845
8846         memcpy(vmx_msr_bitmap_legacy_x2apic,
8847                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8848         memcpy(vmx_msr_bitmap_longmode_x2apic,
8849                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8850
8851         if (enable_apicv) {
8852                 for (msr = 0x800; msr <= 0x8ff; msr++)
8853                         vmx_disable_intercept_msr_read_x2apic(msr);
8854
8855                 /* According SDM, in x2apic mode, the whole id reg is used.
8856                  * But in KVM, it only use the highest eight bits. Need to
8857                  * intercept it */
8858                 vmx_enable_intercept_msr_read_x2apic(0x802);
8859                 /* TMCCT */
8860                 vmx_enable_intercept_msr_read_x2apic(0x839);
8861                 /* TPR */
8862                 vmx_disable_intercept_msr_write_x2apic(0x808);
8863                 /* EOI */
8864                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8865                 /* SELF-IPI */
8866                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8867         }
8868
8869         if (enable_ept) {
8870                 kvm_mmu_set_mask_ptes(0ull,
8871                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8872                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8873                         0ull, VMX_EPT_EXECUTABLE_MASK);
8874                 ept_set_mmio_spte_mask();
8875                 kvm_enable_tdp();
8876         } else
8877                 kvm_disable_tdp();
8878
8879         return 0;
8880
8881 out7:
8882         free_page((unsigned long)vmx_vmwrite_bitmap);
8883 out6:
8884         free_page((unsigned long)vmx_vmread_bitmap);
8885 out5:
8886         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8887 out4:
8888         free_page((unsigned long)vmx_msr_bitmap_longmode);
8889 out3:
8890         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8891 out2:
8892         free_page((unsigned long)vmx_msr_bitmap_legacy);
8893 out1:
8894         free_page((unsigned long)vmx_io_bitmap_b);
8895 out:
8896         free_page((unsigned long)vmx_io_bitmap_a);
8897         return r;
8898 }
8899
8900 static void __exit vmx_exit(void)
8901 {
8902         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8903         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8904         free_page((unsigned long)vmx_msr_bitmap_legacy);
8905         free_page((unsigned long)vmx_msr_bitmap_longmode);
8906         free_page((unsigned long)vmx_io_bitmap_b);
8907         free_page((unsigned long)vmx_io_bitmap_a);
8908         free_page((unsigned long)vmx_vmwrite_bitmap);
8909         free_page((unsigned long)vmx_vmread_bitmap);
8910
8911 #ifdef CONFIG_KEXEC
8912         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8913         synchronize_rcu();
8914 #endif
8915
8916         kvm_exit();
8917 }
8918
8919 module_init(vmx_init)
8920 module_exit(vmx_exit)