2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
34 #include <asm/kvm_para.h>
36 #include <asm/virtext.h>
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
62 static bool erratum_383_found __read_mostly;
64 static const u32 host_save_user_msrs[] = {
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
82 /* These are the merged vectors */
85 /* gpa pointers to the real vectors */
89 /* A VMEXIT is required but not yet emulated */
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
100 /* cache for intercepts of the guest */
103 u32 intercept_exceptions;
106 /* Nested Paging related state */
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
114 struct kvm_vcpu vcpu;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
134 struct nested_state nested;
138 unsigned int3_injected;
139 unsigned long int3_rip;
143 #define MSR_INVALID 0xffffffffU
145 static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148 } direct_access_msrs[] = {
149 { .index = MSR_STAR, .always = true },
150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled = true;
170 static bool npt_enabled;
174 module_param(npt, int, S_IRUGO);
176 static int nested = 1;
177 module_param(nested, int, S_IRUGO);
179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
180 static void svm_complete_interrupts(struct vcpu_svm *svm);
182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
183 static int nested_svm_intercept(struct vcpu_svm *svm);
184 static int nested_svm_vmexit(struct vcpu_svm *svm);
185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
191 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
192 VMCB_ASID, /* ASID */
196 #define VMCB_ALWAYS_DIRTY_MASK 0U
198 static inline void mark_all_dirty(struct vmcb *vmcb)
200 vmcb->control.clean = 0;
203 static inline void mark_all_clean(struct vmcb *vmcb)
205 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
206 & ~VMCB_ALWAYS_DIRTY_MASK;
209 static inline void mark_dirty(struct vmcb *vmcb, int bit)
211 vmcb->control.clean &= ~(1 << bit);
214 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
216 return container_of(vcpu, struct vcpu_svm, vcpu);
219 static void recalc_intercepts(struct vcpu_svm *svm)
221 struct vmcb_control_area *c, *h;
222 struct nested_state *g;
224 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
226 if (!is_guest_mode(&svm->vcpu))
229 c = &svm->vmcb->control;
230 h = &svm->nested.hsave->control;
233 c->intercept_cr = h->intercept_cr | g->intercept_cr;
234 c->intercept_dr = h->intercept_dr | g->intercept_dr;
235 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
236 c->intercept = h->intercept | g->intercept;
239 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
241 if (is_guest_mode(&svm->vcpu))
242 return svm->nested.hsave;
247 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
249 struct vmcb *vmcb = get_host_vmcb(svm);
251 vmcb->control.intercept_cr |= (1U << bit);
253 recalc_intercepts(svm);
256 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
258 struct vmcb *vmcb = get_host_vmcb(svm);
260 vmcb->control.intercept_cr &= ~(1U << bit);
262 recalc_intercepts(svm);
265 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
267 struct vmcb *vmcb = get_host_vmcb(svm);
269 return vmcb->control.intercept_cr & (1U << bit);
272 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
274 struct vmcb *vmcb = get_host_vmcb(svm);
276 vmcb->control.intercept_dr |= (1U << bit);
278 recalc_intercepts(svm);
281 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
283 struct vmcb *vmcb = get_host_vmcb(svm);
285 vmcb->control.intercept_dr &= ~(1U << bit);
287 recalc_intercepts(svm);
290 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
292 struct vmcb *vmcb = get_host_vmcb(svm);
294 vmcb->control.intercept_exceptions |= (1U << bit);
296 recalc_intercepts(svm);
299 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
301 struct vmcb *vmcb = get_host_vmcb(svm);
303 vmcb->control.intercept_exceptions &= ~(1U << bit);
305 recalc_intercepts(svm);
308 static inline void set_intercept(struct vcpu_svm *svm, int bit)
310 struct vmcb *vmcb = get_host_vmcb(svm);
312 vmcb->control.intercept |= (1ULL << bit);
314 recalc_intercepts(svm);
317 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
319 struct vmcb *vmcb = get_host_vmcb(svm);
321 vmcb->control.intercept &= ~(1ULL << bit);
323 recalc_intercepts(svm);
326 static inline void enable_gif(struct vcpu_svm *svm)
328 svm->vcpu.arch.hflags |= HF_GIF_MASK;
331 static inline void disable_gif(struct vcpu_svm *svm)
333 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
336 static inline bool gif_set(struct vcpu_svm *svm)
338 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
341 static unsigned long iopm_base;
343 struct kvm_ldttss_desc {
346 unsigned base1:8, type:5, dpl:2, p:1;
347 unsigned limit1:4, zero0:3, g:1, base2:8;
350 } __attribute__((packed));
352 struct svm_cpu_data {
358 struct kvm_ldttss_desc *tss_desc;
360 struct page *save_area;
363 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
364 static uint32_t svm_features;
366 struct svm_init_data {
371 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
373 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
374 #define MSRS_RANGE_SIZE 2048
375 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
377 static u32 svm_msrpm_offset(u32 msr)
382 for (i = 0; i < NUM_MSR_MAPS; i++) {
383 if (msr < msrpm_ranges[i] ||
384 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
387 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
388 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
390 /* Now we have the u8 offset - but need the u32 offset */
394 /* MSR not in any range */
398 #define MAX_INST_SIZE 15
400 static inline void clgi(void)
402 asm volatile (__ex(SVM_CLGI));
405 static inline void stgi(void)
407 asm volatile (__ex(SVM_STGI));
410 static inline void invlpga(unsigned long addr, u32 asid)
412 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
415 static inline void force_new_asid(struct kvm_vcpu *vcpu)
417 to_svm(vcpu)->asid_generation--;
420 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
422 force_new_asid(vcpu);
425 static int get_npt_level(void)
428 return PT64_ROOT_LEVEL;
430 return PT32E_ROOT_LEVEL;
434 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
436 vcpu->arch.efer = efer;
437 if (!npt_enabled && !(efer & EFER_LMA))
440 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
443 static int is_external_interrupt(u32 info)
445 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
446 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
449 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
451 struct vcpu_svm *svm = to_svm(vcpu);
454 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
455 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
459 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
461 struct vcpu_svm *svm = to_svm(vcpu);
464 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
466 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
470 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
472 struct vcpu_svm *svm = to_svm(vcpu);
474 if (svm->vmcb->control.next_rip != 0)
475 svm->next_rip = svm->vmcb->control.next_rip;
477 if (!svm->next_rip) {
478 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
480 printk(KERN_DEBUG "%s: NOP\n", __func__);
483 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
484 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
485 __func__, kvm_rip_read(vcpu), svm->next_rip);
487 kvm_rip_write(vcpu, svm->next_rip);
488 svm_set_interrupt_shadow(vcpu, 0);
491 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
492 bool has_error_code, u32 error_code,
495 struct vcpu_svm *svm = to_svm(vcpu);
498 * If we are within a nested VM we'd better #VMEXIT and let the guest
499 * handle the exception
502 nested_svm_check_exception(svm, nr, has_error_code, error_code))
505 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
506 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
509 * For guest debugging where we have to reinject #BP if some
510 * INT3 is guest-owned:
511 * Emulate nRIP by moving RIP forward. Will fail if injection
512 * raises a fault that is not intercepted. Still better than
513 * failing in all cases.
515 skip_emulated_instruction(&svm->vcpu);
516 rip = kvm_rip_read(&svm->vcpu);
517 svm->int3_rip = rip + svm->vmcb->save.cs.base;
518 svm->int3_injected = rip - old_rip;
521 svm->vmcb->control.event_inj = nr
523 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
524 | SVM_EVTINJ_TYPE_EXEPT;
525 svm->vmcb->control.event_inj_err = error_code;
528 static void svm_init_erratum_383(void)
534 if (!cpu_has_amd_erratum(amd_erratum_383))
537 /* Use _safe variants to not break nested virtualization */
538 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
544 low = lower_32_bits(val);
545 high = upper_32_bits(val);
547 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
549 erratum_383_found = true;
552 static int has_svm(void)
556 if (!cpu_has_svm(&msg)) {
557 printk(KERN_INFO "has_svm: %s\n", msg);
564 static void svm_hardware_disable(void *garbage)
569 static int svm_hardware_enable(void *garbage)
572 struct svm_cpu_data *sd;
574 struct desc_ptr gdt_descr;
575 struct desc_struct *gdt;
576 int me = raw_smp_processor_id();
578 rdmsrl(MSR_EFER, efer);
579 if (efer & EFER_SVME)
583 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
587 sd = per_cpu(svm_data, me);
590 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
595 sd->asid_generation = 1;
596 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
597 sd->next_asid = sd->max_asid + 1;
599 native_store_gdt(&gdt_descr);
600 gdt = (struct desc_struct *)gdt_descr.address;
601 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
603 wrmsrl(MSR_EFER, efer | EFER_SVME);
605 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
607 svm_init_erratum_383();
612 static void svm_cpu_uninit(int cpu)
614 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
619 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
620 __free_page(sd->save_area);
624 static int svm_cpu_init(int cpu)
626 struct svm_cpu_data *sd;
629 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
633 sd->save_area = alloc_page(GFP_KERNEL);
638 per_cpu(svm_data, cpu) = sd;
648 static bool valid_msr_intercept(u32 index)
652 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
653 if (direct_access_msrs[i].index == index)
659 static void set_msr_interception(u32 *msrpm, unsigned msr,
662 u8 bit_read, bit_write;
667 * If this warning triggers extend the direct_access_msrs list at the
668 * beginning of the file
670 WARN_ON(!valid_msr_intercept(msr));
672 offset = svm_msrpm_offset(msr);
673 bit_read = 2 * (msr & 0x0f);
674 bit_write = 2 * (msr & 0x0f) + 1;
677 BUG_ON(offset == MSR_INVALID);
679 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
680 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
685 static void svm_vcpu_init_msrpm(u32 *msrpm)
689 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
691 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
692 if (!direct_access_msrs[i].always)
695 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
699 static void add_msr_offset(u32 offset)
703 for (i = 0; i < MSRPM_OFFSETS; ++i) {
705 /* Offset already in list? */
706 if (msrpm_offsets[i] == offset)
709 /* Slot used by another offset? */
710 if (msrpm_offsets[i] != MSR_INVALID)
713 /* Add offset to list */
714 msrpm_offsets[i] = offset;
720 * If this BUG triggers the msrpm_offsets table has an overflow. Just
721 * increase MSRPM_OFFSETS in this case.
726 static void init_msrpm_offsets(void)
730 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
732 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
735 offset = svm_msrpm_offset(direct_access_msrs[i].index);
736 BUG_ON(offset == MSR_INVALID);
738 add_msr_offset(offset);
742 static void svm_enable_lbrv(struct vcpu_svm *svm)
744 u32 *msrpm = svm->msrpm;
746 svm->vmcb->control.lbr_ctl = 1;
747 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
748 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
749 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
750 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
753 static void svm_disable_lbrv(struct vcpu_svm *svm)
755 u32 *msrpm = svm->msrpm;
757 svm->vmcb->control.lbr_ctl = 0;
758 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
759 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
760 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
761 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
764 static __init int svm_hardware_setup(void)
767 struct page *iopm_pages;
771 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
776 iopm_va = page_address(iopm_pages);
777 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
778 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
780 init_msrpm_offsets();
782 if (boot_cpu_has(X86_FEATURE_NX))
783 kvm_enable_efer_bits(EFER_NX);
785 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
786 kvm_enable_efer_bits(EFER_FFXSR);
789 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
790 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
793 for_each_possible_cpu(cpu) {
794 r = svm_cpu_init(cpu);
799 svm_features = cpuid_edx(SVM_CPUID_FUNC);
801 if (!boot_cpu_has(X86_FEATURE_NPT))
804 if (npt_enabled && !npt) {
805 printk(KERN_INFO "kvm: Nested Paging disabled\n");
810 printk(KERN_INFO "kvm: Nested Paging enabled\n");
818 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
823 static __exit void svm_hardware_unsetup(void)
827 for_each_possible_cpu(cpu)
830 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
834 static void init_seg(struct vmcb_seg *seg)
837 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
838 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
843 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
846 seg->attrib = SVM_SELECTOR_P_MASK | type;
851 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
853 struct vcpu_svm *svm = to_svm(vcpu);
854 u64 g_tsc_offset = 0;
856 if (is_guest_mode(vcpu)) {
857 g_tsc_offset = svm->vmcb->control.tsc_offset -
858 svm->nested.hsave->control.tsc_offset;
859 svm->nested.hsave->control.tsc_offset = offset;
862 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
864 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
867 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
869 struct vcpu_svm *svm = to_svm(vcpu);
871 svm->vmcb->control.tsc_offset += adjustment;
872 if (is_guest_mode(vcpu))
873 svm->nested.hsave->control.tsc_offset += adjustment;
874 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
877 static void init_vmcb(struct vcpu_svm *svm)
879 struct vmcb_control_area *control = &svm->vmcb->control;
880 struct vmcb_save_area *save = &svm->vmcb->save;
882 svm->vcpu.fpu_active = 1;
883 svm->vcpu.arch.hflags = 0;
885 set_cr_intercept(svm, INTERCEPT_CR0_READ);
886 set_cr_intercept(svm, INTERCEPT_CR3_READ);
887 set_cr_intercept(svm, INTERCEPT_CR4_READ);
888 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
889 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
890 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
891 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
893 set_dr_intercept(svm, INTERCEPT_DR0_READ);
894 set_dr_intercept(svm, INTERCEPT_DR1_READ);
895 set_dr_intercept(svm, INTERCEPT_DR2_READ);
896 set_dr_intercept(svm, INTERCEPT_DR3_READ);
897 set_dr_intercept(svm, INTERCEPT_DR4_READ);
898 set_dr_intercept(svm, INTERCEPT_DR5_READ);
899 set_dr_intercept(svm, INTERCEPT_DR6_READ);
900 set_dr_intercept(svm, INTERCEPT_DR7_READ);
902 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
903 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
904 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
905 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
906 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
907 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
908 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
909 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
911 set_exception_intercept(svm, PF_VECTOR);
912 set_exception_intercept(svm, UD_VECTOR);
913 set_exception_intercept(svm, MC_VECTOR);
915 set_intercept(svm, INTERCEPT_INTR);
916 set_intercept(svm, INTERCEPT_NMI);
917 set_intercept(svm, INTERCEPT_SMI);
918 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
919 set_intercept(svm, INTERCEPT_CPUID);
920 set_intercept(svm, INTERCEPT_INVD);
921 set_intercept(svm, INTERCEPT_HLT);
922 set_intercept(svm, INTERCEPT_INVLPG);
923 set_intercept(svm, INTERCEPT_INVLPGA);
924 set_intercept(svm, INTERCEPT_IOIO_PROT);
925 set_intercept(svm, INTERCEPT_MSR_PROT);
926 set_intercept(svm, INTERCEPT_TASK_SWITCH);
927 set_intercept(svm, INTERCEPT_SHUTDOWN);
928 set_intercept(svm, INTERCEPT_VMRUN);
929 set_intercept(svm, INTERCEPT_VMMCALL);
930 set_intercept(svm, INTERCEPT_VMLOAD);
931 set_intercept(svm, INTERCEPT_VMSAVE);
932 set_intercept(svm, INTERCEPT_STGI);
933 set_intercept(svm, INTERCEPT_CLGI);
934 set_intercept(svm, INTERCEPT_SKINIT);
935 set_intercept(svm, INTERCEPT_WBINVD);
936 set_intercept(svm, INTERCEPT_MONITOR);
937 set_intercept(svm, INTERCEPT_MWAIT);
939 control->iopm_base_pa = iopm_base;
940 control->msrpm_base_pa = __pa(svm->msrpm);
941 control->int_ctl = V_INTR_MASKING_MASK;
949 save->cs.selector = 0xf000;
950 /* Executable/Readable Code Segment */
951 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
952 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
953 save->cs.limit = 0xffff;
955 * cs.base should really be 0xffff0000, but vmx can't handle that, so
956 * be consistent with it.
958 * Replace when we have real mode working for vmx.
960 save->cs.base = 0xf0000;
962 save->gdtr.limit = 0xffff;
963 save->idtr.limit = 0xffff;
965 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
966 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
968 svm_set_efer(&svm->vcpu, 0);
969 save->dr6 = 0xffff0ff0;
972 save->rip = 0x0000fff0;
973 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
976 * This is the guest-visible cr0 value.
977 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
979 svm->vcpu.arch.cr0 = 0;
980 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
982 save->cr4 = X86_CR4_PAE;
986 /* Setup VMCB for Nested Paging */
987 control->nested_ctl = 1;
988 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
989 clr_intercept(svm, INTERCEPT_INVLPG);
990 clr_exception_intercept(svm, PF_VECTOR);
991 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
992 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
993 save->g_pat = 0x0007040600070406ULL;
997 force_new_asid(&svm->vcpu);
999 svm->nested.vmcb = 0;
1000 svm->vcpu.arch.hflags = 0;
1002 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1003 control->pause_filter_count = 3000;
1004 set_intercept(svm, INTERCEPT_PAUSE);
1007 mark_all_dirty(svm->vmcb);
1012 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1014 struct vcpu_svm *svm = to_svm(vcpu);
1018 if (!kvm_vcpu_is_bsp(vcpu)) {
1019 kvm_rip_write(vcpu, 0);
1020 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1021 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1023 vcpu->arch.regs_avail = ~0;
1024 vcpu->arch.regs_dirty = ~0;
1029 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1031 struct vcpu_svm *svm;
1033 struct page *msrpm_pages;
1034 struct page *hsave_page;
1035 struct page *nested_msrpm_pages;
1038 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1044 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1049 page = alloc_page(GFP_KERNEL);
1053 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1057 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1058 if (!nested_msrpm_pages)
1061 hsave_page = alloc_page(GFP_KERNEL);
1065 svm->nested.hsave = page_address(hsave_page);
1067 svm->msrpm = page_address(msrpm_pages);
1068 svm_vcpu_init_msrpm(svm->msrpm);
1070 svm->nested.msrpm = page_address(nested_msrpm_pages);
1071 svm_vcpu_init_msrpm(svm->nested.msrpm);
1073 svm->vmcb = page_address(page);
1074 clear_page(svm->vmcb);
1075 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1076 svm->asid_generation = 0;
1078 kvm_write_tsc(&svm->vcpu, 0);
1080 err = fx_init(&svm->vcpu);
1084 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1085 if (kvm_vcpu_is_bsp(&svm->vcpu))
1086 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1091 __free_page(hsave_page);
1093 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1095 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1099 kvm_vcpu_uninit(&svm->vcpu);
1101 kmem_cache_free(kvm_vcpu_cache, svm);
1103 return ERR_PTR(err);
1106 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1108 struct vcpu_svm *svm = to_svm(vcpu);
1110 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1111 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1112 __free_page(virt_to_page(svm->nested.hsave));
1113 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1114 kvm_vcpu_uninit(vcpu);
1115 kmem_cache_free(kvm_vcpu_cache, svm);
1118 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1120 struct vcpu_svm *svm = to_svm(vcpu);
1123 if (unlikely(cpu != vcpu->cpu)) {
1124 svm->asid_generation = 0;
1125 mark_all_dirty(svm->vmcb);
1128 #ifdef CONFIG_X86_64
1129 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1131 savesegment(fs, svm->host.fs);
1132 savesegment(gs, svm->host.gs);
1133 svm->host.ldt = kvm_read_ldt();
1135 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1136 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1139 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1141 struct vcpu_svm *svm = to_svm(vcpu);
1144 ++vcpu->stat.host_state_reload;
1145 kvm_load_ldt(svm->host.ldt);
1146 #ifdef CONFIG_X86_64
1147 loadsegment(fs, svm->host.fs);
1148 load_gs_index(svm->host.gs);
1149 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1151 loadsegment(gs, svm->host.gs);
1153 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1154 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1157 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1159 return to_svm(vcpu)->vmcb->save.rflags;
1162 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1164 to_svm(vcpu)->vmcb->save.rflags = rflags;
1167 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1170 case VCPU_EXREG_PDPTR:
1171 BUG_ON(!npt_enabled);
1172 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1179 static void svm_set_vintr(struct vcpu_svm *svm)
1181 set_intercept(svm, INTERCEPT_VINTR);
1184 static void svm_clear_vintr(struct vcpu_svm *svm)
1186 clr_intercept(svm, INTERCEPT_VINTR);
1189 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1191 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1194 case VCPU_SREG_CS: return &save->cs;
1195 case VCPU_SREG_DS: return &save->ds;
1196 case VCPU_SREG_ES: return &save->es;
1197 case VCPU_SREG_FS: return &save->fs;
1198 case VCPU_SREG_GS: return &save->gs;
1199 case VCPU_SREG_SS: return &save->ss;
1200 case VCPU_SREG_TR: return &save->tr;
1201 case VCPU_SREG_LDTR: return &save->ldtr;
1207 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1209 struct vmcb_seg *s = svm_seg(vcpu, seg);
1214 static void svm_get_segment(struct kvm_vcpu *vcpu,
1215 struct kvm_segment *var, int seg)
1217 struct vmcb_seg *s = svm_seg(vcpu, seg);
1219 var->base = s->base;
1220 var->limit = s->limit;
1221 var->selector = s->selector;
1222 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1223 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1224 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1225 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1226 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1227 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1228 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1229 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1232 * AMD's VMCB does not have an explicit unusable field, so emulate it
1233 * for cross vendor migration purposes by "not present"
1235 var->unusable = !var->present || (var->type == 0);
1240 * SVM always stores 0 for the 'G' bit in the CS selector in
1241 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1242 * Intel's VMENTRY has a check on the 'G' bit.
1244 var->g = s->limit > 0xfffff;
1248 * Work around a bug where the busy flag in the tr selector
1258 * The accessed bit must always be set in the segment
1259 * descriptor cache, although it can be cleared in the
1260 * descriptor, the cached bit always remains at 1. Since
1261 * Intel has a check on this, set it here to support
1262 * cross-vendor migration.
1269 * On AMD CPUs sometimes the DB bit in the segment
1270 * descriptor is left as 1, although the whole segment has
1271 * been made unusable. Clear it here to pass an Intel VMX
1272 * entry check when cross vendor migrating.
1280 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1282 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1287 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1289 struct vcpu_svm *svm = to_svm(vcpu);
1291 dt->size = svm->vmcb->save.idtr.limit;
1292 dt->address = svm->vmcb->save.idtr.base;
1295 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1297 struct vcpu_svm *svm = to_svm(vcpu);
1299 svm->vmcb->save.idtr.limit = dt->size;
1300 svm->vmcb->save.idtr.base = dt->address ;
1303 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1305 struct vcpu_svm *svm = to_svm(vcpu);
1307 dt->size = svm->vmcb->save.gdtr.limit;
1308 dt->address = svm->vmcb->save.gdtr.base;
1311 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1313 struct vcpu_svm *svm = to_svm(vcpu);
1315 svm->vmcb->save.gdtr.limit = dt->size;
1316 svm->vmcb->save.gdtr.base = dt->address ;
1319 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1323 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1327 static void update_cr0_intercept(struct vcpu_svm *svm)
1329 ulong gcr0 = svm->vcpu.arch.cr0;
1330 u64 *hcr0 = &svm->vmcb->save.cr0;
1332 if (!svm->vcpu.fpu_active)
1333 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1335 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1336 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1339 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1340 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1341 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1343 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1344 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1348 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1350 struct vcpu_svm *svm = to_svm(vcpu);
1352 if (is_guest_mode(vcpu)) {
1354 * We are here because we run in nested mode, the host kvm
1355 * intercepts cr0 writes but the l1 hypervisor does not.
1356 * But the L1 hypervisor may intercept selective cr0 writes.
1357 * This needs to be checked here.
1359 unsigned long old, new;
1361 /* Remove bits that would trigger a real cr0 write intercept */
1362 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1363 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1366 /* cr0 write with ts and mp unchanged */
1367 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1368 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1369 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1370 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1371 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1377 #ifdef CONFIG_X86_64
1378 if (vcpu->arch.efer & EFER_LME) {
1379 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1380 vcpu->arch.efer |= EFER_LMA;
1381 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1384 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1385 vcpu->arch.efer &= ~EFER_LMA;
1386 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1390 vcpu->arch.cr0 = cr0;
1393 cr0 |= X86_CR0_PG | X86_CR0_WP;
1395 if (!vcpu->fpu_active)
1398 * re-enable caching here because the QEMU bios
1399 * does not do it - this results in some delay at
1402 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1403 svm->vmcb->save.cr0 = cr0;
1404 update_cr0_intercept(svm);
1407 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1409 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1410 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1412 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1413 force_new_asid(vcpu);
1415 vcpu->arch.cr4 = cr4;
1418 cr4 |= host_cr4_mce;
1419 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1422 static void svm_set_segment(struct kvm_vcpu *vcpu,
1423 struct kvm_segment *var, int seg)
1425 struct vcpu_svm *svm = to_svm(vcpu);
1426 struct vmcb_seg *s = svm_seg(vcpu, seg);
1428 s->base = var->base;
1429 s->limit = var->limit;
1430 s->selector = var->selector;
1434 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1435 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1436 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1437 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1438 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1439 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1440 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1441 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1443 if (seg == VCPU_SREG_CS)
1445 = (svm->vmcb->save.cs.attrib
1446 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1450 static void update_db_intercept(struct kvm_vcpu *vcpu)
1452 struct vcpu_svm *svm = to_svm(vcpu);
1454 clr_exception_intercept(svm, DB_VECTOR);
1455 clr_exception_intercept(svm, BP_VECTOR);
1457 if (svm->nmi_singlestep)
1458 set_exception_intercept(svm, DB_VECTOR);
1460 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1461 if (vcpu->guest_debug &
1462 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1463 set_exception_intercept(svm, DB_VECTOR);
1464 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1465 set_exception_intercept(svm, BP_VECTOR);
1467 vcpu->guest_debug = 0;
1470 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1472 struct vcpu_svm *svm = to_svm(vcpu);
1474 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1475 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1477 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1479 update_db_intercept(vcpu);
1482 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1484 if (sd->next_asid > sd->max_asid) {
1485 ++sd->asid_generation;
1487 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1490 svm->asid_generation = sd->asid_generation;
1491 svm->vmcb->control.asid = sd->next_asid++;
1493 mark_dirty(svm->vmcb, VMCB_ASID);
1496 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1498 struct vcpu_svm *svm = to_svm(vcpu);
1500 svm->vmcb->save.dr7 = value;
1503 static int pf_interception(struct vcpu_svm *svm)
1505 u64 fault_address = svm->vmcb->control.exit_info_2;
1509 switch (svm->apf_reason) {
1511 error_code = svm->vmcb->control.exit_info_1;
1513 trace_kvm_page_fault(fault_address, error_code);
1514 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1515 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1516 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1518 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1519 svm->apf_reason = 0;
1520 local_irq_disable();
1521 kvm_async_pf_task_wait(fault_address);
1524 case KVM_PV_REASON_PAGE_READY:
1525 svm->apf_reason = 0;
1526 local_irq_disable();
1527 kvm_async_pf_task_wake(fault_address);
1534 static int db_interception(struct vcpu_svm *svm)
1536 struct kvm_run *kvm_run = svm->vcpu.run;
1538 if (!(svm->vcpu.guest_debug &
1539 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1540 !svm->nmi_singlestep) {
1541 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1545 if (svm->nmi_singlestep) {
1546 svm->nmi_singlestep = false;
1547 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1548 svm->vmcb->save.rflags &=
1549 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1550 update_db_intercept(&svm->vcpu);
1553 if (svm->vcpu.guest_debug &
1554 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1555 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1556 kvm_run->debug.arch.pc =
1557 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1558 kvm_run->debug.arch.exception = DB_VECTOR;
1565 static int bp_interception(struct vcpu_svm *svm)
1567 struct kvm_run *kvm_run = svm->vcpu.run;
1569 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1570 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1571 kvm_run->debug.arch.exception = BP_VECTOR;
1575 static int ud_interception(struct vcpu_svm *svm)
1579 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1580 if (er != EMULATE_DONE)
1581 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1585 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1587 struct vcpu_svm *svm = to_svm(vcpu);
1589 clr_exception_intercept(svm, NM_VECTOR);
1591 svm->vcpu.fpu_active = 1;
1592 update_cr0_intercept(svm);
1595 static int nm_interception(struct vcpu_svm *svm)
1597 svm_fpu_activate(&svm->vcpu);
1601 static bool is_erratum_383(void)
1606 if (!erratum_383_found)
1609 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1613 /* Bit 62 may or may not be set for this mce */
1614 value &= ~(1ULL << 62);
1616 if (value != 0xb600000000010015ULL)
1619 /* Clear MCi_STATUS registers */
1620 for (i = 0; i < 6; ++i)
1621 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1623 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1627 value &= ~(1ULL << 2);
1628 low = lower_32_bits(value);
1629 high = upper_32_bits(value);
1631 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1634 /* Flush tlb to evict multi-match entries */
1640 static void svm_handle_mce(struct vcpu_svm *svm)
1642 if (is_erratum_383()) {
1644 * Erratum 383 triggered. Guest state is corrupt so kill the
1647 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1649 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1655 * On an #MC intercept the MCE handler is not called automatically in
1656 * the host. So do it by hand here.
1660 /* not sure if we ever come back to this point */
1665 static int mc_interception(struct vcpu_svm *svm)
1670 static int shutdown_interception(struct vcpu_svm *svm)
1672 struct kvm_run *kvm_run = svm->vcpu.run;
1675 * VMCB is undefined after a SHUTDOWN intercept
1676 * so reinitialize it.
1678 clear_page(svm->vmcb);
1681 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1685 static int io_interception(struct vcpu_svm *svm)
1687 struct kvm_vcpu *vcpu = &svm->vcpu;
1688 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1689 int size, in, string;
1692 ++svm->vcpu.stat.io_exits;
1693 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1694 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1696 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1698 port = io_info >> 16;
1699 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1700 svm->next_rip = svm->vmcb->control.exit_info_2;
1701 skip_emulated_instruction(&svm->vcpu);
1703 return kvm_fast_pio_out(vcpu, size, port);
1706 static int nmi_interception(struct vcpu_svm *svm)
1711 static int intr_interception(struct vcpu_svm *svm)
1713 ++svm->vcpu.stat.irq_exits;
1717 static int nop_on_interception(struct vcpu_svm *svm)
1722 static int halt_interception(struct vcpu_svm *svm)
1724 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1725 skip_emulated_instruction(&svm->vcpu);
1726 return kvm_emulate_halt(&svm->vcpu);
1729 static int vmmcall_interception(struct vcpu_svm *svm)
1731 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1732 skip_emulated_instruction(&svm->vcpu);
1733 kvm_emulate_hypercall(&svm->vcpu);
1737 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1739 struct vcpu_svm *svm = to_svm(vcpu);
1741 return svm->nested.nested_cr3;
1744 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1747 struct vcpu_svm *svm = to_svm(vcpu);
1749 svm->vmcb->control.nested_cr3 = root;
1750 force_new_asid(vcpu);
1753 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1754 struct x86_exception *fault)
1756 struct vcpu_svm *svm = to_svm(vcpu);
1758 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1759 svm->vmcb->control.exit_code_hi = 0;
1760 svm->vmcb->control.exit_info_1 = fault->error_code;
1761 svm->vmcb->control.exit_info_2 = fault->address;
1763 nested_svm_vmexit(svm);
1766 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1770 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1772 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1773 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1774 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1775 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1776 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1781 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1783 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1786 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1788 if (!(svm->vcpu.arch.efer & EFER_SVME)
1789 || !is_paging(&svm->vcpu)) {
1790 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1794 if (svm->vmcb->save.cpl) {
1795 kvm_inject_gp(&svm->vcpu, 0);
1802 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1803 bool has_error_code, u32 error_code)
1807 if (!is_guest_mode(&svm->vcpu))
1810 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1811 svm->vmcb->control.exit_code_hi = 0;
1812 svm->vmcb->control.exit_info_1 = error_code;
1813 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1815 vmexit = nested_svm_intercept(svm);
1816 if (vmexit == NESTED_EXIT_DONE)
1817 svm->nested.exit_required = true;
1822 /* This function returns true if it is save to enable the irq window */
1823 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1825 if (!is_guest_mode(&svm->vcpu))
1828 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1831 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1835 * if vmexit was already requested (by intercepted exception
1836 * for instance) do not overwrite it with "external interrupt"
1839 if (svm->nested.exit_required)
1842 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1843 svm->vmcb->control.exit_info_1 = 0;
1844 svm->vmcb->control.exit_info_2 = 0;
1846 if (svm->nested.intercept & 1ULL) {
1848 * The #vmexit can't be emulated here directly because this
1849 * code path runs with irqs and preemtion disabled. A
1850 * #vmexit emulation might sleep. Only signal request for
1853 svm->nested.exit_required = true;
1854 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1861 /* This function returns true if it is save to enable the nmi window */
1862 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1864 if (!is_guest_mode(&svm->vcpu))
1867 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1870 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1871 svm->nested.exit_required = true;
1876 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1882 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1883 if (is_error_page(page))
1891 kvm_release_page_clean(page);
1892 kvm_inject_gp(&svm->vcpu, 0);
1897 static void nested_svm_unmap(struct page *page)
1900 kvm_release_page_dirty(page);
1903 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1909 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1910 return NESTED_EXIT_HOST;
1912 port = svm->vmcb->control.exit_info_1 >> 16;
1913 gpa = svm->nested.vmcb_iopm + (port / 8);
1917 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1920 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1923 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1925 u32 offset, msr, value;
1928 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1929 return NESTED_EXIT_HOST;
1931 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1932 offset = svm_msrpm_offset(msr);
1933 write = svm->vmcb->control.exit_info_1 & 1;
1934 mask = 1 << ((2 * (msr & 0xf)) + write);
1936 if (offset == MSR_INVALID)
1937 return NESTED_EXIT_DONE;
1939 /* Offset is in 32 bit units but need in 8 bit units */
1942 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1943 return NESTED_EXIT_DONE;
1945 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1948 static int nested_svm_exit_special(struct vcpu_svm *svm)
1950 u32 exit_code = svm->vmcb->control.exit_code;
1952 switch (exit_code) {
1955 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1956 return NESTED_EXIT_HOST;
1958 /* For now we are always handling NPFs when using them */
1960 return NESTED_EXIT_HOST;
1962 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1963 /* When we're shadowing, trap PFs, but not async PF */
1964 if (!npt_enabled && svm->apf_reason == 0)
1965 return NESTED_EXIT_HOST;
1967 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1968 nm_interception(svm);
1974 return NESTED_EXIT_CONTINUE;
1978 * If this function returns true, this #vmexit was already handled
1980 static int nested_svm_intercept(struct vcpu_svm *svm)
1982 u32 exit_code = svm->vmcb->control.exit_code;
1983 int vmexit = NESTED_EXIT_HOST;
1985 switch (exit_code) {
1987 vmexit = nested_svm_exit_handled_msr(svm);
1990 vmexit = nested_svm_intercept_ioio(svm);
1992 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
1993 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
1994 if (svm->nested.intercept_cr & bit)
1995 vmexit = NESTED_EXIT_DONE;
1998 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
1999 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2000 if (svm->nested.intercept_dr & bit)
2001 vmexit = NESTED_EXIT_DONE;
2004 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2005 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2006 if (svm->nested.intercept_exceptions & excp_bits)
2007 vmexit = NESTED_EXIT_DONE;
2008 /* async page fault always cause vmexit */
2009 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2010 svm->apf_reason != 0)
2011 vmexit = NESTED_EXIT_DONE;
2014 case SVM_EXIT_ERR: {
2015 vmexit = NESTED_EXIT_DONE;
2019 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2020 if (svm->nested.intercept & exit_bits)
2021 vmexit = NESTED_EXIT_DONE;
2028 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2032 vmexit = nested_svm_intercept(svm);
2034 if (vmexit == NESTED_EXIT_DONE)
2035 nested_svm_vmexit(svm);
2040 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2042 struct vmcb_control_area *dst = &dst_vmcb->control;
2043 struct vmcb_control_area *from = &from_vmcb->control;
2045 dst->intercept_cr = from->intercept_cr;
2046 dst->intercept_dr = from->intercept_dr;
2047 dst->intercept_exceptions = from->intercept_exceptions;
2048 dst->intercept = from->intercept;
2049 dst->iopm_base_pa = from->iopm_base_pa;
2050 dst->msrpm_base_pa = from->msrpm_base_pa;
2051 dst->tsc_offset = from->tsc_offset;
2052 dst->asid = from->asid;
2053 dst->tlb_ctl = from->tlb_ctl;
2054 dst->int_ctl = from->int_ctl;
2055 dst->int_vector = from->int_vector;
2056 dst->int_state = from->int_state;
2057 dst->exit_code = from->exit_code;
2058 dst->exit_code_hi = from->exit_code_hi;
2059 dst->exit_info_1 = from->exit_info_1;
2060 dst->exit_info_2 = from->exit_info_2;
2061 dst->exit_int_info = from->exit_int_info;
2062 dst->exit_int_info_err = from->exit_int_info_err;
2063 dst->nested_ctl = from->nested_ctl;
2064 dst->event_inj = from->event_inj;
2065 dst->event_inj_err = from->event_inj_err;
2066 dst->nested_cr3 = from->nested_cr3;
2067 dst->lbr_ctl = from->lbr_ctl;
2070 static int nested_svm_vmexit(struct vcpu_svm *svm)
2072 struct vmcb *nested_vmcb;
2073 struct vmcb *hsave = svm->nested.hsave;
2074 struct vmcb *vmcb = svm->vmcb;
2077 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2078 vmcb->control.exit_info_1,
2079 vmcb->control.exit_info_2,
2080 vmcb->control.exit_int_info,
2081 vmcb->control.exit_int_info_err);
2083 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2087 /* Exit Guest-Mode */
2088 leave_guest_mode(&svm->vcpu);
2089 svm->nested.vmcb = 0;
2091 /* Give the current vmcb to the guest */
2094 nested_vmcb->save.es = vmcb->save.es;
2095 nested_vmcb->save.cs = vmcb->save.cs;
2096 nested_vmcb->save.ss = vmcb->save.ss;
2097 nested_vmcb->save.ds = vmcb->save.ds;
2098 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2099 nested_vmcb->save.idtr = vmcb->save.idtr;
2100 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2101 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2102 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2103 nested_vmcb->save.cr2 = vmcb->save.cr2;
2104 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2105 nested_vmcb->save.rflags = vmcb->save.rflags;
2106 nested_vmcb->save.rip = vmcb->save.rip;
2107 nested_vmcb->save.rsp = vmcb->save.rsp;
2108 nested_vmcb->save.rax = vmcb->save.rax;
2109 nested_vmcb->save.dr7 = vmcb->save.dr7;
2110 nested_vmcb->save.dr6 = vmcb->save.dr6;
2111 nested_vmcb->save.cpl = vmcb->save.cpl;
2113 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2114 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2115 nested_vmcb->control.int_state = vmcb->control.int_state;
2116 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2117 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2118 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2119 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2120 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2121 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2122 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2125 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2126 * to make sure that we do not lose injected events. So check event_inj
2127 * here and copy it to exit_int_info if it is valid.
2128 * Exit_int_info and event_inj can't be both valid because the case
2129 * below only happens on a VMRUN instruction intercept which has
2130 * no valid exit_int_info set.
2132 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2133 struct vmcb_control_area *nc = &nested_vmcb->control;
2135 nc->exit_int_info = vmcb->control.event_inj;
2136 nc->exit_int_info_err = vmcb->control.event_inj_err;
2139 nested_vmcb->control.tlb_ctl = 0;
2140 nested_vmcb->control.event_inj = 0;
2141 nested_vmcb->control.event_inj_err = 0;
2143 /* We always set V_INTR_MASKING and remember the old value in hflags */
2144 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2145 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2147 /* Restore the original control entries */
2148 copy_vmcb_control_area(vmcb, hsave);
2150 kvm_clear_exception_queue(&svm->vcpu);
2151 kvm_clear_interrupt_queue(&svm->vcpu);
2153 svm->nested.nested_cr3 = 0;
2155 /* Restore selected save entries */
2156 svm->vmcb->save.es = hsave->save.es;
2157 svm->vmcb->save.cs = hsave->save.cs;
2158 svm->vmcb->save.ss = hsave->save.ss;
2159 svm->vmcb->save.ds = hsave->save.ds;
2160 svm->vmcb->save.gdtr = hsave->save.gdtr;
2161 svm->vmcb->save.idtr = hsave->save.idtr;
2162 svm->vmcb->save.rflags = hsave->save.rflags;
2163 svm_set_efer(&svm->vcpu, hsave->save.efer);
2164 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2165 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2167 svm->vmcb->save.cr3 = hsave->save.cr3;
2168 svm->vcpu.arch.cr3 = hsave->save.cr3;
2170 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2172 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2173 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2174 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2175 svm->vmcb->save.dr7 = 0;
2176 svm->vmcb->save.cpl = 0;
2177 svm->vmcb->control.exit_int_info = 0;
2179 mark_all_dirty(svm->vmcb);
2181 nested_svm_unmap(page);
2183 nested_svm_uninit_mmu_context(&svm->vcpu);
2184 kvm_mmu_reset_context(&svm->vcpu);
2185 kvm_mmu_load(&svm->vcpu);
2190 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2193 * This function merges the msr permission bitmaps of kvm and the
2194 * nested vmcb. It is omptimized in that it only merges the parts where
2195 * the kvm msr permission bitmap may contain zero bits
2199 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2202 for (i = 0; i < MSRPM_OFFSETS; i++) {
2206 if (msrpm_offsets[i] == 0xffffffff)
2209 p = msrpm_offsets[i];
2210 offset = svm->nested.vmcb_msrpm + (p * 4);
2212 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2215 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2218 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2223 static bool nested_vmcb_checks(struct vmcb *vmcb)
2225 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2228 if (vmcb->control.asid == 0)
2231 if (vmcb->control.nested_ctl && !npt_enabled)
2237 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2239 struct vmcb *nested_vmcb;
2240 struct vmcb *hsave = svm->nested.hsave;
2241 struct vmcb *vmcb = svm->vmcb;
2245 vmcb_gpa = svm->vmcb->save.rax;
2247 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2251 if (!nested_vmcb_checks(nested_vmcb)) {
2252 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2253 nested_vmcb->control.exit_code_hi = 0;
2254 nested_vmcb->control.exit_info_1 = 0;
2255 nested_vmcb->control.exit_info_2 = 0;
2257 nested_svm_unmap(page);
2262 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2263 nested_vmcb->save.rip,
2264 nested_vmcb->control.int_ctl,
2265 nested_vmcb->control.event_inj,
2266 nested_vmcb->control.nested_ctl);
2268 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2269 nested_vmcb->control.intercept_cr >> 16,
2270 nested_vmcb->control.intercept_exceptions,
2271 nested_vmcb->control.intercept);
2273 /* Clear internal status */
2274 kvm_clear_exception_queue(&svm->vcpu);
2275 kvm_clear_interrupt_queue(&svm->vcpu);
2278 * Save the old vmcb, so we don't need to pick what we save, but can
2279 * restore everything when a VMEXIT occurs
2281 hsave->save.es = vmcb->save.es;
2282 hsave->save.cs = vmcb->save.cs;
2283 hsave->save.ss = vmcb->save.ss;
2284 hsave->save.ds = vmcb->save.ds;
2285 hsave->save.gdtr = vmcb->save.gdtr;
2286 hsave->save.idtr = vmcb->save.idtr;
2287 hsave->save.efer = svm->vcpu.arch.efer;
2288 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2289 hsave->save.cr4 = svm->vcpu.arch.cr4;
2290 hsave->save.rflags = vmcb->save.rflags;
2291 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2292 hsave->save.rsp = vmcb->save.rsp;
2293 hsave->save.rax = vmcb->save.rax;
2295 hsave->save.cr3 = vmcb->save.cr3;
2297 hsave->save.cr3 = svm->vcpu.arch.cr3;
2299 copy_vmcb_control_area(hsave, vmcb);
2301 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2302 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2304 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2306 if (nested_vmcb->control.nested_ctl) {
2307 kvm_mmu_unload(&svm->vcpu);
2308 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2309 nested_svm_init_mmu_context(&svm->vcpu);
2312 /* Load the nested guest state */
2313 svm->vmcb->save.es = nested_vmcb->save.es;
2314 svm->vmcb->save.cs = nested_vmcb->save.cs;
2315 svm->vmcb->save.ss = nested_vmcb->save.ss;
2316 svm->vmcb->save.ds = nested_vmcb->save.ds;
2317 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2318 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2319 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2320 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2321 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2322 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2324 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2325 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2327 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2329 /* Guest paging mode is active - reset mmu */
2330 kvm_mmu_reset_context(&svm->vcpu);
2332 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2333 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2334 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2335 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2337 /* In case we don't even reach vcpu_run, the fields are not updated */
2338 svm->vmcb->save.rax = nested_vmcb->save.rax;
2339 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2340 svm->vmcb->save.rip = nested_vmcb->save.rip;
2341 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2342 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2343 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2345 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2346 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2348 /* cache intercepts */
2349 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2350 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2351 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2352 svm->nested.intercept = nested_vmcb->control.intercept;
2354 force_new_asid(&svm->vcpu);
2355 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2356 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2357 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2359 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2361 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2362 /* We only want the cr8 intercept bits of the guest */
2363 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2364 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2367 /* We don't want to see VMMCALLs from a nested guest */
2368 clr_intercept(svm, INTERCEPT_VMMCALL);
2370 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2371 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2372 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2373 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2374 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2375 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2377 nested_svm_unmap(page);
2379 /* Enter Guest-Mode */
2380 enter_guest_mode(&svm->vcpu);
2383 * Merge guest and host intercepts - must be called with vcpu in
2384 * guest-mode to take affect here
2386 recalc_intercepts(svm);
2388 svm->nested.vmcb = vmcb_gpa;
2392 mark_all_dirty(svm->vmcb);
2397 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2399 to_vmcb->save.fs = from_vmcb->save.fs;
2400 to_vmcb->save.gs = from_vmcb->save.gs;
2401 to_vmcb->save.tr = from_vmcb->save.tr;
2402 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2403 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2404 to_vmcb->save.star = from_vmcb->save.star;
2405 to_vmcb->save.lstar = from_vmcb->save.lstar;
2406 to_vmcb->save.cstar = from_vmcb->save.cstar;
2407 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2408 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2409 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2410 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2413 static int vmload_interception(struct vcpu_svm *svm)
2415 struct vmcb *nested_vmcb;
2418 if (nested_svm_check_permissions(svm))
2421 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2422 skip_emulated_instruction(&svm->vcpu);
2424 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2428 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2429 nested_svm_unmap(page);
2434 static int vmsave_interception(struct vcpu_svm *svm)
2436 struct vmcb *nested_vmcb;
2439 if (nested_svm_check_permissions(svm))
2442 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2443 skip_emulated_instruction(&svm->vcpu);
2445 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2449 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2450 nested_svm_unmap(page);
2455 static int vmrun_interception(struct vcpu_svm *svm)
2457 if (nested_svm_check_permissions(svm))
2460 /* Save rip after vmrun instruction */
2461 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2463 if (!nested_svm_vmrun(svm))
2466 if (!nested_svm_vmrun_msrpm(svm))
2473 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2474 svm->vmcb->control.exit_code_hi = 0;
2475 svm->vmcb->control.exit_info_1 = 0;
2476 svm->vmcb->control.exit_info_2 = 0;
2478 nested_svm_vmexit(svm);
2483 static int stgi_interception(struct vcpu_svm *svm)
2485 if (nested_svm_check_permissions(svm))
2488 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2489 skip_emulated_instruction(&svm->vcpu);
2490 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2497 static int clgi_interception(struct vcpu_svm *svm)
2499 if (nested_svm_check_permissions(svm))
2502 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2503 skip_emulated_instruction(&svm->vcpu);
2507 /* After a CLGI no interrupts should come */
2508 svm_clear_vintr(svm);
2509 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2514 static int invlpga_interception(struct vcpu_svm *svm)
2516 struct kvm_vcpu *vcpu = &svm->vcpu;
2518 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2519 vcpu->arch.regs[VCPU_REGS_RAX]);
2521 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2522 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2524 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2525 skip_emulated_instruction(&svm->vcpu);
2529 static int skinit_interception(struct vcpu_svm *svm)
2531 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2533 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2537 static int invalid_op_interception(struct vcpu_svm *svm)
2539 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2543 static int task_switch_interception(struct vcpu_svm *svm)
2547 int int_type = svm->vmcb->control.exit_int_info &
2548 SVM_EXITINTINFO_TYPE_MASK;
2549 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2551 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2553 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2554 bool has_error_code = false;
2557 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2559 if (svm->vmcb->control.exit_info_2 &
2560 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2561 reason = TASK_SWITCH_IRET;
2562 else if (svm->vmcb->control.exit_info_2 &
2563 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2564 reason = TASK_SWITCH_JMP;
2566 reason = TASK_SWITCH_GATE;
2568 reason = TASK_SWITCH_CALL;
2570 if (reason == TASK_SWITCH_GATE) {
2572 case SVM_EXITINTINFO_TYPE_NMI:
2573 svm->vcpu.arch.nmi_injected = false;
2575 case SVM_EXITINTINFO_TYPE_EXEPT:
2576 if (svm->vmcb->control.exit_info_2 &
2577 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2578 has_error_code = true;
2580 (u32)svm->vmcb->control.exit_info_2;
2582 kvm_clear_exception_queue(&svm->vcpu);
2584 case SVM_EXITINTINFO_TYPE_INTR:
2585 kvm_clear_interrupt_queue(&svm->vcpu);
2592 if (reason != TASK_SWITCH_GATE ||
2593 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2594 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2595 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2596 skip_emulated_instruction(&svm->vcpu);
2598 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2599 has_error_code, error_code) == EMULATE_FAIL) {
2600 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2601 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2602 svm->vcpu.run->internal.ndata = 0;
2608 static int cpuid_interception(struct vcpu_svm *svm)
2610 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2611 kvm_emulate_cpuid(&svm->vcpu);
2615 static int iret_interception(struct vcpu_svm *svm)
2617 ++svm->vcpu.stat.nmi_window_exits;
2618 clr_intercept(svm, INTERCEPT_IRET);
2619 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2623 static int invlpg_interception(struct vcpu_svm *svm)
2625 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2628 static int emulate_on_interception(struct vcpu_svm *svm)
2630 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2633 static int cr0_write_interception(struct vcpu_svm *svm)
2635 struct kvm_vcpu *vcpu = &svm->vcpu;
2638 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2640 if (svm->nested.vmexit_rip) {
2641 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2642 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2643 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2644 svm->nested.vmexit_rip = 0;
2647 return r == EMULATE_DONE;
2650 static int cr8_write_interception(struct vcpu_svm *svm)
2652 struct kvm_run *kvm_run = svm->vcpu.run;
2654 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2655 /* instruction emulation calls kvm_set_cr8() */
2656 emulate_instruction(&svm->vcpu, 0, 0, 0);
2657 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2658 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2661 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2663 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2667 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2669 struct vcpu_svm *svm = to_svm(vcpu);
2672 case MSR_IA32_TSC: {
2673 struct vmcb *vmcb = get_host_vmcb(svm);
2675 *data = vmcb->control.tsc_offset + native_read_tsc();
2679 *data = svm->vmcb->save.star;
2681 #ifdef CONFIG_X86_64
2683 *data = svm->vmcb->save.lstar;
2686 *data = svm->vmcb->save.cstar;
2688 case MSR_KERNEL_GS_BASE:
2689 *data = svm->vmcb->save.kernel_gs_base;
2691 case MSR_SYSCALL_MASK:
2692 *data = svm->vmcb->save.sfmask;
2695 case MSR_IA32_SYSENTER_CS:
2696 *data = svm->vmcb->save.sysenter_cs;
2698 case MSR_IA32_SYSENTER_EIP:
2699 *data = svm->sysenter_eip;
2701 case MSR_IA32_SYSENTER_ESP:
2702 *data = svm->sysenter_esp;
2705 * Nobody will change the following 5 values in the VMCB so we can
2706 * safely return them on rdmsr. They will always be 0 until LBRV is
2709 case MSR_IA32_DEBUGCTLMSR:
2710 *data = svm->vmcb->save.dbgctl;
2712 case MSR_IA32_LASTBRANCHFROMIP:
2713 *data = svm->vmcb->save.br_from;
2715 case MSR_IA32_LASTBRANCHTOIP:
2716 *data = svm->vmcb->save.br_to;
2718 case MSR_IA32_LASTINTFROMIP:
2719 *data = svm->vmcb->save.last_excp_from;
2721 case MSR_IA32_LASTINTTOIP:
2722 *data = svm->vmcb->save.last_excp_to;
2724 case MSR_VM_HSAVE_PA:
2725 *data = svm->nested.hsave_msr;
2728 *data = svm->nested.vm_cr_msr;
2730 case MSR_IA32_UCODE_REV:
2734 return kvm_get_msr_common(vcpu, ecx, data);
2739 static int rdmsr_interception(struct vcpu_svm *svm)
2741 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2744 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2745 trace_kvm_msr_read_ex(ecx);
2746 kvm_inject_gp(&svm->vcpu, 0);
2748 trace_kvm_msr_read(ecx, data);
2750 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2751 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2752 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2753 skip_emulated_instruction(&svm->vcpu);
2758 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2760 struct vcpu_svm *svm = to_svm(vcpu);
2761 int svm_dis, chg_mask;
2763 if (data & ~SVM_VM_CR_VALID_MASK)
2766 chg_mask = SVM_VM_CR_VALID_MASK;
2768 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2769 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2771 svm->nested.vm_cr_msr &= ~chg_mask;
2772 svm->nested.vm_cr_msr |= (data & chg_mask);
2774 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2776 /* check for svm_disable while efer.svme is set */
2777 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2783 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2785 struct vcpu_svm *svm = to_svm(vcpu);
2789 kvm_write_tsc(vcpu, data);
2792 svm->vmcb->save.star = data;
2794 #ifdef CONFIG_X86_64
2796 svm->vmcb->save.lstar = data;
2799 svm->vmcb->save.cstar = data;
2801 case MSR_KERNEL_GS_BASE:
2802 svm->vmcb->save.kernel_gs_base = data;
2804 case MSR_SYSCALL_MASK:
2805 svm->vmcb->save.sfmask = data;
2808 case MSR_IA32_SYSENTER_CS:
2809 svm->vmcb->save.sysenter_cs = data;
2811 case MSR_IA32_SYSENTER_EIP:
2812 svm->sysenter_eip = data;
2813 svm->vmcb->save.sysenter_eip = data;
2815 case MSR_IA32_SYSENTER_ESP:
2816 svm->sysenter_esp = data;
2817 svm->vmcb->save.sysenter_esp = data;
2819 case MSR_IA32_DEBUGCTLMSR:
2820 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2821 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2825 if (data & DEBUGCTL_RESERVED_BITS)
2828 svm->vmcb->save.dbgctl = data;
2829 if (data & (1ULL<<0))
2830 svm_enable_lbrv(svm);
2832 svm_disable_lbrv(svm);
2834 case MSR_VM_HSAVE_PA:
2835 svm->nested.hsave_msr = data;
2838 return svm_set_vm_cr(vcpu, data);
2840 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2843 return kvm_set_msr_common(vcpu, ecx, data);
2848 static int wrmsr_interception(struct vcpu_svm *svm)
2850 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2851 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2852 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2855 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2856 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2857 trace_kvm_msr_write_ex(ecx, data);
2858 kvm_inject_gp(&svm->vcpu, 0);
2860 trace_kvm_msr_write(ecx, data);
2861 skip_emulated_instruction(&svm->vcpu);
2866 static int msr_interception(struct vcpu_svm *svm)
2868 if (svm->vmcb->control.exit_info_1)
2869 return wrmsr_interception(svm);
2871 return rdmsr_interception(svm);
2874 static int interrupt_window_interception(struct vcpu_svm *svm)
2876 struct kvm_run *kvm_run = svm->vcpu.run;
2878 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2879 svm_clear_vintr(svm);
2880 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2882 * If the user space waits to inject interrupts, exit as soon as
2885 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2886 kvm_run->request_interrupt_window &&
2887 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2888 ++svm->vcpu.stat.irq_window_exits;
2889 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2896 static int pause_interception(struct vcpu_svm *svm)
2898 kvm_vcpu_on_spin(&(svm->vcpu));
2902 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2903 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2904 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2905 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2906 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2907 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2908 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2909 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2910 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2911 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2912 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2913 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2914 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2915 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2916 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2917 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2918 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2919 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2920 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2921 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2922 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2923 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2924 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2925 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2926 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2927 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2928 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2929 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2930 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2931 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2932 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2933 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2934 [SVM_EXIT_INTR] = intr_interception,
2935 [SVM_EXIT_NMI] = nmi_interception,
2936 [SVM_EXIT_SMI] = nop_on_interception,
2937 [SVM_EXIT_INIT] = nop_on_interception,
2938 [SVM_EXIT_VINTR] = interrupt_window_interception,
2939 [SVM_EXIT_CPUID] = cpuid_interception,
2940 [SVM_EXIT_IRET] = iret_interception,
2941 [SVM_EXIT_INVD] = emulate_on_interception,
2942 [SVM_EXIT_PAUSE] = pause_interception,
2943 [SVM_EXIT_HLT] = halt_interception,
2944 [SVM_EXIT_INVLPG] = invlpg_interception,
2945 [SVM_EXIT_INVLPGA] = invlpga_interception,
2946 [SVM_EXIT_IOIO] = io_interception,
2947 [SVM_EXIT_MSR] = msr_interception,
2948 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2949 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2950 [SVM_EXIT_VMRUN] = vmrun_interception,
2951 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2952 [SVM_EXIT_VMLOAD] = vmload_interception,
2953 [SVM_EXIT_VMSAVE] = vmsave_interception,
2954 [SVM_EXIT_STGI] = stgi_interception,
2955 [SVM_EXIT_CLGI] = clgi_interception,
2956 [SVM_EXIT_SKINIT] = skinit_interception,
2957 [SVM_EXIT_WBINVD] = emulate_on_interception,
2958 [SVM_EXIT_MONITOR] = invalid_op_interception,
2959 [SVM_EXIT_MWAIT] = invalid_op_interception,
2960 [SVM_EXIT_NPF] = pf_interception,
2963 void dump_vmcb(struct kvm_vcpu *vcpu)
2965 struct vcpu_svm *svm = to_svm(vcpu);
2966 struct vmcb_control_area *control = &svm->vmcb->control;
2967 struct vmcb_save_area *save = &svm->vmcb->save;
2969 pr_err("VMCB Control Area:\n");
2970 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2971 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
2972 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2973 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
2974 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2975 pr_err("intercepts: %016llx\n", control->intercept);
2976 pr_err("pause filter count: %d\n", control->pause_filter_count);
2977 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2978 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2979 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2980 pr_err("asid: %d\n", control->asid);
2981 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2982 pr_err("int_ctl: %08x\n", control->int_ctl);
2983 pr_err("int_vector: %08x\n", control->int_vector);
2984 pr_err("int_state: %08x\n", control->int_state);
2985 pr_err("exit_code: %08x\n", control->exit_code);
2986 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2987 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2988 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2989 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2990 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2991 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2992 pr_err("event_inj: %08x\n", control->event_inj);
2993 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2994 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2995 pr_err("next_rip: %016llx\n", control->next_rip);
2996 pr_err("VMCB State Save Area:\n");
2997 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2998 save->es.selector, save->es.attrib,
2999 save->es.limit, save->es.base);
3000 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3001 save->cs.selector, save->cs.attrib,
3002 save->cs.limit, save->cs.base);
3003 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3004 save->ss.selector, save->ss.attrib,
3005 save->ss.limit, save->ss.base);
3006 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3007 save->ds.selector, save->ds.attrib,
3008 save->ds.limit, save->ds.base);
3009 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3010 save->fs.selector, save->fs.attrib,
3011 save->fs.limit, save->fs.base);
3012 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3013 save->gs.selector, save->gs.attrib,
3014 save->gs.limit, save->gs.base);
3015 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3016 save->gdtr.selector, save->gdtr.attrib,
3017 save->gdtr.limit, save->gdtr.base);
3018 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3019 save->ldtr.selector, save->ldtr.attrib,
3020 save->ldtr.limit, save->ldtr.base);
3021 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3022 save->idtr.selector, save->idtr.attrib,
3023 save->idtr.limit, save->idtr.base);
3024 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3025 save->tr.selector, save->tr.attrib,
3026 save->tr.limit, save->tr.base);
3027 pr_err("cpl: %d efer: %016llx\n",
3028 save->cpl, save->efer);
3029 pr_err("cr0: %016llx cr2: %016llx\n",
3030 save->cr0, save->cr2);
3031 pr_err("cr3: %016llx cr4: %016llx\n",
3032 save->cr3, save->cr4);
3033 pr_err("dr6: %016llx dr7: %016llx\n",
3034 save->dr6, save->dr7);
3035 pr_err("rip: %016llx rflags: %016llx\n",
3036 save->rip, save->rflags);
3037 pr_err("rsp: %016llx rax: %016llx\n",
3038 save->rsp, save->rax);
3039 pr_err("star: %016llx lstar: %016llx\n",
3040 save->star, save->lstar);
3041 pr_err("cstar: %016llx sfmask: %016llx\n",
3042 save->cstar, save->sfmask);
3043 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3044 save->kernel_gs_base, save->sysenter_cs);
3045 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3046 save->sysenter_esp, save->sysenter_eip);
3047 pr_err("gpat: %016llx dbgctl: %016llx\n",
3048 save->g_pat, save->dbgctl);
3049 pr_err("br_from: %016llx br_to: %016llx\n",
3050 save->br_from, save->br_to);
3051 pr_err("excp_from: %016llx excp_to: %016llx\n",
3052 save->last_excp_from, save->last_excp_to);
3056 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3058 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3060 *info1 = control->exit_info_1;
3061 *info2 = control->exit_info_2;
3064 static int handle_exit(struct kvm_vcpu *vcpu)
3066 struct vcpu_svm *svm = to_svm(vcpu);
3067 struct kvm_run *kvm_run = vcpu->run;
3068 u32 exit_code = svm->vmcb->control.exit_code;
3070 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3072 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3073 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3075 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3077 if (unlikely(svm->nested.exit_required)) {
3078 nested_svm_vmexit(svm);
3079 svm->nested.exit_required = false;
3084 if (is_guest_mode(vcpu)) {
3087 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3088 svm->vmcb->control.exit_info_1,
3089 svm->vmcb->control.exit_info_2,
3090 svm->vmcb->control.exit_int_info,
3091 svm->vmcb->control.exit_int_info_err);
3093 vmexit = nested_svm_exit_special(svm);
3095 if (vmexit == NESTED_EXIT_CONTINUE)
3096 vmexit = nested_svm_exit_handled(svm);
3098 if (vmexit == NESTED_EXIT_DONE)
3102 svm_complete_interrupts(svm);
3104 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3105 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3106 kvm_run->fail_entry.hardware_entry_failure_reason
3107 = svm->vmcb->control.exit_code;
3108 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3113 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3114 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3115 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3116 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3117 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3119 __func__, svm->vmcb->control.exit_int_info,
3122 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3123 || !svm_exit_handlers[exit_code]) {
3124 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3125 kvm_run->hw.hardware_exit_reason = exit_code;
3129 return svm_exit_handlers[exit_code](svm);
3132 static void reload_tss(struct kvm_vcpu *vcpu)
3134 int cpu = raw_smp_processor_id();
3136 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3137 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3141 static void pre_svm_run(struct vcpu_svm *svm)
3143 int cpu = raw_smp_processor_id();
3145 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3147 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3148 /* FIXME: handle wraparound of asid_generation */
3149 if (svm->asid_generation != sd->asid_generation)
3153 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3155 struct vcpu_svm *svm = to_svm(vcpu);
3157 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3158 vcpu->arch.hflags |= HF_NMI_MASK;
3159 set_intercept(svm, INTERCEPT_IRET);
3160 ++vcpu->stat.nmi_injections;
3163 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3165 struct vmcb_control_area *control;
3167 control = &svm->vmcb->control;
3168 control->int_vector = irq;
3169 control->int_ctl &= ~V_INTR_PRIO_MASK;
3170 control->int_ctl |= V_IRQ_MASK |
3171 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3174 static void svm_set_irq(struct kvm_vcpu *vcpu)
3176 struct vcpu_svm *svm = to_svm(vcpu);
3178 BUG_ON(!(gif_set(svm)));
3180 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3181 ++vcpu->stat.irq_injections;
3183 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3184 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3187 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3189 struct vcpu_svm *svm = to_svm(vcpu);
3191 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3198 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3201 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3203 struct vcpu_svm *svm = to_svm(vcpu);
3204 struct vmcb *vmcb = svm->vmcb;
3206 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3207 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3208 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3213 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3215 struct vcpu_svm *svm = to_svm(vcpu);
3217 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3220 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3222 struct vcpu_svm *svm = to_svm(vcpu);
3225 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3226 set_intercept(svm, INTERCEPT_IRET);
3228 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3229 clr_intercept(svm, INTERCEPT_IRET);
3233 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3235 struct vcpu_svm *svm = to_svm(vcpu);
3236 struct vmcb *vmcb = svm->vmcb;
3239 if (!gif_set(svm) ||
3240 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3243 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3245 if (is_guest_mode(vcpu))
3246 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3251 static void enable_irq_window(struct kvm_vcpu *vcpu)
3253 struct vcpu_svm *svm = to_svm(vcpu);
3256 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3257 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3258 * get that intercept, this function will be called again though and
3259 * we'll get the vintr intercept.
3261 if (gif_set(svm) && nested_svm_intr(svm)) {
3263 svm_inject_irq(svm, 0x0);
3267 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3269 struct vcpu_svm *svm = to_svm(vcpu);
3271 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3273 return; /* IRET will cause a vm exit */
3276 * Something prevents NMI from been injected. Single step over possible
3277 * problem (IRET or exception injection or interrupt shadow)
3279 svm->nmi_singlestep = true;
3280 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3281 update_db_intercept(vcpu);
3284 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3289 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3291 force_new_asid(vcpu);
3294 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3298 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3300 struct vcpu_svm *svm = to_svm(vcpu);
3302 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3305 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3306 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3307 kvm_set_cr8(vcpu, cr8);
3311 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3313 struct vcpu_svm *svm = to_svm(vcpu);
3316 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3319 cr8 = kvm_get_cr8(vcpu);
3320 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3321 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3324 static void svm_complete_interrupts(struct vcpu_svm *svm)
3328 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3329 unsigned int3_injected = svm->int3_injected;
3331 svm->int3_injected = 0;
3333 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3334 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3335 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3338 svm->vcpu.arch.nmi_injected = false;
3339 kvm_clear_exception_queue(&svm->vcpu);
3340 kvm_clear_interrupt_queue(&svm->vcpu);
3342 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3345 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3347 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3348 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3351 case SVM_EXITINTINFO_TYPE_NMI:
3352 svm->vcpu.arch.nmi_injected = true;
3354 case SVM_EXITINTINFO_TYPE_EXEPT:
3356 * In case of software exceptions, do not reinject the vector,
3357 * but re-execute the instruction instead. Rewind RIP first
3358 * if we emulated INT3 before.
3360 if (kvm_exception_is_soft(vector)) {
3361 if (vector == BP_VECTOR && int3_injected &&
3362 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3363 kvm_rip_write(&svm->vcpu,
3364 kvm_rip_read(&svm->vcpu) -
3368 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3369 u32 err = svm->vmcb->control.exit_int_info_err;
3370 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3373 kvm_requeue_exception(&svm->vcpu, vector);
3375 case SVM_EXITINTINFO_TYPE_INTR:
3376 kvm_queue_interrupt(&svm->vcpu, vector, false);
3383 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3385 struct vcpu_svm *svm = to_svm(vcpu);
3386 struct vmcb_control_area *control = &svm->vmcb->control;
3388 control->exit_int_info = control->event_inj;
3389 control->exit_int_info_err = control->event_inj_err;
3390 control->event_inj = 0;
3391 svm_complete_interrupts(svm);
3394 #ifdef CONFIG_X86_64
3400 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3402 struct vcpu_svm *svm = to_svm(vcpu);
3404 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3405 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3406 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3409 * A vmexit emulation is required before the vcpu can be executed
3412 if (unlikely(svm->nested.exit_required))
3417 sync_lapic_to_cr8(vcpu);
3419 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3426 "push %%"R"bp; \n\t"
3427 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3428 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3429 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3430 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3431 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3432 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3433 #ifdef CONFIG_X86_64
3434 "mov %c[r8](%[svm]), %%r8 \n\t"
3435 "mov %c[r9](%[svm]), %%r9 \n\t"
3436 "mov %c[r10](%[svm]), %%r10 \n\t"
3437 "mov %c[r11](%[svm]), %%r11 \n\t"
3438 "mov %c[r12](%[svm]), %%r12 \n\t"
3439 "mov %c[r13](%[svm]), %%r13 \n\t"
3440 "mov %c[r14](%[svm]), %%r14 \n\t"
3441 "mov %c[r15](%[svm]), %%r15 \n\t"
3444 /* Enter guest mode */
3446 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3447 __ex(SVM_VMLOAD) "\n\t"
3448 __ex(SVM_VMRUN) "\n\t"
3449 __ex(SVM_VMSAVE) "\n\t"
3452 /* Save guest registers, load host registers */
3453 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3454 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3455 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3456 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3457 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3458 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3459 #ifdef CONFIG_X86_64
3460 "mov %%r8, %c[r8](%[svm]) \n\t"
3461 "mov %%r9, %c[r9](%[svm]) \n\t"
3462 "mov %%r10, %c[r10](%[svm]) \n\t"
3463 "mov %%r11, %c[r11](%[svm]) \n\t"
3464 "mov %%r12, %c[r12](%[svm]) \n\t"
3465 "mov %%r13, %c[r13](%[svm]) \n\t"
3466 "mov %%r14, %c[r14](%[svm]) \n\t"
3467 "mov %%r15, %c[r15](%[svm]) \n\t"
3472 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3473 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3474 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3475 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3476 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3477 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3478 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3479 #ifdef CONFIG_X86_64
3480 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3481 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3482 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3483 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3484 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3485 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3486 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3487 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3490 , R"bx", R"cx", R"dx", R"si", R"di"
3491 #ifdef CONFIG_X86_64
3492 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3496 #ifdef CONFIG_X86_64
3497 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3499 loadsegment(fs, svm->host.fs);
3504 local_irq_disable();
3508 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3509 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3510 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3511 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3513 sync_cr8_to_lapic(vcpu);
3517 /* if exit due to PF check for async PF */
3518 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3519 svm->apf_reason = kvm_read_and_reset_pf_reason();
3522 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3523 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3527 * We need to handle MC intercepts here before the vcpu has a chance to
3528 * change the physical cpu
3530 if (unlikely(svm->vmcb->control.exit_code ==
3531 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3532 svm_handle_mce(svm);
3534 mark_all_clean(svm->vmcb);
3539 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3541 struct vcpu_svm *svm = to_svm(vcpu);
3543 svm->vmcb->save.cr3 = root;
3544 force_new_asid(vcpu);
3547 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3549 struct vcpu_svm *svm = to_svm(vcpu);
3551 svm->vmcb->control.nested_cr3 = root;
3553 /* Also sync guest cr3 here in case we live migrate */
3554 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3556 force_new_asid(vcpu);
3559 static int is_disabled(void)
3563 rdmsrl(MSR_VM_CR, vm_cr);
3564 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3571 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3574 * Patch in the VMMCALL instruction:
3576 hypercall[0] = 0x0f;
3577 hypercall[1] = 0x01;
3578 hypercall[2] = 0xd9;
3581 static void svm_check_processor_compat(void *rtn)
3586 static bool svm_cpu_has_accelerated_tpr(void)
3591 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3596 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3600 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3604 /* Mask out xsave bit as long as it is not supported by SVM */
3605 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3609 entry->ecx |= (1 << 2); /* Set SVM bit */
3612 entry->eax = 1; /* SVM revision 1 */
3613 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3614 ASID emulation to nested SVM */
3615 entry->ecx = 0; /* Reserved */
3616 entry->edx = 0; /* Per default do not support any
3617 additional features */
3619 /* Support next_rip if host supports it */
3620 if (boot_cpu_has(X86_FEATURE_NRIPS))
3621 entry->edx |= SVM_FEATURE_NRIP;
3623 /* Support NPT for the guest if enabled */
3625 entry->edx |= SVM_FEATURE_NPT;
3631 static const struct trace_print_flags svm_exit_reasons_str[] = {
3632 { SVM_EXIT_READ_CR0, "read_cr0" },
3633 { SVM_EXIT_READ_CR3, "read_cr3" },
3634 { SVM_EXIT_READ_CR4, "read_cr4" },
3635 { SVM_EXIT_READ_CR8, "read_cr8" },
3636 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3637 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3638 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3639 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3640 { SVM_EXIT_READ_DR0, "read_dr0" },
3641 { SVM_EXIT_READ_DR1, "read_dr1" },
3642 { SVM_EXIT_READ_DR2, "read_dr2" },
3643 { SVM_EXIT_READ_DR3, "read_dr3" },
3644 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3645 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3646 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3647 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3648 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3649 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3650 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3651 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3652 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3653 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3654 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3655 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3656 { SVM_EXIT_INTR, "interrupt" },
3657 { SVM_EXIT_NMI, "nmi" },
3658 { SVM_EXIT_SMI, "smi" },
3659 { SVM_EXIT_INIT, "init" },
3660 { SVM_EXIT_VINTR, "vintr" },
3661 { SVM_EXIT_CPUID, "cpuid" },
3662 { SVM_EXIT_INVD, "invd" },
3663 { SVM_EXIT_HLT, "hlt" },
3664 { SVM_EXIT_INVLPG, "invlpg" },
3665 { SVM_EXIT_INVLPGA, "invlpga" },
3666 { SVM_EXIT_IOIO, "io" },
3667 { SVM_EXIT_MSR, "msr" },
3668 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3669 { SVM_EXIT_SHUTDOWN, "shutdown" },
3670 { SVM_EXIT_VMRUN, "vmrun" },
3671 { SVM_EXIT_VMMCALL, "hypercall" },
3672 { SVM_EXIT_VMLOAD, "vmload" },
3673 { SVM_EXIT_VMSAVE, "vmsave" },
3674 { SVM_EXIT_STGI, "stgi" },
3675 { SVM_EXIT_CLGI, "clgi" },
3676 { SVM_EXIT_SKINIT, "skinit" },
3677 { SVM_EXIT_WBINVD, "wbinvd" },
3678 { SVM_EXIT_MONITOR, "monitor" },
3679 { SVM_EXIT_MWAIT, "mwait" },
3680 { SVM_EXIT_NPF, "npf" },
3684 static int svm_get_lpage_level(void)
3686 return PT_PDPE_LEVEL;
3689 static bool svm_rdtscp_supported(void)
3694 static bool svm_has_wbinvd_exit(void)
3699 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3701 struct vcpu_svm *svm = to_svm(vcpu);
3703 set_exception_intercept(svm, NM_VECTOR);
3704 update_cr0_intercept(svm);
3707 static struct kvm_x86_ops svm_x86_ops = {
3708 .cpu_has_kvm_support = has_svm,
3709 .disabled_by_bios = is_disabled,
3710 .hardware_setup = svm_hardware_setup,
3711 .hardware_unsetup = svm_hardware_unsetup,
3712 .check_processor_compatibility = svm_check_processor_compat,
3713 .hardware_enable = svm_hardware_enable,
3714 .hardware_disable = svm_hardware_disable,
3715 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3717 .vcpu_create = svm_create_vcpu,
3718 .vcpu_free = svm_free_vcpu,
3719 .vcpu_reset = svm_vcpu_reset,
3721 .prepare_guest_switch = svm_prepare_guest_switch,
3722 .vcpu_load = svm_vcpu_load,
3723 .vcpu_put = svm_vcpu_put,
3725 .set_guest_debug = svm_guest_debug,
3726 .get_msr = svm_get_msr,
3727 .set_msr = svm_set_msr,
3728 .get_segment_base = svm_get_segment_base,
3729 .get_segment = svm_get_segment,
3730 .set_segment = svm_set_segment,
3731 .get_cpl = svm_get_cpl,
3732 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3733 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3734 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3735 .set_cr0 = svm_set_cr0,
3736 .set_cr3 = svm_set_cr3,
3737 .set_cr4 = svm_set_cr4,
3738 .set_efer = svm_set_efer,
3739 .get_idt = svm_get_idt,
3740 .set_idt = svm_set_idt,
3741 .get_gdt = svm_get_gdt,
3742 .set_gdt = svm_set_gdt,
3743 .set_dr7 = svm_set_dr7,
3744 .cache_reg = svm_cache_reg,
3745 .get_rflags = svm_get_rflags,
3746 .set_rflags = svm_set_rflags,
3747 .fpu_activate = svm_fpu_activate,
3748 .fpu_deactivate = svm_fpu_deactivate,
3750 .tlb_flush = svm_flush_tlb,
3752 .run = svm_vcpu_run,
3753 .handle_exit = handle_exit,
3754 .skip_emulated_instruction = skip_emulated_instruction,
3755 .set_interrupt_shadow = svm_set_interrupt_shadow,
3756 .get_interrupt_shadow = svm_get_interrupt_shadow,
3757 .patch_hypercall = svm_patch_hypercall,
3758 .set_irq = svm_set_irq,
3759 .set_nmi = svm_inject_nmi,
3760 .queue_exception = svm_queue_exception,
3761 .cancel_injection = svm_cancel_injection,
3762 .interrupt_allowed = svm_interrupt_allowed,
3763 .nmi_allowed = svm_nmi_allowed,
3764 .get_nmi_mask = svm_get_nmi_mask,
3765 .set_nmi_mask = svm_set_nmi_mask,
3766 .enable_nmi_window = enable_nmi_window,
3767 .enable_irq_window = enable_irq_window,
3768 .update_cr8_intercept = update_cr8_intercept,
3770 .set_tss_addr = svm_set_tss_addr,
3771 .get_tdp_level = get_npt_level,
3772 .get_mt_mask = svm_get_mt_mask,
3774 .get_exit_info = svm_get_exit_info,
3775 .exit_reasons_str = svm_exit_reasons_str,
3777 .get_lpage_level = svm_get_lpage_level,
3779 .cpuid_update = svm_cpuid_update,
3781 .rdtscp_supported = svm_rdtscp_supported,
3783 .set_supported_cpuid = svm_set_supported_cpuid,
3785 .has_wbinvd_exit = svm_has_wbinvd_exit,
3787 .write_tsc_offset = svm_write_tsc_offset,
3788 .adjust_tsc_offset = svm_adjust_tsc_offset,
3790 .set_tdp_cr3 = set_tdp_cr3,
3793 static int __init svm_init(void)
3795 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3796 __alignof__(struct vcpu_svm), THIS_MODULE);
3799 static void __exit svm_exit(void)
3804 module_init(svm_init)
3805 module_exit(svm_exit)