2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
32 #include <asm/virtext.h>
34 #define __ex(x) __kvm_handle_fault_on_reboot(x)
36 MODULE_AUTHOR("Qumranet");
37 MODULE_LICENSE("GPL");
39 #define IOPM_ALLOC_ORDER 2
40 #define MSRPM_ALLOC_ORDER 1
42 #define SEG_TYPE_LDT 2
43 #define SEG_TYPE_BUSY_TSS16 3
45 #define SVM_FEATURE_NPT (1 << 0)
46 #define SVM_FEATURE_LBRV (1 << 1)
47 #define SVM_FEATURE_SVML (1 << 2)
49 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
51 /* Turn on to get debugging output*/
52 /* #define NESTED_DEBUG */
55 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
57 #define nsvm_printk(fmt, args...) do {} while(0)
60 /* enable NPT for AMD64 and X86 with PAE */
61 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
62 static bool npt_enabled = true;
64 static bool npt_enabled = false;
68 module_param(npt, int, S_IRUGO);
70 static int nested = 0;
71 module_param(nested, int, S_IRUGO);
73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
75 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
76 static int nested_svm_vmexit(struct vcpu_svm *svm);
77 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
78 void *arg2, void *opaque);
79 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
80 bool has_error_code, u32 error_code);
82 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
84 return container_of(vcpu, struct vcpu_svm, vcpu);
87 static inline bool is_nested(struct vcpu_svm *svm)
89 return svm->nested_vmcb;
92 static unsigned long iopm_base;
94 struct kvm_ldttss_desc {
97 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
98 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
101 } __attribute__((packed));
103 struct svm_cpu_data {
109 struct kvm_ldttss_desc *tss_desc;
111 struct page *save_area;
114 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
115 static uint32_t svm_features;
117 struct svm_init_data {
122 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
125 #define MSRS_RANGE_SIZE 2048
126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
128 #define MAX_INST_SIZE 15
130 static inline u32 svm_has(u32 feat)
132 return svm_features & feat;
135 static inline void clgi(void)
137 asm volatile (__ex(SVM_CLGI));
140 static inline void stgi(void)
142 asm volatile (__ex(SVM_STGI));
145 static inline void invlpga(unsigned long addr, u32 asid)
147 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
150 static inline unsigned long kvm_read_cr2(void)
154 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
158 static inline void kvm_write_cr2(unsigned long val)
160 asm volatile ("mov %0, %%cr2" :: "r" (val));
163 static inline void force_new_asid(struct kvm_vcpu *vcpu)
165 to_svm(vcpu)->asid_generation--;
168 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
170 force_new_asid(vcpu);
173 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
175 if (!npt_enabled && !(efer & EFER_LMA))
178 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
179 vcpu->arch.shadow_efer = efer;
182 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
183 bool has_error_code, u32 error_code)
185 struct vcpu_svm *svm = to_svm(vcpu);
187 /* If we are within a nested VM we'd better #VMEXIT and let the
188 guest handle the exception */
189 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
192 svm->vmcb->control.event_inj = nr
194 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
195 | SVM_EVTINJ_TYPE_EXEPT;
196 svm->vmcb->control.event_inj_err = error_code;
199 static int is_external_interrupt(u32 info)
201 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
202 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
205 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
207 struct vcpu_svm *svm = to_svm(vcpu);
209 if (!svm->next_rip) {
210 printk(KERN_DEBUG "%s: NOP\n", __func__);
213 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
214 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
215 __func__, kvm_rip_read(vcpu), svm->next_rip);
217 kvm_rip_write(vcpu, svm->next_rip);
218 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
221 static int has_svm(void)
225 if (!cpu_has_svm(&msg)) {
226 printk(KERN_INFO "has_svm: %s\n", msg);
233 static void svm_hardware_disable(void *garbage)
238 static void svm_hardware_enable(void *garbage)
241 struct svm_cpu_data *svm_data;
243 struct desc_ptr gdt_descr;
244 struct desc_struct *gdt;
245 int me = raw_smp_processor_id();
248 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
251 svm_data = per_cpu(svm_data, me);
254 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
259 svm_data->asid_generation = 1;
260 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
261 svm_data->next_asid = svm_data->max_asid + 1;
263 asm volatile ("sgdt %0" : "=m"(gdt_descr));
264 gdt = (struct desc_struct *)gdt_descr.address;
265 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
267 rdmsrl(MSR_EFER, efer);
268 wrmsrl(MSR_EFER, efer | EFER_SVME);
270 wrmsrl(MSR_VM_HSAVE_PA,
271 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
274 static void svm_cpu_uninit(int cpu)
276 struct svm_cpu_data *svm_data
277 = per_cpu(svm_data, raw_smp_processor_id());
282 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
283 __free_page(svm_data->save_area);
287 static int svm_cpu_init(int cpu)
289 struct svm_cpu_data *svm_data;
292 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
296 svm_data->save_area = alloc_page(GFP_KERNEL);
298 if (!svm_data->save_area)
301 per_cpu(svm_data, cpu) = svm_data;
311 static void set_msr_interception(u32 *msrpm, unsigned msr,
316 for (i = 0; i < NUM_MSR_MAPS; i++) {
317 if (msr >= msrpm_ranges[i] &&
318 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
319 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
320 msrpm_ranges[i]) * 2;
322 u32 *base = msrpm + (msr_offset / 32);
323 u32 msr_shift = msr_offset % 32;
324 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
325 *base = (*base & ~(0x3 << msr_shift)) |
333 static void svm_vcpu_init_msrpm(u32 *msrpm)
335 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
338 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
339 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
340 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
341 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
342 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
343 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
345 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
346 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
347 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
348 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
351 static void svm_enable_lbrv(struct vcpu_svm *svm)
353 u32 *msrpm = svm->msrpm;
355 svm->vmcb->control.lbr_ctl = 1;
356 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
357 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
358 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
359 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
362 static void svm_disable_lbrv(struct vcpu_svm *svm)
364 u32 *msrpm = svm->msrpm;
366 svm->vmcb->control.lbr_ctl = 0;
367 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
368 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
369 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
370 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
373 static __init int svm_hardware_setup(void)
376 struct page *iopm_pages;
380 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
385 iopm_va = page_address(iopm_pages);
386 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
387 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
389 if (boot_cpu_has(X86_FEATURE_NX))
390 kvm_enable_efer_bits(EFER_NX);
392 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
393 kvm_enable_efer_bits(EFER_FFXSR);
396 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
397 kvm_enable_efer_bits(EFER_SVME);
400 for_each_online_cpu(cpu) {
401 r = svm_cpu_init(cpu);
406 svm_features = cpuid_edx(SVM_CPUID_FUNC);
408 if (!svm_has(SVM_FEATURE_NPT))
411 if (npt_enabled && !npt) {
412 printk(KERN_INFO "kvm: Nested Paging disabled\n");
417 printk(KERN_INFO "kvm: Nested Paging enabled\n");
425 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
430 static __exit void svm_hardware_unsetup(void)
434 for_each_online_cpu(cpu)
437 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
441 static void init_seg(struct vmcb_seg *seg)
444 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
445 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
450 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
453 seg->attrib = SVM_SELECTOR_P_MASK | type;
458 static void init_vmcb(struct vcpu_svm *svm)
460 struct vmcb_control_area *control = &svm->vmcb->control;
461 struct vmcb_save_area *save = &svm->vmcb->save;
463 control->intercept_cr_read = INTERCEPT_CR0_MASK |
467 control->intercept_cr_write = INTERCEPT_CR0_MASK |
472 control->intercept_dr_read = INTERCEPT_DR0_MASK |
477 control->intercept_dr_write = INTERCEPT_DR0_MASK |
484 control->intercept_exceptions = (1 << PF_VECTOR) |
489 control->intercept = (1ULL << INTERCEPT_INTR) |
490 (1ULL << INTERCEPT_NMI) |
491 (1ULL << INTERCEPT_SMI) |
492 (1ULL << INTERCEPT_CPUID) |
493 (1ULL << INTERCEPT_INVD) |
494 (1ULL << INTERCEPT_HLT) |
495 (1ULL << INTERCEPT_INVLPG) |
496 (1ULL << INTERCEPT_INVLPGA) |
497 (1ULL << INTERCEPT_IOIO_PROT) |
498 (1ULL << INTERCEPT_MSR_PROT) |
499 (1ULL << INTERCEPT_TASK_SWITCH) |
500 (1ULL << INTERCEPT_SHUTDOWN) |
501 (1ULL << INTERCEPT_VMRUN) |
502 (1ULL << INTERCEPT_VMMCALL) |
503 (1ULL << INTERCEPT_VMLOAD) |
504 (1ULL << INTERCEPT_VMSAVE) |
505 (1ULL << INTERCEPT_STGI) |
506 (1ULL << INTERCEPT_CLGI) |
507 (1ULL << INTERCEPT_SKINIT) |
508 (1ULL << INTERCEPT_WBINVD) |
509 (1ULL << INTERCEPT_MONITOR) |
510 (1ULL << INTERCEPT_MWAIT);
512 control->iopm_base_pa = iopm_base;
513 control->msrpm_base_pa = __pa(svm->msrpm);
514 control->tsc_offset = 0;
515 control->int_ctl = V_INTR_MASKING_MASK;
523 save->cs.selector = 0xf000;
524 /* Executable/Readable Code Segment */
525 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
526 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
527 save->cs.limit = 0xffff;
529 * cs.base should really be 0xffff0000, but vmx can't handle that, so
530 * be consistent with it.
532 * Replace when we have real mode working for vmx.
534 save->cs.base = 0xf0000;
536 save->gdtr.limit = 0xffff;
537 save->idtr.limit = 0xffff;
539 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
540 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
542 save->efer = EFER_SVME;
543 save->dr6 = 0xffff0ff0;
546 save->rip = 0x0000fff0;
547 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
550 * cr0 val on cpu init should be 0x60000010, we enable cpu
551 * cache by default. the orderly way is to enable cache in bios.
553 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
554 save->cr4 = X86_CR4_PAE;
558 /* Setup VMCB for Nested Paging */
559 control->nested_ctl = 1;
560 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
561 (1ULL << INTERCEPT_INVLPG));
562 control->intercept_exceptions &= ~(1 << PF_VECTOR);
563 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
565 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
567 save->g_pat = 0x0007040600070406ULL;
568 /* enable caching because the QEMU Bios doesn't enable it */
569 save->cr0 = X86_CR0_ET;
573 force_new_asid(&svm->vcpu);
575 svm->nested_vmcb = 0;
576 svm->vcpu.arch.hflags = HF_GIF_MASK;
579 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
581 struct vcpu_svm *svm = to_svm(vcpu);
585 if (vcpu->vcpu_id != 0) {
586 kvm_rip_write(vcpu, 0);
587 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
588 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
590 vcpu->arch.regs_avail = ~0;
591 vcpu->arch.regs_dirty = ~0;
596 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
598 struct vcpu_svm *svm;
600 struct page *msrpm_pages;
601 struct page *hsave_page;
602 struct page *nested_msrpm_pages;
605 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
611 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
615 page = alloc_page(GFP_KERNEL);
622 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
626 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
627 if (!nested_msrpm_pages)
630 svm->msrpm = page_address(msrpm_pages);
631 svm_vcpu_init_msrpm(svm->msrpm);
633 hsave_page = alloc_page(GFP_KERNEL);
636 svm->hsave = page_address(hsave_page);
638 svm->nested_msrpm = page_address(nested_msrpm_pages);
640 svm->vmcb = page_address(page);
641 clear_page(svm->vmcb);
642 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
643 svm->asid_generation = 0;
647 svm->vcpu.fpu_active = 1;
648 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
649 if (svm->vcpu.vcpu_id == 0)
650 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
655 kvm_vcpu_uninit(&svm->vcpu);
657 kmem_cache_free(kvm_vcpu_cache, svm);
662 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
664 struct vcpu_svm *svm = to_svm(vcpu);
666 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
667 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
668 __free_page(virt_to_page(svm->hsave));
669 __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
670 kvm_vcpu_uninit(vcpu);
671 kmem_cache_free(kvm_vcpu_cache, svm);
674 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
676 struct vcpu_svm *svm = to_svm(vcpu);
679 if (unlikely(cpu != vcpu->cpu)) {
683 * Make sure that the guest sees a monotonically
687 delta = vcpu->arch.host_tsc - tsc_this;
688 svm->vmcb->control.tsc_offset += delta;
690 kvm_migrate_timers(vcpu);
693 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
694 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
697 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
699 struct vcpu_svm *svm = to_svm(vcpu);
702 ++vcpu->stat.host_state_reload;
703 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
704 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
706 rdtscll(vcpu->arch.host_tsc);
709 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
711 return to_svm(vcpu)->vmcb->save.rflags;
714 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
716 to_svm(vcpu)->vmcb->save.rflags = rflags;
719 static void svm_set_vintr(struct vcpu_svm *svm)
721 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
724 static void svm_clear_vintr(struct vcpu_svm *svm)
726 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
729 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
731 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
734 case VCPU_SREG_CS: return &save->cs;
735 case VCPU_SREG_DS: return &save->ds;
736 case VCPU_SREG_ES: return &save->es;
737 case VCPU_SREG_FS: return &save->fs;
738 case VCPU_SREG_GS: return &save->gs;
739 case VCPU_SREG_SS: return &save->ss;
740 case VCPU_SREG_TR: return &save->tr;
741 case VCPU_SREG_LDTR: return &save->ldtr;
747 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
749 struct vmcb_seg *s = svm_seg(vcpu, seg);
754 static void svm_get_segment(struct kvm_vcpu *vcpu,
755 struct kvm_segment *var, int seg)
757 struct vmcb_seg *s = svm_seg(vcpu, seg);
760 var->limit = s->limit;
761 var->selector = s->selector;
762 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
763 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
764 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
765 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
766 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
767 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
768 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
769 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
771 /* AMD's VMCB does not have an explicit unusable field, so emulate it
772 * for cross vendor migration purposes by "not present"
774 var->unusable = !var->present || (var->type == 0);
779 * SVM always stores 0 for the 'G' bit in the CS selector in
780 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
781 * Intel's VMENTRY has a check on the 'G' bit.
783 var->g = s->limit > 0xfffff;
787 * Work around a bug where the busy flag in the tr selector
797 * The accessed bit must always be set in the segment
798 * descriptor cache, although it can be cleared in the
799 * descriptor, the cached bit always remains at 1. Since
800 * Intel has a check on this, set it here to support
801 * cross-vendor migration.
809 static int svm_get_cpl(struct kvm_vcpu *vcpu)
811 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
816 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
818 struct vcpu_svm *svm = to_svm(vcpu);
820 dt->limit = svm->vmcb->save.idtr.limit;
821 dt->base = svm->vmcb->save.idtr.base;
824 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
826 struct vcpu_svm *svm = to_svm(vcpu);
828 svm->vmcb->save.idtr.limit = dt->limit;
829 svm->vmcb->save.idtr.base = dt->base ;
832 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
834 struct vcpu_svm *svm = to_svm(vcpu);
836 dt->limit = svm->vmcb->save.gdtr.limit;
837 dt->base = svm->vmcb->save.gdtr.base;
840 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
842 struct vcpu_svm *svm = to_svm(vcpu);
844 svm->vmcb->save.gdtr.limit = dt->limit;
845 svm->vmcb->save.gdtr.base = dt->base ;
848 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
852 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
854 struct vcpu_svm *svm = to_svm(vcpu);
857 if (vcpu->arch.shadow_efer & EFER_LME) {
858 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
859 vcpu->arch.shadow_efer |= EFER_LMA;
860 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
863 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
864 vcpu->arch.shadow_efer &= ~EFER_LMA;
865 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
872 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
873 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
874 vcpu->fpu_active = 1;
877 vcpu->arch.cr0 = cr0;
878 cr0 |= X86_CR0_PG | X86_CR0_WP;
879 if (!vcpu->fpu_active) {
880 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
885 * re-enable caching here because the QEMU bios
886 * does not do it - this results in some delay at
889 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
890 svm->vmcb->save.cr0 = cr0;
893 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
895 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
896 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
898 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
899 force_new_asid(vcpu);
901 vcpu->arch.cr4 = cr4;
905 to_svm(vcpu)->vmcb->save.cr4 = cr4;
908 static void svm_set_segment(struct kvm_vcpu *vcpu,
909 struct kvm_segment *var, int seg)
911 struct vcpu_svm *svm = to_svm(vcpu);
912 struct vmcb_seg *s = svm_seg(vcpu, seg);
915 s->limit = var->limit;
916 s->selector = var->selector;
920 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
921 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
922 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
923 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
924 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
925 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
926 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
927 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
929 if (seg == VCPU_SREG_CS)
931 = (svm->vmcb->save.cs.attrib
932 >> SVM_SELECTOR_DPL_SHIFT) & 3;
936 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
938 int old_debug = vcpu->guest_debug;
939 struct vcpu_svm *svm = to_svm(vcpu);
941 vcpu->guest_debug = dbg->control;
943 svm->vmcb->control.intercept_exceptions &=
944 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
945 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
946 if (vcpu->guest_debug &
947 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
948 svm->vmcb->control.intercept_exceptions |=
950 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
951 svm->vmcb->control.intercept_exceptions |=
954 vcpu->guest_debug = 0;
956 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
957 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
959 svm->vmcb->save.dr7 = vcpu->arch.dr7;
961 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
962 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
963 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
964 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
969 static int svm_get_irq(struct kvm_vcpu *vcpu)
971 if (!vcpu->arch.interrupt.pending)
973 return vcpu->arch.interrupt.nr;
976 static void load_host_msrs(struct kvm_vcpu *vcpu)
979 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
983 static void save_host_msrs(struct kvm_vcpu *vcpu)
986 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
990 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
992 if (svm_data->next_asid > svm_data->max_asid) {
993 ++svm_data->asid_generation;
994 svm_data->next_asid = 1;
995 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
998 svm->vcpu.cpu = svm_data->cpu;
999 svm->asid_generation = svm_data->asid_generation;
1000 svm->vmcb->control.asid = svm_data->next_asid++;
1003 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1005 struct vcpu_svm *svm = to_svm(vcpu);
1010 val = vcpu->arch.db[dr];
1013 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1014 val = vcpu->arch.dr6;
1016 val = svm->vmcb->save.dr6;
1019 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1020 val = vcpu->arch.dr7;
1022 val = svm->vmcb->save.dr7;
1028 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1032 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1035 struct vcpu_svm *svm = to_svm(vcpu);
1037 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
1043 vcpu->arch.db[dr] = value;
1044 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1045 vcpu->arch.eff_db[dr] = value;
1048 if (vcpu->arch.cr4 & X86_CR4_DE)
1049 *exception = UD_VECTOR;
1052 if (value & 0xffffffff00000000ULL) {
1053 *exception = GP_VECTOR;
1056 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1059 if (value & 0xffffffff00000000ULL) {
1060 *exception = GP_VECTOR;
1063 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1064 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1065 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1066 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1070 /* FIXME: Possible case? */
1071 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1073 *exception = UD_VECTOR;
1078 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1083 fault_address = svm->vmcb->control.exit_info_2;
1084 error_code = svm->vmcb->control.exit_info_1;
1087 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1088 (u32)fault_address, (u32)(fault_address >> 32),
1091 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1092 (u32)fault_address, (u32)(fault_address >> 32),
1095 * FIXME: Tis shouldn't be necessary here, but there is a flush
1096 * missing in the MMU code. Until we find this bug, flush the
1097 * complete TLB here on an NPF
1100 svm_flush_tlb(&svm->vcpu);
1102 if (svm->vcpu.arch.interrupt.pending ||
1103 svm->vcpu.arch.exception.pending)
1104 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1106 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1109 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1111 if (!(svm->vcpu.guest_debug &
1112 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1113 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1116 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1117 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1118 kvm_run->debug.arch.exception = DB_VECTOR;
1122 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1124 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1125 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1126 kvm_run->debug.arch.exception = BP_VECTOR;
1130 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1134 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1135 if (er != EMULATE_DONE)
1136 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1140 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1142 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1143 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1144 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1145 svm->vcpu.fpu_active = 1;
1150 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1153 * On an #MC intercept the MCE handler is not called automatically in
1154 * the host. So do it by hand here.
1158 /* not sure if we ever come back to this point */
1163 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1166 * VMCB is undefined after a SHUTDOWN intercept
1167 * so reinitialize it.
1169 clear_page(svm->vmcb);
1172 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1176 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1178 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1179 int size, in, string;
1182 ++svm->vcpu.stat.io_exits;
1184 svm->next_rip = svm->vmcb->control.exit_info_2;
1186 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1189 if (emulate_instruction(&svm->vcpu,
1190 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1195 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1196 port = io_info >> 16;
1197 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1199 skip_emulated_instruction(&svm->vcpu);
1200 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1203 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1205 KVMTRACE_0D(NMI, &svm->vcpu, handler);
1209 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1211 ++svm->vcpu.stat.irq_exits;
1212 KVMTRACE_0D(INTR, &svm->vcpu, handler);
1216 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1221 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1223 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1224 skip_emulated_instruction(&svm->vcpu);
1225 return kvm_emulate_halt(&svm->vcpu);
1228 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1230 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1231 skip_emulated_instruction(&svm->vcpu);
1232 kvm_emulate_hypercall(&svm->vcpu);
1236 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1238 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1239 || !is_paging(&svm->vcpu)) {
1240 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1244 if (svm->vmcb->save.cpl) {
1245 kvm_inject_gp(&svm->vcpu, 0);
1252 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1253 bool has_error_code, u32 error_code)
1255 if (is_nested(svm)) {
1256 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1257 svm->vmcb->control.exit_code_hi = 0;
1258 svm->vmcb->control.exit_info_1 = error_code;
1259 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1260 if (nested_svm_exit_handled(svm, false)) {
1261 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1263 nested_svm_vmexit(svm);
1271 static inline int nested_svm_intr(struct vcpu_svm *svm)
1273 if (is_nested(svm)) {
1274 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1277 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1280 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1282 if (nested_svm_exit_handled(svm, false)) {
1283 nsvm_printk("VMexit -> INTR\n");
1284 nested_svm_vmexit(svm);
1292 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1296 down_read(¤t->mm->mmap_sem);
1297 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1298 up_read(¤t->mm->mmap_sem);
1300 if (is_error_page(page)) {
1301 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1303 kvm_release_page_clean(page);
1304 kvm_inject_gp(&svm->vcpu, 0);
1310 static int nested_svm_do(struct vcpu_svm *svm,
1311 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1312 int (*handler)(struct vcpu_svm *svm,
1317 struct page *arg1_page;
1318 struct page *arg2_page = NULL;
1323 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1324 if(arg1_page == NULL)
1328 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1329 if(arg2_page == NULL) {
1330 kvm_release_page_clean(arg1_page);
1335 arg1 = kmap_atomic(arg1_page, KM_USER0);
1337 arg2 = kmap_atomic(arg2_page, KM_USER1);
1339 retval = handler(svm, arg1, arg2, opaque);
1341 kunmap_atomic(arg1, KM_USER0);
1343 kunmap_atomic(arg2, KM_USER1);
1345 kvm_release_page_dirty(arg1_page);
1347 kvm_release_page_dirty(arg2_page);
1352 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1357 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1358 bool kvm_overrides = *(bool *)opaque;
1359 u32 exit_code = svm->vmcb->control.exit_code;
1361 if (kvm_overrides) {
1362 switch (exit_code) {
1366 /* For now we are always handling NPFs when using them */
1371 /* When we're shadowing, trap PFs */
1372 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1381 switch (exit_code) {
1382 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1383 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1384 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1388 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1389 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1390 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1394 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1395 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1396 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1400 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1401 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1402 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1406 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1407 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1408 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1413 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1414 nsvm_printk("exit code: 0x%x\n", exit_code);
1415 if (nested_vmcb->control.intercept & exit_bits)
1423 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1424 void *arg1, void *arg2,
1427 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1428 u8 *msrpm = (u8 *)arg2;
1430 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1431 u32 param = svm->vmcb->control.exit_info_1 & 1;
1433 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1441 case 0xc0000000 ... 0xc0001fff:
1442 t0 = (8192 + msr - 0xc0000000) * 2;
1446 case 0xc0010000 ... 0xc0011fff:
1447 t0 = (16384 + msr - 0xc0010000) * 2;
1455 if (msrpm[t1] & ((1 << param) << t0))
1461 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1463 bool k = kvm_override;
1465 switch (svm->vmcb->control.exit_code) {
1467 return nested_svm_do(svm, svm->nested_vmcb,
1468 svm->nested_vmcb_msrpm, NULL,
1469 nested_svm_exit_handled_msr);
1473 return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1474 nested_svm_exit_handled_real);
1477 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1478 void *arg2, void *opaque)
1480 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1481 struct vmcb *hsave = svm->hsave;
1482 u64 nested_save[] = { nested_vmcb->save.cr0,
1483 nested_vmcb->save.cr3,
1484 nested_vmcb->save.cr4,
1485 nested_vmcb->save.efer,
1486 nested_vmcb->control.intercept_cr_read,
1487 nested_vmcb->control.intercept_cr_write,
1488 nested_vmcb->control.intercept_dr_read,
1489 nested_vmcb->control.intercept_dr_write,
1490 nested_vmcb->control.intercept_exceptions,
1491 nested_vmcb->control.intercept,
1492 nested_vmcb->control.msrpm_base_pa,
1493 nested_vmcb->control.iopm_base_pa,
1494 nested_vmcb->control.tsc_offset };
1496 /* Give the current vmcb to the guest */
1497 memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1498 nested_vmcb->save.cr0 = nested_save[0];
1500 nested_vmcb->save.cr3 = nested_save[1];
1501 nested_vmcb->save.cr4 = nested_save[2];
1502 nested_vmcb->save.efer = nested_save[3];
1503 nested_vmcb->control.intercept_cr_read = nested_save[4];
1504 nested_vmcb->control.intercept_cr_write = nested_save[5];
1505 nested_vmcb->control.intercept_dr_read = nested_save[6];
1506 nested_vmcb->control.intercept_dr_write = nested_save[7];
1507 nested_vmcb->control.intercept_exceptions = nested_save[8];
1508 nested_vmcb->control.intercept = nested_save[9];
1509 nested_vmcb->control.msrpm_base_pa = nested_save[10];
1510 nested_vmcb->control.iopm_base_pa = nested_save[11];
1511 nested_vmcb->control.tsc_offset = nested_save[12];
1513 /* We always set V_INTR_MASKING and remember the old value in hflags */
1514 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1515 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1517 if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1518 (nested_vmcb->control.int_vector)) {
1519 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1520 nested_vmcb->control.int_vector);
1523 /* Restore the original control entries */
1524 svm->vmcb->control = hsave->control;
1526 /* Kill any pending exceptions */
1527 if (svm->vcpu.arch.exception.pending == true)
1528 nsvm_printk("WARNING: Pending Exception\n");
1529 svm->vcpu.arch.exception.pending = false;
1531 /* Restore selected save entries */
1532 svm->vmcb->save.es = hsave->save.es;
1533 svm->vmcb->save.cs = hsave->save.cs;
1534 svm->vmcb->save.ss = hsave->save.ss;
1535 svm->vmcb->save.ds = hsave->save.ds;
1536 svm->vmcb->save.gdtr = hsave->save.gdtr;
1537 svm->vmcb->save.idtr = hsave->save.idtr;
1538 svm->vmcb->save.rflags = hsave->save.rflags;
1539 svm_set_efer(&svm->vcpu, hsave->save.efer);
1540 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1541 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1543 svm->vmcb->save.cr3 = hsave->save.cr3;
1544 svm->vcpu.arch.cr3 = hsave->save.cr3;
1546 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1548 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1549 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1550 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1551 svm->vmcb->save.dr7 = 0;
1552 svm->vmcb->save.cpl = 0;
1553 svm->vmcb->control.exit_int_info = 0;
1555 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1556 /* Exit nested SVM mode */
1557 svm->nested_vmcb = 0;
1562 static int nested_svm_vmexit(struct vcpu_svm *svm)
1564 nsvm_printk("VMexit\n");
1565 if (nested_svm_do(svm, svm->nested_vmcb, 0,
1566 NULL, nested_svm_vmexit_real))
1569 kvm_mmu_reset_context(&svm->vcpu);
1570 kvm_mmu_load(&svm->vcpu);
1575 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1576 void *arg2, void *opaque)
1579 u32 *nested_msrpm = (u32*)arg1;
1580 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1581 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1582 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1587 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1588 void *arg2, void *opaque)
1590 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1591 struct vmcb *hsave = svm->hsave;
1593 /* nested_vmcb is our indicator if nested SVM is activated */
1594 svm->nested_vmcb = svm->vmcb->save.rax;
1596 /* Clear internal status */
1597 svm->vcpu.arch.exception.pending = false;
1599 /* Save the old vmcb, so we don't need to pick what we save, but
1600 can restore everything when a VMEXIT occurs */
1601 memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1602 /* We need to remember the original CR3 in the SPT case */
1604 hsave->save.cr3 = svm->vcpu.arch.cr3;
1605 hsave->save.cr4 = svm->vcpu.arch.cr4;
1606 hsave->save.rip = svm->next_rip;
1608 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1609 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1611 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1613 /* Load the nested guest state */
1614 svm->vmcb->save.es = nested_vmcb->save.es;
1615 svm->vmcb->save.cs = nested_vmcb->save.cs;
1616 svm->vmcb->save.ss = nested_vmcb->save.ss;
1617 svm->vmcb->save.ds = nested_vmcb->save.ds;
1618 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1619 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1620 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1621 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1622 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1623 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1625 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1626 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1628 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1629 kvm_mmu_reset_context(&svm->vcpu);
1631 svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1632 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1633 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1634 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1635 /* In case we don't even reach vcpu_run, the fields are not updated */
1636 svm->vmcb->save.rax = nested_vmcb->save.rax;
1637 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1638 svm->vmcb->save.rip = nested_vmcb->save.rip;
1639 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1640 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1641 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1643 /* We don't want a nested guest to be more powerful than the guest,
1644 so all intercepts are ORed */
1645 svm->vmcb->control.intercept_cr_read |=
1646 nested_vmcb->control.intercept_cr_read;
1647 svm->vmcb->control.intercept_cr_write |=
1648 nested_vmcb->control.intercept_cr_write;
1649 svm->vmcb->control.intercept_dr_read |=
1650 nested_vmcb->control.intercept_dr_read;
1651 svm->vmcb->control.intercept_dr_write |=
1652 nested_vmcb->control.intercept_dr_write;
1653 svm->vmcb->control.intercept_exceptions |=
1654 nested_vmcb->control.intercept_exceptions;
1656 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1658 svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1660 force_new_asid(&svm->vcpu);
1661 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1662 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1663 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1664 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1665 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1666 nested_vmcb->control.int_ctl);
1668 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1669 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1671 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1673 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1674 nested_vmcb->control.exit_int_info,
1675 nested_vmcb->control.int_state);
1677 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1678 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1679 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1680 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1681 nsvm_printk("Injecting Event: 0x%x\n",
1682 nested_vmcb->control.event_inj);
1683 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1684 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1686 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1691 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1693 to_vmcb->save.fs = from_vmcb->save.fs;
1694 to_vmcb->save.gs = from_vmcb->save.gs;
1695 to_vmcb->save.tr = from_vmcb->save.tr;
1696 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1697 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1698 to_vmcb->save.star = from_vmcb->save.star;
1699 to_vmcb->save.lstar = from_vmcb->save.lstar;
1700 to_vmcb->save.cstar = from_vmcb->save.cstar;
1701 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1702 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1703 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1704 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1709 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1710 void *arg2, void *opaque)
1712 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1715 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1716 void *arg2, void *opaque)
1718 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1721 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1723 if (nested_svm_check_permissions(svm))
1726 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1727 skip_emulated_instruction(&svm->vcpu);
1729 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1734 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1736 if (nested_svm_check_permissions(svm))
1739 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1740 skip_emulated_instruction(&svm->vcpu);
1742 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1747 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1749 nsvm_printk("VMrun\n");
1750 if (nested_svm_check_permissions(svm))
1753 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1754 skip_emulated_instruction(&svm->vcpu);
1756 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1757 NULL, nested_svm_vmrun))
1760 if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1761 NULL, nested_svm_vmrun_msrpm))
1767 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1769 if (nested_svm_check_permissions(svm))
1772 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1773 skip_emulated_instruction(&svm->vcpu);
1775 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1780 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1782 if (nested_svm_check_permissions(svm))
1785 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1786 skip_emulated_instruction(&svm->vcpu);
1788 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1790 /* After a CLGI no interrupts should come */
1791 svm_clear_vintr(svm);
1792 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1797 static int invalid_op_interception(struct vcpu_svm *svm,
1798 struct kvm_run *kvm_run)
1800 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1804 static int task_switch_interception(struct vcpu_svm *svm,
1805 struct kvm_run *kvm_run)
1809 int int_type = svm->vmcb->control.exit_int_info &
1810 SVM_EXITINTINFO_TYPE_MASK;
1811 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1813 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1815 if (svm->vmcb->control.exit_info_2 &
1816 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1817 reason = TASK_SWITCH_IRET;
1818 else if (svm->vmcb->control.exit_info_2 &
1819 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1820 reason = TASK_SWITCH_JMP;
1821 else if (svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID)
1822 reason = TASK_SWITCH_GATE;
1824 reason = TASK_SWITCH_CALL;
1827 if (reason != TASK_SWITCH_GATE ||
1828 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1829 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1830 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
1831 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0,
1832 EMULTYPE_SKIP) != EMULATE_DONE)
1836 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
1839 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1841 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1842 kvm_emulate_cpuid(&svm->vcpu);
1846 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1848 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1849 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1853 static int emulate_on_interception(struct vcpu_svm *svm,
1854 struct kvm_run *kvm_run)
1856 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1857 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1861 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1863 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
1864 /* instruction emulation calls kvm_set_cr8() */
1865 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1866 if (irqchip_in_kernel(svm->vcpu.kvm))
1868 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
1870 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1874 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1876 struct vcpu_svm *svm = to_svm(vcpu);
1879 case MSR_IA32_TIME_STAMP_COUNTER: {
1883 *data = svm->vmcb->control.tsc_offset + tsc;
1887 *data = svm->vmcb->save.star;
1889 #ifdef CONFIG_X86_64
1891 *data = svm->vmcb->save.lstar;
1894 *data = svm->vmcb->save.cstar;
1896 case MSR_KERNEL_GS_BASE:
1897 *data = svm->vmcb->save.kernel_gs_base;
1899 case MSR_SYSCALL_MASK:
1900 *data = svm->vmcb->save.sfmask;
1903 case MSR_IA32_SYSENTER_CS:
1904 *data = svm->vmcb->save.sysenter_cs;
1906 case MSR_IA32_SYSENTER_EIP:
1907 *data = svm->vmcb->save.sysenter_eip;
1909 case MSR_IA32_SYSENTER_ESP:
1910 *data = svm->vmcb->save.sysenter_esp;
1912 /* Nobody will change the following 5 values in the VMCB so
1913 we can safely return them on rdmsr. They will always be 0
1914 until LBRV is implemented. */
1915 case MSR_IA32_DEBUGCTLMSR:
1916 *data = svm->vmcb->save.dbgctl;
1918 case MSR_IA32_LASTBRANCHFROMIP:
1919 *data = svm->vmcb->save.br_from;
1921 case MSR_IA32_LASTBRANCHTOIP:
1922 *data = svm->vmcb->save.br_to;
1924 case MSR_IA32_LASTINTFROMIP:
1925 *data = svm->vmcb->save.last_excp_from;
1927 case MSR_IA32_LASTINTTOIP:
1928 *data = svm->vmcb->save.last_excp_to;
1930 case MSR_VM_HSAVE_PA:
1931 *data = svm->hsave_msr;
1936 case MSR_IA32_UCODE_REV:
1940 return kvm_get_msr_common(vcpu, ecx, data);
1945 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1947 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1950 if (svm_get_msr(&svm->vcpu, ecx, &data))
1951 kvm_inject_gp(&svm->vcpu, 0);
1953 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1954 (u32)(data >> 32), handler);
1956 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1957 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1958 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1959 skip_emulated_instruction(&svm->vcpu);
1964 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1966 struct vcpu_svm *svm = to_svm(vcpu);
1969 case MSR_IA32_TIME_STAMP_COUNTER: {
1973 svm->vmcb->control.tsc_offset = data - tsc;
1977 svm->vmcb->save.star = data;
1979 #ifdef CONFIG_X86_64
1981 svm->vmcb->save.lstar = data;
1984 svm->vmcb->save.cstar = data;
1986 case MSR_KERNEL_GS_BASE:
1987 svm->vmcb->save.kernel_gs_base = data;
1989 case MSR_SYSCALL_MASK:
1990 svm->vmcb->save.sfmask = data;
1993 case MSR_IA32_SYSENTER_CS:
1994 svm->vmcb->save.sysenter_cs = data;
1996 case MSR_IA32_SYSENTER_EIP:
1997 svm->vmcb->save.sysenter_eip = data;
1999 case MSR_IA32_SYSENTER_ESP:
2000 svm->vmcb->save.sysenter_esp = data;
2002 case MSR_IA32_DEBUGCTLMSR:
2003 if (!svm_has(SVM_FEATURE_LBRV)) {
2004 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2008 if (data & DEBUGCTL_RESERVED_BITS)
2011 svm->vmcb->save.dbgctl = data;
2012 if (data & (1ULL<<0))
2013 svm_enable_lbrv(svm);
2015 svm_disable_lbrv(svm);
2017 case MSR_K7_EVNTSEL0:
2018 case MSR_K7_EVNTSEL1:
2019 case MSR_K7_EVNTSEL2:
2020 case MSR_K7_EVNTSEL3:
2021 case MSR_K7_PERFCTR0:
2022 case MSR_K7_PERFCTR1:
2023 case MSR_K7_PERFCTR2:
2024 case MSR_K7_PERFCTR3:
2026 * Just discard all writes to the performance counters; this
2027 * should keep both older linux and windows 64-bit guests
2030 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2033 case MSR_VM_HSAVE_PA:
2034 svm->hsave_msr = data;
2037 return kvm_set_msr_common(vcpu, ecx, data);
2042 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2044 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2045 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2046 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2048 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2051 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2052 if (svm_set_msr(&svm->vcpu, ecx, data))
2053 kvm_inject_gp(&svm->vcpu, 0);
2055 skip_emulated_instruction(&svm->vcpu);
2059 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2061 if (svm->vmcb->control.exit_info_1)
2062 return wrmsr_interception(svm, kvm_run);
2064 return rdmsr_interception(svm, kvm_run);
2067 static int interrupt_window_interception(struct vcpu_svm *svm,
2068 struct kvm_run *kvm_run)
2070 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2072 svm_clear_vintr(svm);
2073 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2075 * If the user space waits to inject interrupts, exit as soon as
2078 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2079 kvm_run->request_interrupt_window &&
2080 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2081 ++svm->vcpu.stat.irq_window_exits;
2082 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2089 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2090 struct kvm_run *kvm_run) = {
2091 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2092 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2093 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2094 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2096 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2097 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2098 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2099 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2100 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2101 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2102 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2103 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2104 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2105 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2106 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2107 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2108 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2109 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2110 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2111 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2112 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2113 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2114 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2115 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2116 [SVM_EXIT_INTR] = intr_interception,
2117 [SVM_EXIT_NMI] = nmi_interception,
2118 [SVM_EXIT_SMI] = nop_on_interception,
2119 [SVM_EXIT_INIT] = nop_on_interception,
2120 [SVM_EXIT_VINTR] = interrupt_window_interception,
2121 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2122 [SVM_EXIT_CPUID] = cpuid_interception,
2123 [SVM_EXIT_INVD] = emulate_on_interception,
2124 [SVM_EXIT_HLT] = halt_interception,
2125 [SVM_EXIT_INVLPG] = invlpg_interception,
2126 [SVM_EXIT_INVLPGA] = invalid_op_interception,
2127 [SVM_EXIT_IOIO] = io_interception,
2128 [SVM_EXIT_MSR] = msr_interception,
2129 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2130 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2131 [SVM_EXIT_VMRUN] = vmrun_interception,
2132 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2133 [SVM_EXIT_VMLOAD] = vmload_interception,
2134 [SVM_EXIT_VMSAVE] = vmsave_interception,
2135 [SVM_EXIT_STGI] = stgi_interception,
2136 [SVM_EXIT_CLGI] = clgi_interception,
2137 [SVM_EXIT_SKINIT] = invalid_op_interception,
2138 [SVM_EXIT_WBINVD] = emulate_on_interception,
2139 [SVM_EXIT_MONITOR] = invalid_op_interception,
2140 [SVM_EXIT_MWAIT] = invalid_op_interception,
2141 [SVM_EXIT_NPF] = pf_interception,
2144 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2146 struct vcpu_svm *svm = to_svm(vcpu);
2147 u32 exit_code = svm->vmcb->control.exit_code;
2149 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2150 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2152 if (is_nested(svm)) {
2153 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2154 exit_code, svm->vmcb->control.exit_info_1,
2155 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2156 if (nested_svm_exit_handled(svm, true)) {
2157 nested_svm_vmexit(svm);
2158 nsvm_printk("-> #VMEXIT\n");
2165 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2166 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2169 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2170 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2171 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2172 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2173 kvm_inject_gp(vcpu, 0);
2178 kvm_mmu_reset_context(vcpu);
2184 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2185 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2186 kvm_run->fail_entry.hardware_entry_failure_reason
2187 = svm->vmcb->control.exit_code;
2191 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2192 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2193 exit_code != SVM_EXIT_NPF)
2194 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2196 __func__, svm->vmcb->control.exit_int_info,
2199 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2200 || !svm_exit_handlers[exit_code]) {
2201 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2202 kvm_run->hw.hardware_exit_reason = exit_code;
2206 return svm_exit_handlers[exit_code](svm, kvm_run);
2209 static void reload_tss(struct kvm_vcpu *vcpu)
2211 int cpu = raw_smp_processor_id();
2213 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2214 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2218 static void pre_svm_run(struct vcpu_svm *svm)
2220 int cpu = raw_smp_processor_id();
2222 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2224 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2225 if (svm->vcpu.cpu != cpu ||
2226 svm->asid_generation != svm_data->asid_generation)
2227 new_asid(svm, svm_data);
2231 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2233 struct vmcb_control_area *control;
2235 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2237 ++svm->vcpu.stat.irq_injections;
2238 control = &svm->vmcb->control;
2239 control->int_vector = irq;
2240 control->int_ctl &= ~V_INTR_PRIO_MASK;
2241 control->int_ctl |= V_IRQ_MASK |
2242 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2245 static void svm_queue_irq(struct vcpu_svm *svm, unsigned nr)
2247 svm->vmcb->control.event_inj = nr |
2248 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2251 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2253 struct vcpu_svm *svm = to_svm(vcpu);
2255 nested_svm_intr(svm);
2257 svm_queue_irq(svm, irq);
2260 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
2262 struct vcpu_svm *svm = to_svm(vcpu);
2263 struct vmcb *vmcb = svm->vmcb;
2266 if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
2269 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2271 max_irr = kvm_lapic_find_highest_irr(vcpu);
2275 tpr = kvm_lapic_get_cr8(vcpu) << 4;
2277 if (tpr >= (max_irr & 0xf0))
2278 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2281 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2283 struct vcpu_svm *svm = to_svm(vcpu);
2284 struct vmcb *vmcb = svm->vmcb;
2285 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2286 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2287 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2290 static void enable_irq_window(struct kvm_vcpu *vcpu)
2292 svm_set_vintr(to_svm(vcpu));
2293 svm_inject_irq(to_svm(vcpu), 0x0);
2296 static void svm_intr_inject(struct kvm_vcpu *vcpu)
2298 /* try to reinject previous events if any */
2299 if (vcpu->arch.interrupt.pending) {
2300 svm_queue_irq(to_svm(vcpu), vcpu->arch.interrupt.nr);
2304 /* try to inject new event if pending */
2305 if (kvm_cpu_has_interrupt(vcpu)) {
2306 if (svm_interrupt_allowed(vcpu)) {
2307 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
2308 svm_queue_irq(to_svm(vcpu), vcpu->arch.interrupt.nr);
2313 static void svm_intr_assist(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2315 struct vcpu_svm *svm = to_svm(vcpu);
2316 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
2317 kvm_run->request_interrupt_window;
2319 if (nested_svm_intr(svm))
2322 svm_intr_inject(vcpu);
2324 if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
2325 enable_irq_window(vcpu);
2328 update_cr8_intercept(vcpu);
2331 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2336 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2338 force_new_asid(vcpu);
2341 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2345 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2347 struct vcpu_svm *svm = to_svm(vcpu);
2349 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2350 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2351 kvm_set_cr8(vcpu, cr8);
2355 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2357 struct vcpu_svm *svm = to_svm(vcpu);
2360 cr8 = kvm_get_cr8(vcpu);
2361 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2362 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2365 static void svm_complete_interrupts(struct vcpu_svm *svm)
2369 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2371 svm->vcpu.arch.nmi_injected = false;
2372 kvm_clear_exception_queue(&svm->vcpu);
2373 kvm_clear_interrupt_queue(&svm->vcpu);
2375 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2378 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2379 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2382 case SVM_EXITINTINFO_TYPE_NMI:
2383 svm->vcpu.arch.nmi_injected = true;
2385 case SVM_EXITINTINFO_TYPE_EXEPT:
2386 /* In case of software exception do not reinject an exception
2387 vector, but re-execute and instruction instead */
2388 if (vector == BP_VECTOR || vector == OF_VECTOR)
2390 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2391 u32 err = svm->vmcb->control.exit_int_info_err;
2392 kvm_queue_exception_e(&svm->vcpu, vector, err);
2395 kvm_queue_exception(&svm->vcpu, vector);
2397 case SVM_EXITINTINFO_TYPE_INTR:
2398 kvm_queue_interrupt(&svm->vcpu, vector);
2405 #ifdef CONFIG_X86_64
2411 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2413 struct vcpu_svm *svm = to_svm(vcpu);
2418 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2419 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2420 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2424 sync_lapic_to_cr8(vcpu);
2426 save_host_msrs(vcpu);
2427 fs_selector = kvm_read_fs();
2428 gs_selector = kvm_read_gs();
2429 ldt_selector = kvm_read_ldt();
2430 svm->host_cr2 = kvm_read_cr2();
2431 if (!is_nested(svm))
2432 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2433 /* required for live migration with NPT */
2435 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2442 "push %%"R"bp; \n\t"
2443 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2444 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2445 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2446 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2447 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2448 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2449 #ifdef CONFIG_X86_64
2450 "mov %c[r8](%[svm]), %%r8 \n\t"
2451 "mov %c[r9](%[svm]), %%r9 \n\t"
2452 "mov %c[r10](%[svm]), %%r10 \n\t"
2453 "mov %c[r11](%[svm]), %%r11 \n\t"
2454 "mov %c[r12](%[svm]), %%r12 \n\t"
2455 "mov %c[r13](%[svm]), %%r13 \n\t"
2456 "mov %c[r14](%[svm]), %%r14 \n\t"
2457 "mov %c[r15](%[svm]), %%r15 \n\t"
2460 /* Enter guest mode */
2462 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2463 __ex(SVM_VMLOAD) "\n\t"
2464 __ex(SVM_VMRUN) "\n\t"
2465 __ex(SVM_VMSAVE) "\n\t"
2468 /* Save guest registers, load host registers */
2469 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2470 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2471 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2472 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2473 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2474 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2475 #ifdef CONFIG_X86_64
2476 "mov %%r8, %c[r8](%[svm]) \n\t"
2477 "mov %%r9, %c[r9](%[svm]) \n\t"
2478 "mov %%r10, %c[r10](%[svm]) \n\t"
2479 "mov %%r11, %c[r11](%[svm]) \n\t"
2480 "mov %%r12, %c[r12](%[svm]) \n\t"
2481 "mov %%r13, %c[r13](%[svm]) \n\t"
2482 "mov %%r14, %c[r14](%[svm]) \n\t"
2483 "mov %%r15, %c[r15](%[svm]) \n\t"
2488 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2489 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2490 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2491 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2492 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2493 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2494 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2495 #ifdef CONFIG_X86_64
2496 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2497 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2498 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2499 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2500 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2501 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2502 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2503 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2506 , R"bx", R"cx", R"dx", R"si", R"di"
2507 #ifdef CONFIG_X86_64
2508 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2512 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2513 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2514 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2515 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2517 kvm_write_cr2(svm->host_cr2);
2519 kvm_load_fs(fs_selector);
2520 kvm_load_gs(gs_selector);
2521 kvm_load_ldt(ldt_selector);
2522 load_host_msrs(vcpu);
2526 local_irq_disable();
2530 sync_cr8_to_lapic(vcpu);
2534 svm_complete_interrupts(svm);
2539 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2541 struct vcpu_svm *svm = to_svm(vcpu);
2544 svm->vmcb->control.nested_cr3 = root;
2545 force_new_asid(vcpu);
2549 svm->vmcb->save.cr3 = root;
2550 force_new_asid(vcpu);
2552 if (vcpu->fpu_active) {
2553 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2554 svm->vmcb->save.cr0 |= X86_CR0_TS;
2555 vcpu->fpu_active = 0;
2559 static int is_disabled(void)
2563 rdmsrl(MSR_VM_CR, vm_cr);
2564 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2571 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2574 * Patch in the VMMCALL instruction:
2576 hypercall[0] = 0x0f;
2577 hypercall[1] = 0x01;
2578 hypercall[2] = 0xd9;
2581 static void svm_check_processor_compat(void *rtn)
2586 static bool svm_cpu_has_accelerated_tpr(void)
2591 static int get_npt_level(void)
2593 #ifdef CONFIG_X86_64
2594 return PT64_ROOT_LEVEL;
2596 return PT32E_ROOT_LEVEL;
2600 static int svm_get_mt_mask_shift(void)
2605 static struct kvm_x86_ops svm_x86_ops = {
2606 .cpu_has_kvm_support = has_svm,
2607 .disabled_by_bios = is_disabled,
2608 .hardware_setup = svm_hardware_setup,
2609 .hardware_unsetup = svm_hardware_unsetup,
2610 .check_processor_compatibility = svm_check_processor_compat,
2611 .hardware_enable = svm_hardware_enable,
2612 .hardware_disable = svm_hardware_disable,
2613 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2615 .vcpu_create = svm_create_vcpu,
2616 .vcpu_free = svm_free_vcpu,
2617 .vcpu_reset = svm_vcpu_reset,
2619 .prepare_guest_switch = svm_prepare_guest_switch,
2620 .vcpu_load = svm_vcpu_load,
2621 .vcpu_put = svm_vcpu_put,
2623 .set_guest_debug = svm_guest_debug,
2624 .get_msr = svm_get_msr,
2625 .set_msr = svm_set_msr,
2626 .get_segment_base = svm_get_segment_base,
2627 .get_segment = svm_get_segment,
2628 .set_segment = svm_set_segment,
2629 .get_cpl = svm_get_cpl,
2630 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2631 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2632 .set_cr0 = svm_set_cr0,
2633 .set_cr3 = svm_set_cr3,
2634 .set_cr4 = svm_set_cr4,
2635 .set_efer = svm_set_efer,
2636 .get_idt = svm_get_idt,
2637 .set_idt = svm_set_idt,
2638 .get_gdt = svm_get_gdt,
2639 .set_gdt = svm_set_gdt,
2640 .get_dr = svm_get_dr,
2641 .set_dr = svm_set_dr,
2642 .get_rflags = svm_get_rflags,
2643 .set_rflags = svm_set_rflags,
2645 .tlb_flush = svm_flush_tlb,
2647 .run = svm_vcpu_run,
2648 .handle_exit = handle_exit,
2649 .skip_emulated_instruction = skip_emulated_instruction,
2650 .patch_hypercall = svm_patch_hypercall,
2651 .get_irq = svm_get_irq,
2652 .set_irq = svm_set_irq,
2653 .queue_exception = svm_queue_exception,
2654 .inject_pending_irq = svm_intr_assist,
2655 .interrupt_allowed = svm_interrupt_allowed,
2657 .set_tss_addr = svm_set_tss_addr,
2658 .get_tdp_level = get_npt_level,
2659 .get_mt_mask_shift = svm_get_mt_mask_shift,
2662 static int __init svm_init(void)
2664 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2668 static void __exit svm_exit(void)
2673 module_init(svm_init)
2674 module_exit(svm_exit)