arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34 #include <asm/kvm_para.h>
  35
  36 #include <asm/virtext.h>
  37 #include "trace.h"
  38
  39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  40
  41 MODULE_AUTHOR("Qumranet");
  42 MODULE_LICENSE("GPL");
  43
  44 #define IOPM_ALLOC_ORDER 2
  45 #define MSRPM_ALLOC_ORDER 1
  46
  47 #define SEG_TYPE_LDT 2
  48 #define SEG_TYPE_BUSY_TSS16 3
  49
  50 #define SVM_FEATURE_NPT            (1 <<  0)
  51 #define SVM_FEATURE_LBRV           (1 <<  1)
  52 #define SVM_FEATURE_SVML           (1 <<  2)
  53 #define SVM_FEATURE_NRIP           (1 <<  3)
  54 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  55 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  56 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  57 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  58 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  59
  60 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  61 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  62 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  63
  64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  65
  66 static bool erratum_383_found __read_mostly;
  67
  68 static const u32 host_save_user_msrs[] = {
  69 #ifdef CONFIG_X86_64
  70         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  71         MSR_FS_BASE,
  72 #endif
  73         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  74 };
  75
  76 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  77
  78 struct kvm_vcpu;
  79
  80 struct nested_state {
  81         struct vmcb *hsave;
  82         u64 hsave_msr;
  83         u64 vm_cr_msr;
  84         u64 vmcb;
  85
  86         /* These are the merged vectors */
  87         u32 *msrpm;
  88
  89         /* gpa pointers to the real vectors */
  90         u64 vmcb_msrpm;
  91         u64 vmcb_iopm;
  92
  93         /* A VMEXIT is required but not yet emulated */
  94         bool exit_required;
  95
  96         /*
  97          * If we vmexit during an instruction emulation we need this to restore
  98          * the l1 guest rip after the emulation
  99          */
 100         unsigned long vmexit_rip;
 101         unsigned long vmexit_rsp;
 102         unsigned long vmexit_rax;
 103
 104         /* cache for intercepts of the guest */
 105         u32 intercept_cr;
 106         u32 intercept_dr;
 107         u32 intercept_exceptions;
 108         u64 intercept;
 109
 110         /* Nested Paging related state */
 111         u64 nested_cr3;
 112 };
 113
 114 #define MSRPM_OFFSETS   16
 115 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 116
 117 struct vcpu_svm {
 118         struct kvm_vcpu vcpu;
 119         struct vmcb *vmcb;
 120         unsigned long vmcb_pa;
 121         struct svm_cpu_data *svm_data;
 122         uint64_t asid_generation;
 123         uint64_t sysenter_esp;
 124         uint64_t sysenter_eip;
 125
 126         u64 next_rip;
 127
 128         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 129         struct {
 130                 u16 fs;
 131                 u16 gs;
 132                 u16 ldt;
 133                 u64 gs_base;
 134         } host;
 135
 136         u32 *msrpm;
 137
 138         struct nested_state nested;
 139
 140         bool nmi_singlestep;
 141
 142         unsigned int3_injected;
 143         unsigned long int3_rip;
 144         u32 apf_reason;
 145 };
 146
 147 #define MSR_INVALID                     0xffffffffU
 148
 149 static struct svm_direct_access_msrs {
 150         u32 index;   /* Index of the MSR */
 151         bool always; /* True if intercept is always on */
 152 } direct_access_msrs[] = {
 153         { .index = MSR_STAR,                            .always = true  },
 154         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 155 #ifdef CONFIG_X86_64
 156         { .index = MSR_GS_BASE,                         .always = true  },
 157         { .index = MSR_FS_BASE,                         .always = true  },
 158         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 159         { .index = MSR_LSTAR,                           .always = true  },
 160         { .index = MSR_CSTAR,                           .always = true  },
 161         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 162 #endif
 163         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 164         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 165         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 166         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 167         { .index = MSR_INVALID,                         .always = false },
 168 };
 169
 170 /* enable NPT for AMD64 and X86 with PAE */
 171 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 172 static bool npt_enabled = true;
 173 #else
 174 static bool npt_enabled;
 175 #endif
 176 static int npt = 1;
 177
 178 module_param(npt, int, S_IRUGO);
 179
 180 static int nested = 1;
 181 module_param(nested, int, S_IRUGO);
 182
 183 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 184 static void svm_complete_interrupts(struct vcpu_svm *svm);
 185
 186 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 187 static int nested_svm_intercept(struct vcpu_svm *svm);
 188 static int nested_svm_vmexit(struct vcpu_svm *svm);
 189 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 190                                       bool has_error_code, u32 error_code);
 191
 192 enum {
 193         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 194                             pause filter count */
 195         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 196         VMCB_ASID,       /* ASID */
 197         VMCB_INTR,       /* int_ctl, int_vector */
 198         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 199         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 200         VMCB_DR,         /* DR6, DR7 */
 201         VMCB_DT,         /* GDT, IDT */
 202         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 203         VMCB_CR2,        /* CR2 only */
 204         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 205         VMCB_DIRTY_MAX,
 206 };
 207
 208 /* TPR and CR2 are always written before VMRUN */
 209 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 210
 211 static inline void mark_all_dirty(struct vmcb *vmcb)
 212 {
 213         vmcb->control.clean = 0;
 214 }
 215
 216 static inline void mark_all_clean(struct vmcb *vmcb)
 217 {
 218         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 219                                & ~VMCB_ALWAYS_DIRTY_MASK;
 220 }
 221
 222 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 223 {
 224         vmcb->control.clean &= ~(1 << bit);
 225 }
 226
 227 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 228 {
 229         return container_of(vcpu, struct vcpu_svm, vcpu);
 230 }
 231
 232 static void recalc_intercepts(struct vcpu_svm *svm)
 233 {
 234         struct vmcb_control_area *c, *h;
 235         struct nested_state *g;
 236
 237         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 238
 239         if (!is_guest_mode(&svm->vcpu))
 240                 return;
 241
 242         c = &svm->vmcb->control;
 243         h = &svm->nested.hsave->control;
 244         g = &svm->nested;
 245
 246         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 247         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 248         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 249         c->intercept = h->intercept | g->intercept;
 250 }
 251
 252 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 253 {
 254         if (is_guest_mode(&svm->vcpu))
 255                 return svm->nested.hsave;
 256         else
 257                 return svm->vmcb;
 258 }
 259
 260 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 261 {
 262         struct vmcb *vmcb = get_host_vmcb(svm);
 263
 264         vmcb->control.intercept_cr |= (1U << bit);
 265
 266         recalc_intercepts(svm);
 267 }
 268
 269 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 270 {
 271         struct vmcb *vmcb = get_host_vmcb(svm);
 272
 273         vmcb->control.intercept_cr &= ~(1U << bit);
 274
 275         recalc_intercepts(svm);
 276 }
 277
 278 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 279 {
 280         struct vmcb *vmcb = get_host_vmcb(svm);
 281
 282         return vmcb->control.intercept_cr & (1U << bit);
 283 }
 284
 285 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
 286 {
 287         struct vmcb *vmcb = get_host_vmcb(svm);
 288
 289         vmcb->control.intercept_dr |= (1U << bit);
 290
 291         recalc_intercepts(svm);
 292 }
 293
 294 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
 295 {
 296         struct vmcb *vmcb = get_host_vmcb(svm);
 297
 298         vmcb->control.intercept_dr &= ~(1U << bit);
 299
 300         recalc_intercepts(svm);
 301 }
 302
 303 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 304 {
 305         struct vmcb *vmcb = get_host_vmcb(svm);
 306
 307         vmcb->control.intercept_exceptions |= (1U << bit);
 308
 309         recalc_intercepts(svm);
 310 }
 311
 312 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 313 {
 314         struct vmcb *vmcb = get_host_vmcb(svm);
 315
 316         vmcb->control.intercept_exceptions &= ~(1U << bit);
 317
 318         recalc_intercepts(svm);
 319 }
 320
 321 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 322 {
 323         struct vmcb *vmcb = get_host_vmcb(svm);
 324
 325         vmcb->control.intercept |= (1ULL << bit);
 326
 327         recalc_intercepts(svm);
 328 }
 329
 330 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 331 {
 332         struct vmcb *vmcb = get_host_vmcb(svm);
 333
 334         vmcb->control.intercept &= ~(1ULL << bit);
 335
 336         recalc_intercepts(svm);
 337 }
 338
 339 static inline void enable_gif(struct vcpu_svm *svm)
 340 {
 341         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 342 }
 343
 344 static inline void disable_gif(struct vcpu_svm *svm)
 345 {
 346         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 347 }
 348
 349 static inline bool gif_set(struct vcpu_svm *svm)
 350 {
 351         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 352 }
 353
 354 static unsigned long iopm_base;
 355
 356 struct kvm_ldttss_desc {
 357         u16 limit0;
 358         u16 base0;
 359         unsigned base1:8, type:5, dpl:2, p:1;
 360         unsigned limit1:4, zero0:3, g:1, base2:8;
 361         u32 base3;
 362         u32 zero1;
 363 } __attribute__((packed));
 364
 365 struct svm_cpu_data {
 366         int cpu;
 367
 368         u64 asid_generation;
 369         u32 max_asid;
 370         u32 next_asid;
 371         struct kvm_ldttss_desc *tss_desc;
 372
 373         struct page *save_area;
 374 };
 375
 376 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 377 static uint32_t svm_features;
 378
 379 struct svm_init_data {
 380         int cpu;
 381         int r;
 382 };
 383
 384 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 385
 386 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 387 #define MSRS_RANGE_SIZE 2048
 388 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 389
 390 static u32 svm_msrpm_offset(u32 msr)
 391 {
 392         u32 offset;
 393         int i;
 394
 395         for (i = 0; i < NUM_MSR_MAPS; i++) {
 396                 if (msr < msrpm_ranges[i] ||
 397                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 398                         continue;
 399
 400                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 401                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 402
 403                 /* Now we have the u8 offset - but need the u32 offset */
 404                 return offset / 4;
 405         }
 406
 407         /* MSR not in any range */
 408         return MSR_INVALID;
 409 }
 410
 411 #define MAX_INST_SIZE 15
 412
 413 static inline void clgi(void)
 414 {
 415         asm volatile (__ex(SVM_CLGI));
 416 }
 417
 418 static inline void stgi(void)
 419 {
 420         asm volatile (__ex(SVM_STGI));
 421 }
 422
 423 static inline void invlpga(unsigned long addr, u32 asid)
 424 {
 425         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 426 }
 427
 428 static int get_npt_level(void)
 429 {
 430 #ifdef CONFIG_X86_64
 431         return PT64_ROOT_LEVEL;
 432 #else
 433         return PT32E_ROOT_LEVEL;
 434 #endif
 435 }
 436
 437 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 438 {
 439         vcpu->arch.efer = efer;
 440         if (!npt_enabled && !(efer & EFER_LMA))
 441                 efer &= ~EFER_LME;
 442
 443         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 444         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 445 }
 446
 447 static int is_external_interrupt(u32 info)
 448 {
 449         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 450         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 451 }
 452
 453 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 454 {
 455         struct vcpu_svm *svm = to_svm(vcpu);
 456         u32 ret = 0;
 457
 458         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 459                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 460         return ret & mask;
 461 }
 462
 463 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 464 {
 465         struct vcpu_svm *svm = to_svm(vcpu);
 466
 467         if (mask == 0)
 468                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 469         else
 470                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 471
 472 }
 473
 474 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 475 {
 476         struct vcpu_svm *svm = to_svm(vcpu);
 477
 478         if (svm->vmcb->control.next_rip != 0)
 479                 svm->next_rip = svm->vmcb->control.next_rip;
 480
 481         if (!svm->next_rip) {
 482                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 483                                 EMULATE_DONE)
 484                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 485                 return;
 486         }
 487         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 488                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 489                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 490
 491         kvm_rip_write(vcpu, svm->next_rip);
 492         svm_set_interrupt_shadow(vcpu, 0);
 493 }
 494
 495 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 496                                 bool has_error_code, u32 error_code,
 497                                 bool reinject)
 498 {
 499         struct vcpu_svm *svm = to_svm(vcpu);
 500
 501         /*
 502          * If we are within a nested VM we'd better #VMEXIT and let the guest
 503          * handle the exception
 504          */
 505         if (!reinject &&
 506             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 507                 return;
 508
 509         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 510                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 511
 512                 /*
 513                  * For guest debugging where we have to reinject #BP if some
 514                  * INT3 is guest-owned:
 515                  * Emulate nRIP by moving RIP forward. Will fail if injection
 516                  * raises a fault that is not intercepted. Still better than
 517                  * failing in all cases.
 518                  */
 519                 skip_emulated_instruction(&svm->vcpu);
 520                 rip = kvm_rip_read(&svm->vcpu);
 521                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 522                 svm->int3_injected = rip - old_rip;
 523         }
 524
 525         svm->vmcb->control.event_inj = nr
 526                 | SVM_EVTINJ_VALID
 527                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 528                 | SVM_EVTINJ_TYPE_EXEPT;
 529         svm->vmcb->control.event_inj_err = error_code;
 530 }
 531
 532 static void svm_init_erratum_383(void)
 533 {
 534         u32 low, high;
 535         int err;
 536         u64 val;
 537
 538         if (!cpu_has_amd_erratum(amd_erratum_383))
 539                 return;
 540
 541         /* Use _safe variants to not break nested virtualization */
 542         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 543         if (err)
 544                 return;
 545
 546         val |= (1ULL << 47);
 547
 548         low  = lower_32_bits(val);
 549         high = upper_32_bits(val);
 550
 551         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 552
 553         erratum_383_found = true;
 554 }
 555
 556 static int has_svm(void)
 557 {
 558         const char *msg;
 559
 560         if (!cpu_has_svm(&msg)) {
 561                 printk(KERN_INFO "has_svm: %s\n", msg);
 562                 return 0;
 563         }
 564
 565         return 1;
 566 }
 567
 568 static void svm_hardware_disable(void *garbage)
 569 {
 570         cpu_svm_disable();
 571 }
 572
 573 static int svm_hardware_enable(void *garbage)
 574 {
 575
 576         struct svm_cpu_data *sd;
 577         uint64_t efer;
 578         struct desc_ptr gdt_descr;
 579         struct desc_struct *gdt;
 580         int me = raw_smp_processor_id();
 581
 582         rdmsrl(MSR_EFER, efer);
 583         if (efer & EFER_SVME)
 584                 return -EBUSY;
 585
 586         if (!has_svm()) {
 587                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 588                        me);
 589                 return -EINVAL;
 590         }
 591         sd = per_cpu(svm_data, me);
 592
 593         if (!sd) {
 594                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 595                        me);
 596                 return -EINVAL;
 597         }
 598
 599         sd->asid_generation = 1;
 600         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 601         sd->next_asid = sd->max_asid + 1;
 602
 603         native_store_gdt(&gdt_descr);
 604         gdt = (struct desc_struct *)gdt_descr.address;
 605         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 606
 607         wrmsrl(MSR_EFER, efer | EFER_SVME);
 608
 609         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 610
 611         svm_init_erratum_383();
 612
 613         return 0;
 614 }
 615
 616 static void svm_cpu_uninit(int cpu)
 617 {
 618         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 619
 620         if (!sd)
 621                 return;
 622
 623         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 624         __free_page(sd->save_area);
 625         kfree(sd);
 626 }
 627
 628 static int svm_cpu_init(int cpu)
 629 {
 630         struct svm_cpu_data *sd;
 631         int r;
 632
 633         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 634         if (!sd)
 635                 return -ENOMEM;
 636         sd->cpu = cpu;
 637         sd->save_area = alloc_page(GFP_KERNEL);
 638         r = -ENOMEM;
 639         if (!sd->save_area)
 640                 goto err_1;
 641
 642         per_cpu(svm_data, cpu) = sd;
 643
 644         return 0;
 645
 646 err_1:
 647         kfree(sd);
 648         return r;
 649
 650 }
 651
 652 static bool valid_msr_intercept(u32 index)
 653 {
 654         int i;
 655
 656         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 657                 if (direct_access_msrs[i].index == index)
 658                         return true;
 659
 660         return false;
 661 }
 662
 663 static void set_msr_interception(u32 *msrpm, unsigned msr,
 664                                  int read, int write)
 665 {
 666         u8 bit_read, bit_write;
 667         unsigned long tmp;
 668         u32 offset;
 669
 670         /*
 671          * If this warning triggers extend the direct_access_msrs list at the
 672          * beginning of the file
 673          */
 674         WARN_ON(!valid_msr_intercept(msr));
 675
 676         offset    = svm_msrpm_offset(msr);
 677         bit_read  = 2 * (msr & 0x0f);
 678         bit_write = 2 * (msr & 0x0f) + 1;
 679         tmp       = msrpm[offset];
 680
 681         BUG_ON(offset == MSR_INVALID);
 682
 683         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 684         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 685
 686         msrpm[offset] = tmp;
 687 }
 688
 689 static void svm_vcpu_init_msrpm(u32 *msrpm)
 690 {
 691         int i;
 692
 693         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 694
 695         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 696                 if (!direct_access_msrs[i].always)
 697                         continue;
 698
 699                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 700         }
 701 }
 702
 703 static void add_msr_offset(u32 offset)
 704 {
 705         int i;
 706
 707         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 708
 709                 /* Offset already in list? */
 710                 if (msrpm_offsets[i] == offset)
 711                         return;
 712
 713                 /* Slot used by another offset? */
 714                 if (msrpm_offsets[i] != MSR_INVALID)
 715                         continue;
 716
 717                 /* Add offset to list */
 718                 msrpm_offsets[i] = offset;
 719
 720                 return;
 721         }
 722
 723         /*
 724          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 725          * increase MSRPM_OFFSETS in this case.
 726          */
 727         BUG();
 728 }
 729
 730 static void init_msrpm_offsets(void)
 731 {
 732         int i;
 733
 734         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 735
 736         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 737                 u32 offset;
 738
 739                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 740                 BUG_ON(offset == MSR_INVALID);
 741
 742                 add_msr_offset(offset);
 743         }
 744 }
 745
 746 static void svm_enable_lbrv(struct vcpu_svm *svm)
 747 {
 748         u32 *msrpm = svm->msrpm;
 749
 750         svm->vmcb->control.lbr_ctl = 1;
 751         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 752         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 753         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 754         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 755 }
 756
 757 static void svm_disable_lbrv(struct vcpu_svm *svm)
 758 {
 759         u32 *msrpm = svm->msrpm;
 760
 761         svm->vmcb->control.lbr_ctl = 0;
 762         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 763         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 764         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 765         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 766 }
 767
 768 static __init int svm_hardware_setup(void)
 769 {
 770         int cpu;
 771         struct page *iopm_pages;
 772         void *iopm_va;
 773         int r;
 774
 775         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 776
 777         if (!iopm_pages)
 778                 return -ENOMEM;
 779
 780         iopm_va = page_address(iopm_pages);
 781         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 782         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 783
 784         init_msrpm_offsets();
 785
 786         if (boot_cpu_has(X86_FEATURE_NX))
 787                 kvm_enable_efer_bits(EFER_NX);
 788
 789         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 790                 kvm_enable_efer_bits(EFER_FFXSR);
 791
 792         if (nested) {
 793                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 794                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 795         }
 796
 797         for_each_possible_cpu(cpu) {
 798                 r = svm_cpu_init(cpu);
 799                 if (r)
 800                         goto err;
 801         }
 802
 803         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 804
 805         if (!boot_cpu_has(X86_FEATURE_NPT))
 806                 npt_enabled = false;
 807
 808         if (npt_enabled && !npt) {
 809                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 810                 npt_enabled = false;
 811         }
 812
 813         if (npt_enabled) {
 814                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 815                 kvm_enable_tdp();
 816         } else
 817                 kvm_disable_tdp();
 818
 819         return 0;
 820
 821 err:
 822         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 823         iopm_base = 0;
 824         return r;
 825 }
 826
 827 static __exit void svm_hardware_unsetup(void)
 828 {
 829         int cpu;
 830
 831         for_each_possible_cpu(cpu)
 832                 svm_cpu_uninit(cpu);
 833
 834         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 835         iopm_base = 0;
 836 }
 837
 838 static void init_seg(struct vmcb_seg *seg)
 839 {
 840         seg->selector = 0;
 841         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 842                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 843         seg->limit = 0xffff;
 844         seg->base = 0;
 845 }
 846
 847 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 848 {
 849         seg->selector = 0;
 850         seg->attrib = SVM_SELECTOR_P_MASK | type;
 851         seg->limit = 0xffff;
 852         seg->base = 0;
 853 }
 854
 855 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 856 {
 857         struct vcpu_svm *svm = to_svm(vcpu);
 858         u64 g_tsc_offset = 0;
 859
 860         if (is_guest_mode(vcpu)) {
 861                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 862                                svm->nested.hsave->control.tsc_offset;
 863                 svm->nested.hsave->control.tsc_offset = offset;
 864         }
 865
 866         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 867
 868         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 869 }
 870
 871 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
 872 {
 873         struct vcpu_svm *svm = to_svm(vcpu);
 874
 875         svm->vmcb->control.tsc_offset += adjustment;
 876         if (is_guest_mode(vcpu))
 877                 svm->nested.hsave->control.tsc_offset += adjustment;
 878         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 879 }
 880
 881 static void init_vmcb(struct vcpu_svm *svm)
 882 {
 883         struct vmcb_control_area *control = &svm->vmcb->control;
 884         struct vmcb_save_area *save = &svm->vmcb->save;
 885
 886         svm->vcpu.fpu_active = 1;
 887         svm->vcpu.arch.hflags = 0;
 888
 889         set_cr_intercept(svm, INTERCEPT_CR0_READ);
 890         set_cr_intercept(svm, INTERCEPT_CR3_READ);
 891         set_cr_intercept(svm, INTERCEPT_CR4_READ);
 892         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
 893         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
 894         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
 895         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
 896
 897         set_dr_intercept(svm, INTERCEPT_DR0_READ);
 898         set_dr_intercept(svm, INTERCEPT_DR1_READ);
 899         set_dr_intercept(svm, INTERCEPT_DR2_READ);
 900         set_dr_intercept(svm, INTERCEPT_DR3_READ);
 901         set_dr_intercept(svm, INTERCEPT_DR4_READ);
 902         set_dr_intercept(svm, INTERCEPT_DR5_READ);
 903         set_dr_intercept(svm, INTERCEPT_DR6_READ);
 904         set_dr_intercept(svm, INTERCEPT_DR7_READ);
 905
 906         set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
 907         set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
 908         set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
 909         set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
 910         set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
 911         set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
 912         set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
 913         set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
 914
 915         set_exception_intercept(svm, PF_VECTOR);
 916         set_exception_intercept(svm, UD_VECTOR);
 917         set_exception_intercept(svm, MC_VECTOR);
 918
 919         set_intercept(svm, INTERCEPT_INTR);
 920         set_intercept(svm, INTERCEPT_NMI);
 921         set_intercept(svm, INTERCEPT_SMI);
 922         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
 923         set_intercept(svm, INTERCEPT_CPUID);
 924         set_intercept(svm, INTERCEPT_INVD);
 925         set_intercept(svm, INTERCEPT_HLT);
 926         set_intercept(svm, INTERCEPT_INVLPG);
 927         set_intercept(svm, INTERCEPT_INVLPGA);
 928         set_intercept(svm, INTERCEPT_IOIO_PROT);
 929         set_intercept(svm, INTERCEPT_MSR_PROT);
 930         set_intercept(svm, INTERCEPT_TASK_SWITCH);
 931         set_intercept(svm, INTERCEPT_SHUTDOWN);
 932         set_intercept(svm, INTERCEPT_VMRUN);
 933         set_intercept(svm, INTERCEPT_VMMCALL);
 934         set_intercept(svm, INTERCEPT_VMLOAD);
 935         set_intercept(svm, INTERCEPT_VMSAVE);
 936         set_intercept(svm, INTERCEPT_STGI);
 937         set_intercept(svm, INTERCEPT_CLGI);
 938         set_intercept(svm, INTERCEPT_SKINIT);
 939         set_intercept(svm, INTERCEPT_WBINVD);
 940         set_intercept(svm, INTERCEPT_MONITOR);
 941         set_intercept(svm, INTERCEPT_MWAIT);
 942         set_intercept(svm, INTERCEPT_XSETBV);
 943
 944         control->iopm_base_pa = iopm_base;
 945         control->msrpm_base_pa = __pa(svm->msrpm);
 946         control->int_ctl = V_INTR_MASKING_MASK;
 947
 948         init_seg(&save->es);
 949         init_seg(&save->ss);
 950         init_seg(&save->ds);
 951         init_seg(&save->fs);
 952         init_seg(&save->gs);
 953
 954         save->cs.selector = 0xf000;
 955         /* Executable/Readable Code Segment */
 956         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 957                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 958         save->cs.limit = 0xffff;
 959         /*
 960          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 961          * be consistent with it.
 962          *
 963          * Replace when we have real mode working for vmx.
 964          */
 965         save->cs.base = 0xf0000;
 966
 967         save->gdtr.limit = 0xffff;
 968         save->idtr.limit = 0xffff;
 969
 970         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 971         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 972
 973         svm_set_efer(&svm->vcpu, 0);
 974         save->dr6 = 0xffff0ff0;
 975         save->dr7 = 0x400;
 976         save->rflags = 2;
 977         save->rip = 0x0000fff0;
 978         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 979
 980         /*
 981          * This is the guest-visible cr0 value.
 982          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 983          */
 984         svm->vcpu.arch.cr0 = 0;
 985         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
 986
 987         save->cr4 = X86_CR4_PAE;
 988         /* rdx = ?? */
 989
 990         if (npt_enabled) {
 991                 /* Setup VMCB for Nested Paging */
 992                 control->nested_ctl = 1;
 993                 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
 994                 clr_intercept(svm, INTERCEPT_INVLPG);
 995                 clr_exception_intercept(svm, PF_VECTOR);
 996                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
 997                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
 998                 save->g_pat = 0x0007040600070406ULL;
 999                 save->cr3 = 0;
1000                 save->cr4 = 0;
1001         }
1002         svm->asid_generation = 0;
1003
1004         svm->nested.vmcb = 0;
1005         svm->vcpu.arch.hflags = 0;
1006
1007         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1008                 control->pause_filter_count = 3000;
1009                 set_intercept(svm, INTERCEPT_PAUSE);
1010         }
1011
1012         mark_all_dirty(svm->vmcb);
1013
1014         enable_gif(svm);
1015 }
1016
1017 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1018 {
1019         struct vcpu_svm *svm = to_svm(vcpu);
1020
1021         init_vmcb(svm);
1022
1023         if (!kvm_vcpu_is_bsp(vcpu)) {
1024                 kvm_rip_write(vcpu, 0);
1025                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1026                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1027         }
1028         vcpu->arch.regs_avail = ~0;
1029         vcpu->arch.regs_dirty = ~0;
1030
1031         return 0;
1032 }
1033
1034 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1035 {
1036         struct vcpu_svm *svm;
1037         struct page *page;
1038         struct page *msrpm_pages;
1039         struct page *hsave_page;
1040         struct page *nested_msrpm_pages;
1041         int err;
1042
1043         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1044         if (!svm) {
1045                 err = -ENOMEM;
1046                 goto out;
1047         }
1048
1049         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1050         if (err)
1051                 goto free_svm;
1052
1053         err = -ENOMEM;
1054         page = alloc_page(GFP_KERNEL);
1055         if (!page)
1056                 goto uninit;
1057
1058         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1059         if (!msrpm_pages)
1060                 goto free_page1;
1061
1062         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1063         if (!nested_msrpm_pages)
1064                 goto free_page2;
1065
1066         hsave_page = alloc_page(GFP_KERNEL);
1067         if (!hsave_page)
1068                 goto free_page3;
1069
1070         svm->nested.hsave = page_address(hsave_page);
1071
1072         svm->msrpm = page_address(msrpm_pages);
1073         svm_vcpu_init_msrpm(svm->msrpm);
1074
1075         svm->nested.msrpm = page_address(nested_msrpm_pages);
1076         svm_vcpu_init_msrpm(svm->nested.msrpm);
1077
1078         svm->vmcb = page_address(page);
1079         clear_page(svm->vmcb);
1080         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1081         svm->asid_generation = 0;
1082         init_vmcb(svm);
1083         kvm_write_tsc(&svm->vcpu, 0);
1084
1085         err = fx_init(&svm->vcpu);
1086         if (err)
1087                 goto free_page4;
1088
1089         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1090         if (kvm_vcpu_is_bsp(&svm->vcpu))
1091                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1092
1093         return &svm->vcpu;
1094
1095 free_page4:
1096         __free_page(hsave_page);
1097 free_page3:
1098         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1099 free_page2:
1100         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1101 free_page1:
1102         __free_page(page);
1103 uninit:
1104         kvm_vcpu_uninit(&svm->vcpu);
1105 free_svm:
1106         kmem_cache_free(kvm_vcpu_cache, svm);
1107 out:
1108         return ERR_PTR(err);
1109 }
1110
1111 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1112 {
1113         struct vcpu_svm *svm = to_svm(vcpu);
1114
1115         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1116         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1117         __free_page(virt_to_page(svm->nested.hsave));
1118         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1119         kvm_vcpu_uninit(vcpu);
1120         kmem_cache_free(kvm_vcpu_cache, svm);
1121 }
1122
1123 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1124 {
1125         struct vcpu_svm *svm = to_svm(vcpu);
1126         int i;
1127
1128         if (unlikely(cpu != vcpu->cpu)) {
1129                 svm->asid_generation = 0;
1130                 mark_all_dirty(svm->vmcb);
1131         }
1132
1133 #ifdef CONFIG_X86_64
1134         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1135 #endif
1136         savesegment(fs, svm->host.fs);
1137         savesegment(gs, svm->host.gs);
1138         svm->host.ldt = kvm_read_ldt();
1139
1140         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1141                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1142 }
1143
1144 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1145 {
1146         struct vcpu_svm *svm = to_svm(vcpu);
1147         int i;
1148
1149         ++vcpu->stat.host_state_reload;
1150         kvm_load_ldt(svm->host.ldt);
1151 #ifdef CONFIG_X86_64
1152         loadsegment(fs, svm->host.fs);
1153         load_gs_index(svm->host.gs);
1154         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1155 #else
1156         loadsegment(gs, svm->host.gs);
1157 #endif
1158         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1159                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1160 }
1161
1162 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1163 {
1164         return to_svm(vcpu)->vmcb->save.rflags;
1165 }
1166
1167 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1168 {
1169         to_svm(vcpu)->vmcb->save.rflags = rflags;
1170 }
1171
1172 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1173 {
1174         switch (reg) {
1175         case VCPU_EXREG_PDPTR:
1176                 BUG_ON(!npt_enabled);
1177                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1178                 break;
1179         default:
1180                 BUG();
1181         }
1182 }
1183
1184 static void svm_set_vintr(struct vcpu_svm *svm)
1185 {
1186         set_intercept(svm, INTERCEPT_VINTR);
1187 }
1188
1189 static void svm_clear_vintr(struct vcpu_svm *svm)
1190 {
1191         clr_intercept(svm, INTERCEPT_VINTR);
1192 }
1193
1194 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1195 {
1196         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1197
1198         switch (seg) {
1199         case VCPU_SREG_CS: return &save->cs;
1200         case VCPU_SREG_DS: return &save->ds;
1201         case VCPU_SREG_ES: return &save->es;
1202         case VCPU_SREG_FS: return &save->fs;
1203         case VCPU_SREG_GS: return &save->gs;
1204         case VCPU_SREG_SS: return &save->ss;
1205         case VCPU_SREG_TR: return &save->tr;
1206         case VCPU_SREG_LDTR: return &save->ldtr;
1207         }
1208         BUG();
1209         return NULL;
1210 }
1211
1212 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1213 {
1214         struct vmcb_seg *s = svm_seg(vcpu, seg);
1215
1216         return s->base;
1217 }
1218
1219 static void svm_get_segment(struct kvm_vcpu *vcpu,
1220                             struct kvm_segment *var, int seg)
1221 {
1222         struct vmcb_seg *s = svm_seg(vcpu, seg);
1223
1224         var->base = s->base;
1225         var->limit = s->limit;
1226         var->selector = s->selector;
1227         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1228         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1229         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1230         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1231         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1232         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1233         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1234         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1235
1236         /*
1237          * AMD's VMCB does not have an explicit unusable field, so emulate it
1238          * for cross vendor migration purposes by "not present"
1239          */
1240         var->unusable = !var->present || (var->type == 0);
1241
1242         switch (seg) {
1243         case VCPU_SREG_CS:
1244                 /*
1245                  * SVM always stores 0 for the 'G' bit in the CS selector in
1246                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1247                  * Intel's VMENTRY has a check on the 'G' bit.
1248                  */
1249                 var->g = s->limit > 0xfffff;
1250                 break;
1251         case VCPU_SREG_TR:
1252                 /*
1253                  * Work around a bug where the busy flag in the tr selector
1254                  * isn't exposed
1255                  */
1256                 var->type |= 0x2;
1257                 break;
1258         case VCPU_SREG_DS:
1259         case VCPU_SREG_ES:
1260         case VCPU_SREG_FS:
1261         case VCPU_SREG_GS:
1262                 /*
1263                  * The accessed bit must always be set in the segment
1264                  * descriptor cache, although it can be cleared in the
1265                  * descriptor, the cached bit always remains at 1. Since
1266                  * Intel has a check on this, set it here to support
1267                  * cross-vendor migration.
1268                  */
1269                 if (!var->unusable)
1270                         var->type |= 0x1;
1271                 break;
1272         case VCPU_SREG_SS:
1273                 /*
1274                  * On AMD CPUs sometimes the DB bit in the segment
1275                  * descriptor is left as 1, although the whole segment has
1276                  * been made unusable. Clear it here to pass an Intel VMX
1277                  * entry check when cross vendor migrating.
1278                  */
1279                 if (var->unusable)
1280                         var->db = 0;
1281                 break;
1282         }
1283 }
1284
1285 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1286 {
1287         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1288
1289         return save->cpl;
1290 }
1291
1292 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1293 {
1294         struct vcpu_svm *svm = to_svm(vcpu);
1295
1296         dt->size = svm->vmcb->save.idtr.limit;
1297         dt->address = svm->vmcb->save.idtr.base;
1298 }
1299
1300 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1301 {
1302         struct vcpu_svm *svm = to_svm(vcpu);
1303
1304         svm->vmcb->save.idtr.limit = dt->size;
1305         svm->vmcb->save.idtr.base = dt->address ;
1306         mark_dirty(svm->vmcb, VMCB_DT);
1307 }
1308
1309 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1310 {
1311         struct vcpu_svm *svm = to_svm(vcpu);
1312
1313         dt->size = svm->vmcb->save.gdtr.limit;
1314         dt->address = svm->vmcb->save.gdtr.base;
1315 }
1316
1317 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1318 {
1319         struct vcpu_svm *svm = to_svm(vcpu);
1320
1321         svm->vmcb->save.gdtr.limit = dt->size;
1322         svm->vmcb->save.gdtr.base = dt->address ;
1323         mark_dirty(svm->vmcb, VMCB_DT);
1324 }
1325
1326 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1327 {
1328 }
1329
1330 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1331 {
1332 }
1333
1334 static void update_cr0_intercept(struct vcpu_svm *svm)
1335 {
1336         ulong gcr0 = svm->vcpu.arch.cr0;
1337         u64 *hcr0 = &svm->vmcb->save.cr0;
1338
1339         if (!svm->vcpu.fpu_active)
1340                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1341         else
1342                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1343                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1344
1345         mark_dirty(svm->vmcb, VMCB_CR);
1346
1347         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1348                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1349                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1350         } else {
1351                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1352                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1353         }
1354 }
1355
1356 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1357 {
1358         struct vcpu_svm *svm = to_svm(vcpu);
1359
1360         if (is_guest_mode(vcpu)) {
1361                 /*
1362                  * We are here because we run in nested mode, the host kvm
1363                  * intercepts cr0 writes but the l1 hypervisor does not.
1364                  * But the L1 hypervisor may intercept selective cr0 writes.
1365                  * This needs to be checked here.
1366                  */
1367                 unsigned long old, new;
1368
1369                 /* Remove bits that would trigger a real cr0 write intercept */
1370                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1371                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1372
1373                 if (old == new) {
1374                         /* cr0 write with ts and mp unchanged */
1375                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1376                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1377                                 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1378                                 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1379                                 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1380                                 return;
1381                         }
1382                 }
1383         }
1384
1385 #ifdef CONFIG_X86_64
1386         if (vcpu->arch.efer & EFER_LME) {
1387                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1388                         vcpu->arch.efer |= EFER_LMA;
1389                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1390                 }
1391
1392                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1393                         vcpu->arch.efer &= ~EFER_LMA;
1394                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1395                 }
1396         }
1397 #endif
1398         vcpu->arch.cr0 = cr0;
1399
1400         if (!npt_enabled)
1401                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1402
1403         if (!vcpu->fpu_active)
1404                 cr0 |= X86_CR0_TS;
1405         /*
1406          * re-enable caching here because the QEMU bios
1407          * does not do it - this results in some delay at
1408          * reboot
1409          */
1410         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1411         svm->vmcb->save.cr0 = cr0;
1412         mark_dirty(svm->vmcb, VMCB_CR);
1413         update_cr0_intercept(svm);
1414 }
1415
1416 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1417 {
1418         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1419         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1420
1421         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1422                 svm_flush_tlb(vcpu);
1423
1424         vcpu->arch.cr4 = cr4;
1425         if (!npt_enabled)
1426                 cr4 |= X86_CR4_PAE;
1427         cr4 |= host_cr4_mce;
1428         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1429         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1430 }
1431
1432 static void svm_set_segment(struct kvm_vcpu *vcpu,
1433                             struct kvm_segment *var, int seg)
1434 {
1435         struct vcpu_svm *svm = to_svm(vcpu);
1436         struct vmcb_seg *s = svm_seg(vcpu, seg);
1437
1438         s->base = var->base;
1439         s->limit = var->limit;
1440         s->selector = var->selector;
1441         if (var->unusable)
1442                 s->attrib = 0;
1443         else {
1444                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1445                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1446                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1447                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1448                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1449                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1450                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1451                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1452         }
1453         if (seg == VCPU_SREG_CS)
1454                 svm->vmcb->save.cpl
1455                         = (svm->vmcb->save.cs.attrib
1456                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1457
1458         mark_dirty(svm->vmcb, VMCB_SEG);
1459 }
1460
1461 static void update_db_intercept(struct kvm_vcpu *vcpu)
1462 {
1463         struct vcpu_svm *svm = to_svm(vcpu);
1464
1465         clr_exception_intercept(svm, DB_VECTOR);
1466         clr_exception_intercept(svm, BP_VECTOR);
1467
1468         if (svm->nmi_singlestep)
1469                 set_exception_intercept(svm, DB_VECTOR);
1470
1471         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1472                 if (vcpu->guest_debug &
1473                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1474                         set_exception_intercept(svm, DB_VECTOR);
1475                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1476                         set_exception_intercept(svm, BP_VECTOR);
1477         } else
1478                 vcpu->guest_debug = 0;
1479 }
1480
1481 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1482 {
1483         struct vcpu_svm *svm = to_svm(vcpu);
1484
1485         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1486                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1487         else
1488                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1489
1490         mark_dirty(svm->vmcb, VMCB_DR);
1491
1492         update_db_intercept(vcpu);
1493 }
1494
1495 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1496 {
1497         if (sd->next_asid > sd->max_asid) {
1498                 ++sd->asid_generation;
1499                 sd->next_asid = 1;
1500                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1501         }
1502
1503         svm->asid_generation = sd->asid_generation;
1504         svm->vmcb->control.asid = sd->next_asid++;
1505
1506         mark_dirty(svm->vmcb, VMCB_ASID);
1507 }
1508
1509 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1510 {
1511         struct vcpu_svm *svm = to_svm(vcpu);
1512
1513         svm->vmcb->save.dr7 = value;
1514         mark_dirty(svm->vmcb, VMCB_DR);
1515 }
1516
1517 static int pf_interception(struct vcpu_svm *svm)
1518 {
1519         u64 fault_address = svm->vmcb->control.exit_info_2;
1520         u32 error_code;
1521         int r = 1;
1522
1523         switch (svm->apf_reason) {
1524         default:
1525                 error_code = svm->vmcb->control.exit_info_1;
1526
1527                 trace_kvm_page_fault(fault_address, error_code);
1528                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1529                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1530                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1531                         svm->vmcb->control.insn_bytes,
1532                         svm->vmcb->control.insn_len);
1533                 break;
1534         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1535                 svm->apf_reason = 0;
1536                 local_irq_disable();
1537                 kvm_async_pf_task_wait(fault_address);
1538                 local_irq_enable();
1539                 break;
1540         case KVM_PV_REASON_PAGE_READY:
1541                 svm->apf_reason = 0;
1542                 local_irq_disable();
1543                 kvm_async_pf_task_wake(fault_address);
1544                 local_irq_enable();
1545                 break;
1546         }
1547         return r;
1548 }
1549
1550 static int db_interception(struct vcpu_svm *svm)
1551 {
1552         struct kvm_run *kvm_run = svm->vcpu.run;
1553
1554         if (!(svm->vcpu.guest_debug &
1555               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1556                 !svm->nmi_singlestep) {
1557                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1558                 return 1;
1559         }
1560
1561         if (svm->nmi_singlestep) {
1562                 svm->nmi_singlestep = false;
1563                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1564                         svm->vmcb->save.rflags &=
1565                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1566                 update_db_intercept(&svm->vcpu);
1567         }
1568
1569         if (svm->vcpu.guest_debug &
1570             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1571                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1572                 kvm_run->debug.arch.pc =
1573                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1574                 kvm_run->debug.arch.exception = DB_VECTOR;
1575                 return 0;
1576         }
1577
1578         return 1;
1579 }
1580
1581 static int bp_interception(struct vcpu_svm *svm)
1582 {
1583         struct kvm_run *kvm_run = svm->vcpu.run;
1584
1585         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1586         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1587         kvm_run->debug.arch.exception = BP_VECTOR;
1588         return 0;
1589 }
1590
1591 static int ud_interception(struct vcpu_svm *svm)
1592 {
1593         int er;
1594
1595         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1596         if (er != EMULATE_DONE)
1597                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1598         return 1;
1599 }
1600
1601 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1602 {
1603         struct vcpu_svm *svm = to_svm(vcpu);
1604
1605         clr_exception_intercept(svm, NM_VECTOR);
1606
1607         svm->vcpu.fpu_active = 1;
1608         update_cr0_intercept(svm);
1609 }
1610
1611 static int nm_interception(struct vcpu_svm *svm)
1612 {
1613         svm_fpu_activate(&svm->vcpu);
1614         return 1;
1615 }
1616
1617 static bool is_erratum_383(void)
1618 {
1619         int err, i;
1620         u64 value;
1621
1622         if (!erratum_383_found)
1623                 return false;
1624
1625         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1626         if (err)
1627                 return false;
1628
1629         /* Bit 62 may or may not be set for this mce */
1630         value &= ~(1ULL << 62);
1631
1632         if (value != 0xb600000000010015ULL)
1633                 return false;
1634
1635         /* Clear MCi_STATUS registers */
1636         for (i = 0; i < 6; ++i)
1637                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1638
1639         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1640         if (!err) {
1641                 u32 low, high;
1642
1643                 value &= ~(1ULL << 2);
1644                 low    = lower_32_bits(value);
1645                 high   = upper_32_bits(value);
1646
1647                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1648         }
1649
1650         /* Flush tlb to evict multi-match entries */
1651         __flush_tlb_all();
1652
1653         return true;
1654 }
1655
1656 static void svm_handle_mce(struct vcpu_svm *svm)
1657 {
1658         if (is_erratum_383()) {
1659                 /*
1660                  * Erratum 383 triggered. Guest state is corrupt so kill the
1661                  * guest.
1662                  */
1663                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1664
1665                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1666
1667                 return;
1668         }
1669
1670         /*
1671          * On an #MC intercept the MCE handler is not called automatically in
1672          * the host. So do it by hand here.
1673          */
1674         asm volatile (
1675                 "int $0x12\n");
1676         /* not sure if we ever come back to this point */
1677
1678         return;
1679 }
1680
1681 static int mc_interception(struct vcpu_svm *svm)
1682 {
1683         return 1;
1684 }
1685
1686 static int shutdown_interception(struct vcpu_svm *svm)
1687 {
1688         struct kvm_run *kvm_run = svm->vcpu.run;
1689
1690         /*
1691          * VMCB is undefined after a SHUTDOWN intercept
1692          * so reinitialize it.
1693          */
1694         clear_page(svm->vmcb);
1695         init_vmcb(svm);
1696
1697         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1698         return 0;
1699 }
1700
1701 static int io_interception(struct vcpu_svm *svm)
1702 {
1703         struct kvm_vcpu *vcpu = &svm->vcpu;
1704         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1705         int size, in, string;
1706         unsigned port;
1707
1708         ++svm->vcpu.stat.io_exits;
1709         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1710         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1711         if (string || in)
1712                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1713
1714         port = io_info >> 16;
1715         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1716         svm->next_rip = svm->vmcb->control.exit_info_2;
1717         skip_emulated_instruction(&svm->vcpu);
1718
1719         return kvm_fast_pio_out(vcpu, size, port);
1720 }
1721
1722 static int nmi_interception(struct vcpu_svm *svm)
1723 {
1724         return 1;
1725 }
1726
1727 static int intr_interception(struct vcpu_svm *svm)
1728 {
1729         ++svm->vcpu.stat.irq_exits;
1730         return 1;
1731 }
1732
1733 static int nop_on_interception(struct vcpu_svm *svm)
1734 {
1735         return 1;
1736 }
1737
1738 static int halt_interception(struct vcpu_svm *svm)
1739 {
1740         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1741         skip_emulated_instruction(&svm->vcpu);
1742         return kvm_emulate_halt(&svm->vcpu);
1743 }
1744
1745 static int vmmcall_interception(struct vcpu_svm *svm)
1746 {
1747         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1748         skip_emulated_instruction(&svm->vcpu);
1749         kvm_emulate_hypercall(&svm->vcpu);
1750         return 1;
1751 }
1752
1753 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1754 {
1755         struct vcpu_svm *svm = to_svm(vcpu);
1756
1757         return svm->nested.nested_cr3;
1758 }
1759
1760 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1761                                    unsigned long root)
1762 {
1763         struct vcpu_svm *svm = to_svm(vcpu);
1764
1765         svm->vmcb->control.nested_cr3 = root;
1766         mark_dirty(svm->vmcb, VMCB_NPT);
1767         svm_flush_tlb(vcpu);
1768 }
1769
1770 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1771                                        struct x86_exception *fault)
1772 {
1773         struct vcpu_svm *svm = to_svm(vcpu);
1774
1775         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1776         svm->vmcb->control.exit_code_hi = 0;
1777         svm->vmcb->control.exit_info_1 = fault->error_code;
1778         svm->vmcb->control.exit_info_2 = fault->address;
1779
1780         nested_svm_vmexit(svm);
1781 }
1782
1783 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1784 {
1785         int r;
1786
1787         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1788
1789         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1790         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1791         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1792         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1793         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1794
1795         return r;
1796 }
1797
1798 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1799 {
1800         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1801 }
1802
1803 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1804 {
1805         if (!(svm->vcpu.arch.efer & EFER_SVME)
1806             || !is_paging(&svm->vcpu)) {
1807                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1808                 return 1;
1809         }
1810
1811         if (svm->vmcb->save.cpl) {
1812                 kvm_inject_gp(&svm->vcpu, 0);
1813                 return 1;
1814         }
1815
1816        return 0;
1817 }
1818
1819 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1820                                       bool has_error_code, u32 error_code)
1821 {
1822         int vmexit;
1823
1824         if (!is_guest_mode(&svm->vcpu))
1825                 return 0;
1826
1827         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1828         svm->vmcb->control.exit_code_hi = 0;
1829         svm->vmcb->control.exit_info_1 = error_code;
1830         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1831
1832         vmexit = nested_svm_intercept(svm);
1833         if (vmexit == NESTED_EXIT_DONE)
1834                 svm->nested.exit_required = true;
1835
1836         return vmexit;
1837 }
1838
1839 /* This function returns true if it is save to enable the irq window */
1840 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1841 {
1842         if (!is_guest_mode(&svm->vcpu))
1843                 return true;
1844
1845         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1846                 return true;
1847
1848         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1849                 return false;
1850
1851         /*
1852          * if vmexit was already requested (by intercepted exception
1853          * for instance) do not overwrite it with "external interrupt"
1854          * vmexit.
1855          */
1856         if (svm->nested.exit_required)
1857                 return false;
1858
1859         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1860         svm->vmcb->control.exit_info_1 = 0;
1861         svm->vmcb->control.exit_info_2 = 0;
1862
1863         if (svm->nested.intercept & 1ULL) {
1864                 /*
1865                  * The #vmexit can't be emulated here directly because this
1866                  * code path runs with irqs and preemtion disabled. A
1867                  * #vmexit emulation might sleep. Only signal request for
1868                  * the #vmexit here.
1869                  */
1870                 svm->nested.exit_required = true;
1871                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1872                 return false;
1873         }
1874
1875         return true;
1876 }
1877
1878 /* This function returns true if it is save to enable the nmi window */
1879 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1880 {
1881         if (!is_guest_mode(&svm->vcpu))
1882                 return true;
1883
1884         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1885                 return true;
1886
1887         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1888         svm->nested.exit_required = true;
1889
1890         return false;
1891 }
1892
1893 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1894 {
1895         struct page *page;
1896
1897         might_sleep();
1898
1899         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1900         if (is_error_page(page))
1901                 goto error;
1902
1903         *_page = page;
1904
1905         return kmap(page);
1906
1907 error:
1908         kvm_release_page_clean(page);
1909         kvm_inject_gp(&svm->vcpu, 0);
1910
1911         return NULL;
1912 }
1913
1914 static void nested_svm_unmap(struct page *page)
1915 {
1916         kunmap(page);
1917         kvm_release_page_dirty(page);
1918 }
1919
1920 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1921 {
1922         unsigned port;
1923         u8 val, bit;
1924         u64 gpa;
1925
1926         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1927                 return NESTED_EXIT_HOST;
1928
1929         port = svm->vmcb->control.exit_info_1 >> 16;
1930         gpa  = svm->nested.vmcb_iopm + (port / 8);
1931         bit  = port % 8;
1932         val  = 0;
1933
1934         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1935                 val &= (1 << bit);
1936
1937         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1938 }
1939
1940 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1941 {
1942         u32 offset, msr, value;
1943         int write, mask;
1944
1945         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1946                 return NESTED_EXIT_HOST;
1947
1948         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1949         offset = svm_msrpm_offset(msr);
1950         write  = svm->vmcb->control.exit_info_1 & 1;
1951         mask   = 1 << ((2 * (msr & 0xf)) + write);
1952
1953         if (offset == MSR_INVALID)
1954                 return NESTED_EXIT_DONE;
1955
1956         /* Offset is in 32 bit units but need in 8 bit units */
1957         offset *= 4;
1958
1959         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1960                 return NESTED_EXIT_DONE;
1961
1962         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1963 }
1964
1965 static int nested_svm_exit_special(struct vcpu_svm *svm)
1966 {
1967         u32 exit_code = svm->vmcb->control.exit_code;
1968
1969         switch (exit_code) {
1970         case SVM_EXIT_INTR:
1971         case SVM_EXIT_NMI:
1972         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1973                 return NESTED_EXIT_HOST;
1974         case SVM_EXIT_NPF:
1975                 /* For now we are always handling NPFs when using them */
1976                 if (npt_enabled)
1977                         return NESTED_EXIT_HOST;
1978                 break;
1979         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1980                 /* When we're shadowing, trap PFs, but not async PF */
1981                 if (!npt_enabled && svm->apf_reason == 0)
1982                         return NESTED_EXIT_HOST;
1983                 break;
1984         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1985                 nm_interception(svm);
1986                 break;
1987         default:
1988                 break;
1989         }
1990
1991         return NESTED_EXIT_CONTINUE;
1992 }
1993
1994 /*
1995  * If this function returns true, this #vmexit was already handled
1996  */
1997 static int nested_svm_intercept(struct vcpu_svm *svm)
1998 {
1999         u32 exit_code = svm->vmcb->control.exit_code;
2000         int vmexit = NESTED_EXIT_HOST;
2001
2002         switch (exit_code) {
2003         case SVM_EXIT_MSR:
2004                 vmexit = nested_svm_exit_handled_msr(svm);
2005                 break;
2006         case SVM_EXIT_IOIO:
2007                 vmexit = nested_svm_intercept_ioio(svm);
2008                 break;
2009         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2010                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2011                 if (svm->nested.intercept_cr & bit)
2012                         vmexit = NESTED_EXIT_DONE;
2013                 break;
2014         }
2015         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2016                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2017                 if (svm->nested.intercept_dr & bit)
2018                         vmexit = NESTED_EXIT_DONE;
2019                 break;
2020         }
2021         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2022                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2023                 if (svm->nested.intercept_exceptions & excp_bits)
2024                         vmexit = NESTED_EXIT_DONE;
2025                 /* async page fault always cause vmexit */
2026                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2027                          svm->apf_reason != 0)
2028                         vmexit = NESTED_EXIT_DONE;
2029                 break;
2030         }
2031         case SVM_EXIT_ERR: {
2032                 vmexit = NESTED_EXIT_DONE;
2033                 break;
2034         }
2035         default: {
2036                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2037                 if (svm->nested.intercept & exit_bits)
2038                         vmexit = NESTED_EXIT_DONE;
2039         }
2040         }
2041
2042         return vmexit;
2043 }
2044
2045 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2046 {
2047         int vmexit;
2048
2049         vmexit = nested_svm_intercept(svm);
2050
2051         if (vmexit == NESTED_EXIT_DONE)
2052                 nested_svm_vmexit(svm);
2053
2054         return vmexit;
2055 }
2056
2057 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2058 {
2059         struct vmcb_control_area *dst  = &dst_vmcb->control;
2060         struct vmcb_control_area *from = &from_vmcb->control;
2061
2062         dst->intercept_cr         = from->intercept_cr;
2063         dst->intercept_dr         = from->intercept_dr;
2064         dst->intercept_exceptions = from->intercept_exceptions;
2065         dst->intercept            = from->intercept;
2066         dst->iopm_base_pa         = from->iopm_base_pa;
2067         dst->msrpm_base_pa        = from->msrpm_base_pa;
2068         dst->tsc_offset           = from->tsc_offset;
2069         dst->asid                 = from->asid;
2070         dst->tlb_ctl              = from->tlb_ctl;
2071         dst->int_ctl              = from->int_ctl;
2072         dst->int_vector           = from->int_vector;
2073         dst->int_state            = from->int_state;
2074         dst->exit_code            = from->exit_code;
2075         dst->exit_code_hi         = from->exit_code_hi;
2076         dst->exit_info_1          = from->exit_info_1;
2077         dst->exit_info_2          = from->exit_info_2;
2078         dst->exit_int_info        = from->exit_int_info;
2079         dst->exit_int_info_err    = from->exit_int_info_err;
2080         dst->nested_ctl           = from->nested_ctl;
2081         dst->event_inj            = from->event_inj;
2082         dst->event_inj_err        = from->event_inj_err;
2083         dst->nested_cr3           = from->nested_cr3;
2084         dst->lbr_ctl              = from->lbr_ctl;
2085 }
2086
2087 static int nested_svm_vmexit(struct vcpu_svm *svm)
2088 {
2089         struct vmcb *nested_vmcb;
2090         struct vmcb *hsave = svm->nested.hsave;
2091         struct vmcb *vmcb = svm->vmcb;
2092         struct page *page;
2093
2094         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2095                                        vmcb->control.exit_info_1,
2096                                        vmcb->control.exit_info_2,
2097                                        vmcb->control.exit_int_info,
2098                                        vmcb->control.exit_int_info_err);
2099
2100         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2101         if (!nested_vmcb)
2102                 return 1;
2103
2104         /* Exit Guest-Mode */
2105         leave_guest_mode(&svm->vcpu);
2106         svm->nested.vmcb = 0;
2107
2108         /* Give the current vmcb to the guest */
2109         disable_gif(svm);
2110
2111         nested_vmcb->save.es     = vmcb->save.es;
2112         nested_vmcb->save.cs     = vmcb->save.cs;
2113         nested_vmcb->save.ss     = vmcb->save.ss;
2114         nested_vmcb->save.ds     = vmcb->save.ds;
2115         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2116         nested_vmcb->save.idtr   = vmcb->save.idtr;
2117         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2118         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2119         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2120         nested_vmcb->save.cr2    = vmcb->save.cr2;
2121         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2122         nested_vmcb->save.rflags = vmcb->save.rflags;
2123         nested_vmcb->save.rip    = vmcb->save.rip;
2124         nested_vmcb->save.rsp    = vmcb->save.rsp;
2125         nested_vmcb->save.rax    = vmcb->save.rax;
2126         nested_vmcb->save.dr7    = vmcb->save.dr7;
2127         nested_vmcb->save.dr6    = vmcb->save.dr6;
2128         nested_vmcb->save.cpl    = vmcb->save.cpl;
2129
2130         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2131         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2132         nested_vmcb->control.int_state         = vmcb->control.int_state;
2133         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2134         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2135         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2136         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2137         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2138         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2139         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2140
2141         /*
2142          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2143          * to make sure that we do not lose injected events. So check event_inj
2144          * here and copy it to exit_int_info if it is valid.
2145          * Exit_int_info and event_inj can't be both valid because the case
2146          * below only happens on a VMRUN instruction intercept which has
2147          * no valid exit_int_info set.
2148          */
2149         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2150                 struct vmcb_control_area *nc = &nested_vmcb->control;
2151
2152                 nc->exit_int_info     = vmcb->control.event_inj;
2153                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2154         }
2155
2156         nested_vmcb->control.tlb_ctl           = 0;
2157         nested_vmcb->control.event_inj         = 0;
2158         nested_vmcb->control.event_inj_err     = 0;
2159
2160         /* We always set V_INTR_MASKING and remember the old value in hflags */
2161         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2162                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2163
2164         /* Restore the original control entries */
2165         copy_vmcb_control_area(vmcb, hsave);
2166
2167         kvm_clear_exception_queue(&svm->vcpu);
2168         kvm_clear_interrupt_queue(&svm->vcpu);
2169
2170         svm->nested.nested_cr3 = 0;
2171
2172         /* Restore selected save entries */
2173         svm->vmcb->save.es = hsave->save.es;
2174         svm->vmcb->save.cs = hsave->save.cs;
2175         svm->vmcb->save.ss = hsave->save.ss;
2176         svm->vmcb->save.ds = hsave->save.ds;
2177         svm->vmcb->save.gdtr = hsave->save.gdtr;
2178         svm->vmcb->save.idtr = hsave->save.idtr;
2179         svm->vmcb->save.rflags = hsave->save.rflags;
2180         svm_set_efer(&svm->vcpu, hsave->save.efer);
2181         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2182         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2183         if (npt_enabled) {
2184                 svm->vmcb->save.cr3 = hsave->save.cr3;
2185                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2186         } else {
2187                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2188         }
2189         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2190         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2191         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2192         svm->vmcb->save.dr7 = 0;
2193         svm->vmcb->save.cpl = 0;
2194         svm->vmcb->control.exit_int_info = 0;
2195
2196         mark_all_dirty(svm->vmcb);
2197
2198         nested_svm_unmap(page);
2199
2200         nested_svm_uninit_mmu_context(&svm->vcpu);
2201         kvm_mmu_reset_context(&svm->vcpu);
2202         kvm_mmu_load(&svm->vcpu);
2203
2204         return 0;
2205 }
2206
2207 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2208 {
2209         /*
2210          * This function merges the msr permission bitmaps of kvm and the
2211          * nested vmcb. It is omptimized in that it only merges the parts where
2212          * the kvm msr permission bitmap may contain zero bits
2213          */
2214         int i;
2215
2216         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2217                 return true;
2218
2219         for (i = 0; i < MSRPM_OFFSETS; i++) {
2220                 u32 value, p;
2221                 u64 offset;
2222
2223                 if (msrpm_offsets[i] == 0xffffffff)
2224                         break;
2225
2226                 p      = msrpm_offsets[i];
2227                 offset = svm->nested.vmcb_msrpm + (p * 4);
2228
2229                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2230                         return false;
2231
2232                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2233         }
2234
2235         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2236
2237         return true;
2238 }
2239
2240 static bool nested_vmcb_checks(struct vmcb *vmcb)
2241 {
2242         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2243                 return false;
2244
2245         if (vmcb->control.asid == 0)
2246                 return false;
2247
2248         if (vmcb->control.nested_ctl && !npt_enabled)
2249                 return false;
2250
2251         return true;
2252 }
2253
2254 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2255 {
2256         struct vmcb *nested_vmcb;
2257         struct vmcb *hsave = svm->nested.hsave;
2258         struct vmcb *vmcb = svm->vmcb;
2259         struct page *page;
2260         u64 vmcb_gpa;
2261
2262         vmcb_gpa = svm->vmcb->save.rax;
2263
2264         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2265         if (!nested_vmcb)
2266                 return false;
2267
2268         if (!nested_vmcb_checks(nested_vmcb)) {
2269                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2270                 nested_vmcb->control.exit_code_hi = 0;
2271                 nested_vmcb->control.exit_info_1  = 0;
2272                 nested_vmcb->control.exit_info_2  = 0;
2273
2274                 nested_svm_unmap(page);
2275
2276                 return false;
2277         }
2278
2279         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2280                                nested_vmcb->save.rip,
2281                                nested_vmcb->control.int_ctl,
2282                                nested_vmcb->control.event_inj,
2283                                nested_vmcb->control.nested_ctl);
2284
2285         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2286                                     nested_vmcb->control.intercept_cr >> 16,
2287                                     nested_vmcb->control.intercept_exceptions,
2288                                     nested_vmcb->control.intercept);
2289
2290         /* Clear internal status */
2291         kvm_clear_exception_queue(&svm->vcpu);
2292         kvm_clear_interrupt_queue(&svm->vcpu);
2293
2294         /*
2295          * Save the old vmcb, so we don't need to pick what we save, but can
2296          * restore everything when a VMEXIT occurs
2297          */
2298         hsave->save.es     = vmcb->save.es;
2299         hsave->save.cs     = vmcb->save.cs;
2300         hsave->save.ss     = vmcb->save.ss;
2301         hsave->save.ds     = vmcb->save.ds;
2302         hsave->save.gdtr   = vmcb->save.gdtr;
2303         hsave->save.idtr   = vmcb->save.idtr;
2304         hsave->save.efer   = svm->vcpu.arch.efer;
2305         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2306         hsave->save.cr4    = svm->vcpu.arch.cr4;
2307         hsave->save.rflags = vmcb->save.rflags;
2308         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2309         hsave->save.rsp    = vmcb->save.rsp;
2310         hsave->save.rax    = vmcb->save.rax;
2311         if (npt_enabled)
2312                 hsave->save.cr3    = vmcb->save.cr3;
2313         else
2314                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2315
2316         copy_vmcb_control_area(hsave, vmcb);
2317
2318         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2319                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2320         else
2321                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2322
2323         if (nested_vmcb->control.nested_ctl) {
2324                 kvm_mmu_unload(&svm->vcpu);
2325                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2326                 nested_svm_init_mmu_context(&svm->vcpu);
2327         }
2328
2329         /* Load the nested guest state */
2330         svm->vmcb->save.es = nested_vmcb->save.es;
2331         svm->vmcb->save.cs = nested_vmcb->save.cs;
2332         svm->vmcb->save.ss = nested_vmcb->save.ss;
2333         svm->vmcb->save.ds = nested_vmcb->save.ds;
2334         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2335         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2336         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2337         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2338         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2339         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2340         if (npt_enabled) {
2341                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2342                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2343         } else
2344                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2345
2346         /* Guest paging mode is active - reset mmu */
2347         kvm_mmu_reset_context(&svm->vcpu);
2348
2349         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2350         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2351         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2352         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2353
2354         /* In case we don't even reach vcpu_run, the fields are not updated */
2355         svm->vmcb->save.rax = nested_vmcb->save.rax;
2356         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2357         svm->vmcb->save.rip = nested_vmcb->save.rip;
2358         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2359         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2360         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2361
2362         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2363         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2364
2365         /* cache intercepts */
2366         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2367         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2368         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2369         svm->nested.intercept            = nested_vmcb->control.intercept;
2370
2371         svm_flush_tlb(&svm->vcpu);
2372         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2373         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2374                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2375         else
2376                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2377
2378         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2379                 /* We only want the cr8 intercept bits of the guest */
2380                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2381                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2382         }
2383
2384         /* We don't want to see VMMCALLs from a nested guest */
2385         clr_intercept(svm, INTERCEPT_VMMCALL);
2386
2387         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2388         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2389         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2390         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2391         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2392         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2393
2394         nested_svm_unmap(page);
2395
2396         /* Enter Guest-Mode */
2397         enter_guest_mode(&svm->vcpu);
2398
2399         /*
2400          * Merge guest and host intercepts - must be called  with vcpu in
2401          * guest-mode to take affect here
2402          */
2403         recalc_intercepts(svm);
2404
2405         svm->nested.vmcb = vmcb_gpa;
2406
2407         enable_gif(svm);
2408
2409         mark_all_dirty(svm->vmcb);
2410
2411         return true;
2412 }
2413
2414 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2415 {
2416         to_vmcb->save.fs = from_vmcb->save.fs;
2417         to_vmcb->save.gs = from_vmcb->save.gs;
2418         to_vmcb->save.tr = from_vmcb->save.tr;
2419         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2420         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2421         to_vmcb->save.star = from_vmcb->save.star;
2422         to_vmcb->save.lstar = from_vmcb->save.lstar;
2423         to_vmcb->save.cstar = from_vmcb->save.cstar;
2424         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2425         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2426         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2427         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2428 }
2429
2430 static int vmload_interception(struct vcpu_svm *svm)
2431 {
2432         struct vmcb *nested_vmcb;
2433         struct page *page;
2434
2435         if (nested_svm_check_permissions(svm))
2436                 return 1;
2437
2438         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2439         skip_emulated_instruction(&svm->vcpu);
2440
2441         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2442         if (!nested_vmcb)
2443                 return 1;
2444
2445         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2446         nested_svm_unmap(page);
2447
2448         return 1;
2449 }
2450
2451 static int vmsave_interception(struct vcpu_svm *svm)
2452 {
2453         struct vmcb *nested_vmcb;
2454         struct page *page;
2455
2456         if (nested_svm_check_permissions(svm))
2457                 return 1;
2458
2459         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2460         skip_emulated_instruction(&svm->vcpu);
2461
2462         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2463         if (!nested_vmcb)
2464                 return 1;
2465
2466         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2467         nested_svm_unmap(page);
2468
2469         return 1;
2470 }
2471
2472 static int vmrun_interception(struct vcpu_svm *svm)
2473 {
2474         if (nested_svm_check_permissions(svm))
2475                 return 1;
2476
2477         /* Save rip after vmrun instruction */
2478         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2479
2480         if (!nested_svm_vmrun(svm))
2481                 return 1;
2482
2483         if (!nested_svm_vmrun_msrpm(svm))
2484                 goto failed;
2485
2486         return 1;
2487
2488 failed:
2489
2490         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2491         svm->vmcb->control.exit_code_hi = 0;
2492         svm->vmcb->control.exit_info_1  = 0;
2493         svm->vmcb->control.exit_info_2  = 0;
2494
2495         nested_svm_vmexit(svm);
2496
2497         return 1;
2498 }
2499
2500 static int stgi_interception(struct vcpu_svm *svm)
2501 {
2502         if (nested_svm_check_permissions(svm))
2503                 return 1;
2504
2505         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2506         skip_emulated_instruction(&svm->vcpu);
2507         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2508
2509         enable_gif(svm);
2510
2511         return 1;
2512 }
2513
2514 static int clgi_interception(struct vcpu_svm *svm)
2515 {
2516         if (nested_svm_check_permissions(svm))
2517                 return 1;
2518
2519         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2520         skip_emulated_instruction(&svm->vcpu);
2521
2522         disable_gif(svm);
2523
2524         /* After a CLGI no interrupts should come */
2525         svm_clear_vintr(svm);
2526         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2527
2528         mark_dirty(svm->vmcb, VMCB_INTR);
2529
2530         return 1;
2531 }
2532
2533 static int invlpga_interception(struct vcpu_svm *svm)
2534 {
2535         struct kvm_vcpu *vcpu = &svm->vcpu;
2536
2537         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2538                           vcpu->arch.regs[VCPU_REGS_RAX]);
2539
2540         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2541         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2542
2543         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2544         skip_emulated_instruction(&svm->vcpu);
2545         return 1;
2546 }
2547
2548 static int skinit_interception(struct vcpu_svm *svm)
2549 {
2550         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2551
2552         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2553         return 1;
2554 }
2555
2556 static int xsetbv_interception(struct vcpu_svm *svm)
2557 {
2558         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2559         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2560
2561         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2562                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2563                 skip_emulated_instruction(&svm->vcpu);
2564         }
2565
2566         return 1;
2567 }
2568
2569 static int invalid_op_interception(struct vcpu_svm *svm)
2570 {
2571         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2572         return 1;
2573 }
2574
2575 static int task_switch_interception(struct vcpu_svm *svm)
2576 {
2577         u16 tss_selector;
2578         int reason;
2579         int int_type = svm->vmcb->control.exit_int_info &
2580                 SVM_EXITINTINFO_TYPE_MASK;
2581         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2582         uint32_t type =
2583                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2584         uint32_t idt_v =
2585                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2586         bool has_error_code = false;
2587         u32 error_code = 0;
2588
2589         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2590
2591         if (svm->vmcb->control.exit_info_2 &
2592             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2593                 reason = TASK_SWITCH_IRET;
2594         else if (svm->vmcb->control.exit_info_2 &
2595                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2596                 reason = TASK_SWITCH_JMP;
2597         else if (idt_v)
2598                 reason = TASK_SWITCH_GATE;
2599         else
2600                 reason = TASK_SWITCH_CALL;
2601
2602         if (reason == TASK_SWITCH_GATE) {
2603                 switch (type) {
2604                 case SVM_EXITINTINFO_TYPE_NMI:
2605                         svm->vcpu.arch.nmi_injected = false;
2606                         break;
2607                 case SVM_EXITINTINFO_TYPE_EXEPT:
2608                         if (svm->vmcb->control.exit_info_2 &
2609                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2610                                 has_error_code = true;
2611                                 error_code =
2612                                         (u32)svm->vmcb->control.exit_info_2;
2613                         }
2614                         kvm_clear_exception_queue(&svm->vcpu);
2615                         break;
2616                 case SVM_EXITINTINFO_TYPE_INTR:
2617                         kvm_clear_interrupt_queue(&svm->vcpu);
2618                         break;
2619                 default:
2620                         break;
2621                 }
2622         }
2623
2624         if (reason != TASK_SWITCH_GATE ||
2625             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2626             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2627              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2628                 skip_emulated_instruction(&svm->vcpu);
2629
2630         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2631                                 has_error_code, error_code) == EMULATE_FAIL) {
2632                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2633                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2634                 svm->vcpu.run->internal.ndata = 0;
2635                 return 0;
2636         }
2637         return 1;
2638 }
2639
2640 static int cpuid_interception(struct vcpu_svm *svm)
2641 {
2642         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2643         kvm_emulate_cpuid(&svm->vcpu);
2644         return 1;
2645 }
2646
2647 static int iret_interception(struct vcpu_svm *svm)
2648 {
2649         ++svm->vcpu.stat.nmi_window_exits;
2650         clr_intercept(svm, INTERCEPT_IRET);
2651         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2652         return 1;
2653 }
2654
2655 static int invlpg_interception(struct vcpu_svm *svm)
2656 {
2657         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2658                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2659
2660         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2661         skip_emulated_instruction(&svm->vcpu);
2662         return 1;
2663 }
2664
2665 static int emulate_on_interception(struct vcpu_svm *svm)
2666 {
2667         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2668 }
2669
2670 #define CR_VALID (1ULL << 63)
2671
2672 static int cr_interception(struct vcpu_svm *svm)
2673 {
2674         int reg, cr;
2675         unsigned long val;
2676         int err;
2677
2678         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2679                 return emulate_on_interception(svm);
2680
2681         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2682                 return emulate_on_interception(svm);
2683
2684         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2685         cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2686
2687         err = 0;
2688         if (cr >= 16) { /* mov to cr */
2689                 cr -= 16;
2690                 val = kvm_register_read(&svm->vcpu, reg);
2691                 switch (cr) {
2692                 case 0:
2693                         err = kvm_set_cr0(&svm->vcpu, val);
2694                         break;
2695                 case 3:
2696                         err = kvm_set_cr3(&svm->vcpu, val);
2697                         break;
2698                 case 4:
2699                         err = kvm_set_cr4(&svm->vcpu, val);
2700                         break;
2701                 case 8:
2702                         err = kvm_set_cr8(&svm->vcpu, val);
2703                         break;
2704                 default:
2705                         WARN(1, "unhandled write to CR%d", cr);
2706                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2707                         return 1;
2708                 }
2709         } else { /* mov from cr */
2710                 switch (cr) {
2711                 case 0:
2712                         val = kvm_read_cr0(&svm->vcpu);
2713                         break;
2714                 case 2:
2715                         val = svm->vcpu.arch.cr2;
2716                         break;
2717                 case 3:
2718                         val = kvm_read_cr3(&svm->vcpu);
2719                         break;
2720                 case 4:
2721                         val = kvm_read_cr4(&svm->vcpu);
2722                         break;
2723                 case 8:
2724                         val = kvm_get_cr8(&svm->vcpu);
2725                         break;
2726                 default:
2727                         WARN(1, "unhandled read from CR%d", cr);
2728                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2729                         return 1;
2730                 }
2731                 kvm_register_write(&svm->vcpu, reg, val);
2732         }
2733         kvm_complete_insn_gp(&svm->vcpu, err);
2734
2735         return 1;
2736 }
2737
2738 static int cr0_write_interception(struct vcpu_svm *svm)
2739 {
2740         struct kvm_vcpu *vcpu = &svm->vcpu;
2741         int r;
2742
2743         r = cr_interception(svm);
2744
2745         if (svm->nested.vmexit_rip) {
2746                 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2747                 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2748                 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2749                 svm->nested.vmexit_rip = 0;
2750         }
2751
2752         return r;
2753 }
2754
2755 static int dr_interception(struct vcpu_svm *svm)
2756 {
2757         int reg, dr;
2758         unsigned long val;
2759         int err;
2760
2761         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2762                 return emulate_on_interception(svm);
2763
2764         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2765         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2766
2767         if (dr >= 16) { /* mov to DRn */
2768                 val = kvm_register_read(&svm->vcpu, reg);
2769                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2770         } else {
2771                 err = kvm_get_dr(&svm->vcpu, dr, &val);
2772                 if (!err)
2773                         kvm_register_write(&svm->vcpu, reg, val);
2774         }
2775
2776         return 1;
2777 }
2778
2779 static int cr8_write_interception(struct vcpu_svm *svm)
2780 {
2781         struct kvm_run *kvm_run = svm->vcpu.run;
2782         int r;
2783
2784         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2785         /* instruction emulation calls kvm_set_cr8() */
2786         r = cr_interception(svm);
2787         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2788                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2789                 return r;
2790         }
2791         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2792                 return r;
2793         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2794         return 0;
2795 }
2796
2797 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2798 {
2799         struct vcpu_svm *svm = to_svm(vcpu);
2800
2801         switch (ecx) {
2802         case MSR_IA32_TSC: {
2803                 struct vmcb *vmcb = get_host_vmcb(svm);
2804
2805                 *data = vmcb->control.tsc_offset + native_read_tsc();
2806                 break;
2807         }
2808         case MSR_STAR:
2809                 *data = svm->vmcb->save.star;
2810                 break;
2811 #ifdef CONFIG_X86_64
2812         case MSR_LSTAR:
2813                 *data = svm->vmcb->save.lstar;
2814                 break;
2815         case MSR_CSTAR:
2816                 *data = svm->vmcb->save.cstar;
2817                 break;
2818         case MSR_KERNEL_GS_BASE:
2819                 *data = svm->vmcb->save.kernel_gs_base;
2820                 break;
2821         case MSR_SYSCALL_MASK:
2822                 *data = svm->vmcb->save.sfmask;
2823                 break;
2824 #endif
2825         case MSR_IA32_SYSENTER_CS:
2826                 *data = svm->vmcb->save.sysenter_cs;
2827                 break;
2828         case MSR_IA32_SYSENTER_EIP:
2829                 *data = svm->sysenter_eip;
2830                 break;
2831         case MSR_IA32_SYSENTER_ESP:
2832                 *data = svm->sysenter_esp;
2833                 break;
2834         /*
2835          * Nobody will change the following 5 values in the VMCB so we can
2836          * safely return them on rdmsr. They will always be 0 until LBRV is
2837          * implemented.
2838          */
2839         case MSR_IA32_DEBUGCTLMSR:
2840                 *data = svm->vmcb->save.dbgctl;
2841                 break;
2842         case MSR_IA32_LASTBRANCHFROMIP:
2843                 *data = svm->vmcb->save.br_from;
2844                 break;
2845         case MSR_IA32_LASTBRANCHTOIP:
2846                 *data = svm->vmcb->save.br_to;
2847                 break;
2848         case MSR_IA32_LASTINTFROMIP:
2849                 *data = svm->vmcb->save.last_excp_from;
2850                 break;
2851         case MSR_IA32_LASTINTTOIP:
2852                 *data = svm->vmcb->save.last_excp_to;
2853                 break;
2854         case MSR_VM_HSAVE_PA:
2855                 *data = svm->nested.hsave_msr;
2856                 break;
2857         case MSR_VM_CR:
2858                 *data = svm->nested.vm_cr_msr;
2859                 break;
2860         case MSR_IA32_UCODE_REV:
2861                 *data = 0x01000065;
2862                 break;
2863         default:
2864                 return kvm_get_msr_common(vcpu, ecx, data);
2865         }
2866         return 0;
2867 }
2868
2869 static int rdmsr_interception(struct vcpu_svm *svm)
2870 {
2871         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2872         u64 data;
2873
2874         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2875                 trace_kvm_msr_read_ex(ecx);
2876                 kvm_inject_gp(&svm->vcpu, 0);
2877         } else {
2878                 trace_kvm_msr_read(ecx, data);
2879
2880                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2881                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2882                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2883                 skip_emulated_instruction(&svm->vcpu);
2884         }
2885         return 1;
2886 }
2887
2888 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2889 {
2890         struct vcpu_svm *svm = to_svm(vcpu);
2891         int svm_dis, chg_mask;
2892
2893         if (data & ~SVM_VM_CR_VALID_MASK)
2894                 return 1;
2895
2896         chg_mask = SVM_VM_CR_VALID_MASK;
2897
2898         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2899                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2900
2901         svm->nested.vm_cr_msr &= ~chg_mask;
2902         svm->nested.vm_cr_msr |= (data & chg_mask);
2903
2904         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2905
2906         /* check for svm_disable while efer.svme is set */
2907         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2908                 return 1;
2909
2910         return 0;
2911 }
2912
2913 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2914 {
2915         struct vcpu_svm *svm = to_svm(vcpu);
2916
2917         switch (ecx) {
2918         case MSR_IA32_TSC:
2919                 kvm_write_tsc(vcpu, data);
2920                 break;
2921         case MSR_STAR:
2922                 svm->vmcb->save.star = data;
2923                 break;
2924 #ifdef CONFIG_X86_64
2925         case MSR_LSTAR:
2926                 svm->vmcb->save.lstar = data;
2927                 break;
2928         case MSR_CSTAR:
2929                 svm->vmcb->save.cstar = data;
2930                 break;
2931         case MSR_KERNEL_GS_BASE:
2932                 svm->vmcb->save.kernel_gs_base = data;
2933                 break;
2934         case MSR_SYSCALL_MASK:
2935                 svm->vmcb->save.sfmask = data;
2936                 break;
2937 #endif
2938         case MSR_IA32_SYSENTER_CS:
2939                 svm->vmcb->save.sysenter_cs = data;
2940                 break;
2941         case MSR_IA32_SYSENTER_EIP:
2942                 svm->sysenter_eip = data;
2943                 svm->vmcb->save.sysenter_eip = data;
2944                 break;
2945         case MSR_IA32_SYSENTER_ESP:
2946                 svm->sysenter_esp = data;
2947                 svm->vmcb->save.sysenter_esp = data;
2948                 break;
2949         case MSR_IA32_DEBUGCTLMSR:
2950                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2951                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2952                                         __func__, data);
2953                         break;
2954                 }
2955                 if (data & DEBUGCTL_RESERVED_BITS)
2956                         return 1;
2957
2958                 svm->vmcb->save.dbgctl = data;
2959                 mark_dirty(svm->vmcb, VMCB_LBR);
2960                 if (data & (1ULL<<0))
2961                         svm_enable_lbrv(svm);
2962                 else
2963                         svm_disable_lbrv(svm);
2964                 break;
2965         case MSR_VM_HSAVE_PA:
2966                 svm->nested.hsave_msr = data;
2967                 break;
2968         case MSR_VM_CR:
2969                 return svm_set_vm_cr(vcpu, data);
2970         case MSR_VM_IGNNE:
2971                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2972                 break;
2973         default:
2974                 return kvm_set_msr_common(vcpu, ecx, data);
2975         }
2976         return 0;
2977 }
2978
2979 static int wrmsr_interception(struct vcpu_svm *svm)
2980 {
2981         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2982         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2983                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2984
2985
2986         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2987         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2988                 trace_kvm_msr_write_ex(ecx, data);
2989                 kvm_inject_gp(&svm->vcpu, 0);
2990         } else {
2991                 trace_kvm_msr_write(ecx, data);
2992                 skip_emulated_instruction(&svm->vcpu);
2993         }
2994         return 1;
2995 }
2996
2997 static int msr_interception(struct vcpu_svm *svm)
2998 {
2999         if (svm->vmcb->control.exit_info_1)
3000                 return wrmsr_interception(svm);
3001         else
3002                 return rdmsr_interception(svm);
3003 }
3004
3005 static int interrupt_window_interception(struct vcpu_svm *svm)
3006 {
3007         struct kvm_run *kvm_run = svm->vcpu.run;
3008
3009         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3010         svm_clear_vintr(svm);
3011         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3012         mark_dirty(svm->vmcb, VMCB_INTR);
3013         /*
3014          * If the user space waits to inject interrupts, exit as soon as
3015          * possible
3016          */
3017         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3018             kvm_run->request_interrupt_window &&
3019             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3020                 ++svm->vcpu.stat.irq_window_exits;
3021                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3022                 return 0;
3023         }
3024
3025         return 1;
3026 }
3027
3028 static int pause_interception(struct vcpu_svm *svm)
3029 {
3030         kvm_vcpu_on_spin(&(svm->vcpu));
3031         return 1;
3032 }
3033
3034 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3035         [SVM_EXIT_READ_CR0]                     = cr_interception,
3036         [SVM_EXIT_READ_CR3]                     = cr_interception,
3037         [SVM_EXIT_READ_CR4]                     = cr_interception,
3038         [SVM_EXIT_READ_CR8]                     = cr_interception,
3039         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
3040         [SVM_EXIT_WRITE_CR0]                    = cr0_write_interception,
3041         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3042         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3043         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3044         [SVM_EXIT_READ_DR0]                     = dr_interception,
3045         [SVM_EXIT_READ_DR1]                     = dr_interception,
3046         [SVM_EXIT_READ_DR2]                     = dr_interception,
3047         [SVM_EXIT_READ_DR3]                     = dr_interception,
3048         [SVM_EXIT_READ_DR4]                     = dr_interception,
3049         [SVM_EXIT_READ_DR5]                     = dr_interception,
3050         [SVM_EXIT_READ_DR6]                     = dr_interception,
3051         [SVM_EXIT_READ_DR7]                     = dr_interception,
3052         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3053         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3054         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3055         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3056         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3057         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3058         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3059         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3060         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3061         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3062         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3063         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3064         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3065         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3066         [SVM_EXIT_INTR]                         = intr_interception,
3067         [SVM_EXIT_NMI]                          = nmi_interception,
3068         [SVM_EXIT_SMI]                          = nop_on_interception,
3069         [SVM_EXIT_INIT]                         = nop_on_interception,
3070         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3071         [SVM_EXIT_CPUID]                        = cpuid_interception,
3072         [SVM_EXIT_IRET]                         = iret_interception,
3073         [SVM_EXIT_INVD]                         = emulate_on_interception,
3074         [SVM_EXIT_PAUSE]                        = pause_interception,
3075         [SVM_EXIT_HLT]                          = halt_interception,
3076         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3077         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3078         [SVM_EXIT_IOIO]                         = io_interception,
3079         [SVM_EXIT_MSR]                          = msr_interception,
3080         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3081         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3082         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3083         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3084         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3085         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3086         [SVM_EXIT_STGI]                         = stgi_interception,
3087         [SVM_EXIT_CLGI]                         = clgi_interception,
3088         [SVM_EXIT_SKINIT]                       = skinit_interception,
3089         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
3090         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
3091         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
3092         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3093         [SVM_EXIT_NPF]                          = pf_interception,
3094 };
3095
3096 void dump_vmcb(struct kvm_vcpu *vcpu)
3097 {
3098         struct vcpu_svm *svm = to_svm(vcpu);
3099         struct vmcb_control_area *control = &svm->vmcb->control;
3100         struct vmcb_save_area *save = &svm->vmcb->save;
3101
3102         pr_err("VMCB Control Area:\n");
3103         pr_err("cr_read:            %04x\n", control->intercept_cr & 0xffff);
3104         pr_err("cr_write:           %04x\n", control->intercept_cr >> 16);
3105         pr_err("dr_read:            %04x\n", control->intercept_dr & 0xffff);
3106         pr_err("dr_write:           %04x\n", control->intercept_dr >> 16);
3107         pr_err("exceptions:         %08x\n", control->intercept_exceptions);
3108         pr_err("intercepts:         %016llx\n", control->intercept);
3109         pr_err("pause filter count: %d\n", control->pause_filter_count);
3110         pr_err("iopm_base_pa:       %016llx\n", control->iopm_base_pa);
3111         pr_err("msrpm_base_pa:      %016llx\n", control->msrpm_base_pa);
3112         pr_err("tsc_offset:         %016llx\n", control->tsc_offset);
3113         pr_err("asid:               %d\n", control->asid);
3114         pr_err("tlb_ctl:            %d\n", control->tlb_ctl);
3115         pr_err("int_ctl:            %08x\n", control->int_ctl);
3116         pr_err("int_vector:         %08x\n", control->int_vector);
3117         pr_err("int_state:          %08x\n", control->int_state);
3118         pr_err("exit_code:          %08x\n", control->exit_code);
3119         pr_err("exit_info1:         %016llx\n", control->exit_info_1);
3120         pr_err("exit_info2:         %016llx\n", control->exit_info_2);
3121         pr_err("exit_int_info:      %08x\n", control->exit_int_info);
3122         pr_err("exit_int_info_err:  %08x\n", control->exit_int_info_err);
3123         pr_err("nested_ctl:         %lld\n", control->nested_ctl);
3124         pr_err("nested_cr3:         %016llx\n", control->nested_cr3);
3125         pr_err("event_inj:          %08x\n", control->event_inj);
3126         pr_err("event_inj_err:      %08x\n", control->event_inj_err);
3127         pr_err("lbr_ctl:            %lld\n", control->lbr_ctl);
3128         pr_err("next_rip:           %016llx\n", control->next_rip);
3129         pr_err("VMCB State Save Area:\n");
3130         pr_err("es:   s: %04x a: %04x l: %08x b: %016llx\n",
3131                 save->es.selector, save->es.attrib,
3132                 save->es.limit, save->es.base);
3133         pr_err("cs:   s: %04x a: %04x l: %08x b: %016llx\n",
3134                 save->cs.selector, save->cs.attrib,
3135                 save->cs.limit, save->cs.base);
3136         pr_err("ss:   s: %04x a: %04x l: %08x b: %016llx\n",
3137                 save->ss.selector, save->ss.attrib,
3138                 save->ss.limit, save->ss.base);
3139         pr_err("ds:   s: %04x a: %04x l: %08x b: %016llx\n",
3140                 save->ds.selector, save->ds.attrib,
3141                 save->ds.limit, save->ds.base);
3142         pr_err("fs:   s: %04x a: %04x l: %08x b: %016llx\n",
3143                 save->fs.selector, save->fs.attrib,
3144                 save->fs.limit, save->fs.base);
3145         pr_err("gs:   s: %04x a: %04x l: %08x b: %016llx\n",
3146                 save->gs.selector, save->gs.attrib,
3147                 save->gs.limit, save->gs.base);
3148         pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3149                 save->gdtr.selector, save->gdtr.attrib,
3150                 save->gdtr.limit, save->gdtr.base);
3151         pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3152                 save->ldtr.selector, save->ldtr.attrib,
3153                 save->ldtr.limit, save->ldtr.base);
3154         pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3155                 save->idtr.selector, save->idtr.attrib,
3156                 save->idtr.limit, save->idtr.base);
3157         pr_err("tr:   s: %04x a: %04x l: %08x b: %016llx\n",
3158                 save->tr.selector, save->tr.attrib,
3159                 save->tr.limit, save->tr.base);
3160         pr_err("cpl:            %d                efer:         %016llx\n",
3161                 save->cpl, save->efer);
3162         pr_err("cr0:            %016llx cr2:          %016llx\n",
3163                 save->cr0, save->cr2);
3164         pr_err("cr3:            %016llx cr4:          %016llx\n",
3165                 save->cr3, save->cr4);
3166         pr_err("dr6:            %016llx dr7:          %016llx\n",
3167                 save->dr6, save->dr7);
3168         pr_err("rip:            %016llx rflags:       %016llx\n",
3169                 save->rip, save->rflags);
3170         pr_err("rsp:            %016llx rax:          %016llx\n",
3171                 save->rsp, save->rax);
3172         pr_err("star:           %016llx lstar:        %016llx\n",
3173                 save->star, save->lstar);
3174         pr_err("cstar:          %016llx sfmask:       %016llx\n",
3175                 save->cstar, save->sfmask);
3176         pr_err("kernel_gs_base: %016llx sysenter_cs:  %016llx\n",
3177                 save->kernel_gs_base, save->sysenter_cs);
3178         pr_err("sysenter_esp:   %016llx sysenter_eip: %016llx\n",
3179                 save->sysenter_esp, save->sysenter_eip);
3180         pr_err("gpat:           %016llx dbgctl:       %016llx\n",
3181                 save->g_pat, save->dbgctl);
3182         pr_err("br_from:        %016llx br_to:        %016llx\n",
3183                 save->br_from, save->br_to);
3184         pr_err("excp_from:      %016llx excp_to:      %016llx\n",
3185                 save->last_excp_from, save->last_excp_to);
3186
3187 }
3188
3189 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3190 {
3191         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3192
3193         *info1 = control->exit_info_1;
3194         *info2 = control->exit_info_2;
3195 }
3196
3197 static int handle_exit(struct kvm_vcpu *vcpu)
3198 {
3199         struct vcpu_svm *svm = to_svm(vcpu);
3200         struct kvm_run *kvm_run = vcpu->run;
3201         u32 exit_code = svm->vmcb->control.exit_code;
3202
3203         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3204
3205         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3206                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3207         if (npt_enabled)
3208                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3209
3210         if (unlikely(svm->nested.exit_required)) {
3211                 nested_svm_vmexit(svm);
3212                 svm->nested.exit_required = false;
3213
3214                 return 1;
3215         }
3216
3217         if (is_guest_mode(vcpu)) {
3218                 int vmexit;
3219
3220                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3221                                         svm->vmcb->control.exit_info_1,
3222                                         svm->vmcb->control.exit_info_2,
3223                                         svm->vmcb->control.exit_int_info,
3224                                         svm->vmcb->control.exit_int_info_err);
3225
3226                 vmexit = nested_svm_exit_special(svm);
3227
3228                 if (vmexit == NESTED_EXIT_CONTINUE)
3229                         vmexit = nested_svm_exit_handled(svm);
3230
3231                 if (vmexit == NESTED_EXIT_DONE)
3232                         return 1;
3233         }
3234
3235         svm_complete_interrupts(svm);
3236
3237         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3238                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3239                 kvm_run->fail_entry.hardware_entry_failure_reason
3240                         = svm->vmcb->control.exit_code;
3241                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3242                 dump_vmcb(vcpu);
3243                 return 0;
3244         }
3245
3246         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3247             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3248             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3249             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3250                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3251                        "exit_code 0x%x\n",
3252                        __func__, svm->vmcb->control.exit_int_info,
3253                        exit_code);
3254
3255         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3256             || !svm_exit_handlers[exit_code]) {
3257                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3258                 kvm_run->hw.hardware_exit_reason = exit_code;
3259                 return 0;
3260         }
3261
3262         return svm_exit_handlers[exit_code](svm);
3263 }
3264
3265 static void reload_tss(struct kvm_vcpu *vcpu)
3266 {
3267         int cpu = raw_smp_processor_id();
3268
3269         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3270         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3271         load_TR_desc();
3272 }
3273
3274 static void pre_svm_run(struct vcpu_svm *svm)
3275 {
3276         int cpu = raw_smp_processor_id();
3277
3278         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3279
3280         /* FIXME: handle wraparound of asid_generation */
3281         if (svm->asid_generation != sd->asid_generation)
3282                 new_asid(svm, sd);
3283 }
3284
3285 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3286 {
3287         struct vcpu_svm *svm = to_svm(vcpu);
3288
3289         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3290         vcpu->arch.hflags |= HF_NMI_MASK;
3291         set_intercept(svm, INTERCEPT_IRET);
3292         ++vcpu->stat.nmi_injections;
3293 }
3294
3295 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3296 {
3297         struct vmcb_control_area *control;
3298
3299         control = &svm->vmcb->control;
3300         control->int_vector = irq;
3301         control->int_ctl &= ~V_INTR_PRIO_MASK;
3302         control->int_ctl |= V_IRQ_MASK |
3303                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3304         mark_dirty(svm->vmcb, VMCB_INTR);
3305 }
3306
3307 static void svm_set_irq(struct kvm_vcpu *vcpu)
3308 {
3309         struct vcpu_svm *svm = to_svm(vcpu);
3310
3311         BUG_ON(!(gif_set(svm)));
3312
3313         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3314         ++vcpu->stat.irq_injections;
3315
3316         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3317                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3318 }
3319
3320 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3321 {
3322         struct vcpu_svm *svm = to_svm(vcpu);
3323
3324         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3325                 return;
3326
3327         if (irr == -1)
3328                 return;
3329
3330         if (tpr >= irr)
3331                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3332 }
3333
3334 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3335 {
3336         struct vcpu_svm *svm = to_svm(vcpu);
3337         struct vmcb *vmcb = svm->vmcb;
3338         int ret;
3339         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3340               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3341         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3342
3343         return ret;
3344 }
3345
3346 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3347 {
3348         struct vcpu_svm *svm = to_svm(vcpu);
3349
3350         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3351 }
3352
3353 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3354 {
3355         struct vcpu_svm *svm = to_svm(vcpu);
3356
3357         if (masked) {
3358                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3359                 set_intercept(svm, INTERCEPT_IRET);
3360         } else {
3361                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3362                 clr_intercept(svm, INTERCEPT_IRET);
3363         }
3364 }
3365
3366 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3367 {
3368         struct vcpu_svm *svm = to_svm(vcpu);
3369         struct vmcb *vmcb = svm->vmcb;
3370         int ret;
3371
3372         if (!gif_set(svm) ||
3373              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3374                 return 0;
3375
3376         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3377
3378         if (is_guest_mode(vcpu))
3379                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3380
3381         return ret;
3382 }
3383
3384 static void enable_irq_window(struct kvm_vcpu *vcpu)
3385 {
3386         struct vcpu_svm *svm = to_svm(vcpu);
3387
3388         /*
3389          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3390          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3391          * get that intercept, this function will be called again though and
3392          * we'll get the vintr intercept.
3393          */
3394         if (gif_set(svm) && nested_svm_intr(svm)) {
3395                 svm_set_vintr(svm);
3396                 svm_inject_irq(svm, 0x0);
3397         }
3398 }
3399
3400 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3401 {
3402         struct vcpu_svm *svm = to_svm(vcpu);
3403
3404         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3405             == HF_NMI_MASK)
3406                 return; /* IRET will cause a vm exit */
3407
3408         /*
3409          * Something prevents NMI from been injected. Single step over possible
3410          * problem (IRET or exception injection or interrupt shadow)
3411          */
3412         svm->nmi_singlestep = true;
3413         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3414         update_db_intercept(vcpu);
3415 }
3416
3417 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3418 {
3419         return 0;
3420 }
3421
3422 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3423 {
3424         struct vcpu_svm *svm = to_svm(vcpu);
3425
3426         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3427                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3428         else
3429                 svm->asid_generation--;
3430 }
3431
3432 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3433 {
3434 }
3435
3436 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3437 {
3438         struct vcpu_svm *svm = to_svm(vcpu);
3439
3440         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3441                 return;
3442
3443         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3444                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3445                 kvm_set_cr8(vcpu, cr8);
3446         }
3447 }
3448
3449 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3450 {
3451         struct vcpu_svm *svm = to_svm(vcpu);
3452         u64 cr8;
3453
3454         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3455                 return;
3456
3457         cr8 = kvm_get_cr8(vcpu);
3458         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3459         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3460 }
3461
3462 static void svm_complete_interrupts(struct vcpu_svm *svm)
3463 {
3464         u8 vector;
3465         int type;
3466         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3467         unsigned int3_injected = svm->int3_injected;
3468
3469         svm->int3_injected = 0;
3470
3471         if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3472                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3473                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3474         }
3475
3476         svm->vcpu.arch.nmi_injected = false;
3477         kvm_clear_exception_queue(&svm->vcpu);
3478         kvm_clear_interrupt_queue(&svm->vcpu);
3479
3480         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3481                 return;
3482
3483         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3484
3485         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3486         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3487
3488         switch (type) {
3489         case SVM_EXITINTINFO_TYPE_NMI:
3490                 svm->vcpu.arch.nmi_injected = true;
3491                 break;
3492         case SVM_EXITINTINFO_TYPE_EXEPT:
3493                 /*
3494                  * In case of software exceptions, do not reinject the vector,
3495                  * but re-execute the instruction instead. Rewind RIP first
3496                  * if we emulated INT3 before.
3497                  */
3498                 if (kvm_exception_is_soft(vector)) {
3499                         if (vector == BP_VECTOR && int3_injected &&
3500                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3501                                 kvm_rip_write(&svm->vcpu,
3502                                               kvm_rip_read(&svm->vcpu) -
3503                                               int3_injected);
3504                         break;
3505                 }
3506                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3507                         u32 err = svm->vmcb->control.exit_int_info_err;
3508                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3509
3510                 } else
3511                         kvm_requeue_exception(&svm->vcpu, vector);
3512                 break;
3513         case SVM_EXITINTINFO_TYPE_INTR:
3514                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3515                 break;
3516         default:
3517                 break;
3518         }
3519 }
3520
3521 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3522 {
3523         struct vcpu_svm *svm = to_svm(vcpu);
3524         struct vmcb_control_area *control = &svm->vmcb->control;
3525
3526         control->exit_int_info = control->event_inj;
3527         control->exit_int_info_err = control->event_inj_err;
3528         control->event_inj = 0;
3529         svm_complete_interrupts(svm);
3530 }
3531
3532 #ifdef CONFIG_X86_64
3533 #define R "r"
3534 #else
3535 #define R "e"
3536 #endif
3537
3538 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3539 {
3540         struct vcpu_svm *svm = to_svm(vcpu);
3541
3542         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3543         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3544         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3545
3546         /*
3547          * A vmexit emulation is required before the vcpu can be executed
3548          * again.
3549          */
3550         if (unlikely(svm->nested.exit_required))
3551                 return;
3552
3553         pre_svm_run(svm);
3554
3555         sync_lapic_to_cr8(vcpu);
3556
3557         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3558
3559         clgi();
3560
3561         local_irq_enable();
3562
3563         asm volatile (
3564                 "push %%"R"bp; \n\t"
3565                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3566                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3567                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3568                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3569                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3570                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3571 #ifdef CONFIG_X86_64
3572                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3573                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3574                 "mov %c[r10](%[svm]), %%r10 \n\t"
3575                 "mov %c[r11](%[svm]), %%r11 \n\t"
3576                 "mov %c[r12](%[svm]), %%r12 \n\t"
3577                 "mov %c[r13](%[svm]), %%r13 \n\t"
3578                 "mov %c[r14](%[svm]), %%r14 \n\t"
3579                 "mov %c[r15](%[svm]), %%r15 \n\t"
3580 #endif
3581
3582                 /* Enter guest mode */
3583                 "push %%"R"ax \n\t"
3584                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3585                 __ex(SVM_VMLOAD) "\n\t"
3586                 __ex(SVM_VMRUN) "\n\t"
3587                 __ex(SVM_VMSAVE) "\n\t"
3588                 "pop %%"R"ax \n\t"
3589
3590                 /* Save guest registers, load host registers */
3591                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3592                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3593                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3594                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3595                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3596                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3597 #ifdef CONFIG_X86_64
3598                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3599                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3600                 "mov %%r10, %c[r10](%[svm]) \n\t"
3601                 "mov %%r11, %c[r11](%[svm]) \n\t"
3602                 "mov %%r12, %c[r12](%[svm]) \n\t"
3603                 "mov %%r13, %c[r13](%[svm]) \n\t"
3604                 "mov %%r14, %c[r14](%[svm]) \n\t"
3605                 "mov %%r15, %c[r15](%[svm]) \n\t"
3606 #endif
3607                 "pop %%"R"bp"
3608                 :
3609                 : [svm]"a"(svm),
3610                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3611                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3612                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3613                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3614                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3615                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3616                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3617 #ifdef CONFIG_X86_64
3618                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3619                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3620                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3621                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3622                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3623                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3624                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3625                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3626 #endif
3627                 : "cc", "memory"
3628                 , R"bx", R"cx", R"dx", R"si", R"di"
3629 #ifdef CONFIG_X86_64
3630                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3631 #endif
3632                 );
3633
3634 #ifdef CONFIG_X86_64
3635         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3636 #else
3637         loadsegment(fs, svm->host.fs);
3638 #endif
3639
3640         reload_tss(vcpu);
3641
3642         local_irq_disable();
3643
3644         stgi();
3645
3646         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3647         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3648         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3649         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3650
3651         sync_cr8_to_lapic(vcpu);
3652
3653         svm->next_rip = 0;
3654
3655         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3656
3657         /* if exit due to PF check for async PF */
3658         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3659                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3660
3661         if (npt_enabled) {
3662                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3663                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3664         }
3665
3666         /*
3667          * We need to handle MC intercepts here before the vcpu has a chance to
3668          * change the physical cpu
3669          */
3670         if (unlikely(svm->vmcb->control.exit_code ==
3671                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3672                 svm_handle_mce(svm);
3673
3674         mark_all_clean(svm->vmcb);
3675 }
3676
3677 #undef R
3678
3679 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3680 {
3681         struct vcpu_svm *svm = to_svm(vcpu);
3682
3683         svm->vmcb->save.cr3 = root;
3684         mark_dirty(svm->vmcb, VMCB_CR);
3685         svm_flush_tlb(vcpu);
3686 }
3687
3688 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3689 {
3690         struct vcpu_svm *svm = to_svm(vcpu);
3691
3692         svm->vmcb->control.nested_cr3 = root;
3693         mark_dirty(svm->vmcb, VMCB_NPT);
3694
3695         /* Also sync guest cr3 here in case we live migrate */
3696         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3697         mark_dirty(svm->vmcb, VMCB_CR);
3698
3699         svm_flush_tlb(vcpu);
3700 }
3701
3702 static int is_disabled(void)
3703 {
3704         u64 vm_cr;
3705
3706         rdmsrl(MSR_VM_CR, vm_cr);
3707         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3708                 return 1;
3709
3710         return 0;
3711 }
3712
3713 static void
3714 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3715 {
3716         /*
3717          * Patch in the VMMCALL instruction:
3718          */
3719         hypercall[0] = 0x0f;
3720         hypercall[1] = 0x01;
3721         hypercall[2] = 0xd9;
3722 }
3723
3724 static void svm_check_processor_compat(void *rtn)
3725 {
3726         *(int *)rtn = 0;
3727 }
3728
3729 static bool svm_cpu_has_accelerated_tpr(void)
3730 {
3731         return false;
3732 }
3733
3734 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3735 {
3736         return 0;
3737 }
3738
3739 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3740 {
3741 }
3742
3743 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3744 {
3745         switch (func) {
3746         case 0x80000001:
3747                 if (nested)
3748                         entry->ecx |= (1 << 2); /* Set SVM bit */
3749                 break;
3750         case 0x8000000A:
3751                 entry->eax = 1; /* SVM revision 1 */
3752                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3753                                    ASID emulation to nested SVM */
3754                 entry->ecx = 0; /* Reserved */
3755                 entry->edx = 0; /* Per default do not support any
3756                                    additional features */
3757
3758                 /* Support next_rip if host supports it */
3759                 if (boot_cpu_has(X86_FEATURE_NRIPS))
3760                         entry->edx |= SVM_FEATURE_NRIP;
3761
3762                 /* Support NPT for the guest if enabled */
3763                 if (npt_enabled)
3764                         entry->edx |= SVM_FEATURE_NPT;
3765
3766                 break;
3767         }
3768 }
3769
3770 static const struct trace_print_flags svm_exit_reasons_str[] = {
3771         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3772         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3773         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3774         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3775         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3776         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3777         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3778         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3779         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3780         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3781         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3782         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3783         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3784         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3785         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3786         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3787         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3788         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3789         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3790         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3791         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3792         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3793         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3794         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3795         { SVM_EXIT_INTR,                        "interrupt" },
3796         { SVM_EXIT_NMI,                         "nmi" },
3797         { SVM_EXIT_SMI,                         "smi" },
3798         { SVM_EXIT_INIT,                        "init" },
3799         { SVM_EXIT_VINTR,                       "vintr" },
3800         { SVM_EXIT_CPUID,                       "cpuid" },
3801         { SVM_EXIT_INVD,                        "invd" },
3802         { SVM_EXIT_HLT,                         "hlt" },
3803         { SVM_EXIT_INVLPG,                      "invlpg" },
3804         { SVM_EXIT_INVLPGA,                     "invlpga" },
3805         { SVM_EXIT_IOIO,                        "io" },
3806         { SVM_EXIT_MSR,                         "msr" },
3807         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3808         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3809         { SVM_EXIT_VMRUN,                       "vmrun" },
3810         { SVM_EXIT_VMMCALL,                     "hypercall" },
3811         { SVM_EXIT_VMLOAD,                      "vmload" },
3812         { SVM_EXIT_VMSAVE,                      "vmsave" },
3813         { SVM_EXIT_STGI,                        "stgi" },
3814         { SVM_EXIT_CLGI,                        "clgi" },
3815         { SVM_EXIT_SKINIT,                      "skinit" },
3816         { SVM_EXIT_WBINVD,                      "wbinvd" },
3817         { SVM_EXIT_MONITOR,                     "monitor" },
3818         { SVM_EXIT_MWAIT,                       "mwait" },
3819         { SVM_EXIT_XSETBV,                      "xsetbv" },
3820         { SVM_EXIT_NPF,                         "npf" },
3821         { -1, NULL }
3822 };
3823
3824 static int svm_get_lpage_level(void)
3825 {
3826         return PT_PDPE_LEVEL;
3827 }
3828
3829 static bool svm_rdtscp_supported(void)
3830 {
3831         return false;
3832 }
3833
3834 static bool svm_has_wbinvd_exit(void)
3835 {
3836         return true;
3837 }
3838
3839 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3840 {
3841         struct vcpu_svm *svm = to_svm(vcpu);
3842
3843         set_exception_intercept(svm, NM_VECTOR);
3844         update_cr0_intercept(svm);
3845 }
3846
3847 static struct kvm_x86_ops svm_x86_ops = {
3848         .cpu_has_kvm_support = has_svm,
3849         .disabled_by_bios = is_disabled,
3850         .hardware_setup = svm_hardware_setup,
3851         .hardware_unsetup = svm_hardware_unsetup,
3852         .check_processor_compatibility = svm_check_processor_compat,
3853         .hardware_enable = svm_hardware_enable,
3854         .hardware_disable = svm_hardware_disable,
3855         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3856
3857         .vcpu_create = svm_create_vcpu,
3858         .vcpu_free = svm_free_vcpu,
3859         .vcpu_reset = svm_vcpu_reset,
3860
3861         .prepare_guest_switch = svm_prepare_guest_switch,
3862         .vcpu_load = svm_vcpu_load,
3863         .vcpu_put = svm_vcpu_put,
3864
3865         .set_guest_debug = svm_guest_debug,
3866         .get_msr = svm_get_msr,
3867         .set_msr = svm_set_msr,
3868         .get_segment_base = svm_get_segment_base,
3869         .get_segment = svm_get_segment,
3870         .set_segment = svm_set_segment,
3871         .get_cpl = svm_get_cpl,
3872         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3873         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3874         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3875         .set_cr0 = svm_set_cr0,
3876         .set_cr3 = svm_set_cr3,
3877         .set_cr4 = svm_set_cr4,
3878         .set_efer = svm_set_efer,
3879         .get_idt = svm_get_idt,
3880         .set_idt = svm_set_idt,
3881         .get_gdt = svm_get_gdt,
3882         .set_gdt = svm_set_gdt,
3883         .set_dr7 = svm_set_dr7,
3884         .cache_reg = svm_cache_reg,
3885         .get_rflags = svm_get_rflags,
3886         .set_rflags = svm_set_rflags,
3887         .fpu_activate = svm_fpu_activate,
3888         .fpu_deactivate = svm_fpu_deactivate,
3889
3890         .tlb_flush = svm_flush_tlb,
3891
3892         .run = svm_vcpu_run,
3893         .handle_exit = handle_exit,
3894         .skip_emulated_instruction = skip_emulated_instruction,
3895         .set_interrupt_shadow = svm_set_interrupt_shadow,
3896         .get_interrupt_shadow = svm_get_interrupt_shadow,
3897         .patch_hypercall = svm_patch_hypercall,
3898         .set_irq = svm_set_irq,
3899         .set_nmi = svm_inject_nmi,
3900         .queue_exception = svm_queue_exception,
3901         .cancel_injection = svm_cancel_injection,
3902         .interrupt_allowed = svm_interrupt_allowed,
3903         .nmi_allowed = svm_nmi_allowed,
3904         .get_nmi_mask = svm_get_nmi_mask,
3905         .set_nmi_mask = svm_set_nmi_mask,
3906         .enable_nmi_window = enable_nmi_window,
3907         .enable_irq_window = enable_irq_window,
3908         .update_cr8_intercept = update_cr8_intercept,
3909
3910         .set_tss_addr = svm_set_tss_addr,
3911         .get_tdp_level = get_npt_level,
3912         .get_mt_mask = svm_get_mt_mask,
3913
3914         .get_exit_info = svm_get_exit_info,
3915         .exit_reasons_str = svm_exit_reasons_str,
3916
3917         .get_lpage_level = svm_get_lpage_level,
3918
3919         .cpuid_update = svm_cpuid_update,
3920
3921         .rdtscp_supported = svm_rdtscp_supported,
3922
3923         .set_supported_cpuid = svm_set_supported_cpuid,
3924
3925         .has_wbinvd_exit = svm_has_wbinvd_exit,
3926
3927         .write_tsc_offset = svm_write_tsc_offset,
3928         .adjust_tsc_offset = svm_adjust_tsc_offset,
3929
3930         .set_tdp_cr3 = set_tdp_cr3,
3931 };
3932
3933 static int __init svm_init(void)
3934 {
3935         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3936                         __alignof__(struct vcpu_svm), THIS_MODULE);
3937 }
3938
3939 static void __exit svm_exit(void)
3940 {
3941         kvm_exit();
3942 }
3943
3944 module_init(svm_init)
3945 module_exit(svm_exit)