arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34 #include <asm/kvm_para.h>
  35
  36 #include <asm/virtext.h>
  37 #include "trace.h"
  38
  39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  40
  41 MODULE_AUTHOR("Qumranet");
  42 MODULE_LICENSE("GPL");
  43
  44 #define IOPM_ALLOC_ORDER 2
  45 #define MSRPM_ALLOC_ORDER 1
  46
  47 #define SEG_TYPE_LDT 2
  48 #define SEG_TYPE_BUSY_TSS16 3
  49
  50 #define SVM_FEATURE_NPT            (1 <<  0)
  51 #define SVM_FEATURE_LBRV           (1 <<  1)
  52 #define SVM_FEATURE_SVML           (1 <<  2)
  53 #define SVM_FEATURE_NRIP           (1 <<  3)
  54 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  55
  56 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  57 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  58 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  59
  60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  61
  62 static bool erratum_383_found __read_mostly;
  63
  64 static const u32 host_save_user_msrs[] = {
  65 #ifdef CONFIG_X86_64
  66         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  67         MSR_FS_BASE,
  68 #endif
  69         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  70 };
  71
  72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  73
  74 struct kvm_vcpu;
  75
  76 struct nested_state {
  77         struct vmcb *hsave;
  78         u64 hsave_msr;
  79         u64 vm_cr_msr;
  80         u64 vmcb;
  81
  82         /* These are the merged vectors */
  83         u32 *msrpm;
  84
  85         /* gpa pointers to the real vectors */
  86         u64 vmcb_msrpm;
  87         u64 vmcb_iopm;
  88
  89         /* A VMEXIT is required but not yet emulated */
  90         bool exit_required;
  91
  92         /*
  93          * If we vmexit during an instruction emulation we need this to restore
  94          * the l1 guest rip after the emulation
  95          */
  96         unsigned long vmexit_rip;
  97         unsigned long vmexit_rsp;
  98         unsigned long vmexit_rax;
  99
 100         /* cache for intercepts of the guest */
 101         u32 intercept_cr;
 102         u32 intercept_dr;
 103         u32 intercept_exceptions;
 104         u64 intercept;
 105
 106         /* Nested Paging related state */
 107         u64 nested_cr3;
 108 };
 109
 110 #define MSRPM_OFFSETS   16
 111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 112
 113 struct vcpu_svm {
 114         struct kvm_vcpu vcpu;
 115         struct vmcb *vmcb;
 116         unsigned long vmcb_pa;
 117         struct svm_cpu_data *svm_data;
 118         uint64_t asid_generation;
 119         uint64_t sysenter_esp;
 120         uint64_t sysenter_eip;
 121
 122         u64 next_rip;
 123
 124         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 125         struct {
 126                 u16 fs;
 127                 u16 gs;
 128                 u16 ldt;
 129                 u64 gs_base;
 130         } host;
 131
 132         u32 *msrpm;
 133
 134         struct nested_state nested;
 135
 136         bool nmi_singlestep;
 137
 138         unsigned int3_injected;
 139         unsigned long int3_rip;
 140         u32 apf_reason;
 141 };
 142
 143 #define MSR_INVALID                     0xffffffffU
 144
 145 static struct svm_direct_access_msrs {
 146         u32 index;   /* Index of the MSR */
 147         bool always; /* True if intercept is always on */
 148 } direct_access_msrs[] = {
 149         { .index = MSR_STAR,                            .always = true  },
 150         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 151 #ifdef CONFIG_X86_64
 152         { .index = MSR_GS_BASE,                         .always = true  },
 153         { .index = MSR_FS_BASE,                         .always = true  },
 154         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 155         { .index = MSR_LSTAR,                           .always = true  },
 156         { .index = MSR_CSTAR,                           .always = true  },
 157         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 158 #endif
 159         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 160         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 161         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 162         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 163         { .index = MSR_INVALID,                         .always = false },
 164 };
 165
 166 /* enable NPT for AMD64 and X86 with PAE */
 167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 168 static bool npt_enabled = true;
 169 #else
 170 static bool npt_enabled;
 171 #endif
 172 static int npt = 1;
 173
 174 module_param(npt, int, S_IRUGO);
 175
 176 static int nested = 1;
 177 module_param(nested, int, S_IRUGO);
 178
 179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 180 static void svm_complete_interrupts(struct vcpu_svm *svm);
 181
 182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 183 static int nested_svm_intercept(struct vcpu_svm *svm);
 184 static int nested_svm_vmexit(struct vcpu_svm *svm);
 185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 186                                       bool has_error_code, u32 error_code);
 187
 188 enum {
 189         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 190                             pause filter count */
 191         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 192         VMCB_ASID,       /* ASID */
 193         VMCB_INTR,       /* int_ctl, int_vector */
 194         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 195         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 196         VMCB_DR,         /* DR6, DR7 */
 197         VMCB_DT,         /* GDT, IDT */
 198         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 199         VMCB_CR2,        /* CR2 only */
 200         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 201         VMCB_DIRTY_MAX,
 202 };
 203
 204 /* TPR and CR2 are always written before VMRUN */
 205 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 206
 207 static inline void mark_all_dirty(struct vmcb *vmcb)
 208 {
 209         vmcb->control.clean = 0;
 210 }
 211
 212 static inline void mark_all_clean(struct vmcb *vmcb)
 213 {
 214         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 215                                & ~VMCB_ALWAYS_DIRTY_MASK;
 216 }
 217
 218 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 219 {
 220         vmcb->control.clean &= ~(1 << bit);
 221 }
 222
 223 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 224 {
 225         return container_of(vcpu, struct vcpu_svm, vcpu);
 226 }
 227
 228 static void recalc_intercepts(struct vcpu_svm *svm)
 229 {
 230         struct vmcb_control_area *c, *h;
 231         struct nested_state *g;
 232
 233         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 234
 235         if (!is_guest_mode(&svm->vcpu))
 236                 return;
 237
 238         c = &svm->vmcb->control;
 239         h = &svm->nested.hsave->control;
 240         g = &svm->nested;
 241
 242         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 243         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 244         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 245         c->intercept = h->intercept | g->intercept;
 246 }
 247
 248 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 249 {
 250         if (is_guest_mode(&svm->vcpu))
 251                 return svm->nested.hsave;
 252         else
 253                 return svm->vmcb;
 254 }
 255
 256 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 257 {
 258         struct vmcb *vmcb = get_host_vmcb(svm);
 259
 260         vmcb->control.intercept_cr |= (1U << bit);
 261
 262         recalc_intercepts(svm);
 263 }
 264
 265 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 266 {
 267         struct vmcb *vmcb = get_host_vmcb(svm);
 268
 269         vmcb->control.intercept_cr &= ~(1U << bit);
 270
 271         recalc_intercepts(svm);
 272 }
 273
 274 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 275 {
 276         struct vmcb *vmcb = get_host_vmcb(svm);
 277
 278         return vmcb->control.intercept_cr & (1U << bit);
 279 }
 280
 281 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
 282 {
 283         struct vmcb *vmcb = get_host_vmcb(svm);
 284
 285         vmcb->control.intercept_dr |= (1U << bit);
 286
 287         recalc_intercepts(svm);
 288 }
 289
 290 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
 291 {
 292         struct vmcb *vmcb = get_host_vmcb(svm);
 293
 294         vmcb->control.intercept_dr &= ~(1U << bit);
 295
 296         recalc_intercepts(svm);
 297 }
 298
 299 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 300 {
 301         struct vmcb *vmcb = get_host_vmcb(svm);
 302
 303         vmcb->control.intercept_exceptions |= (1U << bit);
 304
 305         recalc_intercepts(svm);
 306 }
 307
 308 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 309 {
 310         struct vmcb *vmcb = get_host_vmcb(svm);
 311
 312         vmcb->control.intercept_exceptions &= ~(1U << bit);
 313
 314         recalc_intercepts(svm);
 315 }
 316
 317 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 318 {
 319         struct vmcb *vmcb = get_host_vmcb(svm);
 320
 321         vmcb->control.intercept |= (1ULL << bit);
 322
 323         recalc_intercepts(svm);
 324 }
 325
 326 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 327 {
 328         struct vmcb *vmcb = get_host_vmcb(svm);
 329
 330         vmcb->control.intercept &= ~(1ULL << bit);
 331
 332         recalc_intercepts(svm);
 333 }
 334
 335 static inline void enable_gif(struct vcpu_svm *svm)
 336 {
 337         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 338 }
 339
 340 static inline void disable_gif(struct vcpu_svm *svm)
 341 {
 342         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 343 }
 344
 345 static inline bool gif_set(struct vcpu_svm *svm)
 346 {
 347         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 348 }
 349
 350 static unsigned long iopm_base;
 351
 352 struct kvm_ldttss_desc {
 353         u16 limit0;
 354         u16 base0;
 355         unsigned base1:8, type:5, dpl:2, p:1;
 356         unsigned limit1:4, zero0:3, g:1, base2:8;
 357         u32 base3;
 358         u32 zero1;
 359 } __attribute__((packed));
 360
 361 struct svm_cpu_data {
 362         int cpu;
 363
 364         u64 asid_generation;
 365         u32 max_asid;
 366         u32 next_asid;
 367         struct kvm_ldttss_desc *tss_desc;
 368
 369         struct page *save_area;
 370 };
 371
 372 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 373 static uint32_t svm_features;
 374
 375 struct svm_init_data {
 376         int cpu;
 377         int r;
 378 };
 379
 380 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 381
 382 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 383 #define MSRS_RANGE_SIZE 2048
 384 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 385
 386 static u32 svm_msrpm_offset(u32 msr)
 387 {
 388         u32 offset;
 389         int i;
 390
 391         for (i = 0; i < NUM_MSR_MAPS; i++) {
 392                 if (msr < msrpm_ranges[i] ||
 393                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 394                         continue;
 395
 396                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 397                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 398
 399                 /* Now we have the u8 offset - but need the u32 offset */
 400                 return offset / 4;
 401         }
 402
 403         /* MSR not in any range */
 404         return MSR_INVALID;
 405 }
 406
 407 #define MAX_INST_SIZE 15
 408
 409 static inline void clgi(void)
 410 {
 411         asm volatile (__ex(SVM_CLGI));
 412 }
 413
 414 static inline void stgi(void)
 415 {
 416         asm volatile (__ex(SVM_STGI));
 417 }
 418
 419 static inline void invlpga(unsigned long addr, u32 asid)
 420 {
 421         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 422 }
 423
 424 static int get_npt_level(void)
 425 {
 426 #ifdef CONFIG_X86_64
 427         return PT64_ROOT_LEVEL;
 428 #else
 429         return PT32E_ROOT_LEVEL;
 430 #endif
 431 }
 432
 433 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 434 {
 435         vcpu->arch.efer = efer;
 436         if (!npt_enabled && !(efer & EFER_LMA))
 437                 efer &= ~EFER_LME;
 438
 439         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 440         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 441 }
 442
 443 static int is_external_interrupt(u32 info)
 444 {
 445         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 446         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 447 }
 448
 449 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 450 {
 451         struct vcpu_svm *svm = to_svm(vcpu);
 452         u32 ret = 0;
 453
 454         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 455                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 456         return ret & mask;
 457 }
 458
 459 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 460 {
 461         struct vcpu_svm *svm = to_svm(vcpu);
 462
 463         if (mask == 0)
 464                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 465         else
 466                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 467
 468 }
 469
 470 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 471 {
 472         struct vcpu_svm *svm = to_svm(vcpu);
 473
 474         if (svm->vmcb->control.next_rip != 0)
 475                 svm->next_rip = svm->vmcb->control.next_rip;
 476
 477         if (!svm->next_rip) {
 478                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 479                                 EMULATE_DONE)
 480                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 481                 return;
 482         }
 483         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 484                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 485                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 486
 487         kvm_rip_write(vcpu, svm->next_rip);
 488         svm_set_interrupt_shadow(vcpu, 0);
 489 }
 490
 491 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 492                                 bool has_error_code, u32 error_code,
 493                                 bool reinject)
 494 {
 495         struct vcpu_svm *svm = to_svm(vcpu);
 496
 497         /*
 498          * If we are within a nested VM we'd better #VMEXIT and let the guest
 499          * handle the exception
 500          */
 501         if (!reinject &&
 502             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 503                 return;
 504
 505         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 506                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 507
 508                 /*
 509                  * For guest debugging where we have to reinject #BP if some
 510                  * INT3 is guest-owned:
 511                  * Emulate nRIP by moving RIP forward. Will fail if injection
 512                  * raises a fault that is not intercepted. Still better than
 513                  * failing in all cases.
 514                  */
 515                 skip_emulated_instruction(&svm->vcpu);
 516                 rip = kvm_rip_read(&svm->vcpu);
 517                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 518                 svm->int3_injected = rip - old_rip;
 519         }
 520
 521         svm->vmcb->control.event_inj = nr
 522                 | SVM_EVTINJ_VALID
 523                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 524                 | SVM_EVTINJ_TYPE_EXEPT;
 525         svm->vmcb->control.event_inj_err = error_code;
 526 }
 527
 528 static void svm_init_erratum_383(void)
 529 {
 530         u32 low, high;
 531         int err;
 532         u64 val;
 533
 534         if (!cpu_has_amd_erratum(amd_erratum_383))
 535                 return;
 536
 537         /* Use _safe variants to not break nested virtualization */
 538         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 539         if (err)
 540                 return;
 541
 542         val |= (1ULL << 47);
 543
 544         low  = lower_32_bits(val);
 545         high = upper_32_bits(val);
 546
 547         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 548
 549         erratum_383_found = true;
 550 }
 551
 552 static int has_svm(void)
 553 {
 554         const char *msg;
 555
 556         if (!cpu_has_svm(&msg)) {
 557                 printk(KERN_INFO "has_svm: %s\n", msg);
 558                 return 0;
 559         }
 560
 561         return 1;
 562 }
 563
 564 static void svm_hardware_disable(void *garbage)
 565 {
 566         cpu_svm_disable();
 567 }
 568
 569 static int svm_hardware_enable(void *garbage)
 570 {
 571
 572         struct svm_cpu_data *sd;
 573         uint64_t efer;
 574         struct desc_ptr gdt_descr;
 575         struct desc_struct *gdt;
 576         int me = raw_smp_processor_id();
 577
 578         rdmsrl(MSR_EFER, efer);
 579         if (efer & EFER_SVME)
 580                 return -EBUSY;
 581
 582         if (!has_svm()) {
 583                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 584                        me);
 585                 return -EINVAL;
 586         }
 587         sd = per_cpu(svm_data, me);
 588
 589         if (!sd) {
 590                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 591                        me);
 592                 return -EINVAL;
 593         }
 594
 595         sd->asid_generation = 1;
 596         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 597         sd->next_asid = sd->max_asid + 1;
 598
 599         native_store_gdt(&gdt_descr);
 600         gdt = (struct desc_struct *)gdt_descr.address;
 601         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 602
 603         wrmsrl(MSR_EFER, efer | EFER_SVME);
 604
 605         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 606
 607         svm_init_erratum_383();
 608
 609         return 0;
 610 }
 611
 612 static void svm_cpu_uninit(int cpu)
 613 {
 614         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 615
 616         if (!sd)
 617                 return;
 618
 619         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 620         __free_page(sd->save_area);
 621         kfree(sd);
 622 }
 623
 624 static int svm_cpu_init(int cpu)
 625 {
 626         struct svm_cpu_data *sd;
 627         int r;
 628
 629         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 630         if (!sd)
 631                 return -ENOMEM;
 632         sd->cpu = cpu;
 633         sd->save_area = alloc_page(GFP_KERNEL);
 634         r = -ENOMEM;
 635         if (!sd->save_area)
 636                 goto err_1;
 637
 638         per_cpu(svm_data, cpu) = sd;
 639
 640         return 0;
 641
 642 err_1:
 643         kfree(sd);
 644         return r;
 645
 646 }
 647
 648 static bool valid_msr_intercept(u32 index)
 649 {
 650         int i;
 651
 652         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 653                 if (direct_access_msrs[i].index == index)
 654                         return true;
 655
 656         return false;
 657 }
 658
 659 static void set_msr_interception(u32 *msrpm, unsigned msr,
 660                                  int read, int write)
 661 {
 662         u8 bit_read, bit_write;
 663         unsigned long tmp;
 664         u32 offset;
 665
 666         /*
 667          * If this warning triggers extend the direct_access_msrs list at the
 668          * beginning of the file
 669          */
 670         WARN_ON(!valid_msr_intercept(msr));
 671
 672         offset    = svm_msrpm_offset(msr);
 673         bit_read  = 2 * (msr & 0x0f);
 674         bit_write = 2 * (msr & 0x0f) + 1;
 675         tmp       = msrpm[offset];
 676
 677         BUG_ON(offset == MSR_INVALID);
 678
 679         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 680         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 681
 682         msrpm[offset] = tmp;
 683 }
 684
 685 static void svm_vcpu_init_msrpm(u32 *msrpm)
 686 {
 687         int i;
 688
 689         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 690
 691         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 692                 if (!direct_access_msrs[i].always)
 693                         continue;
 694
 695                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 696         }
 697 }
 698
 699 static void add_msr_offset(u32 offset)
 700 {
 701         int i;
 702
 703         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 704
 705                 /* Offset already in list? */
 706                 if (msrpm_offsets[i] == offset)
 707                         return;
 708
 709                 /* Slot used by another offset? */
 710                 if (msrpm_offsets[i] != MSR_INVALID)
 711                         continue;
 712
 713                 /* Add offset to list */
 714                 msrpm_offsets[i] = offset;
 715
 716                 return;
 717         }
 718
 719         /*
 720          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 721          * increase MSRPM_OFFSETS in this case.
 722          */
 723         BUG();
 724 }
 725
 726 static void init_msrpm_offsets(void)
 727 {
 728         int i;
 729
 730         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 731
 732         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 733                 u32 offset;
 734
 735                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 736                 BUG_ON(offset == MSR_INVALID);
 737
 738                 add_msr_offset(offset);
 739         }
 740 }
 741
 742 static void svm_enable_lbrv(struct vcpu_svm *svm)
 743 {
 744         u32 *msrpm = svm->msrpm;
 745
 746         svm->vmcb->control.lbr_ctl = 1;
 747         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 748         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 749         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 750         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 751 }
 752
 753 static void svm_disable_lbrv(struct vcpu_svm *svm)
 754 {
 755         u32 *msrpm = svm->msrpm;
 756
 757         svm->vmcb->control.lbr_ctl = 0;
 758         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 759         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 760         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 761         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 762 }
 763
 764 static __init int svm_hardware_setup(void)
 765 {
 766         int cpu;
 767         struct page *iopm_pages;
 768         void *iopm_va;
 769         int r;
 770
 771         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 772
 773         if (!iopm_pages)
 774                 return -ENOMEM;
 775
 776         iopm_va = page_address(iopm_pages);
 777         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 778         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 779
 780         init_msrpm_offsets();
 781
 782         if (boot_cpu_has(X86_FEATURE_NX))
 783                 kvm_enable_efer_bits(EFER_NX);
 784
 785         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 786                 kvm_enable_efer_bits(EFER_FFXSR);
 787
 788         if (nested) {
 789                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 790                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 791         }
 792
 793         for_each_possible_cpu(cpu) {
 794                 r = svm_cpu_init(cpu);
 795                 if (r)
 796                         goto err;
 797         }
 798
 799         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 800
 801         if (!boot_cpu_has(X86_FEATURE_NPT))
 802                 npt_enabled = false;
 803
 804         if (npt_enabled && !npt) {
 805                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 806                 npt_enabled = false;
 807         }
 808
 809         if (npt_enabled) {
 810                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 811                 kvm_enable_tdp();
 812         } else
 813                 kvm_disable_tdp();
 814
 815         return 0;
 816
 817 err:
 818         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 819         iopm_base = 0;
 820         return r;
 821 }
 822
 823 static __exit void svm_hardware_unsetup(void)
 824 {
 825         int cpu;
 826
 827         for_each_possible_cpu(cpu)
 828                 svm_cpu_uninit(cpu);
 829
 830         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 831         iopm_base = 0;
 832 }
 833
 834 static void init_seg(struct vmcb_seg *seg)
 835 {
 836         seg->selector = 0;
 837         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 838                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 839         seg->limit = 0xffff;
 840         seg->base = 0;
 841 }
 842
 843 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 844 {
 845         seg->selector = 0;
 846         seg->attrib = SVM_SELECTOR_P_MASK | type;
 847         seg->limit = 0xffff;
 848         seg->base = 0;
 849 }
 850
 851 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 852 {
 853         struct vcpu_svm *svm = to_svm(vcpu);
 854         u64 g_tsc_offset = 0;
 855
 856         if (is_guest_mode(vcpu)) {
 857                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 858                                svm->nested.hsave->control.tsc_offset;
 859                 svm->nested.hsave->control.tsc_offset = offset;
 860         }
 861
 862         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 863
 864         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 865 }
 866
 867 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
 868 {
 869         struct vcpu_svm *svm = to_svm(vcpu);
 870
 871         svm->vmcb->control.tsc_offset += adjustment;
 872         if (is_guest_mode(vcpu))
 873                 svm->nested.hsave->control.tsc_offset += adjustment;
 874         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 875 }
 876
 877 static void init_vmcb(struct vcpu_svm *svm)
 878 {
 879         struct vmcb_control_area *control = &svm->vmcb->control;
 880         struct vmcb_save_area *save = &svm->vmcb->save;
 881
 882         svm->vcpu.fpu_active = 1;
 883         svm->vcpu.arch.hflags = 0;
 884
 885         set_cr_intercept(svm, INTERCEPT_CR0_READ);
 886         set_cr_intercept(svm, INTERCEPT_CR3_READ);
 887         set_cr_intercept(svm, INTERCEPT_CR4_READ);
 888         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
 889         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
 890         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
 891         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
 892
 893         set_dr_intercept(svm, INTERCEPT_DR0_READ);
 894         set_dr_intercept(svm, INTERCEPT_DR1_READ);
 895         set_dr_intercept(svm, INTERCEPT_DR2_READ);
 896         set_dr_intercept(svm, INTERCEPT_DR3_READ);
 897         set_dr_intercept(svm, INTERCEPT_DR4_READ);
 898         set_dr_intercept(svm, INTERCEPT_DR5_READ);
 899         set_dr_intercept(svm, INTERCEPT_DR6_READ);
 900         set_dr_intercept(svm, INTERCEPT_DR7_READ);
 901
 902         set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
 903         set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
 904         set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
 905         set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
 906         set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
 907         set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
 908         set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
 909         set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
 910
 911         set_exception_intercept(svm, PF_VECTOR);
 912         set_exception_intercept(svm, UD_VECTOR);
 913         set_exception_intercept(svm, MC_VECTOR);
 914
 915         set_intercept(svm, INTERCEPT_INTR);
 916         set_intercept(svm, INTERCEPT_NMI);
 917         set_intercept(svm, INTERCEPT_SMI);
 918         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
 919         set_intercept(svm, INTERCEPT_CPUID);
 920         set_intercept(svm, INTERCEPT_INVD);
 921         set_intercept(svm, INTERCEPT_HLT);
 922         set_intercept(svm, INTERCEPT_INVLPG);
 923         set_intercept(svm, INTERCEPT_INVLPGA);
 924         set_intercept(svm, INTERCEPT_IOIO_PROT);
 925         set_intercept(svm, INTERCEPT_MSR_PROT);
 926         set_intercept(svm, INTERCEPT_TASK_SWITCH);
 927         set_intercept(svm, INTERCEPT_SHUTDOWN);
 928         set_intercept(svm, INTERCEPT_VMRUN);
 929         set_intercept(svm, INTERCEPT_VMMCALL);
 930         set_intercept(svm, INTERCEPT_VMLOAD);
 931         set_intercept(svm, INTERCEPT_VMSAVE);
 932         set_intercept(svm, INTERCEPT_STGI);
 933         set_intercept(svm, INTERCEPT_CLGI);
 934         set_intercept(svm, INTERCEPT_SKINIT);
 935         set_intercept(svm, INTERCEPT_WBINVD);
 936         set_intercept(svm, INTERCEPT_MONITOR);
 937         set_intercept(svm, INTERCEPT_MWAIT);
 938         set_intercept(svm, INTERCEPT_XSETBV);
 939
 940         control->iopm_base_pa = iopm_base;
 941         control->msrpm_base_pa = __pa(svm->msrpm);
 942         control->int_ctl = V_INTR_MASKING_MASK;
 943
 944         init_seg(&save->es);
 945         init_seg(&save->ss);
 946         init_seg(&save->ds);
 947         init_seg(&save->fs);
 948         init_seg(&save->gs);
 949
 950         save->cs.selector = 0xf000;
 951         /* Executable/Readable Code Segment */
 952         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 953                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 954         save->cs.limit = 0xffff;
 955         /*
 956          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 957          * be consistent with it.
 958          *
 959          * Replace when we have real mode working for vmx.
 960          */
 961         save->cs.base = 0xf0000;
 962
 963         save->gdtr.limit = 0xffff;
 964         save->idtr.limit = 0xffff;
 965
 966         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 967         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 968
 969         svm_set_efer(&svm->vcpu, 0);
 970         save->dr6 = 0xffff0ff0;
 971         save->dr7 = 0x400;
 972         save->rflags = 2;
 973         save->rip = 0x0000fff0;
 974         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 975
 976         /*
 977          * This is the guest-visible cr0 value.
 978          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 979          */
 980         svm->vcpu.arch.cr0 = 0;
 981         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
 982
 983         save->cr4 = X86_CR4_PAE;
 984         /* rdx = ?? */
 985
 986         if (npt_enabled) {
 987                 /* Setup VMCB for Nested Paging */
 988                 control->nested_ctl = 1;
 989                 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
 990                 clr_intercept(svm, INTERCEPT_INVLPG);
 991                 clr_exception_intercept(svm, PF_VECTOR);
 992                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
 993                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
 994                 save->g_pat = 0x0007040600070406ULL;
 995                 save->cr3 = 0;
 996                 save->cr4 = 0;
 997         }
 998         svm->asid_generation = 0;
 999
1000         svm->nested.vmcb = 0;
1001         svm->vcpu.arch.hflags = 0;
1002
1003         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1004                 control->pause_filter_count = 3000;
1005                 set_intercept(svm, INTERCEPT_PAUSE);
1006         }
1007
1008         mark_all_dirty(svm->vmcb);
1009
1010         enable_gif(svm);
1011 }
1012
1013 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1014 {
1015         struct vcpu_svm *svm = to_svm(vcpu);
1016
1017         init_vmcb(svm);
1018
1019         if (!kvm_vcpu_is_bsp(vcpu)) {
1020                 kvm_rip_write(vcpu, 0);
1021                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1022                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1023         }
1024         vcpu->arch.regs_avail = ~0;
1025         vcpu->arch.regs_dirty = ~0;
1026
1027         return 0;
1028 }
1029
1030 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1031 {
1032         struct vcpu_svm *svm;
1033         struct page *page;
1034         struct page *msrpm_pages;
1035         struct page *hsave_page;
1036         struct page *nested_msrpm_pages;
1037         int err;
1038
1039         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1040         if (!svm) {
1041                 err = -ENOMEM;
1042                 goto out;
1043         }
1044
1045         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1046         if (err)
1047                 goto free_svm;
1048
1049         err = -ENOMEM;
1050         page = alloc_page(GFP_KERNEL);
1051         if (!page)
1052                 goto uninit;
1053
1054         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1055         if (!msrpm_pages)
1056                 goto free_page1;
1057
1058         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1059         if (!nested_msrpm_pages)
1060                 goto free_page2;
1061
1062         hsave_page = alloc_page(GFP_KERNEL);
1063         if (!hsave_page)
1064                 goto free_page3;
1065
1066         svm->nested.hsave = page_address(hsave_page);
1067
1068         svm->msrpm = page_address(msrpm_pages);
1069         svm_vcpu_init_msrpm(svm->msrpm);
1070
1071         svm->nested.msrpm = page_address(nested_msrpm_pages);
1072         svm_vcpu_init_msrpm(svm->nested.msrpm);
1073
1074         svm->vmcb = page_address(page);
1075         clear_page(svm->vmcb);
1076         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1077         svm->asid_generation = 0;
1078         init_vmcb(svm);
1079         kvm_write_tsc(&svm->vcpu, 0);
1080
1081         err = fx_init(&svm->vcpu);
1082         if (err)
1083                 goto free_page4;
1084
1085         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1086         if (kvm_vcpu_is_bsp(&svm->vcpu))
1087                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1088
1089         return &svm->vcpu;
1090
1091 free_page4:
1092         __free_page(hsave_page);
1093 free_page3:
1094         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1095 free_page2:
1096         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1097 free_page1:
1098         __free_page(page);
1099 uninit:
1100         kvm_vcpu_uninit(&svm->vcpu);
1101 free_svm:
1102         kmem_cache_free(kvm_vcpu_cache, svm);
1103 out:
1104         return ERR_PTR(err);
1105 }
1106
1107 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1108 {
1109         struct vcpu_svm *svm = to_svm(vcpu);
1110
1111         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1112         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1113         __free_page(virt_to_page(svm->nested.hsave));
1114         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1115         kvm_vcpu_uninit(vcpu);
1116         kmem_cache_free(kvm_vcpu_cache, svm);
1117 }
1118
1119 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1120 {
1121         struct vcpu_svm *svm = to_svm(vcpu);
1122         int i;
1123
1124         if (unlikely(cpu != vcpu->cpu)) {
1125                 svm->asid_generation = 0;
1126                 mark_all_dirty(svm->vmcb);
1127         }
1128
1129 #ifdef CONFIG_X86_64
1130         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1131 #endif
1132         savesegment(fs, svm->host.fs);
1133         savesegment(gs, svm->host.gs);
1134         svm->host.ldt = kvm_read_ldt();
1135
1136         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1137                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1138 }
1139
1140 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1141 {
1142         struct vcpu_svm *svm = to_svm(vcpu);
1143         int i;
1144
1145         ++vcpu->stat.host_state_reload;
1146         kvm_load_ldt(svm->host.ldt);
1147 #ifdef CONFIG_X86_64
1148         loadsegment(fs, svm->host.fs);
1149         load_gs_index(svm->host.gs);
1150         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1151 #else
1152         loadsegment(gs, svm->host.gs);
1153 #endif
1154         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1155                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1156 }
1157
1158 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1159 {
1160         return to_svm(vcpu)->vmcb->save.rflags;
1161 }
1162
1163 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1164 {
1165         to_svm(vcpu)->vmcb->save.rflags = rflags;
1166 }
1167
1168 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1169 {
1170         switch (reg) {
1171         case VCPU_EXREG_PDPTR:
1172                 BUG_ON(!npt_enabled);
1173                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1174                 break;
1175         default:
1176                 BUG();
1177         }
1178 }
1179
1180 static void svm_set_vintr(struct vcpu_svm *svm)
1181 {
1182         set_intercept(svm, INTERCEPT_VINTR);
1183 }
1184
1185 static void svm_clear_vintr(struct vcpu_svm *svm)
1186 {
1187         clr_intercept(svm, INTERCEPT_VINTR);
1188 }
1189
1190 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1191 {
1192         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1193
1194         switch (seg) {
1195         case VCPU_SREG_CS: return &save->cs;
1196         case VCPU_SREG_DS: return &save->ds;
1197         case VCPU_SREG_ES: return &save->es;
1198         case VCPU_SREG_FS: return &save->fs;
1199         case VCPU_SREG_GS: return &save->gs;
1200         case VCPU_SREG_SS: return &save->ss;
1201         case VCPU_SREG_TR: return &save->tr;
1202         case VCPU_SREG_LDTR: return &save->ldtr;
1203         }
1204         BUG();
1205         return NULL;
1206 }
1207
1208 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1209 {
1210         struct vmcb_seg *s = svm_seg(vcpu, seg);
1211
1212         return s->base;
1213 }
1214
1215 static void svm_get_segment(struct kvm_vcpu *vcpu,
1216                             struct kvm_segment *var, int seg)
1217 {
1218         struct vmcb_seg *s = svm_seg(vcpu, seg);
1219
1220         var->base = s->base;
1221         var->limit = s->limit;
1222         var->selector = s->selector;
1223         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1224         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1225         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1226         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1227         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1228         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1229         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1230         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1231
1232         /*
1233          * AMD's VMCB does not have an explicit unusable field, so emulate it
1234          * for cross vendor migration purposes by "not present"
1235          */
1236         var->unusable = !var->present || (var->type == 0);
1237
1238         switch (seg) {
1239         case VCPU_SREG_CS:
1240                 /*
1241                  * SVM always stores 0 for the 'G' bit in the CS selector in
1242                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1243                  * Intel's VMENTRY has a check on the 'G' bit.
1244                  */
1245                 var->g = s->limit > 0xfffff;
1246                 break;
1247         case VCPU_SREG_TR:
1248                 /*
1249                  * Work around a bug where the busy flag in the tr selector
1250                  * isn't exposed
1251                  */
1252                 var->type |= 0x2;
1253                 break;
1254         case VCPU_SREG_DS:
1255         case VCPU_SREG_ES:
1256         case VCPU_SREG_FS:
1257         case VCPU_SREG_GS:
1258                 /*
1259                  * The accessed bit must always be set in the segment
1260                  * descriptor cache, although it can be cleared in the
1261                  * descriptor, the cached bit always remains at 1. Since
1262                  * Intel has a check on this, set it here to support
1263                  * cross-vendor migration.
1264                  */
1265                 if (!var->unusable)
1266                         var->type |= 0x1;
1267                 break;
1268         case VCPU_SREG_SS:
1269                 /*
1270                  * On AMD CPUs sometimes the DB bit in the segment
1271                  * descriptor is left as 1, although the whole segment has
1272                  * been made unusable. Clear it here to pass an Intel VMX
1273                  * entry check when cross vendor migrating.
1274                  */
1275                 if (var->unusable)
1276                         var->db = 0;
1277                 break;
1278         }
1279 }
1280
1281 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1282 {
1283         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1284
1285         return save->cpl;
1286 }
1287
1288 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1289 {
1290         struct vcpu_svm *svm = to_svm(vcpu);
1291
1292         dt->size = svm->vmcb->save.idtr.limit;
1293         dt->address = svm->vmcb->save.idtr.base;
1294 }
1295
1296 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1297 {
1298         struct vcpu_svm *svm = to_svm(vcpu);
1299
1300         svm->vmcb->save.idtr.limit = dt->size;
1301         svm->vmcb->save.idtr.base = dt->address ;
1302         mark_dirty(svm->vmcb, VMCB_DT);
1303 }
1304
1305 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1306 {
1307         struct vcpu_svm *svm = to_svm(vcpu);
1308
1309         dt->size = svm->vmcb->save.gdtr.limit;
1310         dt->address = svm->vmcb->save.gdtr.base;
1311 }
1312
1313 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1314 {
1315         struct vcpu_svm *svm = to_svm(vcpu);
1316
1317         svm->vmcb->save.gdtr.limit = dt->size;
1318         svm->vmcb->save.gdtr.base = dt->address ;
1319         mark_dirty(svm->vmcb, VMCB_DT);
1320 }
1321
1322 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1323 {
1324 }
1325
1326 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1327 {
1328 }
1329
1330 static void update_cr0_intercept(struct vcpu_svm *svm)
1331 {
1332         ulong gcr0 = svm->vcpu.arch.cr0;
1333         u64 *hcr0 = &svm->vmcb->save.cr0;
1334
1335         if (!svm->vcpu.fpu_active)
1336                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1337         else
1338                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1339                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1340
1341         mark_dirty(svm->vmcb, VMCB_CR);
1342
1343         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1344                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1345                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1346         } else {
1347                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1348                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1349         }
1350 }
1351
1352 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1353 {
1354         struct vcpu_svm *svm = to_svm(vcpu);
1355
1356         if (is_guest_mode(vcpu)) {
1357                 /*
1358                  * We are here because we run in nested mode, the host kvm
1359                  * intercepts cr0 writes but the l1 hypervisor does not.
1360                  * But the L1 hypervisor may intercept selective cr0 writes.
1361                  * This needs to be checked here.
1362                  */
1363                 unsigned long old, new;
1364
1365                 /* Remove bits that would trigger a real cr0 write intercept */
1366                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1367                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1368
1369                 if (old == new) {
1370                         /* cr0 write with ts and mp unchanged */
1371                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1372                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1373                                 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1374                                 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1375                                 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1376                                 return;
1377                         }
1378                 }
1379         }
1380
1381 #ifdef CONFIG_X86_64
1382         if (vcpu->arch.efer & EFER_LME) {
1383                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1384                         vcpu->arch.efer |= EFER_LMA;
1385                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1386                 }
1387
1388                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1389                         vcpu->arch.efer &= ~EFER_LMA;
1390                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1391                 }
1392         }
1393 #endif
1394         vcpu->arch.cr0 = cr0;
1395
1396         if (!npt_enabled)
1397                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1398
1399         if (!vcpu->fpu_active)
1400                 cr0 |= X86_CR0_TS;
1401         /*
1402          * re-enable caching here because the QEMU bios
1403          * does not do it - this results in some delay at
1404          * reboot
1405          */
1406         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1407         svm->vmcb->save.cr0 = cr0;
1408         mark_dirty(svm->vmcb, VMCB_CR);
1409         update_cr0_intercept(svm);
1410 }
1411
1412 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1413 {
1414         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1415         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1416
1417         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1418                 svm_flush_tlb(vcpu);
1419
1420         vcpu->arch.cr4 = cr4;
1421         if (!npt_enabled)
1422                 cr4 |= X86_CR4_PAE;
1423         cr4 |= host_cr4_mce;
1424         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1425         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1426 }
1427
1428 static void svm_set_segment(struct kvm_vcpu *vcpu,
1429                             struct kvm_segment *var, int seg)
1430 {
1431         struct vcpu_svm *svm = to_svm(vcpu);
1432         struct vmcb_seg *s = svm_seg(vcpu, seg);
1433
1434         s->base = var->base;
1435         s->limit = var->limit;
1436         s->selector = var->selector;
1437         if (var->unusable)
1438                 s->attrib = 0;
1439         else {
1440                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1441                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1442                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1443                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1444                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1445                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1446                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1447                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1448         }
1449         if (seg == VCPU_SREG_CS)
1450                 svm->vmcb->save.cpl
1451                         = (svm->vmcb->save.cs.attrib
1452                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1453
1454         mark_dirty(svm->vmcb, VMCB_SEG);
1455 }
1456
1457 static void update_db_intercept(struct kvm_vcpu *vcpu)
1458 {
1459         struct vcpu_svm *svm = to_svm(vcpu);
1460
1461         clr_exception_intercept(svm, DB_VECTOR);
1462         clr_exception_intercept(svm, BP_VECTOR);
1463
1464         if (svm->nmi_singlestep)
1465                 set_exception_intercept(svm, DB_VECTOR);
1466
1467         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1468                 if (vcpu->guest_debug &
1469                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1470                         set_exception_intercept(svm, DB_VECTOR);
1471                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1472                         set_exception_intercept(svm, BP_VECTOR);
1473         } else
1474                 vcpu->guest_debug = 0;
1475 }
1476
1477 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1478 {
1479         struct vcpu_svm *svm = to_svm(vcpu);
1480
1481         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1482                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1483         else
1484                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1485
1486         mark_dirty(svm->vmcb, VMCB_DR);
1487
1488         update_db_intercept(vcpu);
1489 }
1490
1491 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1492 {
1493         if (sd->next_asid > sd->max_asid) {
1494                 ++sd->asid_generation;
1495                 sd->next_asid = 1;
1496                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1497         }
1498
1499         svm->asid_generation = sd->asid_generation;
1500         svm->vmcb->control.asid = sd->next_asid++;
1501
1502         mark_dirty(svm->vmcb, VMCB_ASID);
1503 }
1504
1505 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1506 {
1507         struct vcpu_svm *svm = to_svm(vcpu);
1508
1509         svm->vmcb->save.dr7 = value;
1510         mark_dirty(svm->vmcb, VMCB_DR);
1511 }
1512
1513 static int pf_interception(struct vcpu_svm *svm)
1514 {
1515         u64 fault_address = svm->vmcb->control.exit_info_2;
1516         u32 error_code;
1517         int r = 1;
1518
1519         switch (svm->apf_reason) {
1520         default:
1521                 error_code = svm->vmcb->control.exit_info_1;
1522
1523                 trace_kvm_page_fault(fault_address, error_code);
1524                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1525                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1526                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1527                 break;
1528         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1529                 svm->apf_reason = 0;
1530                 local_irq_disable();
1531                 kvm_async_pf_task_wait(fault_address);
1532                 local_irq_enable();
1533                 break;
1534         case KVM_PV_REASON_PAGE_READY:
1535                 svm->apf_reason = 0;
1536                 local_irq_disable();
1537                 kvm_async_pf_task_wake(fault_address);
1538                 local_irq_enable();
1539                 break;
1540         }
1541         return r;
1542 }
1543
1544 static int db_interception(struct vcpu_svm *svm)
1545 {
1546         struct kvm_run *kvm_run = svm->vcpu.run;
1547
1548         if (!(svm->vcpu.guest_debug &
1549               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1550                 !svm->nmi_singlestep) {
1551                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1552                 return 1;
1553         }
1554
1555         if (svm->nmi_singlestep) {
1556                 svm->nmi_singlestep = false;
1557                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1558                         svm->vmcb->save.rflags &=
1559                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1560                 update_db_intercept(&svm->vcpu);
1561         }
1562
1563         if (svm->vcpu.guest_debug &
1564             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1565                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1566                 kvm_run->debug.arch.pc =
1567                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1568                 kvm_run->debug.arch.exception = DB_VECTOR;
1569                 return 0;
1570         }
1571
1572         return 1;
1573 }
1574
1575 static int bp_interception(struct vcpu_svm *svm)
1576 {
1577         struct kvm_run *kvm_run = svm->vcpu.run;
1578
1579         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1580         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1581         kvm_run->debug.arch.exception = BP_VECTOR;
1582         return 0;
1583 }
1584
1585 static int ud_interception(struct vcpu_svm *svm)
1586 {
1587         int er;
1588
1589         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1590         if (er != EMULATE_DONE)
1591                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1592         return 1;
1593 }
1594
1595 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1596 {
1597         struct vcpu_svm *svm = to_svm(vcpu);
1598
1599         clr_exception_intercept(svm, NM_VECTOR);
1600
1601         svm->vcpu.fpu_active = 1;
1602         update_cr0_intercept(svm);
1603 }
1604
1605 static int nm_interception(struct vcpu_svm *svm)
1606 {
1607         svm_fpu_activate(&svm->vcpu);
1608         return 1;
1609 }
1610
1611 static bool is_erratum_383(void)
1612 {
1613         int err, i;
1614         u64 value;
1615
1616         if (!erratum_383_found)
1617                 return false;
1618
1619         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1620         if (err)
1621                 return false;
1622
1623         /* Bit 62 may or may not be set for this mce */
1624         value &= ~(1ULL << 62);
1625
1626         if (value != 0xb600000000010015ULL)
1627                 return false;
1628
1629         /* Clear MCi_STATUS registers */
1630         for (i = 0; i < 6; ++i)
1631                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1632
1633         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1634         if (!err) {
1635                 u32 low, high;
1636
1637                 value &= ~(1ULL << 2);
1638                 low    = lower_32_bits(value);
1639                 high   = upper_32_bits(value);
1640
1641                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1642         }
1643
1644         /* Flush tlb to evict multi-match entries */
1645         __flush_tlb_all();
1646
1647         return true;
1648 }
1649
1650 static void svm_handle_mce(struct vcpu_svm *svm)
1651 {
1652         if (is_erratum_383()) {
1653                 /*
1654                  * Erratum 383 triggered. Guest state is corrupt so kill the
1655                  * guest.
1656                  */
1657                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1658
1659                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1660
1661                 return;
1662         }
1663
1664         /*
1665          * On an #MC intercept the MCE handler is not called automatically in
1666          * the host. So do it by hand here.
1667          */
1668         asm volatile (
1669                 "int $0x12\n");
1670         /* not sure if we ever come back to this point */
1671
1672         return;
1673 }
1674
1675 static int mc_interception(struct vcpu_svm *svm)
1676 {
1677         return 1;
1678 }
1679
1680 static int shutdown_interception(struct vcpu_svm *svm)
1681 {
1682         struct kvm_run *kvm_run = svm->vcpu.run;
1683
1684         /*
1685          * VMCB is undefined after a SHUTDOWN intercept
1686          * so reinitialize it.
1687          */
1688         clear_page(svm->vmcb);
1689         init_vmcb(svm);
1690
1691         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1692         return 0;
1693 }
1694
1695 static int io_interception(struct vcpu_svm *svm)
1696 {
1697         struct kvm_vcpu *vcpu = &svm->vcpu;
1698         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1699         int size, in, string;
1700         unsigned port;
1701
1702         ++svm->vcpu.stat.io_exits;
1703         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1704         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1705         if (string || in)
1706                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1707
1708         port = io_info >> 16;
1709         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1710         svm->next_rip = svm->vmcb->control.exit_info_2;
1711         skip_emulated_instruction(&svm->vcpu);
1712
1713         return kvm_fast_pio_out(vcpu, size, port);
1714 }
1715
1716 static int nmi_interception(struct vcpu_svm *svm)
1717 {
1718         return 1;
1719 }
1720
1721 static int intr_interception(struct vcpu_svm *svm)
1722 {
1723         ++svm->vcpu.stat.irq_exits;
1724         return 1;
1725 }
1726
1727 static int nop_on_interception(struct vcpu_svm *svm)
1728 {
1729         return 1;
1730 }
1731
1732 static int halt_interception(struct vcpu_svm *svm)
1733 {
1734         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1735         skip_emulated_instruction(&svm->vcpu);
1736         return kvm_emulate_halt(&svm->vcpu);
1737 }
1738
1739 static int vmmcall_interception(struct vcpu_svm *svm)
1740 {
1741         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1742         skip_emulated_instruction(&svm->vcpu);
1743         kvm_emulate_hypercall(&svm->vcpu);
1744         return 1;
1745 }
1746
1747 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1748 {
1749         struct vcpu_svm *svm = to_svm(vcpu);
1750
1751         return svm->nested.nested_cr3;
1752 }
1753
1754 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1755                                    unsigned long root)
1756 {
1757         struct vcpu_svm *svm = to_svm(vcpu);
1758
1759         svm->vmcb->control.nested_cr3 = root;
1760         mark_dirty(svm->vmcb, VMCB_NPT);
1761         svm_flush_tlb(vcpu);
1762 }
1763
1764 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1765                                        struct x86_exception *fault)
1766 {
1767         struct vcpu_svm *svm = to_svm(vcpu);
1768
1769         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1770         svm->vmcb->control.exit_code_hi = 0;
1771         svm->vmcb->control.exit_info_1 = fault->error_code;
1772         svm->vmcb->control.exit_info_2 = fault->address;
1773
1774         nested_svm_vmexit(svm);
1775 }
1776
1777 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1778 {
1779         int r;
1780
1781         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1782
1783         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1784         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1785         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1786         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1787         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1788
1789         return r;
1790 }
1791
1792 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1793 {
1794         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1795 }
1796
1797 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1798 {
1799         if (!(svm->vcpu.arch.efer & EFER_SVME)
1800             || !is_paging(&svm->vcpu)) {
1801                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1802                 return 1;
1803         }
1804
1805         if (svm->vmcb->save.cpl) {
1806                 kvm_inject_gp(&svm->vcpu, 0);
1807                 return 1;
1808         }
1809
1810        return 0;
1811 }
1812
1813 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1814                                       bool has_error_code, u32 error_code)
1815 {
1816         int vmexit;
1817
1818         if (!is_guest_mode(&svm->vcpu))
1819                 return 0;
1820
1821         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1822         svm->vmcb->control.exit_code_hi = 0;
1823         svm->vmcb->control.exit_info_1 = error_code;
1824         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1825
1826         vmexit = nested_svm_intercept(svm);
1827         if (vmexit == NESTED_EXIT_DONE)
1828                 svm->nested.exit_required = true;
1829
1830         return vmexit;
1831 }
1832
1833 /* This function returns true if it is save to enable the irq window */
1834 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1835 {
1836         if (!is_guest_mode(&svm->vcpu))
1837                 return true;
1838
1839         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1840                 return true;
1841
1842         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1843                 return false;
1844
1845         /*
1846          * if vmexit was already requested (by intercepted exception
1847          * for instance) do not overwrite it with "external interrupt"
1848          * vmexit.
1849          */
1850         if (svm->nested.exit_required)
1851                 return false;
1852
1853         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1854         svm->vmcb->control.exit_info_1 = 0;
1855         svm->vmcb->control.exit_info_2 = 0;
1856
1857         if (svm->nested.intercept & 1ULL) {
1858                 /*
1859                  * The #vmexit can't be emulated here directly because this
1860                  * code path runs with irqs and preemtion disabled. A
1861                  * #vmexit emulation might sleep. Only signal request for
1862                  * the #vmexit here.
1863                  */
1864                 svm->nested.exit_required = true;
1865                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1866                 return false;
1867         }
1868
1869         return true;
1870 }
1871
1872 /* This function returns true if it is save to enable the nmi window */
1873 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1874 {
1875         if (!is_guest_mode(&svm->vcpu))
1876                 return true;
1877
1878         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1879                 return true;
1880
1881         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1882         svm->nested.exit_required = true;
1883
1884         return false;
1885 }
1886
1887 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1888 {
1889         struct page *page;
1890
1891         might_sleep();
1892
1893         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1894         if (is_error_page(page))
1895                 goto error;
1896
1897         *_page = page;
1898
1899         return kmap(page);
1900
1901 error:
1902         kvm_release_page_clean(page);
1903         kvm_inject_gp(&svm->vcpu, 0);
1904
1905         return NULL;
1906 }
1907
1908 static void nested_svm_unmap(struct page *page)
1909 {
1910         kunmap(page);
1911         kvm_release_page_dirty(page);
1912 }
1913
1914 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1915 {
1916         unsigned port;
1917         u8 val, bit;
1918         u64 gpa;
1919
1920         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1921                 return NESTED_EXIT_HOST;
1922
1923         port = svm->vmcb->control.exit_info_1 >> 16;
1924         gpa  = svm->nested.vmcb_iopm + (port / 8);
1925         bit  = port % 8;
1926         val  = 0;
1927
1928         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1929                 val &= (1 << bit);
1930
1931         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1932 }
1933
1934 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1935 {
1936         u32 offset, msr, value;
1937         int write, mask;
1938
1939         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1940                 return NESTED_EXIT_HOST;
1941
1942         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1943         offset = svm_msrpm_offset(msr);
1944         write  = svm->vmcb->control.exit_info_1 & 1;
1945         mask   = 1 << ((2 * (msr & 0xf)) + write);
1946
1947         if (offset == MSR_INVALID)
1948                 return NESTED_EXIT_DONE;
1949
1950         /* Offset is in 32 bit units but need in 8 bit units */
1951         offset *= 4;
1952
1953         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1954                 return NESTED_EXIT_DONE;
1955
1956         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1957 }
1958
1959 static int nested_svm_exit_special(struct vcpu_svm *svm)
1960 {
1961         u32 exit_code = svm->vmcb->control.exit_code;
1962
1963         switch (exit_code) {
1964         case SVM_EXIT_INTR:
1965         case SVM_EXIT_NMI:
1966         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1967                 return NESTED_EXIT_HOST;
1968         case SVM_EXIT_NPF:
1969                 /* For now we are always handling NPFs when using them */
1970                 if (npt_enabled)
1971                         return NESTED_EXIT_HOST;
1972                 break;
1973         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1974                 /* When we're shadowing, trap PFs, but not async PF */
1975                 if (!npt_enabled && svm->apf_reason == 0)
1976                         return NESTED_EXIT_HOST;
1977                 break;
1978         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1979                 nm_interception(svm);
1980                 break;
1981         default:
1982                 break;
1983         }
1984
1985         return NESTED_EXIT_CONTINUE;
1986 }
1987
1988 /*
1989  * If this function returns true, this #vmexit was already handled
1990  */
1991 static int nested_svm_intercept(struct vcpu_svm *svm)
1992 {
1993         u32 exit_code = svm->vmcb->control.exit_code;
1994         int vmexit = NESTED_EXIT_HOST;
1995
1996         switch (exit_code) {
1997         case SVM_EXIT_MSR:
1998                 vmexit = nested_svm_exit_handled_msr(svm);
1999                 break;
2000         case SVM_EXIT_IOIO:
2001                 vmexit = nested_svm_intercept_ioio(svm);
2002                 break;
2003         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2004                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2005                 if (svm->nested.intercept_cr & bit)
2006                         vmexit = NESTED_EXIT_DONE;
2007                 break;
2008         }
2009         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2010                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2011                 if (svm->nested.intercept_dr & bit)
2012                         vmexit = NESTED_EXIT_DONE;
2013                 break;
2014         }
2015         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2016                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2017                 if (svm->nested.intercept_exceptions & excp_bits)
2018                         vmexit = NESTED_EXIT_DONE;
2019                 /* async page fault always cause vmexit */
2020                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2021                          svm->apf_reason != 0)
2022                         vmexit = NESTED_EXIT_DONE;
2023                 break;
2024         }
2025         case SVM_EXIT_ERR: {
2026                 vmexit = NESTED_EXIT_DONE;
2027                 break;
2028         }
2029         default: {
2030                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2031                 if (svm->nested.intercept & exit_bits)
2032                         vmexit = NESTED_EXIT_DONE;
2033         }
2034         }
2035
2036         return vmexit;
2037 }
2038
2039 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2040 {
2041         int vmexit;
2042
2043         vmexit = nested_svm_intercept(svm);
2044
2045         if (vmexit == NESTED_EXIT_DONE)
2046                 nested_svm_vmexit(svm);
2047
2048         return vmexit;
2049 }
2050
2051 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2052 {
2053         struct vmcb_control_area *dst  = &dst_vmcb->control;
2054         struct vmcb_control_area *from = &from_vmcb->control;
2055
2056         dst->intercept_cr         = from->intercept_cr;
2057         dst->intercept_dr         = from->intercept_dr;
2058         dst->intercept_exceptions = from->intercept_exceptions;
2059         dst->intercept            = from->intercept;
2060         dst->iopm_base_pa         = from->iopm_base_pa;
2061         dst->msrpm_base_pa        = from->msrpm_base_pa;
2062         dst->tsc_offset           = from->tsc_offset;
2063         dst->asid                 = from->asid;
2064         dst->tlb_ctl              = from->tlb_ctl;
2065         dst->int_ctl              = from->int_ctl;
2066         dst->int_vector           = from->int_vector;
2067         dst->int_state            = from->int_state;
2068         dst->exit_code            = from->exit_code;
2069         dst->exit_code_hi         = from->exit_code_hi;
2070         dst->exit_info_1          = from->exit_info_1;
2071         dst->exit_info_2          = from->exit_info_2;
2072         dst->exit_int_info        = from->exit_int_info;
2073         dst->exit_int_info_err    = from->exit_int_info_err;
2074         dst->nested_ctl           = from->nested_ctl;
2075         dst->event_inj            = from->event_inj;
2076         dst->event_inj_err        = from->event_inj_err;
2077         dst->nested_cr3           = from->nested_cr3;
2078         dst->lbr_ctl              = from->lbr_ctl;
2079 }
2080
2081 static int nested_svm_vmexit(struct vcpu_svm *svm)
2082 {
2083         struct vmcb *nested_vmcb;
2084         struct vmcb *hsave = svm->nested.hsave;
2085         struct vmcb *vmcb = svm->vmcb;
2086         struct page *page;
2087
2088         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2089                                        vmcb->control.exit_info_1,
2090                                        vmcb->control.exit_info_2,
2091                                        vmcb->control.exit_int_info,
2092                                        vmcb->control.exit_int_info_err);
2093
2094         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2095         if (!nested_vmcb)
2096                 return 1;
2097
2098         /* Exit Guest-Mode */
2099         leave_guest_mode(&svm->vcpu);
2100         svm->nested.vmcb = 0;
2101
2102         /* Give the current vmcb to the guest */
2103         disable_gif(svm);
2104
2105         nested_vmcb->save.es     = vmcb->save.es;
2106         nested_vmcb->save.cs     = vmcb->save.cs;
2107         nested_vmcb->save.ss     = vmcb->save.ss;
2108         nested_vmcb->save.ds     = vmcb->save.ds;
2109         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2110         nested_vmcb->save.idtr   = vmcb->save.idtr;
2111         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2112         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2113         nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
2114         nested_vmcb->save.cr2    = vmcb->save.cr2;
2115         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2116         nested_vmcb->save.rflags = vmcb->save.rflags;
2117         nested_vmcb->save.rip    = vmcb->save.rip;
2118         nested_vmcb->save.rsp    = vmcb->save.rsp;
2119         nested_vmcb->save.rax    = vmcb->save.rax;
2120         nested_vmcb->save.dr7    = vmcb->save.dr7;
2121         nested_vmcb->save.dr6    = vmcb->save.dr6;
2122         nested_vmcb->save.cpl    = vmcb->save.cpl;
2123
2124         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2125         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2126         nested_vmcb->control.int_state         = vmcb->control.int_state;
2127         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2128         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2129         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2130         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2131         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2132         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2133         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2134
2135         /*
2136          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2137          * to make sure that we do not lose injected events. So check event_inj
2138          * here and copy it to exit_int_info if it is valid.
2139          * Exit_int_info and event_inj can't be both valid because the case
2140          * below only happens on a VMRUN instruction intercept which has
2141          * no valid exit_int_info set.
2142          */
2143         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2144                 struct vmcb_control_area *nc = &nested_vmcb->control;
2145
2146                 nc->exit_int_info     = vmcb->control.event_inj;
2147                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2148         }
2149
2150         nested_vmcb->control.tlb_ctl           = 0;
2151         nested_vmcb->control.event_inj         = 0;
2152         nested_vmcb->control.event_inj_err     = 0;
2153
2154         /* We always set V_INTR_MASKING and remember the old value in hflags */
2155         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2156                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2157
2158         /* Restore the original control entries */
2159         copy_vmcb_control_area(vmcb, hsave);
2160
2161         kvm_clear_exception_queue(&svm->vcpu);
2162         kvm_clear_interrupt_queue(&svm->vcpu);
2163
2164         svm->nested.nested_cr3 = 0;
2165
2166         /* Restore selected save entries */
2167         svm->vmcb->save.es = hsave->save.es;
2168         svm->vmcb->save.cs = hsave->save.cs;
2169         svm->vmcb->save.ss = hsave->save.ss;
2170         svm->vmcb->save.ds = hsave->save.ds;
2171         svm->vmcb->save.gdtr = hsave->save.gdtr;
2172         svm->vmcb->save.idtr = hsave->save.idtr;
2173         svm->vmcb->save.rflags = hsave->save.rflags;
2174         svm_set_efer(&svm->vcpu, hsave->save.efer);
2175         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2176         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2177         if (npt_enabled) {
2178                 svm->vmcb->save.cr3 = hsave->save.cr3;
2179                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2180         } else {
2181                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2182         }
2183         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2184         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2185         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2186         svm->vmcb->save.dr7 = 0;
2187         svm->vmcb->save.cpl = 0;
2188         svm->vmcb->control.exit_int_info = 0;
2189
2190         mark_all_dirty(svm->vmcb);
2191
2192         nested_svm_unmap(page);
2193
2194         nested_svm_uninit_mmu_context(&svm->vcpu);
2195         kvm_mmu_reset_context(&svm->vcpu);
2196         kvm_mmu_load(&svm->vcpu);
2197
2198         return 0;
2199 }
2200
2201 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2202 {
2203         /*
2204          * This function merges the msr permission bitmaps of kvm and the
2205          * nested vmcb. It is omptimized in that it only merges the parts where
2206          * the kvm msr permission bitmap may contain zero bits
2207          */
2208         int i;
2209
2210         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2211                 return true;
2212
2213         for (i = 0; i < MSRPM_OFFSETS; i++) {
2214                 u32 value, p;
2215                 u64 offset;
2216
2217                 if (msrpm_offsets[i] == 0xffffffff)
2218                         break;
2219
2220                 p      = msrpm_offsets[i];
2221                 offset = svm->nested.vmcb_msrpm + (p * 4);
2222
2223                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2224                         return false;
2225
2226                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2227         }
2228
2229         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2230
2231         return true;
2232 }
2233
2234 static bool nested_vmcb_checks(struct vmcb *vmcb)
2235 {
2236         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2237                 return false;
2238
2239         if (vmcb->control.asid == 0)
2240                 return false;
2241
2242         if (vmcb->control.nested_ctl && !npt_enabled)
2243                 return false;
2244
2245         return true;
2246 }
2247
2248 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2249 {
2250         struct vmcb *nested_vmcb;
2251         struct vmcb *hsave = svm->nested.hsave;
2252         struct vmcb *vmcb = svm->vmcb;
2253         struct page *page;
2254         u64 vmcb_gpa;
2255
2256         vmcb_gpa = svm->vmcb->save.rax;
2257
2258         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2259         if (!nested_vmcb)
2260                 return false;
2261
2262         if (!nested_vmcb_checks(nested_vmcb)) {
2263                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2264                 nested_vmcb->control.exit_code_hi = 0;
2265                 nested_vmcb->control.exit_info_1  = 0;
2266                 nested_vmcb->control.exit_info_2  = 0;
2267
2268                 nested_svm_unmap(page);
2269
2270                 return false;
2271         }
2272
2273         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2274                                nested_vmcb->save.rip,
2275                                nested_vmcb->control.int_ctl,
2276                                nested_vmcb->control.event_inj,
2277                                nested_vmcb->control.nested_ctl);
2278
2279         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2280                                     nested_vmcb->control.intercept_cr >> 16,
2281                                     nested_vmcb->control.intercept_exceptions,
2282                                     nested_vmcb->control.intercept);
2283
2284         /* Clear internal status */
2285         kvm_clear_exception_queue(&svm->vcpu);
2286         kvm_clear_interrupt_queue(&svm->vcpu);
2287
2288         /*
2289          * Save the old vmcb, so we don't need to pick what we save, but can
2290          * restore everything when a VMEXIT occurs
2291          */
2292         hsave->save.es     = vmcb->save.es;
2293         hsave->save.cs     = vmcb->save.cs;
2294         hsave->save.ss     = vmcb->save.ss;
2295         hsave->save.ds     = vmcb->save.ds;
2296         hsave->save.gdtr   = vmcb->save.gdtr;
2297         hsave->save.idtr   = vmcb->save.idtr;
2298         hsave->save.efer   = svm->vcpu.arch.efer;
2299         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2300         hsave->save.cr4    = svm->vcpu.arch.cr4;
2301         hsave->save.rflags = vmcb->save.rflags;
2302         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2303         hsave->save.rsp    = vmcb->save.rsp;
2304         hsave->save.rax    = vmcb->save.rax;
2305         if (npt_enabled)
2306                 hsave->save.cr3    = vmcb->save.cr3;
2307         else
2308                 hsave->save.cr3    = svm->vcpu.arch.cr3;
2309
2310         copy_vmcb_control_area(hsave, vmcb);
2311
2312         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2313                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2314         else
2315                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2316
2317         if (nested_vmcb->control.nested_ctl) {
2318                 kvm_mmu_unload(&svm->vcpu);
2319                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2320                 nested_svm_init_mmu_context(&svm->vcpu);
2321         }
2322
2323         /* Load the nested guest state */
2324         svm->vmcb->save.es = nested_vmcb->save.es;
2325         svm->vmcb->save.cs = nested_vmcb->save.cs;
2326         svm->vmcb->save.ss = nested_vmcb->save.ss;
2327         svm->vmcb->save.ds = nested_vmcb->save.ds;
2328         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2329         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2330         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2331         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2332         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2333         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2334         if (npt_enabled) {
2335                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2336                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2337         } else
2338                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2339
2340         /* Guest paging mode is active - reset mmu */
2341         kvm_mmu_reset_context(&svm->vcpu);
2342
2343         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2344         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2345         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2346         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2347
2348         /* In case we don't even reach vcpu_run, the fields are not updated */
2349         svm->vmcb->save.rax = nested_vmcb->save.rax;
2350         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2351         svm->vmcb->save.rip = nested_vmcb->save.rip;
2352         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2353         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2354         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2355
2356         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2357         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2358
2359         /* cache intercepts */
2360         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2361         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2362         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2363         svm->nested.intercept            = nested_vmcb->control.intercept;
2364
2365         svm_flush_tlb(&svm->vcpu);
2366         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2367         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2368                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2369         else
2370                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2371
2372         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2373                 /* We only want the cr8 intercept bits of the guest */
2374                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2375                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2376         }
2377
2378         /* We don't want to see VMMCALLs from a nested guest */
2379         clr_intercept(svm, INTERCEPT_VMMCALL);
2380
2381         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2382         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2383         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2384         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2385         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2386         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2387
2388         nested_svm_unmap(page);
2389
2390         /* Enter Guest-Mode */
2391         enter_guest_mode(&svm->vcpu);
2392
2393         /*
2394          * Merge guest and host intercepts - must be called  with vcpu in
2395          * guest-mode to take affect here
2396          */
2397         recalc_intercepts(svm);
2398
2399         svm->nested.vmcb = vmcb_gpa;
2400
2401         enable_gif(svm);
2402
2403         mark_all_dirty(svm->vmcb);
2404
2405         return true;
2406 }
2407
2408 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2409 {
2410         to_vmcb->save.fs = from_vmcb->save.fs;
2411         to_vmcb->save.gs = from_vmcb->save.gs;
2412         to_vmcb->save.tr = from_vmcb->save.tr;
2413         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2414         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2415         to_vmcb->save.star = from_vmcb->save.star;
2416         to_vmcb->save.lstar = from_vmcb->save.lstar;
2417         to_vmcb->save.cstar = from_vmcb->save.cstar;
2418         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2419         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2420         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2421         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2422 }
2423
2424 static int vmload_interception(struct vcpu_svm *svm)
2425 {
2426         struct vmcb *nested_vmcb;
2427         struct page *page;
2428
2429         if (nested_svm_check_permissions(svm))
2430                 return 1;
2431
2432         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2433         skip_emulated_instruction(&svm->vcpu);
2434
2435         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2436         if (!nested_vmcb)
2437                 return 1;
2438
2439         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2440         nested_svm_unmap(page);
2441
2442         return 1;
2443 }
2444
2445 static int vmsave_interception(struct vcpu_svm *svm)
2446 {
2447         struct vmcb *nested_vmcb;
2448         struct page *page;
2449
2450         if (nested_svm_check_permissions(svm))
2451                 return 1;
2452
2453         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2454         skip_emulated_instruction(&svm->vcpu);
2455
2456         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2457         if (!nested_vmcb)
2458                 return 1;
2459
2460         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2461         nested_svm_unmap(page);
2462
2463         return 1;
2464 }
2465
2466 static int vmrun_interception(struct vcpu_svm *svm)
2467 {
2468         if (nested_svm_check_permissions(svm))
2469                 return 1;
2470
2471         /* Save rip after vmrun instruction */
2472         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2473
2474         if (!nested_svm_vmrun(svm))
2475                 return 1;
2476
2477         if (!nested_svm_vmrun_msrpm(svm))
2478                 goto failed;
2479
2480         return 1;
2481
2482 failed:
2483
2484         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2485         svm->vmcb->control.exit_code_hi = 0;
2486         svm->vmcb->control.exit_info_1  = 0;
2487         svm->vmcb->control.exit_info_2  = 0;
2488
2489         nested_svm_vmexit(svm);
2490
2491         return 1;
2492 }
2493
2494 static int stgi_interception(struct vcpu_svm *svm)
2495 {
2496         if (nested_svm_check_permissions(svm))
2497                 return 1;
2498
2499         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2500         skip_emulated_instruction(&svm->vcpu);
2501         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2502
2503         enable_gif(svm);
2504
2505         return 1;
2506 }
2507
2508 static int clgi_interception(struct vcpu_svm *svm)
2509 {
2510         if (nested_svm_check_permissions(svm))
2511                 return 1;
2512
2513         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2514         skip_emulated_instruction(&svm->vcpu);
2515
2516         disable_gif(svm);
2517
2518         /* After a CLGI no interrupts should come */
2519         svm_clear_vintr(svm);
2520         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2521
2522         mark_dirty(svm->vmcb, VMCB_INTR);
2523
2524         return 1;
2525 }
2526
2527 static int invlpga_interception(struct vcpu_svm *svm)
2528 {
2529         struct kvm_vcpu *vcpu = &svm->vcpu;
2530
2531         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2532                           vcpu->arch.regs[VCPU_REGS_RAX]);
2533
2534         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2535         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2536
2537         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2538         skip_emulated_instruction(&svm->vcpu);
2539         return 1;
2540 }
2541
2542 static int skinit_interception(struct vcpu_svm *svm)
2543 {
2544         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2545
2546         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2547         return 1;
2548 }
2549
2550 static int xsetbv_interception(struct vcpu_svm *svm)
2551 {
2552         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2553         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2554
2555         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2556                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2557                 skip_emulated_instruction(&svm->vcpu);
2558         }
2559
2560         return 1;
2561 }
2562
2563 static int invalid_op_interception(struct vcpu_svm *svm)
2564 {
2565         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2566         return 1;
2567 }
2568
2569 static int task_switch_interception(struct vcpu_svm *svm)
2570 {
2571         u16 tss_selector;
2572         int reason;
2573         int int_type = svm->vmcb->control.exit_int_info &
2574                 SVM_EXITINTINFO_TYPE_MASK;
2575         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2576         uint32_t type =
2577                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2578         uint32_t idt_v =
2579                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2580         bool has_error_code = false;
2581         u32 error_code = 0;
2582
2583         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2584
2585         if (svm->vmcb->control.exit_info_2 &
2586             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2587                 reason = TASK_SWITCH_IRET;
2588         else if (svm->vmcb->control.exit_info_2 &
2589                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2590                 reason = TASK_SWITCH_JMP;
2591         else if (idt_v)
2592                 reason = TASK_SWITCH_GATE;
2593         else
2594                 reason = TASK_SWITCH_CALL;
2595
2596         if (reason == TASK_SWITCH_GATE) {
2597                 switch (type) {
2598                 case SVM_EXITINTINFO_TYPE_NMI:
2599                         svm->vcpu.arch.nmi_injected = false;
2600                         break;
2601                 case SVM_EXITINTINFO_TYPE_EXEPT:
2602                         if (svm->vmcb->control.exit_info_2 &
2603                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2604                                 has_error_code = true;
2605                                 error_code =
2606                                         (u32)svm->vmcb->control.exit_info_2;
2607                         }
2608                         kvm_clear_exception_queue(&svm->vcpu);
2609                         break;
2610                 case SVM_EXITINTINFO_TYPE_INTR:
2611                         kvm_clear_interrupt_queue(&svm->vcpu);
2612                         break;
2613                 default:
2614                         break;
2615                 }
2616         }
2617
2618         if (reason != TASK_SWITCH_GATE ||
2619             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2620             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2621              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2622                 skip_emulated_instruction(&svm->vcpu);
2623
2624         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2625                                 has_error_code, error_code) == EMULATE_FAIL) {
2626                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2627                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2628                 svm->vcpu.run->internal.ndata = 0;
2629                 return 0;
2630         }
2631         return 1;
2632 }
2633
2634 static int cpuid_interception(struct vcpu_svm *svm)
2635 {
2636         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2637         kvm_emulate_cpuid(&svm->vcpu);
2638         return 1;
2639 }
2640
2641 static int iret_interception(struct vcpu_svm *svm)
2642 {
2643         ++svm->vcpu.stat.nmi_window_exits;
2644         clr_intercept(svm, INTERCEPT_IRET);
2645         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2646         return 1;
2647 }
2648
2649 static int invlpg_interception(struct vcpu_svm *svm)
2650 {
2651         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2652 }
2653
2654 static int emulate_on_interception(struct vcpu_svm *svm)
2655 {
2656         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2657 }
2658
2659 static int cr0_write_interception(struct vcpu_svm *svm)
2660 {
2661         struct kvm_vcpu *vcpu = &svm->vcpu;
2662         int r;
2663
2664         r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2665
2666         if (svm->nested.vmexit_rip) {
2667                 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2668                 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2669                 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2670                 svm->nested.vmexit_rip = 0;
2671         }
2672
2673         return r == EMULATE_DONE;
2674 }
2675
2676 static int cr8_write_interception(struct vcpu_svm *svm)
2677 {
2678         struct kvm_run *kvm_run = svm->vcpu.run;
2679
2680         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2681         /* instruction emulation calls kvm_set_cr8() */
2682         emulate_instruction(&svm->vcpu, 0, 0, 0);
2683         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2684                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2685                 return 1;
2686         }
2687         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2688                 return 1;
2689         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2690         return 0;
2691 }
2692
2693 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2694 {
2695         struct vcpu_svm *svm = to_svm(vcpu);
2696
2697         switch (ecx) {
2698         case MSR_IA32_TSC: {
2699                 struct vmcb *vmcb = get_host_vmcb(svm);
2700
2701                 *data = vmcb->control.tsc_offset + native_read_tsc();
2702                 break;
2703         }
2704         case MSR_STAR:
2705                 *data = svm->vmcb->save.star;
2706                 break;
2707 #ifdef CONFIG_X86_64
2708         case MSR_LSTAR:
2709                 *data = svm->vmcb->save.lstar;
2710                 break;
2711         case MSR_CSTAR:
2712                 *data = svm->vmcb->save.cstar;
2713                 break;
2714         case MSR_KERNEL_GS_BASE:
2715                 *data = svm->vmcb->save.kernel_gs_base;
2716                 break;
2717         case MSR_SYSCALL_MASK:
2718                 *data = svm->vmcb->save.sfmask;
2719                 break;
2720 #endif
2721         case MSR_IA32_SYSENTER_CS:
2722                 *data = svm->vmcb->save.sysenter_cs;
2723                 break;
2724         case MSR_IA32_SYSENTER_EIP:
2725                 *data = svm->sysenter_eip;
2726                 break;
2727         case MSR_IA32_SYSENTER_ESP:
2728                 *data = svm->sysenter_esp;
2729                 break;
2730         /*
2731          * Nobody will change the following 5 values in the VMCB so we can
2732          * safely return them on rdmsr. They will always be 0 until LBRV is
2733          * implemented.
2734          */
2735         case MSR_IA32_DEBUGCTLMSR:
2736                 *data = svm->vmcb->save.dbgctl;
2737                 break;
2738         case MSR_IA32_LASTBRANCHFROMIP:
2739                 *data = svm->vmcb->save.br_from;
2740                 break;
2741         case MSR_IA32_LASTBRANCHTOIP:
2742                 *data = svm->vmcb->save.br_to;
2743                 break;
2744         case MSR_IA32_LASTINTFROMIP:
2745                 *data = svm->vmcb->save.last_excp_from;
2746                 break;
2747         case MSR_IA32_LASTINTTOIP:
2748                 *data = svm->vmcb->save.last_excp_to;
2749                 break;
2750         case MSR_VM_HSAVE_PA:
2751                 *data = svm->nested.hsave_msr;
2752                 break;
2753         case MSR_VM_CR:
2754                 *data = svm->nested.vm_cr_msr;
2755                 break;
2756         case MSR_IA32_UCODE_REV:
2757                 *data = 0x01000065;
2758                 break;
2759         default:
2760                 return kvm_get_msr_common(vcpu, ecx, data);
2761         }
2762         return 0;
2763 }
2764
2765 static int rdmsr_interception(struct vcpu_svm *svm)
2766 {
2767         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2768         u64 data;
2769
2770         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2771                 trace_kvm_msr_read_ex(ecx);
2772                 kvm_inject_gp(&svm->vcpu, 0);
2773         } else {
2774                 trace_kvm_msr_read(ecx, data);
2775
2776                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2777                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2778                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2779                 skip_emulated_instruction(&svm->vcpu);
2780         }
2781         return 1;
2782 }
2783
2784 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2785 {
2786         struct vcpu_svm *svm = to_svm(vcpu);
2787         int svm_dis, chg_mask;
2788
2789         if (data & ~SVM_VM_CR_VALID_MASK)
2790                 return 1;
2791
2792         chg_mask = SVM_VM_CR_VALID_MASK;
2793
2794         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2795                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2796
2797         svm->nested.vm_cr_msr &= ~chg_mask;
2798         svm->nested.vm_cr_msr |= (data & chg_mask);
2799
2800         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2801
2802         /* check for svm_disable while efer.svme is set */
2803         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2804                 return 1;
2805
2806         return 0;
2807 }
2808
2809 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2810 {
2811         struct vcpu_svm *svm = to_svm(vcpu);
2812
2813         switch (ecx) {
2814         case MSR_IA32_TSC:
2815                 kvm_write_tsc(vcpu, data);
2816                 break;
2817         case MSR_STAR:
2818                 svm->vmcb->save.star = data;
2819                 break;
2820 #ifdef CONFIG_X86_64
2821         case MSR_LSTAR:
2822                 svm->vmcb->save.lstar = data;
2823                 break;
2824         case MSR_CSTAR:
2825                 svm->vmcb->save.cstar = data;
2826                 break;
2827         case MSR_KERNEL_GS_BASE:
2828                 svm->vmcb->save.kernel_gs_base = data;
2829                 break;
2830         case MSR_SYSCALL_MASK:
2831                 svm->vmcb->save.sfmask = data;
2832                 break;
2833 #endif
2834         case MSR_IA32_SYSENTER_CS:
2835                 svm->vmcb->save.sysenter_cs = data;
2836                 break;
2837         case MSR_IA32_SYSENTER_EIP:
2838                 svm->sysenter_eip = data;
2839                 svm->vmcb->save.sysenter_eip = data;
2840                 break;
2841         case MSR_IA32_SYSENTER_ESP:
2842                 svm->sysenter_esp = data;
2843                 svm->vmcb->save.sysenter_esp = data;
2844                 break;
2845         case MSR_IA32_DEBUGCTLMSR:
2846                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2847                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2848                                         __func__, data);
2849                         break;
2850                 }
2851                 if (data & DEBUGCTL_RESERVED_BITS)
2852                         return 1;
2853
2854                 svm->vmcb->save.dbgctl = data;
2855                 mark_dirty(svm->vmcb, VMCB_LBR);
2856                 if (data & (1ULL<<0))
2857                         svm_enable_lbrv(svm);
2858                 else
2859                         svm_disable_lbrv(svm);
2860                 break;
2861         case MSR_VM_HSAVE_PA:
2862                 svm->nested.hsave_msr = data;
2863                 break;
2864         case MSR_VM_CR:
2865                 return svm_set_vm_cr(vcpu, data);
2866         case MSR_VM_IGNNE:
2867                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2868                 break;
2869         default:
2870                 return kvm_set_msr_common(vcpu, ecx, data);
2871         }
2872         return 0;
2873 }
2874
2875 static int wrmsr_interception(struct vcpu_svm *svm)
2876 {
2877         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2878         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2879                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2880
2881
2882         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2883         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2884                 trace_kvm_msr_write_ex(ecx, data);
2885                 kvm_inject_gp(&svm->vcpu, 0);
2886         } else {
2887                 trace_kvm_msr_write(ecx, data);
2888                 skip_emulated_instruction(&svm->vcpu);
2889         }
2890         return 1;
2891 }
2892
2893 static int msr_interception(struct vcpu_svm *svm)
2894 {
2895         if (svm->vmcb->control.exit_info_1)
2896                 return wrmsr_interception(svm);
2897         else
2898                 return rdmsr_interception(svm);
2899 }
2900
2901 static int interrupt_window_interception(struct vcpu_svm *svm)
2902 {
2903         struct kvm_run *kvm_run = svm->vcpu.run;
2904
2905         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2906         svm_clear_vintr(svm);
2907         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2908         mark_dirty(svm->vmcb, VMCB_INTR);
2909         /*
2910          * If the user space waits to inject interrupts, exit as soon as
2911          * possible
2912          */
2913         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2914             kvm_run->request_interrupt_window &&
2915             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2916                 ++svm->vcpu.stat.irq_window_exits;
2917                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2918                 return 0;
2919         }
2920
2921         return 1;
2922 }
2923
2924 static int pause_interception(struct vcpu_svm *svm)
2925 {
2926         kvm_vcpu_on_spin(&(svm->vcpu));
2927         return 1;
2928 }
2929
2930 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2931         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2932         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2933         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2934         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2935         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2936         [SVM_EXIT_WRITE_CR0]                    = cr0_write_interception,
2937         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2938         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2939         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2940         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2941         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2942         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2943         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2944         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2945         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2946         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2947         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2948         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2949         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2950         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2951         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2952         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2953         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2954         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2955         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2956         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2957         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2958         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2959         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2960         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2961         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2962         [SVM_EXIT_INTR]                         = intr_interception,
2963         [SVM_EXIT_NMI]                          = nmi_interception,
2964         [SVM_EXIT_SMI]                          = nop_on_interception,
2965         [SVM_EXIT_INIT]                         = nop_on_interception,
2966         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2967         [SVM_EXIT_CPUID]                        = cpuid_interception,
2968         [SVM_EXIT_IRET]                         = iret_interception,
2969         [SVM_EXIT_INVD]                         = emulate_on_interception,
2970         [SVM_EXIT_PAUSE]                        = pause_interception,
2971         [SVM_EXIT_HLT]                          = halt_interception,
2972         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2973         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2974         [SVM_EXIT_IOIO]                         = io_interception,
2975         [SVM_EXIT_MSR]                          = msr_interception,
2976         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2977         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2978         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2979         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2980         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2981         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2982         [SVM_EXIT_STGI]                         = stgi_interception,
2983         [SVM_EXIT_CLGI]                         = clgi_interception,
2984         [SVM_EXIT_SKINIT]                       = skinit_interception,
2985         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2986         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2987         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2988         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
2989         [SVM_EXIT_NPF]                          = pf_interception,
2990 };
2991
2992 void dump_vmcb(struct kvm_vcpu *vcpu)
2993 {
2994         struct vcpu_svm *svm = to_svm(vcpu);
2995         struct vmcb_control_area *control = &svm->vmcb->control;
2996         struct vmcb_save_area *save = &svm->vmcb->save;
2997
2998         pr_err("VMCB Control Area:\n");
2999         pr_err("cr_read:            %04x\n", control->intercept_cr & 0xffff);
3000         pr_err("cr_write:           %04x\n", control->intercept_cr >> 16);
3001         pr_err("dr_read:            %04x\n", control->intercept_dr & 0xffff);
3002         pr_err("dr_write:           %04x\n", control->intercept_dr >> 16);
3003         pr_err("exceptions:         %08x\n", control->intercept_exceptions);
3004         pr_err("intercepts:         %016llx\n", control->intercept);
3005         pr_err("pause filter count: %d\n", control->pause_filter_count);
3006         pr_err("iopm_base_pa:       %016llx\n", control->iopm_base_pa);
3007         pr_err("msrpm_base_pa:      %016llx\n", control->msrpm_base_pa);
3008         pr_err("tsc_offset:         %016llx\n", control->tsc_offset);
3009         pr_err("asid:               %d\n", control->asid);
3010         pr_err("tlb_ctl:            %d\n", control->tlb_ctl);
3011         pr_err("int_ctl:            %08x\n", control->int_ctl);
3012         pr_err("int_vector:         %08x\n", control->int_vector);
3013         pr_err("int_state:          %08x\n", control->int_state);
3014         pr_err("exit_code:          %08x\n", control->exit_code);
3015         pr_err("exit_info1:         %016llx\n", control->exit_info_1);
3016         pr_err("exit_info2:         %016llx\n", control->exit_info_2);
3017         pr_err("exit_int_info:      %08x\n", control->exit_int_info);
3018         pr_err("exit_int_info_err:  %08x\n", control->exit_int_info_err);
3019         pr_err("nested_ctl:         %lld\n", control->nested_ctl);
3020         pr_err("nested_cr3:         %016llx\n", control->nested_cr3);
3021         pr_err("event_inj:          %08x\n", control->event_inj);
3022         pr_err("event_inj_err:      %08x\n", control->event_inj_err);
3023         pr_err("lbr_ctl:            %lld\n", control->lbr_ctl);
3024         pr_err("next_rip:           %016llx\n", control->next_rip);
3025         pr_err("VMCB State Save Area:\n");
3026         pr_err("es:   s: %04x a: %04x l: %08x b: %016llx\n",
3027                 save->es.selector, save->es.attrib,
3028                 save->es.limit, save->es.base);
3029         pr_err("cs:   s: %04x a: %04x l: %08x b: %016llx\n",
3030                 save->cs.selector, save->cs.attrib,
3031                 save->cs.limit, save->cs.base);
3032         pr_err("ss:   s: %04x a: %04x l: %08x b: %016llx\n",
3033                 save->ss.selector, save->ss.attrib,
3034                 save->ss.limit, save->ss.base);
3035         pr_err("ds:   s: %04x a: %04x l: %08x b: %016llx\n",
3036                 save->ds.selector, save->ds.attrib,
3037                 save->ds.limit, save->ds.base);
3038         pr_err("fs:   s: %04x a: %04x l: %08x b: %016llx\n",
3039                 save->fs.selector, save->fs.attrib,
3040                 save->fs.limit, save->fs.base);
3041         pr_err("gs:   s: %04x a: %04x l: %08x b: %016llx\n",
3042                 save->gs.selector, save->gs.attrib,
3043                 save->gs.limit, save->gs.base);
3044         pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3045                 save->gdtr.selector, save->gdtr.attrib,
3046                 save->gdtr.limit, save->gdtr.base);
3047         pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3048                 save->ldtr.selector, save->ldtr.attrib,
3049                 save->ldtr.limit, save->ldtr.base);
3050         pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3051                 save->idtr.selector, save->idtr.attrib,
3052                 save->idtr.limit, save->idtr.base);
3053         pr_err("tr:   s: %04x a: %04x l: %08x b: %016llx\n",
3054                 save->tr.selector, save->tr.attrib,
3055                 save->tr.limit, save->tr.base);
3056         pr_err("cpl:            %d                efer:         %016llx\n",
3057                 save->cpl, save->efer);
3058         pr_err("cr0:            %016llx cr2:          %016llx\n",
3059                 save->cr0, save->cr2);
3060         pr_err("cr3:            %016llx cr4:          %016llx\n",
3061                 save->cr3, save->cr4);
3062         pr_err("dr6:            %016llx dr7:          %016llx\n",
3063                 save->dr6, save->dr7);
3064         pr_err("rip:            %016llx rflags:       %016llx\n",
3065                 save->rip, save->rflags);
3066         pr_err("rsp:            %016llx rax:          %016llx\n",
3067                 save->rsp, save->rax);
3068         pr_err("star:           %016llx lstar:        %016llx\n",
3069                 save->star, save->lstar);
3070         pr_err("cstar:          %016llx sfmask:       %016llx\n",
3071                 save->cstar, save->sfmask);
3072         pr_err("kernel_gs_base: %016llx sysenter_cs:  %016llx\n",
3073                 save->kernel_gs_base, save->sysenter_cs);
3074         pr_err("sysenter_esp:   %016llx sysenter_eip: %016llx\n",
3075                 save->sysenter_esp, save->sysenter_eip);
3076         pr_err("gpat:           %016llx dbgctl:       %016llx\n",
3077                 save->g_pat, save->dbgctl);
3078         pr_err("br_from:        %016llx br_to:        %016llx\n",
3079                 save->br_from, save->br_to);
3080         pr_err("excp_from:      %016llx excp_to:      %016llx\n",
3081                 save->last_excp_from, save->last_excp_to);
3082
3083 }
3084
3085 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3086 {
3087         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3088
3089         *info1 = control->exit_info_1;
3090         *info2 = control->exit_info_2;
3091 }
3092
3093 static int handle_exit(struct kvm_vcpu *vcpu)
3094 {
3095         struct vcpu_svm *svm = to_svm(vcpu);
3096         struct kvm_run *kvm_run = vcpu->run;
3097         u32 exit_code = svm->vmcb->control.exit_code;
3098
3099         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3100
3101         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3102                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3103         if (npt_enabled)
3104                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3105
3106         if (unlikely(svm->nested.exit_required)) {
3107                 nested_svm_vmexit(svm);
3108                 svm->nested.exit_required = false;
3109
3110                 return 1;
3111         }
3112
3113         if (is_guest_mode(vcpu)) {
3114                 int vmexit;
3115
3116                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3117                                         svm->vmcb->control.exit_info_1,
3118                                         svm->vmcb->control.exit_info_2,
3119                                         svm->vmcb->control.exit_int_info,
3120                                         svm->vmcb->control.exit_int_info_err);
3121
3122                 vmexit = nested_svm_exit_special(svm);
3123
3124                 if (vmexit == NESTED_EXIT_CONTINUE)
3125                         vmexit = nested_svm_exit_handled(svm);
3126
3127                 if (vmexit == NESTED_EXIT_DONE)
3128                         return 1;
3129         }
3130
3131         svm_complete_interrupts(svm);
3132
3133         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3134                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3135                 kvm_run->fail_entry.hardware_entry_failure_reason
3136                         = svm->vmcb->control.exit_code;
3137                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3138                 dump_vmcb(vcpu);
3139                 return 0;
3140         }
3141
3142         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3143             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3144             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3145             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3146                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3147                        "exit_code 0x%x\n",
3148                        __func__, svm->vmcb->control.exit_int_info,
3149                        exit_code);
3150
3151         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3152             || !svm_exit_handlers[exit_code]) {
3153                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3154                 kvm_run->hw.hardware_exit_reason = exit_code;
3155                 return 0;
3156         }
3157
3158         return svm_exit_handlers[exit_code](svm);
3159 }
3160
3161 static void reload_tss(struct kvm_vcpu *vcpu)
3162 {
3163         int cpu = raw_smp_processor_id();
3164
3165         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3166         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3167         load_TR_desc();
3168 }
3169
3170 static void pre_svm_run(struct vcpu_svm *svm)
3171 {
3172         int cpu = raw_smp_processor_id();
3173
3174         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3175
3176         /* FIXME: handle wraparound of asid_generation */
3177         if (svm->asid_generation != sd->asid_generation)
3178                 new_asid(svm, sd);
3179 }
3180
3181 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3182 {
3183         struct vcpu_svm *svm = to_svm(vcpu);
3184
3185         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3186         vcpu->arch.hflags |= HF_NMI_MASK;
3187         set_intercept(svm, INTERCEPT_IRET);
3188         ++vcpu->stat.nmi_injections;
3189 }
3190
3191 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3192 {
3193         struct vmcb_control_area *control;
3194
3195         control = &svm->vmcb->control;
3196         control->int_vector = irq;
3197         control->int_ctl &= ~V_INTR_PRIO_MASK;
3198         control->int_ctl |= V_IRQ_MASK |
3199                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3200         mark_dirty(svm->vmcb, VMCB_INTR);
3201 }
3202
3203 static void svm_set_irq(struct kvm_vcpu *vcpu)
3204 {
3205         struct vcpu_svm *svm = to_svm(vcpu);
3206
3207         BUG_ON(!(gif_set(svm)));
3208
3209         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3210         ++vcpu->stat.irq_injections;
3211
3212         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3213                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3214 }
3215
3216 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3217 {
3218         struct vcpu_svm *svm = to_svm(vcpu);
3219
3220         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3221                 return;
3222
3223         if (irr == -1)
3224                 return;
3225
3226         if (tpr >= irr)
3227                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3228 }
3229
3230 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3231 {
3232         struct vcpu_svm *svm = to_svm(vcpu);
3233         struct vmcb *vmcb = svm->vmcb;
3234         int ret;
3235         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3236               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3237         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3238
3239         return ret;
3240 }
3241
3242 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3243 {
3244         struct vcpu_svm *svm = to_svm(vcpu);
3245
3246         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3247 }
3248
3249 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3250 {
3251         struct vcpu_svm *svm = to_svm(vcpu);
3252
3253         if (masked) {
3254                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3255                 set_intercept(svm, INTERCEPT_IRET);
3256         } else {
3257                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3258                 clr_intercept(svm, INTERCEPT_IRET);
3259         }
3260 }
3261
3262 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3263 {
3264         struct vcpu_svm *svm = to_svm(vcpu);
3265         struct vmcb *vmcb = svm->vmcb;
3266         int ret;
3267
3268         if (!gif_set(svm) ||
3269              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3270                 return 0;
3271
3272         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3273
3274         if (is_guest_mode(vcpu))
3275                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3276
3277         return ret;
3278 }
3279
3280 static void enable_irq_window(struct kvm_vcpu *vcpu)
3281 {
3282         struct vcpu_svm *svm = to_svm(vcpu);
3283
3284         /*
3285          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3286          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3287          * get that intercept, this function will be called again though and
3288          * we'll get the vintr intercept.
3289          */
3290         if (gif_set(svm) && nested_svm_intr(svm)) {
3291                 svm_set_vintr(svm);
3292                 svm_inject_irq(svm, 0x0);
3293         }
3294 }
3295
3296 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3297 {
3298         struct vcpu_svm *svm = to_svm(vcpu);
3299
3300         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3301             == HF_NMI_MASK)
3302                 return; /* IRET will cause a vm exit */
3303
3304         /*
3305          * Something prevents NMI from been injected. Single step over possible
3306          * problem (IRET or exception injection or interrupt shadow)
3307          */
3308         svm->nmi_singlestep = true;
3309         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3310         update_db_intercept(vcpu);
3311 }
3312
3313 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3314 {
3315         return 0;
3316 }
3317
3318 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3319 {
3320         struct vcpu_svm *svm = to_svm(vcpu);
3321
3322         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3323                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3324         else
3325                 svm->asid_generation--;
3326 }
3327
3328 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3329 {
3330 }
3331
3332 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3333 {
3334         struct vcpu_svm *svm = to_svm(vcpu);
3335
3336         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3337                 return;
3338
3339         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3340                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3341                 kvm_set_cr8(vcpu, cr8);
3342         }
3343 }
3344
3345 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3346 {
3347         struct vcpu_svm *svm = to_svm(vcpu);
3348         u64 cr8;
3349
3350         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3351                 return;
3352
3353         cr8 = kvm_get_cr8(vcpu);
3354         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3355         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3356 }
3357
3358 static void svm_complete_interrupts(struct vcpu_svm *svm)
3359 {
3360         u8 vector;
3361         int type;
3362         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3363         unsigned int3_injected = svm->int3_injected;
3364
3365         svm->int3_injected = 0;
3366
3367         if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3368                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3369                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3370         }
3371
3372         svm->vcpu.arch.nmi_injected = false;
3373         kvm_clear_exception_queue(&svm->vcpu);
3374         kvm_clear_interrupt_queue(&svm->vcpu);
3375
3376         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3377                 return;
3378
3379         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3380
3381         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3382         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3383
3384         switch (type) {
3385         case SVM_EXITINTINFO_TYPE_NMI:
3386                 svm->vcpu.arch.nmi_injected = true;
3387                 break;
3388         case SVM_EXITINTINFO_TYPE_EXEPT:
3389                 /*
3390                  * In case of software exceptions, do not reinject the vector,
3391                  * but re-execute the instruction instead. Rewind RIP first
3392                  * if we emulated INT3 before.
3393                  */
3394                 if (kvm_exception_is_soft(vector)) {
3395                         if (vector == BP_VECTOR && int3_injected &&
3396                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3397                                 kvm_rip_write(&svm->vcpu,
3398                                               kvm_rip_read(&svm->vcpu) -
3399                                               int3_injected);
3400                         break;
3401                 }
3402                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3403                         u32 err = svm->vmcb->control.exit_int_info_err;
3404                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3405
3406                 } else
3407                         kvm_requeue_exception(&svm->vcpu, vector);
3408                 break;
3409         case SVM_EXITINTINFO_TYPE_INTR:
3410                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3411                 break;
3412         default:
3413                 break;
3414         }
3415 }
3416
3417 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3418 {
3419         struct vcpu_svm *svm = to_svm(vcpu);
3420         struct vmcb_control_area *control = &svm->vmcb->control;
3421
3422         control->exit_int_info = control->event_inj;
3423         control->exit_int_info_err = control->event_inj_err;
3424         control->event_inj = 0;
3425         svm_complete_interrupts(svm);
3426 }
3427
3428 #ifdef CONFIG_X86_64
3429 #define R "r"
3430 #else
3431 #define R "e"
3432 #endif
3433
3434 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3435 {
3436         struct vcpu_svm *svm = to_svm(vcpu);
3437
3438         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3439         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3440         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3441
3442         /*
3443          * A vmexit emulation is required before the vcpu can be executed
3444          * again.
3445          */
3446         if (unlikely(svm->nested.exit_required))
3447                 return;
3448
3449         pre_svm_run(svm);
3450
3451         sync_lapic_to_cr8(vcpu);
3452
3453         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3454
3455         clgi();
3456
3457         local_irq_enable();
3458
3459         asm volatile (
3460                 "push %%"R"bp; \n\t"
3461                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3462                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3463                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3464                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3465                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3466                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3467 #ifdef CONFIG_X86_64
3468                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3469                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3470                 "mov %c[r10](%[svm]), %%r10 \n\t"
3471                 "mov %c[r11](%[svm]), %%r11 \n\t"
3472                 "mov %c[r12](%[svm]), %%r12 \n\t"
3473                 "mov %c[r13](%[svm]), %%r13 \n\t"
3474                 "mov %c[r14](%[svm]), %%r14 \n\t"
3475                 "mov %c[r15](%[svm]), %%r15 \n\t"
3476 #endif
3477
3478                 /* Enter guest mode */
3479                 "push %%"R"ax \n\t"
3480                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3481                 __ex(SVM_VMLOAD) "\n\t"
3482                 __ex(SVM_VMRUN) "\n\t"
3483                 __ex(SVM_VMSAVE) "\n\t"
3484                 "pop %%"R"ax \n\t"
3485
3486                 /* Save guest registers, load host registers */
3487                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3488                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3489                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3490                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3491                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3492                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3493 #ifdef CONFIG_X86_64
3494                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3495                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3496                 "mov %%r10, %c[r10](%[svm]) \n\t"
3497                 "mov %%r11, %c[r11](%[svm]) \n\t"
3498                 "mov %%r12, %c[r12](%[svm]) \n\t"
3499                 "mov %%r13, %c[r13](%[svm]) \n\t"
3500                 "mov %%r14, %c[r14](%[svm]) \n\t"
3501                 "mov %%r15, %c[r15](%[svm]) \n\t"
3502 #endif
3503                 "pop %%"R"bp"
3504                 :
3505                 : [svm]"a"(svm),
3506                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3507                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3508                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3509                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3510                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3511                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3512                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3513 #ifdef CONFIG_X86_64
3514                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3515                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3516                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3517                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3518                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3519                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3520                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3521                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3522 #endif
3523                 : "cc", "memory"
3524                 , R"bx", R"cx", R"dx", R"si", R"di"
3525 #ifdef CONFIG_X86_64
3526                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3527 #endif
3528                 );
3529
3530 #ifdef CONFIG_X86_64
3531         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3532 #else
3533         loadsegment(fs, svm->host.fs);
3534 #endif
3535
3536         reload_tss(vcpu);
3537
3538         local_irq_disable();
3539
3540         stgi();
3541
3542         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3543         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3544         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3545         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3546
3547         sync_cr8_to_lapic(vcpu);
3548
3549         svm->next_rip = 0;
3550
3551         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3552
3553         /* if exit due to PF check for async PF */
3554         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3555                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3556
3557         if (npt_enabled) {
3558                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3559                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3560         }
3561
3562         /*
3563          * We need to handle MC intercepts here before the vcpu has a chance to
3564          * change the physical cpu
3565          */
3566         if (unlikely(svm->vmcb->control.exit_code ==
3567                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3568                 svm_handle_mce(svm);
3569
3570         mark_all_clean(svm->vmcb);
3571 }
3572
3573 #undef R
3574
3575 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3576 {
3577         struct vcpu_svm *svm = to_svm(vcpu);
3578
3579         svm->vmcb->save.cr3 = root;
3580         mark_dirty(svm->vmcb, VMCB_CR);
3581         svm_flush_tlb(vcpu);
3582 }
3583
3584 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3585 {
3586         struct vcpu_svm *svm = to_svm(vcpu);
3587
3588         svm->vmcb->control.nested_cr3 = root;
3589         mark_dirty(svm->vmcb, VMCB_NPT);
3590
3591         /* Also sync guest cr3 here in case we live migrate */
3592         svm->vmcb->save.cr3 = vcpu->arch.cr3;
3593         mark_dirty(svm->vmcb, VMCB_CR);
3594
3595         svm_flush_tlb(vcpu);
3596 }
3597
3598 static int is_disabled(void)
3599 {
3600         u64 vm_cr;
3601
3602         rdmsrl(MSR_VM_CR, vm_cr);
3603         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3604                 return 1;
3605
3606         return 0;
3607 }
3608
3609 static void
3610 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3611 {
3612         /*
3613          * Patch in the VMMCALL instruction:
3614          */
3615         hypercall[0] = 0x0f;
3616         hypercall[1] = 0x01;
3617         hypercall[2] = 0xd9;
3618 }
3619
3620 static void svm_check_processor_compat(void *rtn)
3621 {
3622         *(int *)rtn = 0;
3623 }
3624
3625 static bool svm_cpu_has_accelerated_tpr(void)
3626 {
3627         return false;
3628 }
3629
3630 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3631 {
3632         return 0;
3633 }
3634
3635 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3636 {
3637 }
3638
3639 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3640 {
3641         switch (func) {
3642         case 0x80000001:
3643                 if (nested)
3644                         entry->ecx |= (1 << 2); /* Set SVM bit */
3645                 break;
3646         case 0x8000000A:
3647                 entry->eax = 1; /* SVM revision 1 */
3648                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3649                                    ASID emulation to nested SVM */
3650                 entry->ecx = 0; /* Reserved */
3651                 entry->edx = 0; /* Per default do not support any
3652                                    additional features */
3653
3654                 /* Support next_rip if host supports it */
3655                 if (boot_cpu_has(X86_FEATURE_NRIPS))
3656                         entry->edx |= SVM_FEATURE_NRIP;
3657
3658                 /* Support NPT for the guest if enabled */
3659                 if (npt_enabled)
3660                         entry->edx |= SVM_FEATURE_NPT;
3661
3662                 break;
3663         }
3664 }
3665
3666 static const struct trace_print_flags svm_exit_reasons_str[] = {
3667         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3668         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3669         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3670         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3671         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3672         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3673         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3674         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3675         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3676         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3677         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3678         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3679         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3680         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3681         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3682         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3683         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3684         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3685         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3686         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3687         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3688         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3689         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3690         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3691         { SVM_EXIT_INTR,                        "interrupt" },
3692         { SVM_EXIT_NMI,                         "nmi" },
3693         { SVM_EXIT_SMI,                         "smi" },
3694         { SVM_EXIT_INIT,                        "init" },
3695         { SVM_EXIT_VINTR,                       "vintr" },
3696         { SVM_EXIT_CPUID,                       "cpuid" },
3697         { SVM_EXIT_INVD,                        "invd" },
3698         { SVM_EXIT_HLT,                         "hlt" },
3699         { SVM_EXIT_INVLPG,                      "invlpg" },
3700         { SVM_EXIT_INVLPGA,                     "invlpga" },
3701         { SVM_EXIT_IOIO,                        "io" },
3702         { SVM_EXIT_MSR,                         "msr" },
3703         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3704         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3705         { SVM_EXIT_VMRUN,                       "vmrun" },
3706         { SVM_EXIT_VMMCALL,                     "hypercall" },
3707         { SVM_EXIT_VMLOAD,                      "vmload" },
3708         { SVM_EXIT_VMSAVE,                      "vmsave" },
3709         { SVM_EXIT_STGI,                        "stgi" },
3710         { SVM_EXIT_CLGI,                        "clgi" },
3711         { SVM_EXIT_SKINIT,                      "skinit" },
3712         { SVM_EXIT_WBINVD,                      "wbinvd" },
3713         { SVM_EXIT_MONITOR,                     "monitor" },
3714         { SVM_EXIT_MWAIT,                       "mwait" },
3715         { SVM_EXIT_XSETBV,                      "xsetbv" },
3716         { SVM_EXIT_NPF,                         "npf" },
3717         { -1, NULL }
3718 };
3719
3720 static int svm_get_lpage_level(void)
3721 {
3722         return PT_PDPE_LEVEL;
3723 }
3724
3725 static bool svm_rdtscp_supported(void)
3726 {
3727         return false;
3728 }
3729
3730 static bool svm_has_wbinvd_exit(void)
3731 {
3732         return true;
3733 }
3734
3735 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3736 {
3737         struct vcpu_svm *svm = to_svm(vcpu);
3738
3739         set_exception_intercept(svm, NM_VECTOR);
3740         update_cr0_intercept(svm);
3741 }
3742
3743 static struct kvm_x86_ops svm_x86_ops = {
3744         .cpu_has_kvm_support = has_svm,
3745         .disabled_by_bios = is_disabled,
3746         .hardware_setup = svm_hardware_setup,
3747         .hardware_unsetup = svm_hardware_unsetup,
3748         .check_processor_compatibility = svm_check_processor_compat,
3749         .hardware_enable = svm_hardware_enable,
3750         .hardware_disable = svm_hardware_disable,
3751         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3752
3753         .vcpu_create = svm_create_vcpu,
3754         .vcpu_free = svm_free_vcpu,
3755         .vcpu_reset = svm_vcpu_reset,
3756
3757         .prepare_guest_switch = svm_prepare_guest_switch,
3758         .vcpu_load = svm_vcpu_load,
3759         .vcpu_put = svm_vcpu_put,
3760
3761         .set_guest_debug = svm_guest_debug,
3762         .get_msr = svm_get_msr,
3763         .set_msr = svm_set_msr,
3764         .get_segment_base = svm_get_segment_base,
3765         .get_segment = svm_get_segment,
3766         .set_segment = svm_set_segment,
3767         .get_cpl = svm_get_cpl,
3768         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3769         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3770         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3771         .set_cr0 = svm_set_cr0,
3772         .set_cr3 = svm_set_cr3,
3773         .set_cr4 = svm_set_cr4,
3774         .set_efer = svm_set_efer,
3775         .get_idt = svm_get_idt,
3776         .set_idt = svm_set_idt,
3777         .get_gdt = svm_get_gdt,
3778         .set_gdt = svm_set_gdt,
3779         .set_dr7 = svm_set_dr7,
3780         .cache_reg = svm_cache_reg,
3781         .get_rflags = svm_get_rflags,
3782         .set_rflags = svm_set_rflags,
3783         .fpu_activate = svm_fpu_activate,
3784         .fpu_deactivate = svm_fpu_deactivate,
3785
3786         .tlb_flush = svm_flush_tlb,
3787
3788         .run = svm_vcpu_run,
3789         .handle_exit = handle_exit,
3790         .skip_emulated_instruction = skip_emulated_instruction,
3791         .set_interrupt_shadow = svm_set_interrupt_shadow,
3792         .get_interrupt_shadow = svm_get_interrupt_shadow,
3793         .patch_hypercall = svm_patch_hypercall,
3794         .set_irq = svm_set_irq,
3795         .set_nmi = svm_inject_nmi,
3796         .queue_exception = svm_queue_exception,
3797         .cancel_injection = svm_cancel_injection,
3798         .interrupt_allowed = svm_interrupt_allowed,
3799         .nmi_allowed = svm_nmi_allowed,
3800         .get_nmi_mask = svm_get_nmi_mask,
3801         .set_nmi_mask = svm_set_nmi_mask,
3802         .enable_nmi_window = enable_nmi_window,
3803         .enable_irq_window = enable_irq_window,
3804         .update_cr8_intercept = update_cr8_intercept,
3805
3806         .set_tss_addr = svm_set_tss_addr,
3807         .get_tdp_level = get_npt_level,
3808         .get_mt_mask = svm_get_mt_mask,
3809
3810         .get_exit_info = svm_get_exit_info,
3811         .exit_reasons_str = svm_exit_reasons_str,
3812
3813         .get_lpage_level = svm_get_lpage_level,
3814
3815         .cpuid_update = svm_cpuid_update,
3816
3817         .rdtscp_supported = svm_rdtscp_supported,
3818
3819         .set_supported_cpuid = svm_set_supported_cpuid,
3820
3821         .has_wbinvd_exit = svm_has_wbinvd_exit,
3822
3823         .write_tsc_offset = svm_write_tsc_offset,
3824         .adjust_tsc_offset = svm_adjust_tsc_offset,
3825
3826         .set_tdp_cr3 = set_tdp_cr3,
3827 };
3828
3829 static int __init svm_init(void)
3830 {
3831         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3832                         __alignof__(struct vcpu_svm), THIS_MODULE);
3833 }
3834
3835 static void __exit svm_exit(void)
3836 {
3837         kvm_exit();
3838 }
3839
3840 module_init(svm_init)
3841 module_exit(svm_exit)