arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28
  29 #include <asm/desc.h>
  30
  31 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  32
  33 MODULE_AUTHOR("Qumranet");
  34 MODULE_LICENSE("GPL");
  35
  36 #define IOPM_ALLOC_ORDER 2
  37 #define MSRPM_ALLOC_ORDER 1
  38
  39 #define DB_VECTOR 1
  40 #define UD_VECTOR 6
  41 #define GP_VECTOR 13
  42
  43 #define DR7_GD_MASK (1 << 13)
  44 #define DR6_BD_MASK (1 << 13)
  45
  46 #define SEG_TYPE_LDT 2
  47 #define SEG_TYPE_BUSY_TSS16 3
  48
  49 #define SVM_FEATURE_NPT  (1 << 0)
  50 #define SVM_FEATURE_LBRV (1 << 1)
  51 #define SVM_DEATURE_SVML (1 << 2)
  52
  53 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  54
  55 /* enable NPT for AMD64 and X86 with PAE */
  56 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  57 static bool npt_enabled = true;
  58 #else
  59 static bool npt_enabled = false;
  60 #endif
  61 static int npt = 1;
  62
  63 module_param(npt, int, S_IRUGO);
  64
  65 static void kvm_reput_irq(struct vcpu_svm *svm);
  66 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  67
  68 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  69 {
  70         return container_of(vcpu, struct vcpu_svm, vcpu);
  71 }
  72
  73 static unsigned long iopm_base;
  74
  75 struct kvm_ldttss_desc {
  76         u16 limit0;
  77         u16 base0;
  78         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  79         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  80         u32 base3;
  81         u32 zero1;
  82 } __attribute__((packed));
  83
  84 struct svm_cpu_data {
  85         int cpu;
  86
  87         u64 asid_generation;
  88         u32 max_asid;
  89         u32 next_asid;
  90         struct kvm_ldttss_desc *tss_desc;
  91
  92         struct page *save_area;
  93 };
  94
  95 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  96 static uint32_t svm_features;
  97
  98 struct svm_init_data {
  99         int cpu;
 100         int r;
 101 };
 102
 103 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 104
 105 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 106 #define MSRS_RANGE_SIZE 2048
 107 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 108
 109 #define MAX_INST_SIZE 15
 110
 111 static inline u32 svm_has(u32 feat)
 112 {
 113         return svm_features & feat;
 114 }
 115
 116 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 117 {
 118         int word_index = __ffs(vcpu->arch.irq_summary);
 119         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 120         int irq = word_index * BITS_PER_LONG + bit_index;
 121
 122         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 123         if (!vcpu->arch.irq_pending[word_index])
 124                 clear_bit(word_index, &vcpu->arch.irq_summary);
 125         return irq;
 126 }
 127
 128 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 129 {
 130         set_bit(irq, vcpu->arch.irq_pending);
 131         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 132 }
 133
 134 static inline void clgi(void)
 135 {
 136         asm volatile (__ex(SVM_CLGI));
 137 }
 138
 139 static inline void stgi(void)
 140 {
 141         asm volatile (__ex(SVM_STGI));
 142 }
 143
 144 static inline void invlpga(unsigned long addr, u32 asid)
 145 {
 146         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 147 }
 148
 149 static inline unsigned long kvm_read_cr2(void)
 150 {
 151         unsigned long cr2;
 152
 153         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 154         return cr2;
 155 }
 156
 157 static inline void kvm_write_cr2(unsigned long val)
 158 {
 159         asm volatile ("mov %0, %%cr2" :: "r" (val));
 160 }
 161
 162 static inline unsigned long read_dr6(void)
 163 {
 164         unsigned long dr6;
 165
 166         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 167         return dr6;
 168 }
 169
 170 static inline void write_dr6(unsigned long val)
 171 {
 172         asm volatile ("mov %0, %%dr6" :: "r" (val));
 173 }
 174
 175 static inline unsigned long read_dr7(void)
 176 {
 177         unsigned long dr7;
 178
 179         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 180         return dr7;
 181 }
 182
 183 static inline void write_dr7(unsigned long val)
 184 {
 185         asm volatile ("mov %0, %%dr7" :: "r" (val));
 186 }
 187
 188 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 189 {
 190         to_svm(vcpu)->asid_generation--;
 191 }
 192
 193 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 194 {
 195         force_new_asid(vcpu);
 196 }
 197
 198 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 199 {
 200         if (!npt_enabled && !(efer & EFER_LMA))
 201                 efer &= ~EFER_LME;
 202
 203         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 204         vcpu->arch.shadow_efer = efer;
 205 }
 206
 207 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 208                                 bool has_error_code, u32 error_code)
 209 {
 210         struct vcpu_svm *svm = to_svm(vcpu);
 211
 212         svm->vmcb->control.event_inj = nr
 213                 | SVM_EVTINJ_VALID
 214                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 215                 | SVM_EVTINJ_TYPE_EXEPT;
 216         svm->vmcb->control.event_inj_err = error_code;
 217 }
 218
 219 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 220 {
 221         struct vcpu_svm *svm = to_svm(vcpu);
 222
 223         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 224 }
 225
 226 static int is_external_interrupt(u32 info)
 227 {
 228         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 229         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 230 }
 231
 232 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 233 {
 234         struct vcpu_svm *svm = to_svm(vcpu);
 235
 236         if (!svm->next_rip) {
 237                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 238                 return;
 239         }
 240         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 241                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 242                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 243
 244         kvm_rip_write(vcpu, svm->next_rip);
 245         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 246
 247         vcpu->arch.interrupt_window_open = 1;
 248 }
 249
 250 static int has_svm(void)
 251 {
 252         uint32_t eax, ebx, ecx, edx;
 253
 254         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 255                 printk(KERN_INFO "has_svm: not amd\n");
 256                 return 0;
 257         }
 258
 259         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 260         if (eax < SVM_CPUID_FUNC) {
 261                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 262                 return 0;
 263         }
 264
 265         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 266         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 267                 printk(KERN_DEBUG "has_svm: svm not available\n");
 268                 return 0;
 269         }
 270         return 1;
 271 }
 272
 273 static void svm_hardware_disable(void *garbage)
 274 {
 275         uint64_t efer;
 276
 277         wrmsrl(MSR_VM_HSAVE_PA, 0);
 278         rdmsrl(MSR_EFER, efer);
 279         wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 280 }
 281
 282 static void svm_hardware_enable(void *garbage)
 283 {
 284
 285         struct svm_cpu_data *svm_data;
 286         uint64_t efer;
 287         struct desc_ptr gdt_descr;
 288         struct desc_struct *gdt;
 289         int me = raw_smp_processor_id();
 290
 291         if (!has_svm()) {
 292                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 293                 return;
 294         }
 295         svm_data = per_cpu(svm_data, me);
 296
 297         if (!svm_data) {
 298                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 299                        me);
 300                 return;
 301         }
 302
 303         svm_data->asid_generation = 1;
 304         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 305         svm_data->next_asid = svm_data->max_asid + 1;
 306
 307         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 308         gdt = (struct desc_struct *)gdt_descr.address;
 309         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 310
 311         rdmsrl(MSR_EFER, efer);
 312         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 313
 314         wrmsrl(MSR_VM_HSAVE_PA,
 315                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 316 }
 317
 318 static void svm_cpu_uninit(int cpu)
 319 {
 320         struct svm_cpu_data *svm_data
 321                 = per_cpu(svm_data, raw_smp_processor_id());
 322
 323         if (!svm_data)
 324                 return;
 325
 326         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 327         __free_page(svm_data->save_area);
 328         kfree(svm_data);
 329 }
 330
 331 static int svm_cpu_init(int cpu)
 332 {
 333         struct svm_cpu_data *svm_data;
 334         int r;
 335
 336         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 337         if (!svm_data)
 338                 return -ENOMEM;
 339         svm_data->cpu = cpu;
 340         svm_data->save_area = alloc_page(GFP_KERNEL);
 341         r = -ENOMEM;
 342         if (!svm_data->save_area)
 343                 goto err_1;
 344
 345         per_cpu(svm_data, cpu) = svm_data;
 346
 347         return 0;
 348
 349 err_1:
 350         kfree(svm_data);
 351         return r;
 352
 353 }
 354
 355 static void set_msr_interception(u32 *msrpm, unsigned msr,
 356                                  int read, int write)
 357 {
 358         int i;
 359
 360         for (i = 0; i < NUM_MSR_MAPS; i++) {
 361                 if (msr >= msrpm_ranges[i] &&
 362                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 363                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 364                                           msrpm_ranges[i]) * 2;
 365
 366                         u32 *base = msrpm + (msr_offset / 32);
 367                         u32 msr_shift = msr_offset % 32;
 368                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 369                         *base = (*base & ~(0x3 << msr_shift)) |
 370                                 (mask << msr_shift);
 371                         return;
 372                 }
 373         }
 374         BUG();
 375 }
 376
 377 static void svm_vcpu_init_msrpm(u32 *msrpm)
 378 {
 379         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 380
 381 #ifdef CONFIG_X86_64
 382         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 383         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 384         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 385         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 386         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 387         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 388 #endif
 389         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 390         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 391         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 392         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 393 }
 394
 395 static void svm_enable_lbrv(struct vcpu_svm *svm)
 396 {
 397         u32 *msrpm = svm->msrpm;
 398
 399         svm->vmcb->control.lbr_ctl = 1;
 400         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 401         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 402         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 403         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 404 }
 405
 406 static void svm_disable_lbrv(struct vcpu_svm *svm)
 407 {
 408         u32 *msrpm = svm->msrpm;
 409
 410         svm->vmcb->control.lbr_ctl = 0;
 411         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 412         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 413         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 414         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 415 }
 416
 417 static __init int svm_hardware_setup(void)
 418 {
 419         int cpu;
 420         struct page *iopm_pages;
 421         void *iopm_va;
 422         int r;
 423
 424         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 425
 426         if (!iopm_pages)
 427                 return -ENOMEM;
 428
 429         iopm_va = page_address(iopm_pages);
 430         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 431         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 432         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 433
 434         if (boot_cpu_has(X86_FEATURE_NX))
 435                 kvm_enable_efer_bits(EFER_NX);
 436
 437         for_each_online_cpu(cpu) {
 438                 r = svm_cpu_init(cpu);
 439                 if (r)
 440                         goto err;
 441         }
 442
 443         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 444
 445         if (!svm_has(SVM_FEATURE_NPT))
 446                 npt_enabled = false;
 447
 448         if (npt_enabled && !npt) {
 449                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 450                 npt_enabled = false;
 451         }
 452
 453         if (npt_enabled) {
 454                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 455                 kvm_enable_tdp();
 456         } else
 457                 kvm_disable_tdp();
 458
 459         return 0;
 460
 461 err:
 462         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 463         iopm_base = 0;
 464         return r;
 465 }
 466
 467 static __exit void svm_hardware_unsetup(void)
 468 {
 469         int cpu;
 470
 471         for_each_online_cpu(cpu)
 472                 svm_cpu_uninit(cpu);
 473
 474         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 475         iopm_base = 0;
 476 }
 477
 478 static void init_seg(struct vmcb_seg *seg)
 479 {
 480         seg->selector = 0;
 481         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 482                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 483         seg->limit = 0xffff;
 484         seg->base = 0;
 485 }
 486
 487 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 488 {
 489         seg->selector = 0;
 490         seg->attrib = SVM_SELECTOR_P_MASK | type;
 491         seg->limit = 0xffff;
 492         seg->base = 0;
 493 }
 494
 495 static void init_vmcb(struct vcpu_svm *svm)
 496 {
 497         struct vmcb_control_area *control = &svm->vmcb->control;
 498         struct vmcb_save_area *save = &svm->vmcb->save;
 499
 500         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 501                                         INTERCEPT_CR3_MASK |
 502                                         INTERCEPT_CR4_MASK;
 503
 504         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 505                                         INTERCEPT_CR3_MASK |
 506                                         INTERCEPT_CR4_MASK |
 507                                         INTERCEPT_CR8_MASK;
 508
 509         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 510                                         INTERCEPT_DR1_MASK |
 511                                         INTERCEPT_DR2_MASK |
 512                                         INTERCEPT_DR3_MASK;
 513
 514         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 515                                         INTERCEPT_DR1_MASK |
 516                                         INTERCEPT_DR2_MASK |
 517                                         INTERCEPT_DR3_MASK |
 518                                         INTERCEPT_DR5_MASK |
 519                                         INTERCEPT_DR7_MASK;
 520
 521         control->intercept_exceptions = (1 << PF_VECTOR) |
 522                                         (1 << UD_VECTOR) |
 523                                         (1 << MC_VECTOR);
 524
 525
 526         control->intercept =    (1ULL << INTERCEPT_INTR) |
 527                                 (1ULL << INTERCEPT_NMI) |
 528                                 (1ULL << INTERCEPT_SMI) |
 529                                 (1ULL << INTERCEPT_CPUID) |
 530                                 (1ULL << INTERCEPT_INVD) |
 531                                 (1ULL << INTERCEPT_HLT) |
 532                                 (1ULL << INTERCEPT_INVLPGA) |
 533                                 (1ULL << INTERCEPT_IOIO_PROT) |
 534                                 (1ULL << INTERCEPT_MSR_PROT) |
 535                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 536                                 (1ULL << INTERCEPT_SHUTDOWN) |
 537                                 (1ULL << INTERCEPT_VMRUN) |
 538                                 (1ULL << INTERCEPT_VMMCALL) |
 539                                 (1ULL << INTERCEPT_VMLOAD) |
 540                                 (1ULL << INTERCEPT_VMSAVE) |
 541                                 (1ULL << INTERCEPT_STGI) |
 542                                 (1ULL << INTERCEPT_CLGI) |
 543                                 (1ULL << INTERCEPT_SKINIT) |
 544                                 (1ULL << INTERCEPT_WBINVD) |
 545                                 (1ULL << INTERCEPT_MONITOR) |
 546                                 (1ULL << INTERCEPT_MWAIT);
 547
 548         control->iopm_base_pa = iopm_base;
 549         control->msrpm_base_pa = __pa(svm->msrpm);
 550         control->tsc_offset = 0;
 551         control->int_ctl = V_INTR_MASKING_MASK;
 552
 553         init_seg(&save->es);
 554         init_seg(&save->ss);
 555         init_seg(&save->ds);
 556         init_seg(&save->fs);
 557         init_seg(&save->gs);
 558
 559         save->cs.selector = 0xf000;
 560         /* Executable/Readable Code Segment */
 561         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 562                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 563         save->cs.limit = 0xffff;
 564         /*
 565          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 566          * be consistent with it.
 567          *
 568          * Replace when we have real mode working for vmx.
 569          */
 570         save->cs.base = 0xf0000;
 571
 572         save->gdtr.limit = 0xffff;
 573         save->idtr.limit = 0xffff;
 574
 575         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 576         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 577
 578         save->efer = MSR_EFER_SVME_MASK;
 579         save->dr6 = 0xffff0ff0;
 580         save->dr7 = 0x400;
 581         save->rflags = 2;
 582         save->rip = 0x0000fff0;
 583         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 584
 585         /*
 586          * cr0 val on cpu init should be 0x60000010, we enable cpu
 587          * cache by default. the orderly way is to enable cache in bios.
 588          */
 589         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 590         save->cr4 = X86_CR4_PAE;
 591         /* rdx = ?? */
 592
 593         if (npt_enabled) {
 594                 /* Setup VMCB for Nested Paging */
 595                 control->nested_ctl = 1;
 596                 control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH);
 597                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 598                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 599                                                 INTERCEPT_CR3_MASK);
 600                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 601                                                  INTERCEPT_CR3_MASK);
 602                 save->g_pat = 0x0007040600070406ULL;
 603                 /* enable caching because the QEMU Bios doesn't enable it */
 604                 save->cr0 = X86_CR0_ET;
 605                 save->cr3 = 0;
 606                 save->cr4 = 0;
 607         }
 608         force_new_asid(&svm->vcpu);
 609 }
 610
 611 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 612 {
 613         struct vcpu_svm *svm = to_svm(vcpu);
 614
 615         init_vmcb(svm);
 616
 617         if (vcpu->vcpu_id != 0) {
 618                 kvm_rip_write(vcpu, 0);
 619                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 620                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 621         }
 622         vcpu->arch.regs_avail = ~0;
 623         vcpu->arch.regs_dirty = ~0;
 624
 625         return 0;
 626 }
 627
 628 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 629 {
 630         struct vcpu_svm *svm;
 631         struct page *page;
 632         struct page *msrpm_pages;
 633         int err;
 634
 635         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 636         if (!svm) {
 637                 err = -ENOMEM;
 638                 goto out;
 639         }
 640
 641         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 642         if (err)
 643                 goto free_svm;
 644
 645         page = alloc_page(GFP_KERNEL);
 646         if (!page) {
 647                 err = -ENOMEM;
 648                 goto uninit;
 649         }
 650
 651         err = -ENOMEM;
 652         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 653         if (!msrpm_pages)
 654                 goto uninit;
 655         svm->msrpm = page_address(msrpm_pages);
 656         svm_vcpu_init_msrpm(svm->msrpm);
 657
 658         svm->vmcb = page_address(page);
 659         clear_page(svm->vmcb);
 660         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 661         svm->asid_generation = 0;
 662         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 663         init_vmcb(svm);
 664
 665         fx_init(&svm->vcpu);
 666         svm->vcpu.fpu_active = 1;
 667         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 668         if (svm->vcpu.vcpu_id == 0)
 669                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 670
 671         return &svm->vcpu;
 672
 673 uninit:
 674         kvm_vcpu_uninit(&svm->vcpu);
 675 free_svm:
 676         kmem_cache_free(kvm_vcpu_cache, svm);
 677 out:
 678         return ERR_PTR(err);
 679 }
 680
 681 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 682 {
 683         struct vcpu_svm *svm = to_svm(vcpu);
 684
 685         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 686         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 687         kvm_vcpu_uninit(vcpu);
 688         kmem_cache_free(kvm_vcpu_cache, svm);
 689 }
 690
 691 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 692 {
 693         struct vcpu_svm *svm = to_svm(vcpu);
 694         int i;
 695
 696         if (unlikely(cpu != vcpu->cpu)) {
 697                 u64 tsc_this, delta;
 698
 699                 /*
 700                  * Make sure that the guest sees a monotonically
 701                  * increasing TSC.
 702                  */
 703                 rdtscll(tsc_this);
 704                 delta = vcpu->arch.host_tsc - tsc_this;
 705                 svm->vmcb->control.tsc_offset += delta;
 706                 vcpu->cpu = cpu;
 707                 kvm_migrate_timers(vcpu);
 708         }
 709
 710         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 711                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 712 }
 713
 714 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 715 {
 716         struct vcpu_svm *svm = to_svm(vcpu);
 717         int i;
 718
 719         ++vcpu->stat.host_state_reload;
 720         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 721                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 722
 723         rdtscll(vcpu->arch.host_tsc);
 724 }
 725
 726 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 727 {
 728         return to_svm(vcpu)->vmcb->save.rflags;
 729 }
 730
 731 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 732 {
 733         to_svm(vcpu)->vmcb->save.rflags = rflags;
 734 }
 735
 736 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 737 {
 738         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 739
 740         switch (seg) {
 741         case VCPU_SREG_CS: return &save->cs;
 742         case VCPU_SREG_DS: return &save->ds;
 743         case VCPU_SREG_ES: return &save->es;
 744         case VCPU_SREG_FS: return &save->fs;
 745         case VCPU_SREG_GS: return &save->gs;
 746         case VCPU_SREG_SS: return &save->ss;
 747         case VCPU_SREG_TR: return &save->tr;
 748         case VCPU_SREG_LDTR: return &save->ldtr;
 749         }
 750         BUG();
 751         return NULL;
 752 }
 753
 754 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 755 {
 756         struct vmcb_seg *s = svm_seg(vcpu, seg);
 757
 758         return s->base;
 759 }
 760
 761 static void svm_get_segment(struct kvm_vcpu *vcpu,
 762                             struct kvm_segment *var, int seg)
 763 {
 764         struct vmcb_seg *s = svm_seg(vcpu, seg);
 765
 766         var->base = s->base;
 767         var->limit = s->limit;
 768         var->selector = s->selector;
 769         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 770         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 771         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 772         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 773         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 774         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 775         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 776         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 777         var->unusable = !var->present;
 778 }
 779
 780 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 781 {
 782         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 783
 784         return save->cpl;
 785 }
 786
 787 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 788 {
 789         struct vcpu_svm *svm = to_svm(vcpu);
 790
 791         dt->limit = svm->vmcb->save.idtr.limit;
 792         dt->base = svm->vmcb->save.idtr.base;
 793 }
 794
 795 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 796 {
 797         struct vcpu_svm *svm = to_svm(vcpu);
 798
 799         svm->vmcb->save.idtr.limit = dt->limit;
 800         svm->vmcb->save.idtr.base = dt->base ;
 801 }
 802
 803 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 804 {
 805         struct vcpu_svm *svm = to_svm(vcpu);
 806
 807         dt->limit = svm->vmcb->save.gdtr.limit;
 808         dt->base = svm->vmcb->save.gdtr.base;
 809 }
 810
 811 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 812 {
 813         struct vcpu_svm *svm = to_svm(vcpu);
 814
 815         svm->vmcb->save.gdtr.limit = dt->limit;
 816         svm->vmcb->save.gdtr.base = dt->base ;
 817 }
 818
 819 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 820 {
 821 }
 822
 823 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 824 {
 825         struct vcpu_svm *svm = to_svm(vcpu);
 826
 827 #ifdef CONFIG_X86_64
 828         if (vcpu->arch.shadow_efer & EFER_LME) {
 829                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 830                         vcpu->arch.shadow_efer |= EFER_LMA;
 831                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 832                 }
 833
 834                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 835                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 836                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 837                 }
 838         }
 839 #endif
 840         if (npt_enabled)
 841                 goto set;
 842
 843         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 844                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 845                 vcpu->fpu_active = 1;
 846         }
 847
 848         vcpu->arch.cr0 = cr0;
 849         cr0 |= X86_CR0_PG | X86_CR0_WP;
 850         if (!vcpu->fpu_active) {
 851                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 852                 cr0 |= X86_CR0_TS;
 853         }
 854 set:
 855         /*
 856          * re-enable caching here because the QEMU bios
 857          * does not do it - this results in some delay at
 858          * reboot
 859          */
 860         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 861         svm->vmcb->save.cr0 = cr0;
 862 }
 863
 864 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 865 {
 866         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 867         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 868
 869         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 870                 force_new_asid(vcpu);
 871
 872         vcpu->arch.cr4 = cr4;
 873         if (!npt_enabled)
 874                 cr4 |= X86_CR4_PAE;
 875         cr4 |= host_cr4_mce;
 876         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 877 }
 878
 879 static void svm_set_segment(struct kvm_vcpu *vcpu,
 880                             struct kvm_segment *var, int seg)
 881 {
 882         struct vcpu_svm *svm = to_svm(vcpu);
 883         struct vmcb_seg *s = svm_seg(vcpu, seg);
 884
 885         s->base = var->base;
 886         s->limit = var->limit;
 887         s->selector = var->selector;
 888         if (var->unusable)
 889                 s->attrib = 0;
 890         else {
 891                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 892                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 893                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 894                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 895                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 896                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 897                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 898                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 899         }
 900         if (seg == VCPU_SREG_CS)
 901                 svm->vmcb->save.cpl
 902                         = (svm->vmcb->save.cs.attrib
 903                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 904
 905 }
 906
 907 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 908 {
 909         return -EOPNOTSUPP;
 910 }
 911
 912 static int svm_get_irq(struct kvm_vcpu *vcpu)
 913 {
 914         struct vcpu_svm *svm = to_svm(vcpu);
 915         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 916
 917         if (is_external_interrupt(exit_int_info))
 918                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 919         return -1;
 920 }
 921
 922 static void load_host_msrs(struct kvm_vcpu *vcpu)
 923 {
 924 #ifdef CONFIG_X86_64
 925         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 926 #endif
 927 }
 928
 929 static void save_host_msrs(struct kvm_vcpu *vcpu)
 930 {
 931 #ifdef CONFIG_X86_64
 932         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 933 #endif
 934 }
 935
 936 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 937 {
 938         if (svm_data->next_asid > svm_data->max_asid) {
 939                 ++svm_data->asid_generation;
 940                 svm_data->next_asid = 1;
 941                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 942         }
 943
 944         svm->vcpu.cpu = svm_data->cpu;
 945         svm->asid_generation = svm_data->asid_generation;
 946         svm->vmcb->control.asid = svm_data->next_asid++;
 947 }
 948
 949 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 950 {
 951         unsigned long val = to_svm(vcpu)->db_regs[dr];
 952         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 953         return val;
 954 }
 955
 956 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 957                        int *exception)
 958 {
 959         struct vcpu_svm *svm = to_svm(vcpu);
 960
 961         *exception = 0;
 962
 963         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 964                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 965                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 966                 *exception = DB_VECTOR;
 967                 return;
 968         }
 969
 970         switch (dr) {
 971         case 0 ... 3:
 972                 svm->db_regs[dr] = value;
 973                 return;
 974         case 4 ... 5:
 975                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 976                         *exception = UD_VECTOR;
 977                         return;
 978                 }
 979         case 7: {
 980                 if (value & ~((1ULL << 32) - 1)) {
 981                         *exception = GP_VECTOR;
 982                         return;
 983                 }
 984                 svm->vmcb->save.dr7 = value;
 985                 return;
 986         }
 987         default:
 988                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 989                        __func__, dr);
 990                 *exception = UD_VECTOR;
 991                 return;
 992         }
 993 }
 994
 995 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 996 {
 997         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 998         struct kvm *kvm = svm->vcpu.kvm;
 999         u64 fault_address;
1000         u32 error_code;
1001         bool event_injection = false;
1002
1003         if (!irqchip_in_kernel(kvm) &&
1004             is_external_interrupt(exit_int_info)) {
1005                 event_injection = true;
1006                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1007         }
1008
1009         fault_address  = svm->vmcb->control.exit_info_2;
1010         error_code = svm->vmcb->control.exit_info_1;
1011
1012         if (!npt_enabled)
1013                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1014                             (u32)fault_address, (u32)(fault_address >> 32),
1015                             handler);
1016         else
1017                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1018                             (u32)fault_address, (u32)(fault_address >> 32),
1019                             handler);
1020         /*
1021          * FIXME: Tis shouldn't be necessary here, but there is a flush
1022          * missing in the MMU code. Until we find this bug, flush the
1023          * complete TLB here on an NPF
1024          */
1025         if (npt_enabled)
1026                 svm_flush_tlb(&svm->vcpu);
1027
1028         if (event_injection)
1029                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1030         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1031 }
1032
1033 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1034 {
1035         int er;
1036
1037         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1038         if (er != EMULATE_DONE)
1039                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1040         return 1;
1041 }
1042
1043 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1044 {
1045         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1046         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1047                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1048         svm->vcpu.fpu_active = 1;
1049
1050         return 1;
1051 }
1052
1053 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1054 {
1055         /*
1056          * On an #MC intercept the MCE handler is not called automatically in
1057          * the host. So do it by hand here.
1058          */
1059         asm volatile (
1060                 "int $0x12\n");
1061         /* not sure if we ever come back to this point */
1062
1063         return 1;
1064 }
1065
1066 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1067 {
1068         /*
1069          * VMCB is undefined after a SHUTDOWN intercept
1070          * so reinitialize it.
1071          */
1072         clear_page(svm->vmcb);
1073         init_vmcb(svm);
1074
1075         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1076         return 0;
1077 }
1078
1079 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1080 {
1081         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1082         int size, down, in, string, rep;
1083         unsigned port;
1084
1085         ++svm->vcpu.stat.io_exits;
1086
1087         svm->next_rip = svm->vmcb->control.exit_info_2;
1088
1089         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1090
1091         if (string) {
1092                 if (emulate_instruction(&svm->vcpu,
1093                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1094                         return 0;
1095                 return 1;
1096         }
1097
1098         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1099         port = io_info >> 16;
1100         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1101         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1102         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1103
1104         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1105 }
1106
1107 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1108 {
1109         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1110         return 1;
1111 }
1112
1113 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1114 {
1115         ++svm->vcpu.stat.irq_exits;
1116         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1117         return 1;
1118 }
1119
1120 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1121 {
1122         return 1;
1123 }
1124
1125 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1126 {
1127         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1128         skip_emulated_instruction(&svm->vcpu);
1129         return kvm_emulate_halt(&svm->vcpu);
1130 }
1131
1132 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1133 {
1134         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1135         skip_emulated_instruction(&svm->vcpu);
1136         kvm_emulate_hypercall(&svm->vcpu);
1137         return 1;
1138 }
1139
1140 static int invalid_op_interception(struct vcpu_svm *svm,
1141                                    struct kvm_run *kvm_run)
1142 {
1143         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1144         return 1;
1145 }
1146
1147 static int task_switch_interception(struct vcpu_svm *svm,
1148                                     struct kvm_run *kvm_run)
1149 {
1150         u16 tss_selector;
1151
1152         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1153         if (svm->vmcb->control.exit_info_2 &
1154             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1155                 return kvm_task_switch(&svm->vcpu, tss_selector,
1156                                        TASK_SWITCH_IRET);
1157         if (svm->vmcb->control.exit_info_2 &
1158             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1159                 return kvm_task_switch(&svm->vcpu, tss_selector,
1160                                        TASK_SWITCH_JMP);
1161         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1162 }
1163
1164 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1165 {
1166         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1167         kvm_emulate_cpuid(&svm->vcpu);
1168         return 1;
1169 }
1170
1171 static int emulate_on_interception(struct vcpu_svm *svm,
1172                                    struct kvm_run *kvm_run)
1173 {
1174         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1175                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1176         return 1;
1177 }
1178
1179 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1180 {
1181         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1182         if (irqchip_in_kernel(svm->vcpu.kvm))
1183                 return 1;
1184         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1185         return 0;
1186 }
1187
1188 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1189 {
1190         struct vcpu_svm *svm = to_svm(vcpu);
1191
1192         switch (ecx) {
1193         case MSR_IA32_TIME_STAMP_COUNTER: {
1194                 u64 tsc;
1195
1196                 rdtscll(tsc);
1197                 *data = svm->vmcb->control.tsc_offset + tsc;
1198                 break;
1199         }
1200         case MSR_K6_STAR:
1201                 *data = svm->vmcb->save.star;
1202                 break;
1203 #ifdef CONFIG_X86_64
1204         case MSR_LSTAR:
1205                 *data = svm->vmcb->save.lstar;
1206                 break;
1207         case MSR_CSTAR:
1208                 *data = svm->vmcb->save.cstar;
1209                 break;
1210         case MSR_KERNEL_GS_BASE:
1211                 *data = svm->vmcb->save.kernel_gs_base;
1212                 break;
1213         case MSR_SYSCALL_MASK:
1214                 *data = svm->vmcb->save.sfmask;
1215                 break;
1216 #endif
1217         case MSR_IA32_SYSENTER_CS:
1218                 *data = svm->vmcb->save.sysenter_cs;
1219                 break;
1220         case MSR_IA32_SYSENTER_EIP:
1221                 *data = svm->vmcb->save.sysenter_eip;
1222                 break;
1223         case MSR_IA32_SYSENTER_ESP:
1224                 *data = svm->vmcb->save.sysenter_esp;
1225                 break;
1226         /* Nobody will change the following 5 values in the VMCB so
1227            we can safely return them on rdmsr. They will always be 0
1228            until LBRV is implemented. */
1229         case MSR_IA32_DEBUGCTLMSR:
1230                 *data = svm->vmcb->save.dbgctl;
1231                 break;
1232         case MSR_IA32_LASTBRANCHFROMIP:
1233                 *data = svm->vmcb->save.br_from;
1234                 break;
1235         case MSR_IA32_LASTBRANCHTOIP:
1236                 *data = svm->vmcb->save.br_to;
1237                 break;
1238         case MSR_IA32_LASTINTFROMIP:
1239                 *data = svm->vmcb->save.last_excp_from;
1240                 break;
1241         case MSR_IA32_LASTINTTOIP:
1242                 *data = svm->vmcb->save.last_excp_to;
1243                 break;
1244         default:
1245                 return kvm_get_msr_common(vcpu, ecx, data);
1246         }
1247         return 0;
1248 }
1249
1250 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1251 {
1252         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1253         u64 data;
1254
1255         if (svm_get_msr(&svm->vcpu, ecx, &data))
1256                 kvm_inject_gp(&svm->vcpu, 0);
1257         else {
1258                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1259                             (u32)(data >> 32), handler);
1260
1261                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1262                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1263                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1264                 skip_emulated_instruction(&svm->vcpu);
1265         }
1266         return 1;
1267 }
1268
1269 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1270 {
1271         struct vcpu_svm *svm = to_svm(vcpu);
1272
1273         switch (ecx) {
1274         case MSR_IA32_TIME_STAMP_COUNTER: {
1275                 u64 tsc;
1276
1277                 rdtscll(tsc);
1278                 svm->vmcb->control.tsc_offset = data - tsc;
1279                 break;
1280         }
1281         case MSR_K6_STAR:
1282                 svm->vmcb->save.star = data;
1283                 break;
1284 #ifdef CONFIG_X86_64
1285         case MSR_LSTAR:
1286                 svm->vmcb->save.lstar = data;
1287                 break;
1288         case MSR_CSTAR:
1289                 svm->vmcb->save.cstar = data;
1290                 break;
1291         case MSR_KERNEL_GS_BASE:
1292                 svm->vmcb->save.kernel_gs_base = data;
1293                 break;
1294         case MSR_SYSCALL_MASK:
1295                 svm->vmcb->save.sfmask = data;
1296                 break;
1297 #endif
1298         case MSR_IA32_SYSENTER_CS:
1299                 svm->vmcb->save.sysenter_cs = data;
1300                 break;
1301         case MSR_IA32_SYSENTER_EIP:
1302                 svm->vmcb->save.sysenter_eip = data;
1303                 break;
1304         case MSR_IA32_SYSENTER_ESP:
1305                 svm->vmcb->save.sysenter_esp = data;
1306                 break;
1307         case MSR_IA32_DEBUGCTLMSR:
1308                 if (!svm_has(SVM_FEATURE_LBRV)) {
1309                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1310                                         __func__, data);
1311                         break;
1312                 }
1313                 if (data & DEBUGCTL_RESERVED_BITS)
1314                         return 1;
1315
1316                 svm->vmcb->save.dbgctl = data;
1317                 if (data & (1ULL<<0))
1318                         svm_enable_lbrv(svm);
1319                 else
1320                         svm_disable_lbrv(svm);
1321                 break;
1322         case MSR_K7_EVNTSEL0:
1323         case MSR_K7_EVNTSEL1:
1324         case MSR_K7_EVNTSEL2:
1325         case MSR_K7_EVNTSEL3:
1326         case MSR_K7_PERFCTR0:
1327         case MSR_K7_PERFCTR1:
1328         case MSR_K7_PERFCTR2:
1329         case MSR_K7_PERFCTR3:
1330                 /*
1331                  * Just discard all writes to the performance counters; this
1332                  * should keep both older linux and windows 64-bit guests
1333                  * happy
1334                  */
1335                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1336
1337                 break;
1338         default:
1339                 return kvm_set_msr_common(vcpu, ecx, data);
1340         }
1341         return 0;
1342 }
1343
1344 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1345 {
1346         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1347         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
1348                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1349
1350         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1351                     handler);
1352
1353         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1354         if (svm_set_msr(&svm->vcpu, ecx, data))
1355                 kvm_inject_gp(&svm->vcpu, 0);
1356         else
1357                 skip_emulated_instruction(&svm->vcpu);
1358         return 1;
1359 }
1360
1361 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1362 {
1363         if (svm->vmcb->control.exit_info_1)
1364                 return wrmsr_interception(svm, kvm_run);
1365         else
1366                 return rdmsr_interception(svm, kvm_run);
1367 }
1368
1369 static int interrupt_window_interception(struct vcpu_svm *svm,
1370                                    struct kvm_run *kvm_run)
1371 {
1372         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1373
1374         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1375         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1376         /*
1377          * If the user space waits to inject interrupts, exit as soon as
1378          * possible
1379          */
1380         if (kvm_run->request_interrupt_window &&
1381             !svm->vcpu.arch.irq_summary) {
1382                 ++svm->vcpu.stat.irq_window_exits;
1383                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1384                 return 0;
1385         }
1386
1387         return 1;
1388 }
1389
1390 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1391                                       struct kvm_run *kvm_run) = {
1392         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1393         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1394         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1395         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1396         /* for now: */
1397         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1398         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1399         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1400         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1401         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1402         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1403         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1404         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1405         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1406         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1407         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1408         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1409         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1410         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1411         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1412         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1413         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1414         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1415         [SVM_EXIT_INTR]                         = intr_interception,
1416         [SVM_EXIT_NMI]                          = nmi_interception,
1417         [SVM_EXIT_SMI]                          = nop_on_interception,
1418         [SVM_EXIT_INIT]                         = nop_on_interception,
1419         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1420         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1421         [SVM_EXIT_CPUID]                        = cpuid_interception,
1422         [SVM_EXIT_INVD]                         = emulate_on_interception,
1423         [SVM_EXIT_HLT]                          = halt_interception,
1424         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1425         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1426         [SVM_EXIT_IOIO]                         = io_interception,
1427         [SVM_EXIT_MSR]                          = msr_interception,
1428         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1429         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1430         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1431         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1432         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1433         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1434         [SVM_EXIT_STGI]                         = invalid_op_interception,
1435         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1436         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1437         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1438         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1439         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1440         [SVM_EXIT_NPF]                          = pf_interception,
1441 };
1442
1443 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1444 {
1445         struct vcpu_svm *svm = to_svm(vcpu);
1446         u32 exit_code = svm->vmcb->control.exit_code;
1447
1448         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1449                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1450
1451         if (npt_enabled) {
1452                 int mmu_reload = 0;
1453                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1454                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1455                         mmu_reload = 1;
1456                 }
1457                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1458                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1459                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1460                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1461                                 kvm_inject_gp(vcpu, 0);
1462                                 return 1;
1463                         }
1464                 }
1465                 if (mmu_reload) {
1466                         kvm_mmu_reset_context(vcpu);
1467                         kvm_mmu_load(vcpu);
1468                 }
1469         }
1470
1471         kvm_reput_irq(svm);
1472
1473         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1474                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1475                 kvm_run->fail_entry.hardware_entry_failure_reason
1476                         = svm->vmcb->control.exit_code;
1477                 return 0;
1478         }
1479
1480         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1481             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1482             exit_code != SVM_EXIT_NPF)
1483                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1484                        "exit_code 0x%x\n",
1485                        __func__, svm->vmcb->control.exit_int_info,
1486                        exit_code);
1487
1488         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1489             || !svm_exit_handlers[exit_code]) {
1490                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1491                 kvm_run->hw.hardware_exit_reason = exit_code;
1492                 return 0;
1493         }
1494
1495         return svm_exit_handlers[exit_code](svm, kvm_run);
1496 }
1497
1498 static void reload_tss(struct kvm_vcpu *vcpu)
1499 {
1500         int cpu = raw_smp_processor_id();
1501
1502         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1503         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1504         load_TR_desc();
1505 }
1506
1507 static void pre_svm_run(struct vcpu_svm *svm)
1508 {
1509         int cpu = raw_smp_processor_id();
1510
1511         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1512
1513         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1514         if (svm->vcpu.cpu != cpu ||
1515             svm->asid_generation != svm_data->asid_generation)
1516                 new_asid(svm, svm_data);
1517 }
1518
1519
1520 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1521 {
1522         struct vmcb_control_area *control;
1523
1524         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1525
1526         control = &svm->vmcb->control;
1527         control->int_vector = irq;
1528         control->int_ctl &= ~V_INTR_PRIO_MASK;
1529         control->int_ctl |= V_IRQ_MASK |
1530                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1531 }
1532
1533 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1534 {
1535         struct vcpu_svm *svm = to_svm(vcpu);
1536
1537         svm_inject_irq(svm, irq);
1538 }
1539
1540 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1541 {
1542         struct vcpu_svm *svm = to_svm(vcpu);
1543         struct vmcb *vmcb = svm->vmcb;
1544         int max_irr, tpr;
1545
1546         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1547                 return;
1548
1549         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1550
1551         max_irr = kvm_lapic_find_highest_irr(vcpu);
1552         if (max_irr == -1)
1553                 return;
1554
1555         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1556
1557         if (tpr >= (max_irr & 0xf0))
1558                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1559 }
1560
1561 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1562 {
1563         struct vcpu_svm *svm = to_svm(vcpu);
1564         struct vmcb *vmcb = svm->vmcb;
1565         int intr_vector = -1;
1566
1567         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1568             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1569                 intr_vector = vmcb->control.exit_int_info &
1570                               SVM_EVTINJ_VEC_MASK;
1571                 vmcb->control.exit_int_info = 0;
1572                 svm_inject_irq(svm, intr_vector);
1573                 goto out;
1574         }
1575
1576         if (vmcb->control.int_ctl & V_IRQ_MASK)
1577                 goto out;
1578
1579         if (!kvm_cpu_has_interrupt(vcpu))
1580                 goto out;
1581
1582         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1583             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1584             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1585                 /* unable to deliver irq, set pending irq */
1586                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1587                 svm_inject_irq(svm, 0x0);
1588                 goto out;
1589         }
1590         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1591         intr_vector = kvm_cpu_get_interrupt(vcpu);
1592         svm_inject_irq(svm, intr_vector);
1593         kvm_timer_intr_post(vcpu, intr_vector);
1594 out:
1595         update_cr8_intercept(vcpu);
1596 }
1597
1598 static void kvm_reput_irq(struct vcpu_svm *svm)
1599 {
1600         struct vmcb_control_area *control = &svm->vmcb->control;
1601
1602         if ((control->int_ctl & V_IRQ_MASK)
1603             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1604                 control->int_ctl &= ~V_IRQ_MASK;
1605                 push_irq(&svm->vcpu, control->int_vector);
1606         }
1607
1608         svm->vcpu.arch.interrupt_window_open =
1609                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1610 }
1611
1612 static void svm_do_inject_vector(struct vcpu_svm *svm)
1613 {
1614         struct kvm_vcpu *vcpu = &svm->vcpu;
1615         int word_index = __ffs(vcpu->arch.irq_summary);
1616         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1617         int irq = word_index * BITS_PER_LONG + bit_index;
1618
1619         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1620         if (!vcpu->arch.irq_pending[word_index])
1621                 clear_bit(word_index, &vcpu->arch.irq_summary);
1622         svm_inject_irq(svm, irq);
1623 }
1624
1625 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1626                                        struct kvm_run *kvm_run)
1627 {
1628         struct vcpu_svm *svm = to_svm(vcpu);
1629         struct vmcb_control_area *control = &svm->vmcb->control;
1630
1631         svm->vcpu.arch.interrupt_window_open =
1632                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1633                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1634
1635         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1636                 /*
1637                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1638                  */
1639                 svm_do_inject_vector(svm);
1640
1641         /*
1642          * Interrupts blocked.  Wait for unblock.
1643          */
1644         if (!svm->vcpu.arch.interrupt_window_open &&
1645             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1646                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1647          else
1648                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1649 }
1650
1651 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1652 {
1653         return 0;
1654 }
1655
1656 static void save_db_regs(unsigned long *db_regs)
1657 {
1658         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1659         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1660         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1661         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1662 }
1663
1664 static void load_db_regs(unsigned long *db_regs)
1665 {
1666         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1667         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1668         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1669         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1670 }
1671
1672 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1673 {
1674         force_new_asid(vcpu);
1675 }
1676
1677 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1678 {
1679 }
1680
1681 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1682 {
1683         struct vcpu_svm *svm = to_svm(vcpu);
1684
1685         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1686                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1687                 kvm_lapic_set_tpr(vcpu, cr8);
1688         }
1689 }
1690
1691 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1692 {
1693         struct vcpu_svm *svm = to_svm(vcpu);
1694         u64 cr8;
1695
1696         if (!irqchip_in_kernel(vcpu->kvm))
1697                 return;
1698
1699         cr8 = kvm_get_cr8(vcpu);
1700         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1701         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1702 }
1703
1704 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1705 {
1706         struct vcpu_svm *svm = to_svm(vcpu);
1707         u16 fs_selector;
1708         u16 gs_selector;
1709         u16 ldt_selector;
1710
1711         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
1712         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
1713         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
1714
1715         pre_svm_run(svm);
1716
1717         sync_lapic_to_cr8(vcpu);
1718
1719         save_host_msrs(vcpu);
1720         fs_selector = kvm_read_fs();
1721         gs_selector = kvm_read_gs();
1722         ldt_selector = kvm_read_ldt();
1723         svm->host_cr2 = kvm_read_cr2();
1724         svm->host_dr6 = read_dr6();
1725         svm->host_dr7 = read_dr7();
1726         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1727         /* required for live migration with NPT */
1728         if (npt_enabled)
1729                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1730
1731         if (svm->vmcb->save.dr7 & 0xff) {
1732                 write_dr7(0);
1733                 save_db_regs(svm->host_db_regs);
1734                 load_db_regs(svm->db_regs);
1735         }
1736
1737         clgi();
1738
1739         local_irq_enable();
1740
1741         asm volatile (
1742 #ifdef CONFIG_X86_64
1743                 "push %%rbp; \n\t"
1744 #else
1745                 "push %%ebp; \n\t"
1746 #endif
1747
1748 #ifdef CONFIG_X86_64
1749                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1750                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1751                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1752                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1753                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1754                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1755                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1756                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1757                 "mov %c[r10](%[svm]), %%r10 \n\t"
1758                 "mov %c[r11](%[svm]), %%r11 \n\t"
1759                 "mov %c[r12](%[svm]), %%r12 \n\t"
1760                 "mov %c[r13](%[svm]), %%r13 \n\t"
1761                 "mov %c[r14](%[svm]), %%r14 \n\t"
1762                 "mov %c[r15](%[svm]), %%r15 \n\t"
1763 #else
1764                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1765                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1766                 "mov %c[rdx](%[svm]), %%edx \n\t"
1767                 "mov %c[rsi](%[svm]), %%esi \n\t"
1768                 "mov %c[rdi](%[svm]), %%edi \n\t"
1769                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1770 #endif
1771
1772 #ifdef CONFIG_X86_64
1773                 /* Enter guest mode */
1774                 "push %%rax \n\t"
1775                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1776                 __ex(SVM_VMLOAD) "\n\t"
1777                 __ex(SVM_VMRUN) "\n\t"
1778                 __ex(SVM_VMSAVE) "\n\t"
1779                 "pop %%rax \n\t"
1780 #else
1781                 /* Enter guest mode */
1782                 "push %%eax \n\t"
1783                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1784                 __ex(SVM_VMLOAD) "\n\t"
1785                 __ex(SVM_VMRUN) "\n\t"
1786                 __ex(SVM_VMSAVE) "\n\t"
1787                 "pop %%eax \n\t"
1788 #endif
1789
1790                 /* Save guest registers, load host registers */
1791 #ifdef CONFIG_X86_64
1792                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1793                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1794                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1795                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1796                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1797                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1798                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1799                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1800                 "mov %%r10, %c[r10](%[svm]) \n\t"
1801                 "mov %%r11, %c[r11](%[svm]) \n\t"
1802                 "mov %%r12, %c[r12](%[svm]) \n\t"
1803                 "mov %%r13, %c[r13](%[svm]) \n\t"
1804                 "mov %%r14, %c[r14](%[svm]) \n\t"
1805                 "mov %%r15, %c[r15](%[svm]) \n\t"
1806
1807                 "pop  %%rbp; \n\t"
1808 #else
1809                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1810                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1811                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1812                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1813                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1814                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1815
1816                 "pop  %%ebp; \n\t"
1817 #endif
1818                 :
1819                 : [svm]"a"(svm),
1820                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1821                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1822                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1823                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1824                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1825                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1826                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1827 #ifdef CONFIG_X86_64
1828                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1829                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1830                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1831                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1832                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1833                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1834                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1835                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1836 #endif
1837                 : "cc", "memory"
1838 #ifdef CONFIG_X86_64
1839                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1840                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1841 #else
1842                 , "ebx", "ecx", "edx" , "esi", "edi"
1843 #endif
1844                 );
1845
1846         if ((svm->vmcb->save.dr7 & 0xff))
1847                 load_db_regs(svm->host_db_regs);
1848
1849         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1850         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
1851         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
1852         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
1853
1854         write_dr6(svm->host_dr6);
1855         write_dr7(svm->host_dr7);
1856         kvm_write_cr2(svm->host_cr2);
1857
1858         kvm_load_fs(fs_selector);
1859         kvm_load_gs(gs_selector);
1860         kvm_load_ldt(ldt_selector);
1861         load_host_msrs(vcpu);
1862
1863         reload_tss(vcpu);
1864
1865         local_irq_disable();
1866
1867         stgi();
1868
1869         sync_cr8_to_lapic(vcpu);
1870
1871         svm->next_rip = 0;
1872 }
1873
1874 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1875 {
1876         struct vcpu_svm *svm = to_svm(vcpu);
1877
1878         if (npt_enabled) {
1879                 svm->vmcb->control.nested_cr3 = root;
1880                 force_new_asid(vcpu);
1881                 return;
1882         }
1883
1884         svm->vmcb->save.cr3 = root;
1885         force_new_asid(vcpu);
1886
1887         if (vcpu->fpu_active) {
1888                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1889                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1890                 vcpu->fpu_active = 0;
1891         }
1892 }
1893
1894 static int is_disabled(void)
1895 {
1896         u64 vm_cr;
1897
1898         rdmsrl(MSR_VM_CR, vm_cr);
1899         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1900                 return 1;
1901
1902         return 0;
1903 }
1904
1905 static void
1906 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1907 {
1908         /*
1909          * Patch in the VMMCALL instruction:
1910          */
1911         hypercall[0] = 0x0f;
1912         hypercall[1] = 0x01;
1913         hypercall[2] = 0xd9;
1914 }
1915
1916 static void svm_check_processor_compat(void *rtn)
1917 {
1918         *(int *)rtn = 0;
1919 }
1920
1921 static bool svm_cpu_has_accelerated_tpr(void)
1922 {
1923         return false;
1924 }
1925
1926 static int get_npt_level(void)
1927 {
1928 #ifdef CONFIG_X86_64
1929         return PT64_ROOT_LEVEL;
1930 #else
1931         return PT32E_ROOT_LEVEL;
1932 #endif
1933 }
1934
1935 static struct kvm_x86_ops svm_x86_ops = {
1936         .cpu_has_kvm_support = has_svm,
1937         .disabled_by_bios = is_disabled,
1938         .hardware_setup = svm_hardware_setup,
1939         .hardware_unsetup = svm_hardware_unsetup,
1940         .check_processor_compatibility = svm_check_processor_compat,
1941         .hardware_enable = svm_hardware_enable,
1942         .hardware_disable = svm_hardware_disable,
1943         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1944
1945         .vcpu_create = svm_create_vcpu,
1946         .vcpu_free = svm_free_vcpu,
1947         .vcpu_reset = svm_vcpu_reset,
1948
1949         .prepare_guest_switch = svm_prepare_guest_switch,
1950         .vcpu_load = svm_vcpu_load,
1951         .vcpu_put = svm_vcpu_put,
1952
1953         .set_guest_debug = svm_guest_debug,
1954         .get_msr = svm_get_msr,
1955         .set_msr = svm_set_msr,
1956         .get_segment_base = svm_get_segment_base,
1957         .get_segment = svm_get_segment,
1958         .set_segment = svm_set_segment,
1959         .get_cpl = svm_get_cpl,
1960         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1961         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1962         .set_cr0 = svm_set_cr0,
1963         .set_cr3 = svm_set_cr3,
1964         .set_cr4 = svm_set_cr4,
1965         .set_efer = svm_set_efer,
1966         .get_idt = svm_get_idt,
1967         .set_idt = svm_set_idt,
1968         .get_gdt = svm_get_gdt,
1969         .set_gdt = svm_set_gdt,
1970         .get_dr = svm_get_dr,
1971         .set_dr = svm_set_dr,
1972         .get_rflags = svm_get_rflags,
1973         .set_rflags = svm_set_rflags,
1974
1975         .tlb_flush = svm_flush_tlb,
1976
1977         .run = svm_vcpu_run,
1978         .handle_exit = handle_exit,
1979         .skip_emulated_instruction = skip_emulated_instruction,
1980         .patch_hypercall = svm_patch_hypercall,
1981         .get_irq = svm_get_irq,
1982         .set_irq = svm_set_irq,
1983         .queue_exception = svm_queue_exception,
1984         .exception_injected = svm_exception_injected,
1985         .inject_pending_irq = svm_intr_assist,
1986         .inject_pending_vectors = do_interrupt_requests,
1987
1988         .set_tss_addr = svm_set_tss_addr,
1989         .get_tdp_level = get_npt_level,
1990 };
1991
1992 static int __init svm_init(void)
1993 {
1994         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1995                               THIS_MODULE);
1996 }
1997
1998 static void __exit svm_exit(void)
1999 {
2000         kvm_exit();
2001 }
2002
2003 module_init(svm_init)
2004 module_exit(svm_exit)