arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30
  31 #include <asm/desc.h>
  32
  33 #include <asm/virtext.h>
  34 #include "trace.h"
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 #define IOPM_ALLOC_ORDER 2
  42 #define MSRPM_ALLOC_ORDER 1
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT  (1 << 0)
  48 #define SVM_FEATURE_LBRV (1 << 1)
  49 #define SVM_FEATURE_SVML (1 << 2)
  50 #define SVM_FEATURE_NRIP (1 << 3)
  51 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
  52
  53 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  54 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  55 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  56
  57 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  58
  59 static const u32 host_save_user_msrs[] = {
  60 #ifdef CONFIG_X86_64
  61         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  62         MSR_FS_BASE,
  63 #endif
  64         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  65 };
  66
  67 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  68
  69 struct kvm_vcpu;
  70
  71 struct nested_state {
  72         struct vmcb *hsave;
  73         u64 hsave_msr;
  74         u64 vm_cr_msr;
  75         u64 vmcb;
  76
  77         /* These are the merged vectors */
  78         u32 *msrpm;
  79
  80         /* gpa pointers to the real vectors */
  81         u64 vmcb_msrpm;
  82
  83         /* A VMEXIT is required but not yet emulated */
  84         bool exit_required;
  85
  86         /* cache for intercepts of the guest */
  87         u16 intercept_cr_read;
  88         u16 intercept_cr_write;
  89         u16 intercept_dr_read;
  90         u16 intercept_dr_write;
  91         u32 intercept_exceptions;
  92         u64 intercept;
  93
  94 };
  95
  96 struct vcpu_svm {
  97         struct kvm_vcpu vcpu;
  98         struct vmcb *vmcb;
  99         unsigned long vmcb_pa;
 100         struct svm_cpu_data *svm_data;
 101         uint64_t asid_generation;
 102         uint64_t sysenter_esp;
 103         uint64_t sysenter_eip;
 104
 105         u64 next_rip;
 106
 107         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 108         u64 host_gs_base;
 109
 110         u32 *msrpm;
 111
 112         struct nested_state nested;
 113
 114         bool nmi_singlestep;
 115
 116         unsigned int3_injected;
 117         unsigned long int3_rip;
 118 };
 119
 120 /* enable NPT for AMD64 and X86 with PAE */
 121 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 122 static bool npt_enabled = true;
 123 #else
 124 static bool npt_enabled;
 125 #endif
 126 static int npt = 1;
 127
 128 module_param(npt, int, S_IRUGO);
 129
 130 static int nested = 1;
 131 module_param(nested, int, S_IRUGO);
 132
 133 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 134 static void svm_complete_interrupts(struct vcpu_svm *svm);
 135
 136 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 137 static int nested_svm_intercept(struct vcpu_svm *svm);
 138 static int nested_svm_vmexit(struct vcpu_svm *svm);
 139 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 140                                       bool has_error_code, u32 error_code);
 141
 142 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 143 {
 144         return container_of(vcpu, struct vcpu_svm, vcpu);
 145 }
 146
 147 static inline bool is_nested(struct vcpu_svm *svm)
 148 {
 149         return svm->nested.vmcb;
 150 }
 151
 152 static inline void enable_gif(struct vcpu_svm *svm)
 153 {
 154         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 155 }
 156
 157 static inline void disable_gif(struct vcpu_svm *svm)
 158 {
 159         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 160 }
 161
 162 static inline bool gif_set(struct vcpu_svm *svm)
 163 {
 164         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 165 }
 166
 167 static unsigned long iopm_base;
 168
 169 struct kvm_ldttss_desc {
 170         u16 limit0;
 171         u16 base0;
 172         unsigned base1:8, type:5, dpl:2, p:1;
 173         unsigned limit1:4, zero0:3, g:1, base2:8;
 174         u32 base3;
 175         u32 zero1;
 176 } __attribute__((packed));
 177
 178 struct svm_cpu_data {
 179         int cpu;
 180
 181         u64 asid_generation;
 182         u32 max_asid;
 183         u32 next_asid;
 184         struct kvm_ldttss_desc *tss_desc;
 185
 186         struct page *save_area;
 187 };
 188
 189 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 190 static uint32_t svm_features;
 191
 192 struct svm_init_data {
 193         int cpu;
 194         int r;
 195 };
 196
 197 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 198
 199 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 200 #define MSRS_RANGE_SIZE 2048
 201 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 202
 203 #define MAX_INST_SIZE 15
 204
 205 static inline u32 svm_has(u32 feat)
 206 {
 207         return svm_features & feat;
 208 }
 209
 210 static inline void clgi(void)
 211 {
 212         asm volatile (__ex(SVM_CLGI));
 213 }
 214
 215 static inline void stgi(void)
 216 {
 217         asm volatile (__ex(SVM_STGI));
 218 }
 219
 220 static inline void invlpga(unsigned long addr, u32 asid)
 221 {
 222         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 223 }
 224
 225 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 226 {
 227         to_svm(vcpu)->asid_generation--;
 228 }
 229
 230 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 231 {
 232         force_new_asid(vcpu);
 233 }
 234
 235 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 236 {
 237         if (!npt_enabled && !(efer & EFER_LMA))
 238                 efer &= ~EFER_LME;
 239
 240         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 241         vcpu->arch.efer = efer;
 242 }
 243
 244 static int is_external_interrupt(u32 info)
 245 {
 246         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 247         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 248 }
 249
 250 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 251 {
 252         struct vcpu_svm *svm = to_svm(vcpu);
 253         u32 ret = 0;
 254
 255         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 256                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 257         return ret & mask;
 258 }
 259
 260 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 261 {
 262         struct vcpu_svm *svm = to_svm(vcpu);
 263
 264         if (mask == 0)
 265                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 266         else
 267                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 268
 269 }
 270
 271 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 272 {
 273         struct vcpu_svm *svm = to_svm(vcpu);
 274
 275         if (!svm->next_rip) {
 276                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 277                                 EMULATE_DONE)
 278                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 279                 return;
 280         }
 281         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 282                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 283                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 284
 285         kvm_rip_write(vcpu, svm->next_rip);
 286         svm_set_interrupt_shadow(vcpu, 0);
 287 }
 288
 289 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 290                                 bool has_error_code, u32 error_code)
 291 {
 292         struct vcpu_svm *svm = to_svm(vcpu);
 293
 294         /*
 295          * If we are within a nested VM we'd better #VMEXIT and let the guest
 296          * handle the exception
 297          */
 298         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 299                 return;
 300
 301         if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
 302                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 303
 304                 /*
 305                  * For guest debugging where we have to reinject #BP if some
 306                  * INT3 is guest-owned:
 307                  * Emulate nRIP by moving RIP forward. Will fail if injection
 308                  * raises a fault that is not intercepted. Still better than
 309                  * failing in all cases.
 310                  */
 311                 skip_emulated_instruction(&svm->vcpu);
 312                 rip = kvm_rip_read(&svm->vcpu);
 313                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 314                 svm->int3_injected = rip - old_rip;
 315         }
 316
 317         svm->vmcb->control.event_inj = nr
 318                 | SVM_EVTINJ_VALID
 319                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 320                 | SVM_EVTINJ_TYPE_EXEPT;
 321         svm->vmcb->control.event_inj_err = error_code;
 322 }
 323
 324 static int has_svm(void)
 325 {
 326         const char *msg;
 327
 328         if (!cpu_has_svm(&msg)) {
 329                 printk(KERN_INFO "has_svm: %s\n", msg);
 330                 return 0;
 331         }
 332
 333         return 1;
 334 }
 335
 336 static void svm_hardware_disable(void *garbage)
 337 {
 338         cpu_svm_disable();
 339 }
 340
 341 static int svm_hardware_enable(void *garbage)
 342 {
 343
 344         struct svm_cpu_data *sd;
 345         uint64_t efer;
 346         struct desc_ptr gdt_descr;
 347         struct desc_struct *gdt;
 348         int me = raw_smp_processor_id();
 349
 350         rdmsrl(MSR_EFER, efer);
 351         if (efer & EFER_SVME)
 352                 return -EBUSY;
 353
 354         if (!has_svm()) {
 355                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 356                        me);
 357                 return -EINVAL;
 358         }
 359         sd = per_cpu(svm_data, me);
 360
 361         if (!sd) {
 362                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 363                        me);
 364                 return -EINVAL;
 365         }
 366
 367         sd->asid_generation = 1;
 368         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 369         sd->next_asid = sd->max_asid + 1;
 370
 371         kvm_get_gdt(&gdt_descr);
 372         gdt = (struct desc_struct *)gdt_descr.address;
 373         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 374
 375         wrmsrl(MSR_EFER, efer | EFER_SVME);
 376
 377         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 378
 379         return 0;
 380 }
 381
 382 static void svm_cpu_uninit(int cpu)
 383 {
 384         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 385
 386         if (!sd)
 387                 return;
 388
 389         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 390         __free_page(sd->save_area);
 391         kfree(sd);
 392 }
 393
 394 static int svm_cpu_init(int cpu)
 395 {
 396         struct svm_cpu_data *sd;
 397         int r;
 398
 399         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 400         if (!sd)
 401                 return -ENOMEM;
 402         sd->cpu = cpu;
 403         sd->save_area = alloc_page(GFP_KERNEL);
 404         r = -ENOMEM;
 405         if (!sd->save_area)
 406                 goto err_1;
 407
 408         per_cpu(svm_data, cpu) = sd;
 409
 410         return 0;
 411
 412 err_1:
 413         kfree(sd);
 414         return r;
 415
 416 }
 417
 418 static void set_msr_interception(u32 *msrpm, unsigned msr,
 419                                  int read, int write)
 420 {
 421         int i;
 422
 423         for (i = 0; i < NUM_MSR_MAPS; i++) {
 424                 if (msr >= msrpm_ranges[i] &&
 425                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 426                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 427                                           msrpm_ranges[i]) * 2;
 428
 429                         u32 *base = msrpm + (msr_offset / 32);
 430                         u32 msr_shift = msr_offset % 32;
 431                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 432                         *base = (*base & ~(0x3 << msr_shift)) |
 433                                 (mask << msr_shift);
 434                         return;
 435                 }
 436         }
 437         BUG();
 438 }
 439
 440 static void svm_vcpu_init_msrpm(u32 *msrpm)
 441 {
 442         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 443
 444 #ifdef CONFIG_X86_64
 445         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 446         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 447         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 448         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 449         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 450         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 451 #endif
 452         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 453         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 454 }
 455
 456 static void svm_enable_lbrv(struct vcpu_svm *svm)
 457 {
 458         u32 *msrpm = svm->msrpm;
 459
 460         svm->vmcb->control.lbr_ctl = 1;
 461         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 462         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 463         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 464         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 465 }
 466
 467 static void svm_disable_lbrv(struct vcpu_svm *svm)
 468 {
 469         u32 *msrpm = svm->msrpm;
 470
 471         svm->vmcb->control.lbr_ctl = 0;
 472         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 473         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 474         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 475         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 476 }
 477
 478 static __init int svm_hardware_setup(void)
 479 {
 480         int cpu;
 481         struct page *iopm_pages;
 482         void *iopm_va;
 483         int r;
 484
 485         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 486
 487         if (!iopm_pages)
 488                 return -ENOMEM;
 489
 490         iopm_va = page_address(iopm_pages);
 491         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 492         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 493
 494         if (boot_cpu_has(X86_FEATURE_NX))
 495                 kvm_enable_efer_bits(EFER_NX);
 496
 497         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 498                 kvm_enable_efer_bits(EFER_FFXSR);
 499
 500         if (nested) {
 501                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 502                 kvm_enable_efer_bits(EFER_SVME);
 503         }
 504
 505         for_each_possible_cpu(cpu) {
 506                 r = svm_cpu_init(cpu);
 507                 if (r)
 508                         goto err;
 509         }
 510
 511         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 512
 513         if (!svm_has(SVM_FEATURE_NPT))
 514                 npt_enabled = false;
 515
 516         if (npt_enabled && !npt) {
 517                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 518                 npt_enabled = false;
 519         }
 520
 521         if (npt_enabled) {
 522                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 523                 kvm_enable_tdp();
 524         } else
 525                 kvm_disable_tdp();
 526
 527         return 0;
 528
 529 err:
 530         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 531         iopm_base = 0;
 532         return r;
 533 }
 534
 535 static __exit void svm_hardware_unsetup(void)
 536 {
 537         int cpu;
 538
 539         for_each_possible_cpu(cpu)
 540                 svm_cpu_uninit(cpu);
 541
 542         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 543         iopm_base = 0;
 544 }
 545
 546 static void init_seg(struct vmcb_seg *seg)
 547 {
 548         seg->selector = 0;
 549         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 550                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 551         seg->limit = 0xffff;
 552         seg->base = 0;
 553 }
 554
 555 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 556 {
 557         seg->selector = 0;
 558         seg->attrib = SVM_SELECTOR_P_MASK | type;
 559         seg->limit = 0xffff;
 560         seg->base = 0;
 561 }
 562
 563 static void init_vmcb(struct vcpu_svm *svm)
 564 {
 565         struct vmcb_control_area *control = &svm->vmcb->control;
 566         struct vmcb_save_area *save = &svm->vmcb->save;
 567
 568         svm->vcpu.fpu_active = 1;
 569
 570         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 571                                         INTERCEPT_CR3_MASK |
 572                                         INTERCEPT_CR4_MASK;
 573
 574         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 575                                         INTERCEPT_CR3_MASK |
 576                                         INTERCEPT_CR4_MASK |
 577                                         INTERCEPT_CR8_MASK;
 578
 579         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 580                                         INTERCEPT_DR1_MASK |
 581                                         INTERCEPT_DR2_MASK |
 582                                         INTERCEPT_DR3_MASK |
 583                                         INTERCEPT_DR4_MASK |
 584                                         INTERCEPT_DR5_MASK |
 585                                         INTERCEPT_DR6_MASK |
 586                                         INTERCEPT_DR7_MASK;
 587
 588         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 589                                         INTERCEPT_DR1_MASK |
 590                                         INTERCEPT_DR2_MASK |
 591                                         INTERCEPT_DR3_MASK |
 592                                         INTERCEPT_DR4_MASK |
 593                                         INTERCEPT_DR5_MASK |
 594                                         INTERCEPT_DR6_MASK |
 595                                         INTERCEPT_DR7_MASK;
 596
 597         control->intercept_exceptions = (1 << PF_VECTOR) |
 598                                         (1 << UD_VECTOR) |
 599                                         (1 << MC_VECTOR);
 600
 601
 602         control->intercept =    (1ULL << INTERCEPT_INTR) |
 603                                 (1ULL << INTERCEPT_NMI) |
 604                                 (1ULL << INTERCEPT_SMI) |
 605                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 606                                 (1ULL << INTERCEPT_CPUID) |
 607                                 (1ULL << INTERCEPT_INVD) |
 608                                 (1ULL << INTERCEPT_HLT) |
 609                                 (1ULL << INTERCEPT_INVLPG) |
 610                                 (1ULL << INTERCEPT_INVLPGA) |
 611                                 (1ULL << INTERCEPT_IOIO_PROT) |
 612                                 (1ULL << INTERCEPT_MSR_PROT) |
 613                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 614                                 (1ULL << INTERCEPT_SHUTDOWN) |
 615                                 (1ULL << INTERCEPT_VMRUN) |
 616                                 (1ULL << INTERCEPT_VMMCALL) |
 617                                 (1ULL << INTERCEPT_VMLOAD) |
 618                                 (1ULL << INTERCEPT_VMSAVE) |
 619                                 (1ULL << INTERCEPT_STGI) |
 620                                 (1ULL << INTERCEPT_CLGI) |
 621                                 (1ULL << INTERCEPT_SKINIT) |
 622                                 (1ULL << INTERCEPT_WBINVD) |
 623                                 (1ULL << INTERCEPT_MONITOR) |
 624                                 (1ULL << INTERCEPT_MWAIT);
 625
 626         control->iopm_base_pa = iopm_base;
 627         control->msrpm_base_pa = __pa(svm->msrpm);
 628         control->tsc_offset = 0;
 629         control->int_ctl = V_INTR_MASKING_MASK;
 630
 631         init_seg(&save->es);
 632         init_seg(&save->ss);
 633         init_seg(&save->ds);
 634         init_seg(&save->fs);
 635         init_seg(&save->gs);
 636
 637         save->cs.selector = 0xf000;
 638         /* Executable/Readable Code Segment */
 639         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 640                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 641         save->cs.limit = 0xffff;
 642         /*
 643          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 644          * be consistent with it.
 645          *
 646          * Replace when we have real mode working for vmx.
 647          */
 648         save->cs.base = 0xf0000;
 649
 650         save->gdtr.limit = 0xffff;
 651         save->idtr.limit = 0xffff;
 652
 653         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 654         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 655
 656         save->efer = EFER_SVME;
 657         save->dr6 = 0xffff0ff0;
 658         save->dr7 = 0x400;
 659         save->rflags = 2;
 660         save->rip = 0x0000fff0;
 661         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 662
 663         /*
 664          * This is the guest-visible cr0 value.
 665          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 666          */
 667         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 668         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 669
 670         save->cr4 = X86_CR4_PAE;
 671         /* rdx = ?? */
 672
 673         if (npt_enabled) {
 674                 /* Setup VMCB for Nested Paging */
 675                 control->nested_ctl = 1;
 676                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 677                                         (1ULL << INTERCEPT_INVLPG));
 678                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 679                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 680                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 681                 save->g_pat = 0x0007040600070406ULL;
 682                 save->cr3 = 0;
 683                 save->cr4 = 0;
 684         }
 685         force_new_asid(&svm->vcpu);
 686
 687         svm->nested.vmcb = 0;
 688         svm->vcpu.arch.hflags = 0;
 689
 690         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 691                 control->pause_filter_count = 3000;
 692                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 693         }
 694
 695         enable_gif(svm);
 696 }
 697
 698 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 699 {
 700         struct vcpu_svm *svm = to_svm(vcpu);
 701
 702         init_vmcb(svm);
 703
 704         if (!kvm_vcpu_is_bsp(vcpu)) {
 705                 kvm_rip_write(vcpu, 0);
 706                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 707                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 708         }
 709         vcpu->arch.regs_avail = ~0;
 710         vcpu->arch.regs_dirty = ~0;
 711
 712         return 0;
 713 }
 714
 715 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 716 {
 717         struct vcpu_svm *svm;
 718         struct page *page;
 719         struct page *msrpm_pages;
 720         struct page *hsave_page;
 721         struct page *nested_msrpm_pages;
 722         int err;
 723
 724         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 725         if (!svm) {
 726                 err = -ENOMEM;
 727                 goto out;
 728         }
 729
 730         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 731         if (err)
 732                 goto free_svm;
 733
 734         err = -ENOMEM;
 735         page = alloc_page(GFP_KERNEL);
 736         if (!page)
 737                 goto uninit;
 738
 739         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 740         if (!msrpm_pages)
 741                 goto free_page1;
 742
 743         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 744         if (!nested_msrpm_pages)
 745                 goto free_page2;
 746
 747         hsave_page = alloc_page(GFP_KERNEL);
 748         if (!hsave_page)
 749                 goto free_page3;
 750
 751         svm->nested.hsave = page_address(hsave_page);
 752
 753         svm->msrpm = page_address(msrpm_pages);
 754         svm_vcpu_init_msrpm(svm->msrpm);
 755
 756         svm->nested.msrpm = page_address(nested_msrpm_pages);
 757
 758         svm->vmcb = page_address(page);
 759         clear_page(svm->vmcb);
 760         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 761         svm->asid_generation = 0;
 762         init_vmcb(svm);
 763
 764         fx_init(&svm->vcpu);
 765         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 766         if (kvm_vcpu_is_bsp(&svm->vcpu))
 767                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 768
 769         return &svm->vcpu;
 770
 771 free_page3:
 772         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 773 free_page2:
 774         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 775 free_page1:
 776         __free_page(page);
 777 uninit:
 778         kvm_vcpu_uninit(&svm->vcpu);
 779 free_svm:
 780         kmem_cache_free(kvm_vcpu_cache, svm);
 781 out:
 782         return ERR_PTR(err);
 783 }
 784
 785 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 786 {
 787         struct vcpu_svm *svm = to_svm(vcpu);
 788
 789         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 790         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 791         __free_page(virt_to_page(svm->nested.hsave));
 792         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 793         kvm_vcpu_uninit(vcpu);
 794         kmem_cache_free(kvm_vcpu_cache, svm);
 795 }
 796
 797 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 798 {
 799         struct vcpu_svm *svm = to_svm(vcpu);
 800         int i;
 801
 802         if (unlikely(cpu != vcpu->cpu)) {
 803                 u64 delta;
 804
 805                 if (check_tsc_unstable()) {
 806                         /*
 807                          * Make sure that the guest sees a monotonically
 808                          * increasing TSC.
 809                          */
 810                         delta = vcpu->arch.host_tsc - native_read_tsc();
 811                         svm->vmcb->control.tsc_offset += delta;
 812                         if (is_nested(svm))
 813                                 svm->nested.hsave->control.tsc_offset += delta;
 814                 }
 815                 vcpu->cpu = cpu;
 816                 kvm_migrate_timers(vcpu);
 817                 svm->asid_generation = 0;
 818         }
 819
 820         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 821                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 822 }
 823
 824 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 825 {
 826         struct vcpu_svm *svm = to_svm(vcpu);
 827         int i;
 828
 829         ++vcpu->stat.host_state_reload;
 830         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 831                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 832
 833         vcpu->arch.host_tsc = native_read_tsc();
 834 }
 835
 836 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 837 {
 838         return to_svm(vcpu)->vmcb->save.rflags;
 839 }
 840
 841 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 842 {
 843         to_svm(vcpu)->vmcb->save.rflags = rflags;
 844 }
 845
 846 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 847 {
 848         switch (reg) {
 849         case VCPU_EXREG_PDPTR:
 850                 BUG_ON(!npt_enabled);
 851                 load_pdptrs(vcpu, vcpu->arch.cr3);
 852                 break;
 853         default:
 854                 BUG();
 855         }
 856 }
 857
 858 static void svm_set_vintr(struct vcpu_svm *svm)
 859 {
 860         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 861 }
 862
 863 static void svm_clear_vintr(struct vcpu_svm *svm)
 864 {
 865         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 866 }
 867
 868 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 869 {
 870         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 871
 872         switch (seg) {
 873         case VCPU_SREG_CS: return &save->cs;
 874         case VCPU_SREG_DS: return &save->ds;
 875         case VCPU_SREG_ES: return &save->es;
 876         case VCPU_SREG_FS: return &save->fs;
 877         case VCPU_SREG_GS: return &save->gs;
 878         case VCPU_SREG_SS: return &save->ss;
 879         case VCPU_SREG_TR: return &save->tr;
 880         case VCPU_SREG_LDTR: return &save->ldtr;
 881         }
 882         BUG();
 883         return NULL;
 884 }
 885
 886 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 887 {
 888         struct vmcb_seg *s = svm_seg(vcpu, seg);
 889
 890         return s->base;
 891 }
 892
 893 static void svm_get_segment(struct kvm_vcpu *vcpu,
 894                             struct kvm_segment *var, int seg)
 895 {
 896         struct vmcb_seg *s = svm_seg(vcpu, seg);
 897
 898         var->base = s->base;
 899         var->limit = s->limit;
 900         var->selector = s->selector;
 901         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 902         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 903         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 904         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 905         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 906         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 907         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 908         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 909
 910         /*
 911          * AMD's VMCB does not have an explicit unusable field, so emulate it
 912          * for cross vendor migration purposes by "not present"
 913          */
 914         var->unusable = !var->present || (var->type == 0);
 915
 916         switch (seg) {
 917         case VCPU_SREG_CS:
 918                 /*
 919                  * SVM always stores 0 for the 'G' bit in the CS selector in
 920                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 921                  * Intel's VMENTRY has a check on the 'G' bit.
 922                  */
 923                 var->g = s->limit > 0xfffff;
 924                 break;
 925         case VCPU_SREG_TR:
 926                 /*
 927                  * Work around a bug where the busy flag in the tr selector
 928                  * isn't exposed
 929                  */
 930                 var->type |= 0x2;
 931                 break;
 932         case VCPU_SREG_DS:
 933         case VCPU_SREG_ES:
 934         case VCPU_SREG_FS:
 935         case VCPU_SREG_GS:
 936                 /*
 937                  * The accessed bit must always be set in the segment
 938                  * descriptor cache, although it can be cleared in the
 939                  * descriptor, the cached bit always remains at 1. Since
 940                  * Intel has a check on this, set it here to support
 941                  * cross-vendor migration.
 942                  */
 943                 if (!var->unusable)
 944                         var->type |= 0x1;
 945                 break;
 946         case VCPU_SREG_SS:
 947                 /*
 948                  * On AMD CPUs sometimes the DB bit in the segment
 949                  * descriptor is left as 1, although the whole segment has
 950                  * been made unusable. Clear it here to pass an Intel VMX
 951                  * entry check when cross vendor migrating.
 952                  */
 953                 if (var->unusable)
 954                         var->db = 0;
 955                 break;
 956         }
 957 }
 958
 959 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 960 {
 961         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 962
 963         return save->cpl;
 964 }
 965
 966 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 967 {
 968         struct vcpu_svm *svm = to_svm(vcpu);
 969
 970         dt->size = svm->vmcb->save.idtr.limit;
 971         dt->address = svm->vmcb->save.idtr.base;
 972 }
 973
 974 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 975 {
 976         struct vcpu_svm *svm = to_svm(vcpu);
 977
 978         svm->vmcb->save.idtr.limit = dt->size;
 979         svm->vmcb->save.idtr.base = dt->address ;
 980 }
 981
 982 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 983 {
 984         struct vcpu_svm *svm = to_svm(vcpu);
 985
 986         dt->size = svm->vmcb->save.gdtr.limit;
 987         dt->address = svm->vmcb->save.gdtr.base;
 988 }
 989
 990 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 991 {
 992         struct vcpu_svm *svm = to_svm(vcpu);
 993
 994         svm->vmcb->save.gdtr.limit = dt->size;
 995         svm->vmcb->save.gdtr.base = dt->address ;
 996 }
 997
 998 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
 999 {
1000 }
1001
1002 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1003 {
1004 }
1005
1006 static void update_cr0_intercept(struct vcpu_svm *svm)
1007 {
1008         struct vmcb *vmcb = svm->vmcb;
1009         ulong gcr0 = svm->vcpu.arch.cr0;
1010         u64 *hcr0 = &svm->vmcb->save.cr0;
1011
1012         if (!svm->vcpu.fpu_active)
1013                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1014         else
1015                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1016                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1017
1018
1019         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1020                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1021                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1022                 if (is_nested(svm)) {
1023                         struct vmcb *hsave = svm->nested.hsave;
1024
1025                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1026                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1027                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1028                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1029                 }
1030         } else {
1031                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1032                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1033                 if (is_nested(svm)) {
1034                         struct vmcb *hsave = svm->nested.hsave;
1035
1036                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1037                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1038                 }
1039         }
1040 }
1041
1042 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1043 {
1044         struct vcpu_svm *svm = to_svm(vcpu);
1045
1046 #ifdef CONFIG_X86_64
1047         if (vcpu->arch.efer & EFER_LME) {
1048                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1049                         vcpu->arch.efer |= EFER_LMA;
1050                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1051                 }
1052
1053                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1054                         vcpu->arch.efer &= ~EFER_LMA;
1055                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1056                 }
1057         }
1058 #endif
1059         vcpu->arch.cr0 = cr0;
1060
1061         if (!npt_enabled)
1062                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1063
1064         if (!vcpu->fpu_active)
1065                 cr0 |= X86_CR0_TS;
1066         /*
1067          * re-enable caching here because the QEMU bios
1068          * does not do it - this results in some delay at
1069          * reboot
1070          */
1071         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1072         svm->vmcb->save.cr0 = cr0;
1073         update_cr0_intercept(svm);
1074 }
1075
1076 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1077 {
1078         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1079         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1080
1081         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1082                 force_new_asid(vcpu);
1083
1084         vcpu->arch.cr4 = cr4;
1085         if (!npt_enabled)
1086                 cr4 |= X86_CR4_PAE;
1087         cr4 |= host_cr4_mce;
1088         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1089 }
1090
1091 static void svm_set_segment(struct kvm_vcpu *vcpu,
1092                             struct kvm_segment *var, int seg)
1093 {
1094         struct vcpu_svm *svm = to_svm(vcpu);
1095         struct vmcb_seg *s = svm_seg(vcpu, seg);
1096
1097         s->base = var->base;
1098         s->limit = var->limit;
1099         s->selector = var->selector;
1100         if (var->unusable)
1101                 s->attrib = 0;
1102         else {
1103                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1104                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1105                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1106                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1107                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1108                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1109                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1110                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1111         }
1112         if (seg == VCPU_SREG_CS)
1113                 svm->vmcb->save.cpl
1114                         = (svm->vmcb->save.cs.attrib
1115                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1116
1117 }
1118
1119 static void update_db_intercept(struct kvm_vcpu *vcpu)
1120 {
1121         struct vcpu_svm *svm = to_svm(vcpu);
1122
1123         svm->vmcb->control.intercept_exceptions &=
1124                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1125
1126         if (svm->nmi_singlestep)
1127                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1128
1129         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1130                 if (vcpu->guest_debug &
1131                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1132                         svm->vmcb->control.intercept_exceptions |=
1133                                 1 << DB_VECTOR;
1134                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1135                         svm->vmcb->control.intercept_exceptions |=
1136                                 1 << BP_VECTOR;
1137         } else
1138                 vcpu->guest_debug = 0;
1139 }
1140
1141 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1142 {
1143         struct vcpu_svm *svm = to_svm(vcpu);
1144
1145         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1146                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1147         else
1148                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1149
1150         update_db_intercept(vcpu);
1151 }
1152
1153 static void load_host_msrs(struct kvm_vcpu *vcpu)
1154 {
1155 #ifdef CONFIG_X86_64
1156         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1157 #endif
1158 }
1159
1160 static void save_host_msrs(struct kvm_vcpu *vcpu)
1161 {
1162 #ifdef CONFIG_X86_64
1163         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1164 #endif
1165 }
1166
1167 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1168 {
1169         if (sd->next_asid > sd->max_asid) {
1170                 ++sd->asid_generation;
1171                 sd->next_asid = 1;
1172                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1173         }
1174
1175         svm->asid_generation = sd->asid_generation;
1176         svm->vmcb->control.asid = sd->next_asid++;
1177 }
1178
1179 static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
1180 {
1181         struct vcpu_svm *svm = to_svm(vcpu);
1182
1183         switch (dr) {
1184         case 0 ... 3:
1185                 *dest = vcpu->arch.db[dr];
1186                 break;
1187         case 4:
1188                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1189                         return EMULATE_FAIL; /* will re-inject UD */
1190                 /* fall through */
1191         case 6:
1192                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1193                         *dest = vcpu->arch.dr6;
1194                 else
1195                         *dest = svm->vmcb->save.dr6;
1196                 break;
1197         case 5:
1198                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1199                         return EMULATE_FAIL; /* will re-inject UD */
1200                 /* fall through */
1201         case 7:
1202                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1203                         *dest = vcpu->arch.dr7;
1204                 else
1205                         *dest = svm->vmcb->save.dr7;
1206                 break;
1207         }
1208
1209         return EMULATE_DONE;
1210 }
1211
1212 static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
1213 {
1214         struct vcpu_svm *svm = to_svm(vcpu);
1215
1216         switch (dr) {
1217         case 0 ... 3:
1218                 vcpu->arch.db[dr] = value;
1219                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1220                         vcpu->arch.eff_db[dr] = value;
1221                 break;
1222         case 4:
1223                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1224                         return EMULATE_FAIL; /* will re-inject UD */
1225                 /* fall through */
1226         case 6:
1227                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1228                 break;
1229         case 5:
1230                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1231                         return EMULATE_FAIL; /* will re-inject UD */
1232                 /* fall through */
1233         case 7:
1234                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1235                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1236                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1237                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1238                 }
1239                 break;
1240         }
1241
1242         return EMULATE_DONE;
1243 }
1244
1245 static int pf_interception(struct vcpu_svm *svm)
1246 {
1247         u64 fault_address;
1248         u32 error_code;
1249
1250         fault_address  = svm->vmcb->control.exit_info_2;
1251         error_code = svm->vmcb->control.exit_info_1;
1252
1253         trace_kvm_page_fault(fault_address, error_code);
1254         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1255                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1256         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1257 }
1258
1259 static int db_interception(struct vcpu_svm *svm)
1260 {
1261         struct kvm_run *kvm_run = svm->vcpu.run;
1262
1263         if (!(svm->vcpu.guest_debug &
1264               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1265                 !svm->nmi_singlestep) {
1266                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1267                 return 1;
1268         }
1269
1270         if (svm->nmi_singlestep) {
1271                 svm->nmi_singlestep = false;
1272                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1273                         svm->vmcb->save.rflags &=
1274                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1275                 update_db_intercept(&svm->vcpu);
1276         }
1277
1278         if (svm->vcpu.guest_debug &
1279             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1280                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1281                 kvm_run->debug.arch.pc =
1282                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1283                 kvm_run->debug.arch.exception = DB_VECTOR;
1284                 return 0;
1285         }
1286
1287         return 1;
1288 }
1289
1290 static int bp_interception(struct vcpu_svm *svm)
1291 {
1292         struct kvm_run *kvm_run = svm->vcpu.run;
1293
1294         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1295         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1296         kvm_run->debug.arch.exception = BP_VECTOR;
1297         return 0;
1298 }
1299
1300 static int ud_interception(struct vcpu_svm *svm)
1301 {
1302         int er;
1303
1304         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1305         if (er != EMULATE_DONE)
1306                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1307         return 1;
1308 }
1309
1310 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1311 {
1312         struct vcpu_svm *svm = to_svm(vcpu);
1313         u32 excp;
1314
1315         if (is_nested(svm)) {
1316                 u32 h_excp, n_excp;
1317
1318                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1319                 n_excp  = svm->nested.intercept_exceptions;
1320                 h_excp &= ~(1 << NM_VECTOR);
1321                 excp    = h_excp | n_excp;
1322         } else {
1323                 excp  = svm->vmcb->control.intercept_exceptions;
1324                 excp &= ~(1 << NM_VECTOR);
1325         }
1326
1327         svm->vmcb->control.intercept_exceptions = excp;
1328
1329         svm->vcpu.fpu_active = 1;
1330         update_cr0_intercept(svm);
1331 }
1332
1333 static int nm_interception(struct vcpu_svm *svm)
1334 {
1335         svm_fpu_activate(&svm->vcpu);
1336         return 1;
1337 }
1338
1339 static int mc_interception(struct vcpu_svm *svm)
1340 {
1341         /*
1342          * On an #MC intercept the MCE handler is not called automatically in
1343          * the host. So do it by hand here.
1344          */
1345         asm volatile (
1346                 "int $0x12\n");
1347         /* not sure if we ever come back to this point */
1348
1349         return 1;
1350 }
1351
1352 static int shutdown_interception(struct vcpu_svm *svm)
1353 {
1354         struct kvm_run *kvm_run = svm->vcpu.run;
1355
1356         /*
1357          * VMCB is undefined after a SHUTDOWN intercept
1358          * so reinitialize it.
1359          */
1360         clear_page(svm->vmcb);
1361         init_vmcb(svm);
1362
1363         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1364         return 0;
1365 }
1366
1367 static int io_interception(struct vcpu_svm *svm)
1368 {
1369         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1370         int size, in, string;
1371         unsigned port;
1372
1373         ++svm->vcpu.stat.io_exits;
1374
1375         svm->next_rip = svm->vmcb->control.exit_info_2;
1376
1377         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1378
1379         if (string) {
1380                 if (emulate_instruction(&svm->vcpu,
1381                                         0, 0, 0) == EMULATE_DO_MMIO)
1382                         return 0;
1383                 return 1;
1384         }
1385
1386         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1387         port = io_info >> 16;
1388         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1389
1390         skip_emulated_instruction(&svm->vcpu);
1391         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1392 }
1393
1394 static int nmi_interception(struct vcpu_svm *svm)
1395 {
1396         return 1;
1397 }
1398
1399 static int intr_interception(struct vcpu_svm *svm)
1400 {
1401         ++svm->vcpu.stat.irq_exits;
1402         return 1;
1403 }
1404
1405 static int nop_on_interception(struct vcpu_svm *svm)
1406 {
1407         return 1;
1408 }
1409
1410 static int halt_interception(struct vcpu_svm *svm)
1411 {
1412         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1413         skip_emulated_instruction(&svm->vcpu);
1414         return kvm_emulate_halt(&svm->vcpu);
1415 }
1416
1417 static int vmmcall_interception(struct vcpu_svm *svm)
1418 {
1419         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1420         skip_emulated_instruction(&svm->vcpu);
1421         kvm_emulate_hypercall(&svm->vcpu);
1422         return 1;
1423 }
1424
1425 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1426 {
1427         if (!(svm->vcpu.arch.efer & EFER_SVME)
1428             || !is_paging(&svm->vcpu)) {
1429                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1430                 return 1;
1431         }
1432
1433         if (svm->vmcb->save.cpl) {
1434                 kvm_inject_gp(&svm->vcpu, 0);
1435                 return 1;
1436         }
1437
1438        return 0;
1439 }
1440
1441 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1442                                       bool has_error_code, u32 error_code)
1443 {
1444         int vmexit;
1445
1446         if (!is_nested(svm))
1447                 return 0;
1448
1449         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1450         svm->vmcb->control.exit_code_hi = 0;
1451         svm->vmcb->control.exit_info_1 = error_code;
1452         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1453
1454         vmexit = nested_svm_intercept(svm);
1455         if (vmexit == NESTED_EXIT_DONE)
1456                 svm->nested.exit_required = true;
1457
1458         return vmexit;
1459 }
1460
1461 /* This function returns true if it is save to enable the irq window */
1462 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1463 {
1464         if (!is_nested(svm))
1465                 return true;
1466
1467         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1468                 return true;
1469
1470         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1471                 return false;
1472
1473         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1474
1475         if (svm->nested.intercept & 1ULL) {
1476                 /*
1477                  * The #vmexit can't be emulated here directly because this
1478                  * code path runs with irqs and preemtion disabled. A
1479                  * #vmexit emulation might sleep. Only signal request for
1480                  * the #vmexit here.
1481                  */
1482                 svm->nested.exit_required = true;
1483                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1484                 return false;
1485         }
1486
1487         return true;
1488 }
1489
1490 /* This function returns true if it is save to enable the nmi window */
1491 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1492 {
1493         if (!is_nested(svm))
1494                 return true;
1495
1496         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1497                 return true;
1498
1499         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1500         svm->nested.exit_required = true;
1501
1502         return false;
1503 }
1504
1505 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1506 {
1507         struct page *page;
1508
1509         might_sleep();
1510
1511         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1512         if (is_error_page(page))
1513                 goto error;
1514
1515         *_page = page;
1516
1517         return kmap(page);
1518
1519 error:
1520         kvm_release_page_clean(page);
1521         kvm_inject_gp(&svm->vcpu, 0);
1522
1523         return NULL;
1524 }
1525
1526 static void nested_svm_unmap(struct page *page)
1527 {
1528         kunmap(page);
1529         kvm_release_page_dirty(page);
1530 }
1531
1532 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1533 {
1534         u32 param = svm->vmcb->control.exit_info_1 & 1;
1535         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1536         bool ret = false;
1537         u32 t0, t1;
1538         u8 val;
1539
1540         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1541                 return false;
1542
1543         switch (msr) {
1544         case 0 ... 0x1fff:
1545                 t0 = (msr * 2) % 8;
1546                 t1 = msr / 8;
1547                 break;
1548         case 0xc0000000 ... 0xc0001fff:
1549                 t0 = (8192 + msr - 0xc0000000) * 2;
1550                 t1 = (t0 / 8);
1551                 t0 %= 8;
1552                 break;
1553         case 0xc0010000 ... 0xc0011fff:
1554                 t0 = (16384 + msr - 0xc0010000) * 2;
1555                 t1 = (t0 / 8);
1556                 t0 %= 8;
1557                 break;
1558         default:
1559                 ret = true;
1560                 goto out;
1561         }
1562
1563         if (!kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + t1, &val, 1))
1564                 ret = val & ((1 << param) << t0);
1565
1566 out:
1567         return ret;
1568 }
1569
1570 static int nested_svm_exit_special(struct vcpu_svm *svm)
1571 {
1572         u32 exit_code = svm->vmcb->control.exit_code;
1573
1574         switch (exit_code) {
1575         case SVM_EXIT_INTR:
1576         case SVM_EXIT_NMI:
1577                 return NESTED_EXIT_HOST;
1578         case SVM_EXIT_NPF:
1579                 /* For now we are always handling NPFs when using them */
1580                 if (npt_enabled)
1581                         return NESTED_EXIT_HOST;
1582                 break;
1583         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1584                 /* When we're shadowing, trap PFs */
1585                 if (!npt_enabled)
1586                         return NESTED_EXIT_HOST;
1587                 break;
1588         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1589                 nm_interception(svm);
1590                 break;
1591         default:
1592                 break;
1593         }
1594
1595         return NESTED_EXIT_CONTINUE;
1596 }
1597
1598 /*
1599  * If this function returns true, this #vmexit was already handled
1600  */
1601 static int nested_svm_intercept(struct vcpu_svm *svm)
1602 {
1603         u32 exit_code = svm->vmcb->control.exit_code;
1604         int vmexit = NESTED_EXIT_HOST;
1605
1606         switch (exit_code) {
1607         case SVM_EXIT_MSR:
1608                 vmexit = nested_svm_exit_handled_msr(svm);
1609                 break;
1610         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1611                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1612                 if (svm->nested.intercept_cr_read & cr_bits)
1613                         vmexit = NESTED_EXIT_DONE;
1614                 break;
1615         }
1616         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1617                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1618                 if (svm->nested.intercept_cr_write & cr_bits)
1619                         vmexit = NESTED_EXIT_DONE;
1620                 break;
1621         }
1622         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1623                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1624                 if (svm->nested.intercept_dr_read & dr_bits)
1625                         vmexit = NESTED_EXIT_DONE;
1626                 break;
1627         }
1628         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1629                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1630                 if (svm->nested.intercept_dr_write & dr_bits)
1631                         vmexit = NESTED_EXIT_DONE;
1632                 break;
1633         }
1634         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1635                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1636                 if (svm->nested.intercept_exceptions & excp_bits)
1637                         vmexit = NESTED_EXIT_DONE;
1638                 break;
1639         }
1640         default: {
1641                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1642                 if (svm->nested.intercept & exit_bits)
1643                         vmexit = NESTED_EXIT_DONE;
1644         }
1645         }
1646
1647         return vmexit;
1648 }
1649
1650 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1651 {
1652         int vmexit;
1653
1654         vmexit = nested_svm_intercept(svm);
1655
1656         if (vmexit == NESTED_EXIT_DONE)
1657                 nested_svm_vmexit(svm);
1658
1659         return vmexit;
1660 }
1661
1662 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1663 {
1664         struct vmcb_control_area *dst  = &dst_vmcb->control;
1665         struct vmcb_control_area *from = &from_vmcb->control;
1666
1667         dst->intercept_cr_read    = from->intercept_cr_read;
1668         dst->intercept_cr_write   = from->intercept_cr_write;
1669         dst->intercept_dr_read    = from->intercept_dr_read;
1670         dst->intercept_dr_write   = from->intercept_dr_write;
1671         dst->intercept_exceptions = from->intercept_exceptions;
1672         dst->intercept            = from->intercept;
1673         dst->iopm_base_pa         = from->iopm_base_pa;
1674         dst->msrpm_base_pa        = from->msrpm_base_pa;
1675         dst->tsc_offset           = from->tsc_offset;
1676         dst->asid                 = from->asid;
1677         dst->tlb_ctl              = from->tlb_ctl;
1678         dst->int_ctl              = from->int_ctl;
1679         dst->int_vector           = from->int_vector;
1680         dst->int_state            = from->int_state;
1681         dst->exit_code            = from->exit_code;
1682         dst->exit_code_hi         = from->exit_code_hi;
1683         dst->exit_info_1          = from->exit_info_1;
1684         dst->exit_info_2          = from->exit_info_2;
1685         dst->exit_int_info        = from->exit_int_info;
1686         dst->exit_int_info_err    = from->exit_int_info_err;
1687         dst->nested_ctl           = from->nested_ctl;
1688         dst->event_inj            = from->event_inj;
1689         dst->event_inj_err        = from->event_inj_err;
1690         dst->nested_cr3           = from->nested_cr3;
1691         dst->lbr_ctl              = from->lbr_ctl;
1692 }
1693
1694 static int nested_svm_vmexit(struct vcpu_svm *svm)
1695 {
1696         struct vmcb *nested_vmcb;
1697         struct vmcb *hsave = svm->nested.hsave;
1698         struct vmcb *vmcb = svm->vmcb;
1699         struct page *page;
1700
1701         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1702                                        vmcb->control.exit_info_1,
1703                                        vmcb->control.exit_info_2,
1704                                        vmcb->control.exit_int_info,
1705                                        vmcb->control.exit_int_info_err);
1706
1707         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1708         if (!nested_vmcb)
1709                 return 1;
1710
1711         /* Exit nested SVM mode */
1712         svm->nested.vmcb = 0;
1713
1714         /* Give the current vmcb to the guest */
1715         disable_gif(svm);
1716
1717         nested_vmcb->save.es     = vmcb->save.es;
1718         nested_vmcb->save.cs     = vmcb->save.cs;
1719         nested_vmcb->save.ss     = vmcb->save.ss;
1720         nested_vmcb->save.ds     = vmcb->save.ds;
1721         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1722         nested_vmcb->save.idtr   = vmcb->save.idtr;
1723         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1724         if (npt_enabled)
1725                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1726         else
1727                 nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1728         nested_vmcb->save.cr2    = vmcb->save.cr2;
1729         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1730         nested_vmcb->save.rflags = vmcb->save.rflags;
1731         nested_vmcb->save.rip    = vmcb->save.rip;
1732         nested_vmcb->save.rsp    = vmcb->save.rsp;
1733         nested_vmcb->save.rax    = vmcb->save.rax;
1734         nested_vmcb->save.dr7    = vmcb->save.dr7;
1735         nested_vmcb->save.dr6    = vmcb->save.dr6;
1736         nested_vmcb->save.cpl    = vmcb->save.cpl;
1737
1738         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1739         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1740         nested_vmcb->control.int_state         = vmcb->control.int_state;
1741         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1742         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1743         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1744         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1745         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1746         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1747
1748         /*
1749          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1750          * to make sure that we do not lose injected events. So check event_inj
1751          * here and copy it to exit_int_info if it is valid.
1752          * Exit_int_info and event_inj can't be both valid because the case
1753          * below only happens on a VMRUN instruction intercept which has
1754          * no valid exit_int_info set.
1755          */
1756         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1757                 struct vmcb_control_area *nc = &nested_vmcb->control;
1758
1759                 nc->exit_int_info     = vmcb->control.event_inj;
1760                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1761         }
1762
1763         nested_vmcb->control.tlb_ctl           = 0;
1764         nested_vmcb->control.event_inj         = 0;
1765         nested_vmcb->control.event_inj_err     = 0;
1766
1767         /* We always set V_INTR_MASKING and remember the old value in hflags */
1768         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1769                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1770
1771         /* Restore the original control entries */
1772         copy_vmcb_control_area(vmcb, hsave);
1773
1774         kvm_clear_exception_queue(&svm->vcpu);
1775         kvm_clear_interrupt_queue(&svm->vcpu);
1776
1777         /* Restore selected save entries */
1778         svm->vmcb->save.es = hsave->save.es;
1779         svm->vmcb->save.cs = hsave->save.cs;
1780         svm->vmcb->save.ss = hsave->save.ss;
1781         svm->vmcb->save.ds = hsave->save.ds;
1782         svm->vmcb->save.gdtr = hsave->save.gdtr;
1783         svm->vmcb->save.idtr = hsave->save.idtr;
1784         svm->vmcb->save.rflags = hsave->save.rflags;
1785         svm_set_efer(&svm->vcpu, hsave->save.efer);
1786         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1787         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1788         if (npt_enabled) {
1789                 svm->vmcb->save.cr3 = hsave->save.cr3;
1790                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1791         } else {
1792                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1793         }
1794         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1795         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1796         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1797         svm->vmcb->save.dr7 = 0;
1798         svm->vmcb->save.cpl = 0;
1799         svm->vmcb->control.exit_int_info = 0;
1800
1801         nested_svm_unmap(page);
1802
1803         kvm_mmu_reset_context(&svm->vcpu);
1804         kvm_mmu_load(&svm->vcpu);
1805
1806         return 0;
1807 }
1808
1809 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1810 {
1811         u32 *nested_msrpm;
1812         struct page *page;
1813         int i;
1814
1815         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
1816         if (!nested_msrpm)
1817                 return false;
1818
1819         for (i = 0; i < PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1820                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1821
1822         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1823
1824         nested_svm_unmap(page);
1825
1826         return true;
1827 }
1828
1829 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1830 {
1831         struct vmcb *nested_vmcb;
1832         struct vmcb *hsave = svm->nested.hsave;
1833         struct vmcb *vmcb = svm->vmcb;
1834         struct page *page;
1835         u64 vmcb_gpa;
1836
1837         vmcb_gpa = svm->vmcb->save.rax;
1838
1839         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1840         if (!nested_vmcb)
1841                 return false;
1842
1843         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
1844                                nested_vmcb->save.rip,
1845                                nested_vmcb->control.int_ctl,
1846                                nested_vmcb->control.event_inj,
1847                                nested_vmcb->control.nested_ctl);
1848
1849         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
1850                                     nested_vmcb->control.intercept_cr_write,
1851                                     nested_vmcb->control.intercept_exceptions,
1852                                     nested_vmcb->control.intercept);
1853
1854         /* Clear internal status */
1855         kvm_clear_exception_queue(&svm->vcpu);
1856         kvm_clear_interrupt_queue(&svm->vcpu);
1857
1858         /*
1859          * Save the old vmcb, so we don't need to pick what we save, but can
1860          * restore everything when a VMEXIT occurs
1861          */
1862         hsave->save.es     = vmcb->save.es;
1863         hsave->save.cs     = vmcb->save.cs;
1864         hsave->save.ss     = vmcb->save.ss;
1865         hsave->save.ds     = vmcb->save.ds;
1866         hsave->save.gdtr   = vmcb->save.gdtr;
1867         hsave->save.idtr   = vmcb->save.idtr;
1868         hsave->save.efer   = svm->vcpu.arch.efer;
1869         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
1870         hsave->save.cr4    = svm->vcpu.arch.cr4;
1871         hsave->save.rflags = vmcb->save.rflags;
1872         hsave->save.rip    = svm->next_rip;
1873         hsave->save.rsp    = vmcb->save.rsp;
1874         hsave->save.rax    = vmcb->save.rax;
1875         if (npt_enabled)
1876                 hsave->save.cr3    = vmcb->save.cr3;
1877         else
1878                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1879
1880         copy_vmcb_control_area(hsave, vmcb);
1881
1882         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1883                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1884         else
1885                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1886
1887         /* Load the nested guest state */
1888         svm->vmcb->save.es = nested_vmcb->save.es;
1889         svm->vmcb->save.cs = nested_vmcb->save.cs;
1890         svm->vmcb->save.ss = nested_vmcb->save.ss;
1891         svm->vmcb->save.ds = nested_vmcb->save.ds;
1892         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1893         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1894         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1895         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1896         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1897         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1898         if (npt_enabled) {
1899                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1900                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1901         } else
1902                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1903
1904         /* Guest paging mode is active - reset mmu */
1905         kvm_mmu_reset_context(&svm->vcpu);
1906
1907         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1908         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1909         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1910         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1911
1912         /* In case we don't even reach vcpu_run, the fields are not updated */
1913         svm->vmcb->save.rax = nested_vmcb->save.rax;
1914         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1915         svm->vmcb->save.rip = nested_vmcb->save.rip;
1916         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1917         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1918         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1919
1920         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1921
1922         /* cache intercepts */
1923         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1924         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1925         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1926         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1927         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1928         svm->nested.intercept            = nested_vmcb->control.intercept;
1929
1930         force_new_asid(&svm->vcpu);
1931         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1932         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1933                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1934         else
1935                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1936
1937         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
1938                 /* We only want the cr8 intercept bits of the guest */
1939                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
1940                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1941         }
1942
1943         /*
1944          * We don't want a nested guest to be more powerful than the guest, so
1945          * all intercepts are ORed
1946          */
1947         svm->vmcb->control.intercept_cr_read |=
1948                 nested_vmcb->control.intercept_cr_read;
1949         svm->vmcb->control.intercept_cr_write |=
1950                 nested_vmcb->control.intercept_cr_write;
1951         svm->vmcb->control.intercept_dr_read |=
1952                 nested_vmcb->control.intercept_dr_read;
1953         svm->vmcb->control.intercept_dr_write |=
1954                 nested_vmcb->control.intercept_dr_write;
1955         svm->vmcb->control.intercept_exceptions |=
1956                 nested_vmcb->control.intercept_exceptions;
1957
1958         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1959
1960         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
1961         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1962         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1963         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1964         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1965         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1966
1967         nested_svm_unmap(page);
1968
1969         /* nested_vmcb is our indicator if nested SVM is activated */
1970         svm->nested.vmcb = vmcb_gpa;
1971
1972         enable_gif(svm);
1973
1974         return true;
1975 }
1976
1977 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1978 {
1979         to_vmcb->save.fs = from_vmcb->save.fs;
1980         to_vmcb->save.gs = from_vmcb->save.gs;
1981         to_vmcb->save.tr = from_vmcb->save.tr;
1982         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1983         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1984         to_vmcb->save.star = from_vmcb->save.star;
1985         to_vmcb->save.lstar = from_vmcb->save.lstar;
1986         to_vmcb->save.cstar = from_vmcb->save.cstar;
1987         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1988         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1989         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1990         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1991 }
1992
1993 static int vmload_interception(struct vcpu_svm *svm)
1994 {
1995         struct vmcb *nested_vmcb;
1996         struct page *page;
1997
1998         if (nested_svm_check_permissions(svm))
1999                 return 1;
2000
2001         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2002         skip_emulated_instruction(&svm->vcpu);
2003
2004         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2005         if (!nested_vmcb)
2006                 return 1;
2007
2008         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2009         nested_svm_unmap(page);
2010
2011         return 1;
2012 }
2013
2014 static int vmsave_interception(struct vcpu_svm *svm)
2015 {
2016         struct vmcb *nested_vmcb;
2017         struct page *page;
2018
2019         if (nested_svm_check_permissions(svm))
2020                 return 1;
2021
2022         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2023         skip_emulated_instruction(&svm->vcpu);
2024
2025         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2026         if (!nested_vmcb)
2027                 return 1;
2028
2029         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2030         nested_svm_unmap(page);
2031
2032         return 1;
2033 }
2034
2035 static int vmrun_interception(struct vcpu_svm *svm)
2036 {
2037         if (nested_svm_check_permissions(svm))
2038                 return 1;
2039
2040         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2041         skip_emulated_instruction(&svm->vcpu);
2042
2043         if (!nested_svm_vmrun(svm))
2044                 return 1;
2045
2046         if (!nested_svm_vmrun_msrpm(svm))
2047                 goto failed;
2048
2049         return 1;
2050
2051 failed:
2052
2053         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2054         svm->vmcb->control.exit_code_hi = 0;
2055         svm->vmcb->control.exit_info_1  = 0;
2056         svm->vmcb->control.exit_info_2  = 0;
2057
2058         nested_svm_vmexit(svm);
2059
2060         return 1;
2061 }
2062
2063 static int stgi_interception(struct vcpu_svm *svm)
2064 {
2065         if (nested_svm_check_permissions(svm))
2066                 return 1;
2067
2068         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2069         skip_emulated_instruction(&svm->vcpu);
2070
2071         enable_gif(svm);
2072
2073         return 1;
2074 }
2075
2076 static int clgi_interception(struct vcpu_svm *svm)
2077 {
2078         if (nested_svm_check_permissions(svm))
2079                 return 1;
2080
2081         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2082         skip_emulated_instruction(&svm->vcpu);
2083
2084         disable_gif(svm);
2085
2086         /* After a CLGI no interrupts should come */
2087         svm_clear_vintr(svm);
2088         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2089
2090         return 1;
2091 }
2092
2093 static int invlpga_interception(struct vcpu_svm *svm)
2094 {
2095         struct kvm_vcpu *vcpu = &svm->vcpu;
2096
2097         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2098                           vcpu->arch.regs[VCPU_REGS_RAX]);
2099
2100         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2101         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2102
2103         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2104         skip_emulated_instruction(&svm->vcpu);
2105         return 1;
2106 }
2107
2108 static int skinit_interception(struct vcpu_svm *svm)
2109 {
2110         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2111
2112         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2113         return 1;
2114 }
2115
2116 static int invalid_op_interception(struct vcpu_svm *svm)
2117 {
2118         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2119         return 1;
2120 }
2121
2122 static int task_switch_interception(struct vcpu_svm *svm)
2123 {
2124         u16 tss_selector;
2125         int reason;
2126         int int_type = svm->vmcb->control.exit_int_info &
2127                 SVM_EXITINTINFO_TYPE_MASK;
2128         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2129         uint32_t type =
2130                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2131         uint32_t idt_v =
2132                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2133
2134         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2135
2136         if (svm->vmcb->control.exit_info_2 &
2137             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2138                 reason = TASK_SWITCH_IRET;
2139         else if (svm->vmcb->control.exit_info_2 &
2140                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2141                 reason = TASK_SWITCH_JMP;
2142         else if (idt_v)
2143                 reason = TASK_SWITCH_GATE;
2144         else
2145                 reason = TASK_SWITCH_CALL;
2146
2147         if (reason == TASK_SWITCH_GATE) {
2148                 switch (type) {
2149                 case SVM_EXITINTINFO_TYPE_NMI:
2150                         svm->vcpu.arch.nmi_injected = false;
2151                         break;
2152                 case SVM_EXITINTINFO_TYPE_EXEPT:
2153                         kvm_clear_exception_queue(&svm->vcpu);
2154                         break;
2155                 case SVM_EXITINTINFO_TYPE_INTR:
2156                         kvm_clear_interrupt_queue(&svm->vcpu);
2157                         break;
2158                 default:
2159                         break;
2160                 }
2161         }
2162
2163         if (reason != TASK_SWITCH_GATE ||
2164             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2165             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2166              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2167                 skip_emulated_instruction(&svm->vcpu);
2168
2169         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2170 }
2171
2172 static int cpuid_interception(struct vcpu_svm *svm)
2173 {
2174         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2175         kvm_emulate_cpuid(&svm->vcpu);
2176         return 1;
2177 }
2178
2179 static int iret_interception(struct vcpu_svm *svm)
2180 {
2181         ++svm->vcpu.stat.nmi_window_exits;
2182         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2183         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2184         return 1;
2185 }
2186
2187 static int invlpg_interception(struct vcpu_svm *svm)
2188 {
2189         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2190                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2191         return 1;
2192 }
2193
2194 static int emulate_on_interception(struct vcpu_svm *svm)
2195 {
2196         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2197                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2198         return 1;
2199 }
2200
2201 static int cr8_write_interception(struct vcpu_svm *svm)
2202 {
2203         struct kvm_run *kvm_run = svm->vcpu.run;
2204
2205         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2206         /* instruction emulation calls kvm_set_cr8() */
2207         emulate_instruction(&svm->vcpu, 0, 0, 0);
2208         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2209                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2210                 return 1;
2211         }
2212         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2213                 return 1;
2214         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2215         return 0;
2216 }
2217
2218 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2219 {
2220         struct vcpu_svm *svm = to_svm(vcpu);
2221
2222         switch (ecx) {
2223         case MSR_IA32_TSC: {
2224                 u64 tsc_offset;
2225
2226                 if (is_nested(svm))
2227                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2228                 else
2229                         tsc_offset = svm->vmcb->control.tsc_offset;
2230
2231                 *data = tsc_offset + native_read_tsc();
2232                 break;
2233         }
2234         case MSR_K6_STAR:
2235                 *data = svm->vmcb->save.star;
2236                 break;
2237 #ifdef CONFIG_X86_64
2238         case MSR_LSTAR:
2239                 *data = svm->vmcb->save.lstar;
2240                 break;
2241         case MSR_CSTAR:
2242                 *data = svm->vmcb->save.cstar;
2243                 break;
2244         case MSR_KERNEL_GS_BASE:
2245                 *data = svm->vmcb->save.kernel_gs_base;
2246                 break;
2247         case MSR_SYSCALL_MASK:
2248                 *data = svm->vmcb->save.sfmask;
2249                 break;
2250 #endif
2251         case MSR_IA32_SYSENTER_CS:
2252                 *data = svm->vmcb->save.sysenter_cs;
2253                 break;
2254         case MSR_IA32_SYSENTER_EIP:
2255                 *data = svm->sysenter_eip;
2256                 break;
2257         case MSR_IA32_SYSENTER_ESP:
2258                 *data = svm->sysenter_esp;
2259                 break;
2260         /*
2261          * Nobody will change the following 5 values in the VMCB so we can
2262          * safely return them on rdmsr. They will always be 0 until LBRV is
2263          * implemented.
2264          */
2265         case MSR_IA32_DEBUGCTLMSR:
2266                 *data = svm->vmcb->save.dbgctl;
2267                 break;
2268         case MSR_IA32_LASTBRANCHFROMIP:
2269                 *data = svm->vmcb->save.br_from;
2270                 break;
2271         case MSR_IA32_LASTBRANCHTOIP:
2272                 *data = svm->vmcb->save.br_to;
2273                 break;
2274         case MSR_IA32_LASTINTFROMIP:
2275                 *data = svm->vmcb->save.last_excp_from;
2276                 break;
2277         case MSR_IA32_LASTINTTOIP:
2278                 *data = svm->vmcb->save.last_excp_to;
2279                 break;
2280         case MSR_VM_HSAVE_PA:
2281                 *data = svm->nested.hsave_msr;
2282                 break;
2283         case MSR_VM_CR:
2284                 *data = svm->nested.vm_cr_msr;
2285                 break;
2286         case MSR_IA32_UCODE_REV:
2287                 *data = 0x01000065;
2288                 break;
2289         default:
2290                 return kvm_get_msr_common(vcpu, ecx, data);
2291         }
2292         return 0;
2293 }
2294
2295 static int rdmsr_interception(struct vcpu_svm *svm)
2296 {
2297         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2298         u64 data;
2299
2300         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2301                 trace_kvm_msr_read_ex(ecx);
2302                 kvm_inject_gp(&svm->vcpu, 0);
2303         } else {
2304                 trace_kvm_msr_read(ecx, data);
2305
2306                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2307                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2308                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2309                 skip_emulated_instruction(&svm->vcpu);
2310         }
2311         return 1;
2312 }
2313
2314 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2315 {
2316         struct vcpu_svm *svm = to_svm(vcpu);
2317         int svm_dis, chg_mask;
2318
2319         if (data & ~SVM_VM_CR_VALID_MASK)
2320                 return 1;
2321
2322         chg_mask = SVM_VM_CR_VALID_MASK;
2323
2324         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2325                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2326
2327         svm->nested.vm_cr_msr &= ~chg_mask;
2328         svm->nested.vm_cr_msr |= (data & chg_mask);
2329
2330         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2331
2332         /* check for svm_disable while efer.svme is set */
2333         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2334                 return 1;
2335
2336         return 0;
2337 }
2338
2339 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2340 {
2341         struct vcpu_svm *svm = to_svm(vcpu);
2342
2343         switch (ecx) {
2344         case MSR_IA32_TSC: {
2345                 u64 tsc_offset = data - native_read_tsc();
2346                 u64 g_tsc_offset = 0;
2347
2348                 if (is_nested(svm)) {
2349                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2350                                        svm->nested.hsave->control.tsc_offset;
2351                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2352                 }
2353
2354                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2355
2356                 break;
2357         }
2358         case MSR_K6_STAR:
2359                 svm->vmcb->save.star = data;
2360                 break;
2361 #ifdef CONFIG_X86_64
2362         case MSR_LSTAR:
2363                 svm->vmcb->save.lstar = data;
2364                 break;
2365         case MSR_CSTAR:
2366                 svm->vmcb->save.cstar = data;
2367                 break;
2368         case MSR_KERNEL_GS_BASE:
2369                 svm->vmcb->save.kernel_gs_base = data;
2370                 break;
2371         case MSR_SYSCALL_MASK:
2372                 svm->vmcb->save.sfmask = data;
2373                 break;
2374 #endif
2375         case MSR_IA32_SYSENTER_CS:
2376                 svm->vmcb->save.sysenter_cs = data;
2377                 break;
2378         case MSR_IA32_SYSENTER_EIP:
2379                 svm->sysenter_eip = data;
2380                 svm->vmcb->save.sysenter_eip = data;
2381                 break;
2382         case MSR_IA32_SYSENTER_ESP:
2383                 svm->sysenter_esp = data;
2384                 svm->vmcb->save.sysenter_esp = data;
2385                 break;
2386         case MSR_IA32_DEBUGCTLMSR:
2387                 if (!svm_has(SVM_FEATURE_LBRV)) {
2388                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2389                                         __func__, data);
2390                         break;
2391                 }
2392                 if (data & DEBUGCTL_RESERVED_BITS)
2393                         return 1;
2394
2395                 svm->vmcb->save.dbgctl = data;
2396                 if (data & (1ULL<<0))
2397                         svm_enable_lbrv(svm);
2398                 else
2399                         svm_disable_lbrv(svm);
2400                 break;
2401         case MSR_VM_HSAVE_PA:
2402                 svm->nested.hsave_msr = data;
2403                 break;
2404         case MSR_VM_CR:
2405                 return svm_set_vm_cr(vcpu, data);
2406         case MSR_VM_IGNNE:
2407                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2408                 break;
2409         default:
2410                 return kvm_set_msr_common(vcpu, ecx, data);
2411         }
2412         return 0;
2413 }
2414
2415 static int wrmsr_interception(struct vcpu_svm *svm)
2416 {
2417         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2418         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2419                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2420
2421
2422         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2423         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2424                 trace_kvm_msr_write_ex(ecx, data);
2425                 kvm_inject_gp(&svm->vcpu, 0);
2426         } else {
2427                 trace_kvm_msr_write(ecx, data);
2428                 skip_emulated_instruction(&svm->vcpu);
2429         }
2430         return 1;
2431 }
2432
2433 static int msr_interception(struct vcpu_svm *svm)
2434 {
2435         if (svm->vmcb->control.exit_info_1)
2436                 return wrmsr_interception(svm);
2437         else
2438                 return rdmsr_interception(svm);
2439 }
2440
2441 static int interrupt_window_interception(struct vcpu_svm *svm)
2442 {
2443         struct kvm_run *kvm_run = svm->vcpu.run;
2444
2445         svm_clear_vintr(svm);
2446         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2447         /*
2448          * If the user space waits to inject interrupts, exit as soon as
2449          * possible
2450          */
2451         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2452             kvm_run->request_interrupt_window &&
2453             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2454                 ++svm->vcpu.stat.irq_window_exits;
2455                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2456                 return 0;
2457         }
2458
2459         return 1;
2460 }
2461
2462 static int pause_interception(struct vcpu_svm *svm)
2463 {
2464         kvm_vcpu_on_spin(&(svm->vcpu));
2465         return 1;
2466 }
2467
2468 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2469         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2470         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2471         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2472         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2473         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2474         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2475         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2476         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2477         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2478         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2479         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2480         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2481         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2482         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2483         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2484         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2485         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2486         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2487         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2488         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2489         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2490         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2491         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2492         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2493         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2494         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2495         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2496         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2497         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2498         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2499         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2500         [SVM_EXIT_INTR]                         = intr_interception,
2501         [SVM_EXIT_NMI]                          = nmi_interception,
2502         [SVM_EXIT_SMI]                          = nop_on_interception,
2503         [SVM_EXIT_INIT]                         = nop_on_interception,
2504         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2505         [SVM_EXIT_CPUID]                        = cpuid_interception,
2506         [SVM_EXIT_IRET]                         = iret_interception,
2507         [SVM_EXIT_INVD]                         = emulate_on_interception,
2508         [SVM_EXIT_PAUSE]                        = pause_interception,
2509         [SVM_EXIT_HLT]                          = halt_interception,
2510         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2511         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2512         [SVM_EXIT_IOIO]                         = io_interception,
2513         [SVM_EXIT_MSR]                          = msr_interception,
2514         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2515         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2516         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2517         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2518         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2519         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2520         [SVM_EXIT_STGI]                         = stgi_interception,
2521         [SVM_EXIT_CLGI]                         = clgi_interception,
2522         [SVM_EXIT_SKINIT]                       = skinit_interception,
2523         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2524         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2525         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2526         [SVM_EXIT_NPF]                          = pf_interception,
2527 };
2528
2529 static int handle_exit(struct kvm_vcpu *vcpu)
2530 {
2531         struct vcpu_svm *svm = to_svm(vcpu);
2532         struct kvm_run *kvm_run = vcpu->run;
2533         u32 exit_code = svm->vmcb->control.exit_code;
2534
2535         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2536
2537         if (unlikely(svm->nested.exit_required)) {
2538                 nested_svm_vmexit(svm);
2539                 svm->nested.exit_required = false;
2540
2541                 return 1;
2542         }
2543
2544         if (is_nested(svm)) {
2545                 int vmexit;
2546
2547                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2548                                         svm->vmcb->control.exit_info_1,
2549                                         svm->vmcb->control.exit_info_2,
2550                                         svm->vmcb->control.exit_int_info,
2551                                         svm->vmcb->control.exit_int_info_err);
2552
2553                 vmexit = nested_svm_exit_special(svm);
2554
2555                 if (vmexit == NESTED_EXIT_CONTINUE)
2556                         vmexit = nested_svm_exit_handled(svm);
2557
2558                 if (vmexit == NESTED_EXIT_DONE)
2559                         return 1;
2560         }
2561
2562         svm_complete_interrupts(svm);
2563
2564         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2565                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2566         if (npt_enabled)
2567                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2568
2569         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2570                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2571                 kvm_run->fail_entry.hardware_entry_failure_reason
2572                         = svm->vmcb->control.exit_code;
2573                 return 0;
2574         }
2575
2576         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2577             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2578             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2579                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2580                        "exit_code 0x%x\n",
2581                        __func__, svm->vmcb->control.exit_int_info,
2582                        exit_code);
2583
2584         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2585             || !svm_exit_handlers[exit_code]) {
2586                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2587                 kvm_run->hw.hardware_exit_reason = exit_code;
2588                 return 0;
2589         }
2590
2591         return svm_exit_handlers[exit_code](svm);
2592 }
2593
2594 static void reload_tss(struct kvm_vcpu *vcpu)
2595 {
2596         int cpu = raw_smp_processor_id();
2597
2598         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2599         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2600         load_TR_desc();
2601 }
2602
2603 static void pre_svm_run(struct vcpu_svm *svm)
2604 {
2605         int cpu = raw_smp_processor_id();
2606
2607         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2608
2609         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2610         /* FIXME: handle wraparound of asid_generation */
2611         if (svm->asid_generation != sd->asid_generation)
2612                 new_asid(svm, sd);
2613 }
2614
2615 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2616 {
2617         struct vcpu_svm *svm = to_svm(vcpu);
2618
2619         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2620         vcpu->arch.hflags |= HF_NMI_MASK;
2621         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2622         ++vcpu->stat.nmi_injections;
2623 }
2624
2625 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2626 {
2627         struct vmcb_control_area *control;
2628
2629         trace_kvm_inj_virq(irq);
2630
2631         ++svm->vcpu.stat.irq_injections;
2632         control = &svm->vmcb->control;
2633         control->int_vector = irq;
2634         control->int_ctl &= ~V_INTR_PRIO_MASK;
2635         control->int_ctl |= V_IRQ_MASK |
2636                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2637 }
2638
2639 static void svm_set_irq(struct kvm_vcpu *vcpu)
2640 {
2641         struct vcpu_svm *svm = to_svm(vcpu);
2642
2643         BUG_ON(!(gif_set(svm)));
2644
2645         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2646                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2647 }
2648
2649 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2650 {
2651         struct vcpu_svm *svm = to_svm(vcpu);
2652
2653         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2654                 return;
2655
2656         if (irr == -1)
2657                 return;
2658
2659         if (tpr >= irr)
2660                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2661 }
2662
2663 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2664 {
2665         struct vcpu_svm *svm = to_svm(vcpu);
2666         struct vmcb *vmcb = svm->vmcb;
2667         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2668                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2669 }
2670
2671 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2672 {
2673         struct vcpu_svm *svm = to_svm(vcpu);
2674
2675         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2676 }
2677
2678 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2679 {
2680         struct vcpu_svm *svm = to_svm(vcpu);
2681
2682         if (masked) {
2683                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2684                 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2685         } else {
2686                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2687                 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2688         }
2689 }
2690
2691 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2692 {
2693         struct vcpu_svm *svm = to_svm(vcpu);
2694         struct vmcb *vmcb = svm->vmcb;
2695         int ret;
2696
2697         if (!gif_set(svm) ||
2698              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2699                 return 0;
2700
2701         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2702
2703         if (is_nested(svm))
2704                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2705
2706         return ret;
2707 }
2708
2709 static void enable_irq_window(struct kvm_vcpu *vcpu)
2710 {
2711         struct vcpu_svm *svm = to_svm(vcpu);
2712
2713         /*
2714          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2715          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
2716          * get that intercept, this function will be called again though and
2717          * we'll get the vintr intercept.
2718          */
2719         if (gif_set(svm) && nested_svm_intr(svm)) {
2720                 svm_set_vintr(svm);
2721                 svm_inject_irq(svm, 0x0);
2722         }
2723 }
2724
2725 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2726 {
2727         struct vcpu_svm *svm = to_svm(vcpu);
2728
2729         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2730             == HF_NMI_MASK)
2731                 return; /* IRET will cause a vm exit */
2732
2733         /*
2734          * Something prevents NMI from been injected. Single step over possible
2735          * problem (IRET or exception injection or interrupt shadow)
2736          */
2737         if (gif_set(svm) && nested_svm_nmi(svm)) {
2738                 svm->nmi_singlestep = true;
2739                 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2740                 update_db_intercept(vcpu);
2741         }
2742 }
2743
2744 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2745 {
2746         return 0;
2747 }
2748
2749 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2750 {
2751         force_new_asid(vcpu);
2752 }
2753
2754 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2755 {
2756 }
2757
2758 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2759 {
2760         struct vcpu_svm *svm = to_svm(vcpu);
2761
2762         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2763                 return;
2764
2765         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2766                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2767                 kvm_set_cr8(vcpu, cr8);
2768         }
2769 }
2770
2771 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2772 {
2773         struct vcpu_svm *svm = to_svm(vcpu);
2774         u64 cr8;
2775
2776         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2777                 return;
2778
2779         cr8 = kvm_get_cr8(vcpu);
2780         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2781         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2782 }
2783
2784 static void svm_complete_interrupts(struct vcpu_svm *svm)
2785 {
2786         u8 vector;
2787         int type;
2788         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2789         unsigned int3_injected = svm->int3_injected;
2790
2791         svm->int3_injected = 0;
2792
2793         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2794                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2795
2796         svm->vcpu.arch.nmi_injected = false;
2797         kvm_clear_exception_queue(&svm->vcpu);
2798         kvm_clear_interrupt_queue(&svm->vcpu);
2799
2800         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2801                 return;
2802
2803         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2804         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2805
2806         switch (type) {
2807         case SVM_EXITINTINFO_TYPE_NMI:
2808                 svm->vcpu.arch.nmi_injected = true;
2809                 break;
2810         case SVM_EXITINTINFO_TYPE_EXEPT:
2811                 if (is_nested(svm))
2812                         break;
2813                 /*
2814                  * In case of software exceptions, do not reinject the vector,
2815                  * but re-execute the instruction instead. Rewind RIP first
2816                  * if we emulated INT3 before.
2817                  */
2818                 if (kvm_exception_is_soft(vector)) {
2819                         if (vector == BP_VECTOR && int3_injected &&
2820                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2821                                 kvm_rip_write(&svm->vcpu,
2822                                               kvm_rip_read(&svm->vcpu) -
2823                                               int3_injected);
2824                         break;
2825                 }
2826                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2827                         u32 err = svm->vmcb->control.exit_int_info_err;
2828                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2829
2830                 } else
2831                         kvm_queue_exception(&svm->vcpu, vector);
2832                 break;
2833         case SVM_EXITINTINFO_TYPE_INTR:
2834                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2835                 break;
2836         default:
2837                 break;
2838         }
2839 }
2840
2841 #ifdef CONFIG_X86_64
2842 #define R "r"
2843 #else
2844 #define R "e"
2845 #endif
2846
2847 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2848 {
2849         struct vcpu_svm *svm = to_svm(vcpu);
2850         u16 fs_selector;
2851         u16 gs_selector;
2852         u16 ldt_selector;
2853
2854         /*
2855          * A vmexit emulation is required before the vcpu can be executed
2856          * again.
2857          */
2858         if (unlikely(svm->nested.exit_required))
2859                 return;
2860
2861         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2862         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2863         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2864
2865         pre_svm_run(svm);
2866
2867         sync_lapic_to_cr8(vcpu);
2868
2869         save_host_msrs(vcpu);
2870         fs_selector = kvm_read_fs();
2871         gs_selector = kvm_read_gs();
2872         ldt_selector = kvm_read_ldt();
2873         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2874         /* required for live migration with NPT */
2875         if (npt_enabled)
2876                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2877
2878         clgi();
2879
2880         local_irq_enable();
2881
2882         asm volatile (
2883                 "push %%"R"bp; \n\t"
2884                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2885                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2886                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2887                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2888                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2889                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2890 #ifdef CONFIG_X86_64
2891                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2892                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2893                 "mov %c[r10](%[svm]), %%r10 \n\t"
2894                 "mov %c[r11](%[svm]), %%r11 \n\t"
2895                 "mov %c[r12](%[svm]), %%r12 \n\t"
2896                 "mov %c[r13](%[svm]), %%r13 \n\t"
2897                 "mov %c[r14](%[svm]), %%r14 \n\t"
2898                 "mov %c[r15](%[svm]), %%r15 \n\t"
2899 #endif
2900
2901                 /* Enter guest mode */
2902                 "push %%"R"ax \n\t"
2903                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2904                 __ex(SVM_VMLOAD) "\n\t"
2905                 __ex(SVM_VMRUN) "\n\t"
2906                 __ex(SVM_VMSAVE) "\n\t"
2907                 "pop %%"R"ax \n\t"
2908
2909                 /* Save guest registers, load host registers */
2910                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2911                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2912                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2913                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2914                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2915                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2916 #ifdef CONFIG_X86_64
2917                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2918                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2919                 "mov %%r10, %c[r10](%[svm]) \n\t"
2920                 "mov %%r11, %c[r11](%[svm]) \n\t"
2921                 "mov %%r12, %c[r12](%[svm]) \n\t"
2922                 "mov %%r13, %c[r13](%[svm]) \n\t"
2923                 "mov %%r14, %c[r14](%[svm]) \n\t"
2924                 "mov %%r15, %c[r15](%[svm]) \n\t"
2925 #endif
2926                 "pop %%"R"bp"
2927                 :
2928                 : [svm]"a"(svm),
2929                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2930                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2931                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2932                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2933                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2934                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2935                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2936 #ifdef CONFIG_X86_64
2937                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2938                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2939                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2940                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2941                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2942                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2943                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2944                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2945 #endif
2946                 : "cc", "memory"
2947                 , R"bx", R"cx", R"dx", R"si", R"di"
2948 #ifdef CONFIG_X86_64
2949                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2950 #endif
2951                 );
2952
2953         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2954         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2955         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2956         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2957
2958         kvm_load_fs(fs_selector);
2959         kvm_load_gs(gs_selector);
2960         kvm_load_ldt(ldt_selector);
2961         load_host_msrs(vcpu);
2962
2963         reload_tss(vcpu);
2964
2965         local_irq_disable();
2966
2967         stgi();
2968
2969         sync_cr8_to_lapic(vcpu);
2970
2971         svm->next_rip = 0;
2972
2973         if (npt_enabled) {
2974                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2975                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2976         }
2977 }
2978
2979 #undef R
2980
2981 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2982 {
2983         struct vcpu_svm *svm = to_svm(vcpu);
2984
2985         if (npt_enabled) {
2986                 svm->vmcb->control.nested_cr3 = root;
2987                 force_new_asid(vcpu);
2988                 return;
2989         }
2990
2991         svm->vmcb->save.cr3 = root;
2992         force_new_asid(vcpu);
2993 }
2994
2995 static int is_disabled(void)
2996 {
2997         u64 vm_cr;
2998
2999         rdmsrl(MSR_VM_CR, vm_cr);
3000         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3001                 return 1;
3002
3003         return 0;
3004 }
3005
3006 static void
3007 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3008 {
3009         /*
3010          * Patch in the VMMCALL instruction:
3011          */
3012         hypercall[0] = 0x0f;
3013         hypercall[1] = 0x01;
3014         hypercall[2] = 0xd9;
3015 }
3016
3017 static void svm_check_processor_compat(void *rtn)
3018 {
3019         *(int *)rtn = 0;
3020 }
3021
3022 static bool svm_cpu_has_accelerated_tpr(void)
3023 {
3024         return false;
3025 }
3026
3027 static int get_npt_level(void)
3028 {
3029 #ifdef CONFIG_X86_64
3030         return PT64_ROOT_LEVEL;
3031 #else
3032         return PT32E_ROOT_LEVEL;
3033 #endif
3034 }
3035
3036 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3037 {
3038         return 0;
3039 }
3040
3041 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3042 {
3043 }
3044
3045 static const struct trace_print_flags svm_exit_reasons_str[] = {
3046         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3047         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3048         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3049         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3050         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3051         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3052         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3053         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3054         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3055         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3056         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3057         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3058         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3059         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3060         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3061         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3062         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3063         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3064         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3065         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3066         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3067         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3068         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3069         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3070         { SVM_EXIT_INTR,                        "interrupt" },
3071         { SVM_EXIT_NMI,                         "nmi" },
3072         { SVM_EXIT_SMI,                         "smi" },
3073         { SVM_EXIT_INIT,                        "init" },
3074         { SVM_EXIT_VINTR,                       "vintr" },
3075         { SVM_EXIT_CPUID,                       "cpuid" },
3076         { SVM_EXIT_INVD,                        "invd" },
3077         { SVM_EXIT_HLT,                         "hlt" },
3078         { SVM_EXIT_INVLPG,                      "invlpg" },
3079         { SVM_EXIT_INVLPGA,                     "invlpga" },
3080         { SVM_EXIT_IOIO,                        "io" },
3081         { SVM_EXIT_MSR,                         "msr" },
3082         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3083         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3084         { SVM_EXIT_VMRUN,                       "vmrun" },
3085         { SVM_EXIT_VMMCALL,                     "hypercall" },
3086         { SVM_EXIT_VMLOAD,                      "vmload" },
3087         { SVM_EXIT_VMSAVE,                      "vmsave" },
3088         { SVM_EXIT_STGI,                        "stgi" },
3089         { SVM_EXIT_CLGI,                        "clgi" },
3090         { SVM_EXIT_SKINIT,                      "skinit" },
3091         { SVM_EXIT_WBINVD,                      "wbinvd" },
3092         { SVM_EXIT_MONITOR,                     "monitor" },
3093         { SVM_EXIT_MWAIT,                       "mwait" },
3094         { SVM_EXIT_NPF,                         "npf" },
3095         { -1, NULL }
3096 };
3097
3098 static int svm_get_lpage_level(void)
3099 {
3100         return PT_PDPE_LEVEL;
3101 }
3102
3103 static bool svm_rdtscp_supported(void)
3104 {
3105         return false;
3106 }
3107
3108 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3109 {
3110         struct vcpu_svm *svm = to_svm(vcpu);
3111
3112         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3113         if (is_nested(svm))
3114                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3115         update_cr0_intercept(svm);
3116 }
3117
3118 static struct kvm_x86_ops svm_x86_ops = {
3119         .cpu_has_kvm_support = has_svm,
3120         .disabled_by_bios = is_disabled,
3121         .hardware_setup = svm_hardware_setup,
3122         .hardware_unsetup = svm_hardware_unsetup,
3123         .check_processor_compatibility = svm_check_processor_compat,
3124         .hardware_enable = svm_hardware_enable,
3125         .hardware_disable = svm_hardware_disable,
3126         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3127
3128         .vcpu_create = svm_create_vcpu,
3129         .vcpu_free = svm_free_vcpu,
3130         .vcpu_reset = svm_vcpu_reset,
3131
3132         .prepare_guest_switch = svm_prepare_guest_switch,
3133         .vcpu_load = svm_vcpu_load,
3134         .vcpu_put = svm_vcpu_put,
3135
3136         .set_guest_debug = svm_guest_debug,
3137         .get_msr = svm_get_msr,
3138         .set_msr = svm_set_msr,
3139         .get_segment_base = svm_get_segment_base,
3140         .get_segment = svm_get_segment,
3141         .set_segment = svm_set_segment,
3142         .get_cpl = svm_get_cpl,
3143         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3144         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3145         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3146         .set_cr0 = svm_set_cr0,
3147         .set_cr3 = svm_set_cr3,
3148         .set_cr4 = svm_set_cr4,
3149         .set_efer = svm_set_efer,
3150         .get_idt = svm_get_idt,
3151         .set_idt = svm_set_idt,
3152         .get_gdt = svm_get_gdt,
3153         .set_gdt = svm_set_gdt,
3154         .get_dr = svm_get_dr,
3155         .set_dr = svm_set_dr,
3156         .cache_reg = svm_cache_reg,
3157         .get_rflags = svm_get_rflags,
3158         .set_rflags = svm_set_rflags,
3159         .fpu_activate = svm_fpu_activate,
3160         .fpu_deactivate = svm_fpu_deactivate,
3161
3162         .tlb_flush = svm_flush_tlb,
3163
3164         .run = svm_vcpu_run,
3165         .handle_exit = handle_exit,
3166         .skip_emulated_instruction = skip_emulated_instruction,
3167         .set_interrupt_shadow = svm_set_interrupt_shadow,
3168         .get_interrupt_shadow = svm_get_interrupt_shadow,
3169         .patch_hypercall = svm_patch_hypercall,
3170         .set_irq = svm_set_irq,
3171         .set_nmi = svm_inject_nmi,
3172         .queue_exception = svm_queue_exception,
3173         .interrupt_allowed = svm_interrupt_allowed,
3174         .nmi_allowed = svm_nmi_allowed,
3175         .get_nmi_mask = svm_get_nmi_mask,
3176         .set_nmi_mask = svm_set_nmi_mask,
3177         .enable_nmi_window = enable_nmi_window,
3178         .enable_irq_window = enable_irq_window,
3179         .update_cr8_intercept = update_cr8_intercept,
3180
3181         .set_tss_addr = svm_set_tss_addr,
3182         .get_tdp_level = get_npt_level,
3183         .get_mt_mask = svm_get_mt_mask,
3184
3185         .exit_reasons_str = svm_exit_reasons_str,
3186         .get_lpage_level = svm_get_lpage_level,
3187
3188         .cpuid_update = svm_cpuid_update,
3189
3190         .rdtscp_supported = svm_rdtscp_supported,
3191 };
3192
3193 static int __init svm_init(void)
3194 {
3195         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3196                               THIS_MODULE);
3197 }
3198
3199 static void __exit svm_exit(void)
3200 {
3201         kvm_exit();
3202 }
3203
3204 module_init(svm_init)
3205 module_exit(svm_exit)