arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  31
  32 MODULE_AUTHOR("Qumranet");
  33 MODULE_LICENSE("GPL");
  34
  35 #define IOPM_ALLOC_ORDER 2
  36 #define MSRPM_ALLOC_ORDER 1
  37
  38 #define DB_VECTOR 1
  39 #define UD_VECTOR 6
  40 #define GP_VECTOR 13
  41
  42 #define DR7_GD_MASK (1 << 13)
  43 #define DR6_BD_MASK (1 << 13)
  44
  45 #define SEG_TYPE_LDT 2
  46 #define SEG_TYPE_BUSY_TSS16 3
  47
  48 #define SVM_FEATURE_NPT  (1 << 0)
  49 #define SVM_FEATURE_LBRV (1 << 1)
  50 #define SVM_DEATURE_SVML (1 << 2)
  51
  52 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  53
  54 /* enable NPT for AMD64 and X86 with PAE */
  55 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  56 static bool npt_enabled = true;
  57 #else
  58 static bool npt_enabled = false;
  59 #endif
  60 static int npt = 1;
  61
  62 module_param(npt, int, S_IRUGO);
  63
  64 static void kvm_reput_irq(struct vcpu_svm *svm);
  65 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  66
  67 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  68 {
  69         return container_of(vcpu, struct vcpu_svm, vcpu);
  70 }
  71
  72 static unsigned long iopm_base;
  73
  74 struct kvm_ldttss_desc {
  75         u16 limit0;
  76         u16 base0;
  77         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  78         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  79         u32 base3;
  80         u32 zero1;
  81 } __attribute__((packed));
  82
  83 struct svm_cpu_data {
  84         int cpu;
  85
  86         u64 asid_generation;
  87         u32 max_asid;
  88         u32 next_asid;
  89         struct kvm_ldttss_desc *tss_desc;
  90
  91         struct page *save_area;
  92 };
  93
  94 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  95 static uint32_t svm_features;
  96
  97 struct svm_init_data {
  98         int cpu;
  99         int r;
 100 };
 101
 102 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 103
 104 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 105 #define MSRS_RANGE_SIZE 2048
 106 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 107
 108 #define MAX_INST_SIZE 15
 109
 110 static inline u32 svm_has(u32 feat)
 111 {
 112         return svm_features & feat;
 113 }
 114
 115 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 116 {
 117         int word_index = __ffs(vcpu->arch.irq_summary);
 118         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 119         int irq = word_index * BITS_PER_LONG + bit_index;
 120
 121         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 122         if (!vcpu->arch.irq_pending[word_index])
 123                 clear_bit(word_index, &vcpu->arch.irq_summary);
 124         return irq;
 125 }
 126
 127 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 128 {
 129         set_bit(irq, vcpu->arch.irq_pending);
 130         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 131 }
 132
 133 static inline void clgi(void)
 134 {
 135         asm volatile (__ex(SVM_CLGI));
 136 }
 137
 138 static inline void stgi(void)
 139 {
 140         asm volatile (__ex(SVM_STGI));
 141 }
 142
 143 static inline void invlpga(unsigned long addr, u32 asid)
 144 {
 145         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 146 }
 147
 148 static inline unsigned long kvm_read_cr2(void)
 149 {
 150         unsigned long cr2;
 151
 152         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 153         return cr2;
 154 }
 155
 156 static inline void kvm_write_cr2(unsigned long val)
 157 {
 158         asm volatile ("mov %0, %%cr2" :: "r" (val));
 159 }
 160
 161 static inline unsigned long read_dr6(void)
 162 {
 163         unsigned long dr6;
 164
 165         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 166         return dr6;
 167 }
 168
 169 static inline void write_dr6(unsigned long val)
 170 {
 171         asm volatile ("mov %0, %%dr6" :: "r" (val));
 172 }
 173
 174 static inline unsigned long read_dr7(void)
 175 {
 176         unsigned long dr7;
 177
 178         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 179         return dr7;
 180 }
 181
 182 static inline void write_dr7(unsigned long val)
 183 {
 184         asm volatile ("mov %0, %%dr7" :: "r" (val));
 185 }
 186
 187 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 188 {
 189         to_svm(vcpu)->asid_generation--;
 190 }
 191
 192 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 193 {
 194         force_new_asid(vcpu);
 195 }
 196
 197 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 198 {
 199         if (!npt_enabled && !(efer & EFER_LMA))
 200                 efer &= ~EFER_LME;
 201
 202         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 203         vcpu->arch.shadow_efer = efer;
 204 }
 205
 206 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 207                                 bool has_error_code, u32 error_code)
 208 {
 209         struct vcpu_svm *svm = to_svm(vcpu);
 210
 211         svm->vmcb->control.event_inj = nr
 212                 | SVM_EVTINJ_VALID
 213                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 214                 | SVM_EVTINJ_TYPE_EXEPT;
 215         svm->vmcb->control.event_inj_err = error_code;
 216 }
 217
 218 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 219 {
 220         struct vcpu_svm *svm = to_svm(vcpu);
 221
 222         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 223 }
 224
 225 static int is_external_interrupt(u32 info)
 226 {
 227         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 228         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 229 }
 230
 231 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 232 {
 233         struct vcpu_svm *svm = to_svm(vcpu);
 234
 235         if (!svm->next_rip) {
 236                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 237                 return;
 238         }
 239         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 240                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 241                        __func__,
 242                        svm->vmcb->save.rip,
 243                        svm->next_rip);
 244
 245         vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 246         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 247
 248         vcpu->arch.interrupt_window_open = 1;
 249 }
 250
 251 static int has_svm(void)
 252 {
 253         uint32_t eax, ebx, ecx, edx;
 254
 255         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 256                 printk(KERN_INFO "has_svm: not amd\n");
 257                 return 0;
 258         }
 259
 260         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 261         if (eax < SVM_CPUID_FUNC) {
 262                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 263                 return 0;
 264         }
 265
 266         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 267         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 268                 printk(KERN_DEBUG "has_svm: svm not available\n");
 269                 return 0;
 270         }
 271         return 1;
 272 }
 273
 274 static void svm_hardware_disable(void *garbage)
 275 {
 276         uint64_t efer;
 277
 278         wrmsrl(MSR_VM_HSAVE_PA, 0);
 279         rdmsrl(MSR_EFER, efer);
 280         wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 281 }
 282
 283 static void svm_hardware_enable(void *garbage)
 284 {
 285
 286         struct svm_cpu_data *svm_data;
 287         uint64_t efer;
 288         struct desc_ptr gdt_descr;
 289         struct desc_struct *gdt;
 290         int me = raw_smp_processor_id();
 291
 292         if (!has_svm()) {
 293                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 294                 return;
 295         }
 296         svm_data = per_cpu(svm_data, me);
 297
 298         if (!svm_data) {
 299                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 300                        me);
 301                 return;
 302         }
 303
 304         svm_data->asid_generation = 1;
 305         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 306         svm_data->next_asid = svm_data->max_asid + 1;
 307
 308         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 309         gdt = (struct desc_struct *)gdt_descr.address;
 310         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 311
 312         rdmsrl(MSR_EFER, efer);
 313         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 314
 315         wrmsrl(MSR_VM_HSAVE_PA,
 316                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 317 }
 318
 319 static void svm_cpu_uninit(int cpu)
 320 {
 321         struct svm_cpu_data *svm_data
 322                 = per_cpu(svm_data, raw_smp_processor_id());
 323
 324         if (!svm_data)
 325                 return;
 326
 327         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 328         __free_page(svm_data->save_area);
 329         kfree(svm_data);
 330 }
 331
 332 static int svm_cpu_init(int cpu)
 333 {
 334         struct svm_cpu_data *svm_data;
 335         int r;
 336
 337         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 338         if (!svm_data)
 339                 return -ENOMEM;
 340         svm_data->cpu = cpu;
 341         svm_data->save_area = alloc_page(GFP_KERNEL);
 342         r = -ENOMEM;
 343         if (!svm_data->save_area)
 344                 goto err_1;
 345
 346         per_cpu(svm_data, cpu) = svm_data;
 347
 348         return 0;
 349
 350 err_1:
 351         kfree(svm_data);
 352         return r;
 353
 354 }
 355
 356 static void set_msr_interception(u32 *msrpm, unsigned msr,
 357                                  int read, int write)
 358 {
 359         int i;
 360
 361         for (i = 0; i < NUM_MSR_MAPS; i++) {
 362                 if (msr >= msrpm_ranges[i] &&
 363                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 364                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 365                                           msrpm_ranges[i]) * 2;
 366
 367                         u32 *base = msrpm + (msr_offset / 32);
 368                         u32 msr_shift = msr_offset % 32;
 369                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 370                         *base = (*base & ~(0x3 << msr_shift)) |
 371                                 (mask << msr_shift);
 372                         return;
 373                 }
 374         }
 375         BUG();
 376 }
 377
 378 static void svm_vcpu_init_msrpm(u32 *msrpm)
 379 {
 380         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 381
 382 #ifdef CONFIG_X86_64
 383         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 384         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 385         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 386         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 387         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 388         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 389 #endif
 390         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 391         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 392         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 393         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 394 }
 395
 396 static void svm_enable_lbrv(struct vcpu_svm *svm)
 397 {
 398         u32 *msrpm = svm->msrpm;
 399
 400         svm->vmcb->control.lbr_ctl = 1;
 401         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 402         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 403         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 404         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 405 }
 406
 407 static void svm_disable_lbrv(struct vcpu_svm *svm)
 408 {
 409         u32 *msrpm = svm->msrpm;
 410
 411         svm->vmcb->control.lbr_ctl = 0;
 412         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 413         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 414         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 415         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 416 }
 417
 418 static __init int svm_hardware_setup(void)
 419 {
 420         int cpu;
 421         struct page *iopm_pages;
 422         void *iopm_va;
 423         int r;
 424
 425         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 426
 427         if (!iopm_pages)
 428                 return -ENOMEM;
 429
 430         iopm_va = page_address(iopm_pages);
 431         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 432         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 433         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 434
 435         if (boot_cpu_has(X86_FEATURE_NX))
 436                 kvm_enable_efer_bits(EFER_NX);
 437
 438         for_each_online_cpu(cpu) {
 439                 r = svm_cpu_init(cpu);
 440                 if (r)
 441                         goto err;
 442         }
 443
 444         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 445
 446         if (!svm_has(SVM_FEATURE_NPT))
 447                 npt_enabled = false;
 448
 449         if (npt_enabled && !npt) {
 450                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 451                 npt_enabled = false;
 452         }
 453
 454         if (npt_enabled) {
 455                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 456                 kvm_enable_tdp();
 457         } else
 458                 kvm_disable_tdp();
 459
 460         return 0;
 461
 462 err:
 463         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 464         iopm_base = 0;
 465         return r;
 466 }
 467
 468 static __exit void svm_hardware_unsetup(void)
 469 {
 470         int cpu;
 471
 472         for_each_online_cpu(cpu)
 473                 svm_cpu_uninit(cpu);
 474
 475         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 476         iopm_base = 0;
 477 }
 478
 479 static void init_seg(struct vmcb_seg *seg)
 480 {
 481         seg->selector = 0;
 482         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 483                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 484         seg->limit = 0xffff;
 485         seg->base = 0;
 486 }
 487
 488 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 489 {
 490         seg->selector = 0;
 491         seg->attrib = SVM_SELECTOR_P_MASK | type;
 492         seg->limit = 0xffff;
 493         seg->base = 0;
 494 }
 495
 496 static void init_vmcb(struct vcpu_svm *svm)
 497 {
 498         struct vmcb_control_area *control = &svm->vmcb->control;
 499         struct vmcb_save_area *save = &svm->vmcb->save;
 500
 501         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 502                                         INTERCEPT_CR3_MASK |
 503                                         INTERCEPT_CR4_MASK;
 504
 505         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 506                                         INTERCEPT_CR3_MASK |
 507                                         INTERCEPT_CR4_MASK |
 508                                         INTERCEPT_CR8_MASK;
 509
 510         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 511                                         INTERCEPT_DR1_MASK |
 512                                         INTERCEPT_DR2_MASK |
 513                                         INTERCEPT_DR3_MASK;
 514
 515         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 516                                         INTERCEPT_DR1_MASK |
 517                                         INTERCEPT_DR2_MASK |
 518                                         INTERCEPT_DR3_MASK |
 519                                         INTERCEPT_DR5_MASK |
 520                                         INTERCEPT_DR7_MASK;
 521
 522         control->intercept_exceptions = (1 << PF_VECTOR) |
 523                                         (1 << UD_VECTOR) |
 524                                         (1 << MC_VECTOR);
 525
 526
 527         control->intercept =    (1ULL << INTERCEPT_INTR) |
 528                                 (1ULL << INTERCEPT_NMI) |
 529                                 (1ULL << INTERCEPT_SMI) |
 530                                 (1ULL << INTERCEPT_CPUID) |
 531                                 (1ULL << INTERCEPT_INVD) |
 532                                 (1ULL << INTERCEPT_HLT) |
 533                                 (1ULL << INTERCEPT_INVLPGA) |
 534                                 (1ULL << INTERCEPT_IOIO_PROT) |
 535                                 (1ULL << INTERCEPT_MSR_PROT) |
 536                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 537                                 (1ULL << INTERCEPT_SHUTDOWN) |
 538                                 (1ULL << INTERCEPT_VMRUN) |
 539                                 (1ULL << INTERCEPT_VMMCALL) |
 540                                 (1ULL << INTERCEPT_VMLOAD) |
 541                                 (1ULL << INTERCEPT_VMSAVE) |
 542                                 (1ULL << INTERCEPT_STGI) |
 543                                 (1ULL << INTERCEPT_CLGI) |
 544                                 (1ULL << INTERCEPT_SKINIT) |
 545                                 (1ULL << INTERCEPT_WBINVD) |
 546                                 (1ULL << INTERCEPT_MONITOR) |
 547                                 (1ULL << INTERCEPT_MWAIT);
 548
 549         control->iopm_base_pa = iopm_base;
 550         control->msrpm_base_pa = __pa(svm->msrpm);
 551         control->tsc_offset = 0;
 552         control->int_ctl = V_INTR_MASKING_MASK;
 553
 554         init_seg(&save->es);
 555         init_seg(&save->ss);
 556         init_seg(&save->ds);
 557         init_seg(&save->fs);
 558         init_seg(&save->gs);
 559
 560         save->cs.selector = 0xf000;
 561         /* Executable/Readable Code Segment */
 562         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 563                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 564         save->cs.limit = 0xffff;
 565         /*
 566          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 567          * be consistent with it.
 568          *
 569          * Replace when we have real mode working for vmx.
 570          */
 571         save->cs.base = 0xf0000;
 572
 573         save->gdtr.limit = 0xffff;
 574         save->idtr.limit = 0xffff;
 575
 576         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 577         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 578
 579         save->efer = MSR_EFER_SVME_MASK;
 580         save->dr6 = 0xffff0ff0;
 581         save->dr7 = 0x400;
 582         save->rflags = 2;
 583         save->rip = 0x0000fff0;
 584
 585         /*
 586          * cr0 val on cpu init should be 0x60000010, we enable cpu
 587          * cache by default. the orderly way is to enable cache in bios.
 588          */
 589         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 590         save->cr4 = X86_CR4_PAE;
 591         /* rdx = ?? */
 592
 593         if (npt_enabled) {
 594                 /* Setup VMCB for Nested Paging */
 595                 control->nested_ctl = 1;
 596                 control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH);
 597                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 598                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 599                                                 INTERCEPT_CR3_MASK);
 600                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 601                                                  INTERCEPT_CR3_MASK);
 602                 save->g_pat = 0x0007040600070406ULL;
 603                 /* enable caching because the QEMU Bios doesn't enable it */
 604                 save->cr0 = X86_CR0_ET;
 605                 save->cr3 = 0;
 606                 save->cr4 = 0;
 607         }
 608         force_new_asid(&svm->vcpu);
 609 }
 610
 611 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 612 {
 613         struct vcpu_svm *svm = to_svm(vcpu);
 614
 615         init_vmcb(svm);
 616
 617         if (vcpu->vcpu_id != 0) {
 618                 svm->vmcb->save.rip = 0;
 619                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 620                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 621         }
 622
 623         return 0;
 624 }
 625
 626 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 627 {
 628         struct vcpu_svm *svm;
 629         struct page *page;
 630         struct page *msrpm_pages;
 631         int err;
 632
 633         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 634         if (!svm) {
 635                 err = -ENOMEM;
 636                 goto out;
 637         }
 638
 639         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 640         if (err)
 641                 goto free_svm;
 642
 643         page = alloc_page(GFP_KERNEL);
 644         if (!page) {
 645                 err = -ENOMEM;
 646                 goto uninit;
 647         }
 648
 649         err = -ENOMEM;
 650         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 651         if (!msrpm_pages)
 652                 goto uninit;
 653         svm->msrpm = page_address(msrpm_pages);
 654         svm_vcpu_init_msrpm(svm->msrpm);
 655
 656         svm->vmcb = page_address(page);
 657         clear_page(svm->vmcb);
 658         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 659         svm->asid_generation = 0;
 660         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 661         init_vmcb(svm);
 662
 663         fx_init(&svm->vcpu);
 664         svm->vcpu.fpu_active = 1;
 665         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 666         if (svm->vcpu.vcpu_id == 0)
 667                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 668
 669         return &svm->vcpu;
 670
 671 uninit:
 672         kvm_vcpu_uninit(&svm->vcpu);
 673 free_svm:
 674         kmem_cache_free(kvm_vcpu_cache, svm);
 675 out:
 676         return ERR_PTR(err);
 677 }
 678
 679 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 680 {
 681         struct vcpu_svm *svm = to_svm(vcpu);
 682
 683         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 684         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 685         kvm_vcpu_uninit(vcpu);
 686         kmem_cache_free(kvm_vcpu_cache, svm);
 687 }
 688
 689 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 690 {
 691         struct vcpu_svm *svm = to_svm(vcpu);
 692         int i;
 693
 694         if (unlikely(cpu != vcpu->cpu)) {
 695                 u64 tsc_this, delta;
 696
 697                 /*
 698                  * Make sure that the guest sees a monotonically
 699                  * increasing TSC.
 700                  */
 701                 rdtscll(tsc_this);
 702                 delta = vcpu->arch.host_tsc - tsc_this;
 703                 svm->vmcb->control.tsc_offset += delta;
 704                 vcpu->cpu = cpu;
 705                 kvm_migrate_timers(vcpu);
 706         }
 707
 708         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 709                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 710 }
 711
 712 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 713 {
 714         struct vcpu_svm *svm = to_svm(vcpu);
 715         int i;
 716
 717         ++vcpu->stat.host_state_reload;
 718         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 719                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 720
 721         rdtscll(vcpu->arch.host_tsc);
 722 }
 723
 724 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 725 {
 726         struct vcpu_svm *svm = to_svm(vcpu);
 727
 728         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 729         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 730         vcpu->arch.rip = svm->vmcb->save.rip;
 731 }
 732
 733 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 734 {
 735         struct vcpu_svm *svm = to_svm(vcpu);
 736         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 737         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 738         svm->vmcb->save.rip = vcpu->arch.rip;
 739 }
 740
 741 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 742 {
 743         return to_svm(vcpu)->vmcb->save.rflags;
 744 }
 745
 746 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 747 {
 748         to_svm(vcpu)->vmcb->save.rflags = rflags;
 749 }
 750
 751 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 752 {
 753         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 754
 755         switch (seg) {
 756         case VCPU_SREG_CS: return &save->cs;
 757         case VCPU_SREG_DS: return &save->ds;
 758         case VCPU_SREG_ES: return &save->es;
 759         case VCPU_SREG_FS: return &save->fs;
 760         case VCPU_SREG_GS: return &save->gs;
 761         case VCPU_SREG_SS: return &save->ss;
 762         case VCPU_SREG_TR: return &save->tr;
 763         case VCPU_SREG_LDTR: return &save->ldtr;
 764         }
 765         BUG();
 766         return NULL;
 767 }
 768
 769 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 770 {
 771         struct vmcb_seg *s = svm_seg(vcpu, seg);
 772
 773         return s->base;
 774 }
 775
 776 static void svm_get_segment(struct kvm_vcpu *vcpu,
 777                             struct kvm_segment *var, int seg)
 778 {
 779         struct vmcb_seg *s = svm_seg(vcpu, seg);
 780
 781         var->base = s->base;
 782         var->limit = s->limit;
 783         var->selector = s->selector;
 784         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 785         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 786         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 787         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 788         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 789         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 790         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 791         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 792         var->unusable = !var->present;
 793 }
 794
 795 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 796 {
 797         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 798
 799         return save->cpl;
 800 }
 801
 802 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 803 {
 804         struct vcpu_svm *svm = to_svm(vcpu);
 805
 806         dt->limit = svm->vmcb->save.idtr.limit;
 807         dt->base = svm->vmcb->save.idtr.base;
 808 }
 809
 810 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 811 {
 812         struct vcpu_svm *svm = to_svm(vcpu);
 813
 814         svm->vmcb->save.idtr.limit = dt->limit;
 815         svm->vmcb->save.idtr.base = dt->base ;
 816 }
 817
 818 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 819 {
 820         struct vcpu_svm *svm = to_svm(vcpu);
 821
 822         dt->limit = svm->vmcb->save.gdtr.limit;
 823         dt->base = svm->vmcb->save.gdtr.base;
 824 }
 825
 826 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 827 {
 828         struct vcpu_svm *svm = to_svm(vcpu);
 829
 830         svm->vmcb->save.gdtr.limit = dt->limit;
 831         svm->vmcb->save.gdtr.base = dt->base ;
 832 }
 833
 834 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 835 {
 836 }
 837
 838 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 839 {
 840         struct vcpu_svm *svm = to_svm(vcpu);
 841
 842 #ifdef CONFIG_X86_64
 843         if (vcpu->arch.shadow_efer & EFER_LME) {
 844                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 845                         vcpu->arch.shadow_efer |= EFER_LMA;
 846                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 847                 }
 848
 849                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 850                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 851                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 852                 }
 853         }
 854 #endif
 855         if (npt_enabled)
 856                 goto set;
 857
 858         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 859                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 860                 vcpu->fpu_active = 1;
 861         }
 862
 863         vcpu->arch.cr0 = cr0;
 864         cr0 |= X86_CR0_PG | X86_CR0_WP;
 865         if (!vcpu->fpu_active) {
 866                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 867                 cr0 |= X86_CR0_TS;
 868         }
 869 set:
 870         /*
 871          * re-enable caching here because the QEMU bios
 872          * does not do it - this results in some delay at
 873          * reboot
 874          */
 875         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 876         svm->vmcb->save.cr0 = cr0;
 877 }
 878
 879 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 880 {
 881         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 882         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 883
 884         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 885                 force_new_asid(vcpu);
 886
 887         vcpu->arch.cr4 = cr4;
 888         if (!npt_enabled)
 889                 cr4 |= X86_CR4_PAE;
 890         cr4 |= host_cr4_mce;
 891         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 892 }
 893
 894 static void svm_set_segment(struct kvm_vcpu *vcpu,
 895                             struct kvm_segment *var, int seg)
 896 {
 897         struct vcpu_svm *svm = to_svm(vcpu);
 898         struct vmcb_seg *s = svm_seg(vcpu, seg);
 899
 900         s->base = var->base;
 901         s->limit = var->limit;
 902         s->selector = var->selector;
 903         if (var->unusable)
 904                 s->attrib = 0;
 905         else {
 906                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 907                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 908                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 909                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 910                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 911                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 912                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 913                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 914         }
 915         if (seg == VCPU_SREG_CS)
 916                 svm->vmcb->save.cpl
 917                         = (svm->vmcb->save.cs.attrib
 918                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 919
 920 }
 921
 922 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 923 {
 924         return -EOPNOTSUPP;
 925 }
 926
 927 static int svm_get_irq(struct kvm_vcpu *vcpu)
 928 {
 929         struct vcpu_svm *svm = to_svm(vcpu);
 930         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 931
 932         if (is_external_interrupt(exit_int_info))
 933                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 934         return -1;
 935 }
 936
 937 static void load_host_msrs(struct kvm_vcpu *vcpu)
 938 {
 939 #ifdef CONFIG_X86_64
 940         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 941 #endif
 942 }
 943
 944 static void save_host_msrs(struct kvm_vcpu *vcpu)
 945 {
 946 #ifdef CONFIG_X86_64
 947         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 948 #endif
 949 }
 950
 951 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 952 {
 953         if (svm_data->next_asid > svm_data->max_asid) {
 954                 ++svm_data->asid_generation;
 955                 svm_data->next_asid = 1;
 956                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 957         }
 958
 959         svm->vcpu.cpu = svm_data->cpu;
 960         svm->asid_generation = svm_data->asid_generation;
 961         svm->vmcb->control.asid = svm_data->next_asid++;
 962 }
 963
 964 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 965 {
 966         unsigned long val = to_svm(vcpu)->db_regs[dr];
 967         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 968         return val;
 969 }
 970
 971 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 972                        int *exception)
 973 {
 974         struct vcpu_svm *svm = to_svm(vcpu);
 975
 976         *exception = 0;
 977
 978         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 979                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 980                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 981                 *exception = DB_VECTOR;
 982                 return;
 983         }
 984
 985         switch (dr) {
 986         case 0 ... 3:
 987                 svm->db_regs[dr] = value;
 988                 return;
 989         case 4 ... 5:
 990                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 991                         *exception = UD_VECTOR;
 992                         return;
 993                 }
 994         case 7: {
 995                 if (value & ~((1ULL << 32) - 1)) {
 996                         *exception = GP_VECTOR;
 997                         return;
 998                 }
 999                 svm->vmcb->save.dr7 = value;
1000                 return;
1001         }
1002         default:
1003                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1004                        __func__, dr);
1005                 *exception = UD_VECTOR;
1006                 return;
1007         }
1008 }
1009
1010 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1011 {
1012         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1013         struct kvm *kvm = svm->vcpu.kvm;
1014         u64 fault_address;
1015         u32 error_code;
1016         bool event_injection = false;
1017
1018         if (!irqchip_in_kernel(kvm) &&
1019             is_external_interrupt(exit_int_info)) {
1020                 event_injection = true;
1021                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1022         }
1023
1024         fault_address  = svm->vmcb->control.exit_info_2;
1025         error_code = svm->vmcb->control.exit_info_1;
1026
1027         if (!npt_enabled)
1028                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1029                             (u32)fault_address, (u32)(fault_address >> 32),
1030                             handler);
1031         else
1032                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1033                             (u32)fault_address, (u32)(fault_address >> 32),
1034                             handler);
1035         /*
1036          * FIXME: Tis shouldn't be necessary here, but there is a flush
1037          * missing in the MMU code. Until we find this bug, flush the
1038          * complete TLB here on an NPF
1039          */
1040         if (npt_enabled)
1041                 svm_flush_tlb(&svm->vcpu);
1042
1043         if (event_injection)
1044                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1045         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1046 }
1047
1048 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1049 {
1050         int er;
1051
1052         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1053         if (er != EMULATE_DONE)
1054                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1055         return 1;
1056 }
1057
1058 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1059 {
1060         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1061         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1062                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1063         svm->vcpu.fpu_active = 1;
1064
1065         return 1;
1066 }
1067
1068 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1069 {
1070         /*
1071          * On an #MC intercept the MCE handler is not called automatically in
1072          * the host. So do it by hand here.
1073          */
1074         asm volatile (
1075                 "int $0x12\n");
1076         /* not sure if we ever come back to this point */
1077
1078         return 1;
1079 }
1080
1081 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1082 {
1083         /*
1084          * VMCB is undefined after a SHUTDOWN intercept
1085          * so reinitialize it.
1086          */
1087         clear_page(svm->vmcb);
1088         init_vmcb(svm);
1089
1090         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1091         return 0;
1092 }
1093
1094 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1095 {
1096         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1097         int size, down, in, string, rep;
1098         unsigned port;
1099
1100         ++svm->vcpu.stat.io_exits;
1101
1102         svm->next_rip = svm->vmcb->control.exit_info_2;
1103
1104         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1105
1106         if (string) {
1107                 if (emulate_instruction(&svm->vcpu,
1108                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1109                         return 0;
1110                 return 1;
1111         }
1112
1113         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1114         port = io_info >> 16;
1115         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1116         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1117         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1118
1119         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1120 }
1121
1122 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1123 {
1124         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1125         return 1;
1126 }
1127
1128 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1129 {
1130         ++svm->vcpu.stat.irq_exits;
1131         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1132         return 1;
1133 }
1134
1135 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1136 {
1137         return 1;
1138 }
1139
1140 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1141 {
1142         svm->next_rip = svm->vmcb->save.rip + 1;
1143         skip_emulated_instruction(&svm->vcpu);
1144         return kvm_emulate_halt(&svm->vcpu);
1145 }
1146
1147 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1148 {
1149         svm->next_rip = svm->vmcb->save.rip + 3;
1150         skip_emulated_instruction(&svm->vcpu);
1151         kvm_emulate_hypercall(&svm->vcpu);
1152         return 1;
1153 }
1154
1155 static int invalid_op_interception(struct vcpu_svm *svm,
1156                                    struct kvm_run *kvm_run)
1157 {
1158         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1159         return 1;
1160 }
1161
1162 static int task_switch_interception(struct vcpu_svm *svm,
1163                                     struct kvm_run *kvm_run)
1164 {
1165         u16 tss_selector;
1166
1167         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1168         if (svm->vmcb->control.exit_info_2 &
1169             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1170                 return kvm_task_switch(&svm->vcpu, tss_selector,
1171                                        TASK_SWITCH_IRET);
1172         if (svm->vmcb->control.exit_info_2 &
1173             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1174                 return kvm_task_switch(&svm->vcpu, tss_selector,
1175                                        TASK_SWITCH_JMP);
1176         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1177 }
1178
1179 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1180 {
1181         svm->next_rip = svm->vmcb->save.rip + 2;
1182         kvm_emulate_cpuid(&svm->vcpu);
1183         return 1;
1184 }
1185
1186 static int emulate_on_interception(struct vcpu_svm *svm,
1187                                    struct kvm_run *kvm_run)
1188 {
1189         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1190                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1191         return 1;
1192 }
1193
1194 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1195 {
1196         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1197         if (irqchip_in_kernel(svm->vcpu.kvm))
1198                 return 1;
1199         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1200         return 0;
1201 }
1202
1203 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1204 {
1205         struct vcpu_svm *svm = to_svm(vcpu);
1206
1207         switch (ecx) {
1208         case MSR_IA32_TIME_STAMP_COUNTER: {
1209                 u64 tsc;
1210
1211                 rdtscll(tsc);
1212                 *data = svm->vmcb->control.tsc_offset + tsc;
1213                 break;
1214         }
1215         case MSR_K6_STAR:
1216                 *data = svm->vmcb->save.star;
1217                 break;
1218 #ifdef CONFIG_X86_64
1219         case MSR_LSTAR:
1220                 *data = svm->vmcb->save.lstar;
1221                 break;
1222         case MSR_CSTAR:
1223                 *data = svm->vmcb->save.cstar;
1224                 break;
1225         case MSR_KERNEL_GS_BASE:
1226                 *data = svm->vmcb->save.kernel_gs_base;
1227                 break;
1228         case MSR_SYSCALL_MASK:
1229                 *data = svm->vmcb->save.sfmask;
1230                 break;
1231 #endif
1232         case MSR_IA32_SYSENTER_CS:
1233                 *data = svm->vmcb->save.sysenter_cs;
1234                 break;
1235         case MSR_IA32_SYSENTER_EIP:
1236                 *data = svm->vmcb->save.sysenter_eip;
1237                 break;
1238         case MSR_IA32_SYSENTER_ESP:
1239                 *data = svm->vmcb->save.sysenter_esp;
1240                 break;
1241         /* Nobody will change the following 5 values in the VMCB so
1242            we can safely return them on rdmsr. They will always be 0
1243            until LBRV is implemented. */
1244         case MSR_IA32_DEBUGCTLMSR:
1245                 *data = svm->vmcb->save.dbgctl;
1246                 break;
1247         case MSR_IA32_LASTBRANCHFROMIP:
1248                 *data = svm->vmcb->save.br_from;
1249                 break;
1250         case MSR_IA32_LASTBRANCHTOIP:
1251                 *data = svm->vmcb->save.br_to;
1252                 break;
1253         case MSR_IA32_LASTINTFROMIP:
1254                 *data = svm->vmcb->save.last_excp_from;
1255                 break;
1256         case MSR_IA32_LASTINTTOIP:
1257                 *data = svm->vmcb->save.last_excp_to;
1258                 break;
1259         default:
1260                 return kvm_get_msr_common(vcpu, ecx, data);
1261         }
1262         return 0;
1263 }
1264
1265 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1266 {
1267         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1268         u64 data;
1269
1270         if (svm_get_msr(&svm->vcpu, ecx, &data))
1271                 kvm_inject_gp(&svm->vcpu, 0);
1272         else {
1273                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1274                             (u32)(data >> 32), handler);
1275
1276                 svm->vmcb->save.rax = data & 0xffffffff;
1277                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1278                 svm->next_rip = svm->vmcb->save.rip + 2;
1279                 skip_emulated_instruction(&svm->vcpu);
1280         }
1281         return 1;
1282 }
1283
1284 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1285 {
1286         struct vcpu_svm *svm = to_svm(vcpu);
1287
1288         switch (ecx) {
1289         case MSR_IA32_TIME_STAMP_COUNTER: {
1290                 u64 tsc;
1291
1292                 rdtscll(tsc);
1293                 svm->vmcb->control.tsc_offset = data - tsc;
1294                 break;
1295         }
1296         case MSR_K6_STAR:
1297                 svm->vmcb->save.star = data;
1298                 break;
1299 #ifdef CONFIG_X86_64
1300         case MSR_LSTAR:
1301                 svm->vmcb->save.lstar = data;
1302                 break;
1303         case MSR_CSTAR:
1304                 svm->vmcb->save.cstar = data;
1305                 break;
1306         case MSR_KERNEL_GS_BASE:
1307                 svm->vmcb->save.kernel_gs_base = data;
1308                 break;
1309         case MSR_SYSCALL_MASK:
1310                 svm->vmcb->save.sfmask = data;
1311                 break;
1312 #endif
1313         case MSR_IA32_SYSENTER_CS:
1314                 svm->vmcb->save.sysenter_cs = data;
1315                 break;
1316         case MSR_IA32_SYSENTER_EIP:
1317                 svm->vmcb->save.sysenter_eip = data;
1318                 break;
1319         case MSR_IA32_SYSENTER_ESP:
1320                 svm->vmcb->save.sysenter_esp = data;
1321                 break;
1322         case MSR_IA32_DEBUGCTLMSR:
1323                 if (!svm_has(SVM_FEATURE_LBRV)) {
1324                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1325                                         __func__, data);
1326                         break;
1327                 }
1328                 if (data & DEBUGCTL_RESERVED_BITS)
1329                         return 1;
1330
1331                 svm->vmcb->save.dbgctl = data;
1332                 if (data & (1ULL<<0))
1333                         svm_enable_lbrv(svm);
1334                 else
1335                         svm_disable_lbrv(svm);
1336                 break;
1337         case MSR_K7_EVNTSEL0:
1338         case MSR_K7_EVNTSEL1:
1339         case MSR_K7_EVNTSEL2:
1340         case MSR_K7_EVNTSEL3:
1341         case MSR_K7_PERFCTR0:
1342         case MSR_K7_PERFCTR1:
1343         case MSR_K7_PERFCTR2:
1344         case MSR_K7_PERFCTR3:
1345                 /*
1346                  * Just discard all writes to the performance counters; this
1347                  * should keep both older linux and windows 64-bit guests
1348                  * happy
1349                  */
1350                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1351
1352                 break;
1353         default:
1354                 return kvm_set_msr_common(vcpu, ecx, data);
1355         }
1356         return 0;
1357 }
1358
1359 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1360 {
1361         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1362         u64 data = (svm->vmcb->save.rax & -1u)
1363                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1364
1365         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1366                     handler);
1367
1368         svm->next_rip = svm->vmcb->save.rip + 2;
1369         if (svm_set_msr(&svm->vcpu, ecx, data))
1370                 kvm_inject_gp(&svm->vcpu, 0);
1371         else
1372                 skip_emulated_instruction(&svm->vcpu);
1373         return 1;
1374 }
1375
1376 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1377 {
1378         if (svm->vmcb->control.exit_info_1)
1379                 return wrmsr_interception(svm, kvm_run);
1380         else
1381                 return rdmsr_interception(svm, kvm_run);
1382 }
1383
1384 static int interrupt_window_interception(struct vcpu_svm *svm,
1385                                    struct kvm_run *kvm_run)
1386 {
1387         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1388
1389         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1390         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1391         /*
1392          * If the user space waits to inject interrupts, exit as soon as
1393          * possible
1394          */
1395         if (kvm_run->request_interrupt_window &&
1396             !svm->vcpu.arch.irq_summary) {
1397                 ++svm->vcpu.stat.irq_window_exits;
1398                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1399                 return 0;
1400         }
1401
1402         return 1;
1403 }
1404
1405 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1406                                       struct kvm_run *kvm_run) = {
1407         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1408         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1409         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1410         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1411         /* for now: */
1412         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1413         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1414         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1415         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1416         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1417         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1418         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1419         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1420         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1421         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1422         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1423         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1424         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1425         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1426         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1427         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1428         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1429         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1430         [SVM_EXIT_INTR]                         = intr_interception,
1431         [SVM_EXIT_NMI]                          = nmi_interception,
1432         [SVM_EXIT_SMI]                          = nop_on_interception,
1433         [SVM_EXIT_INIT]                         = nop_on_interception,
1434         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1435         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1436         [SVM_EXIT_CPUID]                        = cpuid_interception,
1437         [SVM_EXIT_INVD]                         = emulate_on_interception,
1438         [SVM_EXIT_HLT]                          = halt_interception,
1439         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1440         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1441         [SVM_EXIT_IOIO]                         = io_interception,
1442         [SVM_EXIT_MSR]                          = msr_interception,
1443         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1444         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1445         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1446         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1447         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1448         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1449         [SVM_EXIT_STGI]                         = invalid_op_interception,
1450         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1451         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1452         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1453         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1454         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1455         [SVM_EXIT_NPF]                          = pf_interception,
1456 };
1457
1458 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1459 {
1460         struct vcpu_svm *svm = to_svm(vcpu);
1461         u32 exit_code = svm->vmcb->control.exit_code;
1462
1463         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1464                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1465
1466         if (npt_enabled) {
1467                 int mmu_reload = 0;
1468                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1469                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1470                         mmu_reload = 1;
1471                 }
1472                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1473                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1474                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1475                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1476                                 kvm_inject_gp(vcpu, 0);
1477                                 return 1;
1478                         }
1479                 }
1480                 if (mmu_reload) {
1481                         kvm_mmu_reset_context(vcpu);
1482                         kvm_mmu_load(vcpu);
1483                 }
1484         }
1485
1486         kvm_reput_irq(svm);
1487
1488         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1489                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1490                 kvm_run->fail_entry.hardware_entry_failure_reason
1491                         = svm->vmcb->control.exit_code;
1492                 return 0;
1493         }
1494
1495         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1496             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1497             exit_code != SVM_EXIT_NPF)
1498                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1499                        "exit_code 0x%x\n",
1500                        __func__, svm->vmcb->control.exit_int_info,
1501                        exit_code);
1502
1503         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1504             || !svm_exit_handlers[exit_code]) {
1505                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1506                 kvm_run->hw.hardware_exit_reason = exit_code;
1507                 return 0;
1508         }
1509
1510         return svm_exit_handlers[exit_code](svm, kvm_run);
1511 }
1512
1513 static void reload_tss(struct kvm_vcpu *vcpu)
1514 {
1515         int cpu = raw_smp_processor_id();
1516
1517         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1518         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1519         load_TR_desc();
1520 }
1521
1522 static void pre_svm_run(struct vcpu_svm *svm)
1523 {
1524         int cpu = raw_smp_processor_id();
1525
1526         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1527
1528         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1529         if (svm->vcpu.cpu != cpu ||
1530             svm->asid_generation != svm_data->asid_generation)
1531                 new_asid(svm, svm_data);
1532 }
1533
1534
1535 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1536 {
1537         struct vmcb_control_area *control;
1538
1539         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1540
1541         control = &svm->vmcb->control;
1542         control->int_vector = irq;
1543         control->int_ctl &= ~V_INTR_PRIO_MASK;
1544         control->int_ctl |= V_IRQ_MASK |
1545                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1546 }
1547
1548 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1549 {
1550         struct vcpu_svm *svm = to_svm(vcpu);
1551
1552         svm_inject_irq(svm, irq);
1553 }
1554
1555 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1556 {
1557         struct vcpu_svm *svm = to_svm(vcpu);
1558         struct vmcb *vmcb = svm->vmcb;
1559         int max_irr, tpr;
1560
1561         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1562                 return;
1563
1564         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1565
1566         max_irr = kvm_lapic_find_highest_irr(vcpu);
1567         if (max_irr == -1)
1568                 return;
1569
1570         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1571
1572         if (tpr >= (max_irr & 0xf0))
1573                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1574 }
1575
1576 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1577 {
1578         struct vcpu_svm *svm = to_svm(vcpu);
1579         struct vmcb *vmcb = svm->vmcb;
1580         int intr_vector = -1;
1581
1582         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1583             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1584                 intr_vector = vmcb->control.exit_int_info &
1585                               SVM_EVTINJ_VEC_MASK;
1586                 vmcb->control.exit_int_info = 0;
1587                 svm_inject_irq(svm, intr_vector);
1588                 goto out;
1589         }
1590
1591         if (vmcb->control.int_ctl & V_IRQ_MASK)
1592                 goto out;
1593
1594         if (!kvm_cpu_has_interrupt(vcpu))
1595                 goto out;
1596
1597         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1598             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1599             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1600                 /* unable to deliver irq, set pending irq */
1601                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1602                 svm_inject_irq(svm, 0x0);
1603                 goto out;
1604         }
1605         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1606         intr_vector = kvm_cpu_get_interrupt(vcpu);
1607         svm_inject_irq(svm, intr_vector);
1608         kvm_timer_intr_post(vcpu, intr_vector);
1609 out:
1610         update_cr8_intercept(vcpu);
1611 }
1612
1613 static void kvm_reput_irq(struct vcpu_svm *svm)
1614 {
1615         struct vmcb_control_area *control = &svm->vmcb->control;
1616
1617         if ((control->int_ctl & V_IRQ_MASK)
1618             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1619                 control->int_ctl &= ~V_IRQ_MASK;
1620                 push_irq(&svm->vcpu, control->int_vector);
1621         }
1622
1623         svm->vcpu.arch.interrupt_window_open =
1624                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1625 }
1626
1627 static void svm_do_inject_vector(struct vcpu_svm *svm)
1628 {
1629         struct kvm_vcpu *vcpu = &svm->vcpu;
1630         int word_index = __ffs(vcpu->arch.irq_summary);
1631         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1632         int irq = word_index * BITS_PER_LONG + bit_index;
1633
1634         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1635         if (!vcpu->arch.irq_pending[word_index])
1636                 clear_bit(word_index, &vcpu->arch.irq_summary);
1637         svm_inject_irq(svm, irq);
1638 }
1639
1640 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1641                                        struct kvm_run *kvm_run)
1642 {
1643         struct vcpu_svm *svm = to_svm(vcpu);
1644         struct vmcb_control_area *control = &svm->vmcb->control;
1645
1646         svm->vcpu.arch.interrupt_window_open =
1647                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1648                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1649
1650         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1651                 /*
1652                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1653                  */
1654                 svm_do_inject_vector(svm);
1655
1656         /*
1657          * Interrupts blocked.  Wait for unblock.
1658          */
1659         if (!svm->vcpu.arch.interrupt_window_open &&
1660             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1661                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1662          else
1663                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1664 }
1665
1666 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1667 {
1668         return 0;
1669 }
1670
1671 static void save_db_regs(unsigned long *db_regs)
1672 {
1673         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1674         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1675         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1676         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1677 }
1678
1679 static void load_db_regs(unsigned long *db_regs)
1680 {
1681         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1682         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1683         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1684         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1685 }
1686
1687 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1688 {
1689         force_new_asid(vcpu);
1690 }
1691
1692 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1693 {
1694 }
1695
1696 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1697 {
1698         struct vcpu_svm *svm = to_svm(vcpu);
1699
1700         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1701                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1702                 kvm_lapic_set_tpr(vcpu, cr8);
1703         }
1704 }
1705
1706 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1707 {
1708         struct vcpu_svm *svm = to_svm(vcpu);
1709         u64 cr8;
1710
1711         if (!irqchip_in_kernel(vcpu->kvm))
1712                 return;
1713
1714         cr8 = kvm_get_cr8(vcpu);
1715         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1716         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1717 }
1718
1719 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1720 {
1721         struct vcpu_svm *svm = to_svm(vcpu);
1722         u16 fs_selector;
1723         u16 gs_selector;
1724         u16 ldt_selector;
1725
1726         pre_svm_run(svm);
1727
1728         sync_lapic_to_cr8(vcpu);
1729
1730         save_host_msrs(vcpu);
1731         fs_selector = kvm_read_fs();
1732         gs_selector = kvm_read_gs();
1733         ldt_selector = kvm_read_ldt();
1734         svm->host_cr2 = kvm_read_cr2();
1735         svm->host_dr6 = read_dr6();
1736         svm->host_dr7 = read_dr7();
1737         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1738         /* required for live migration with NPT */
1739         if (npt_enabled)
1740                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1741
1742         if (svm->vmcb->save.dr7 & 0xff) {
1743                 write_dr7(0);
1744                 save_db_regs(svm->host_db_regs);
1745                 load_db_regs(svm->db_regs);
1746         }
1747
1748         clgi();
1749
1750         local_irq_enable();
1751
1752         asm volatile (
1753 #ifdef CONFIG_X86_64
1754                 "push %%rbp; \n\t"
1755 #else
1756                 "push %%ebp; \n\t"
1757 #endif
1758
1759 #ifdef CONFIG_X86_64
1760                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1761                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1762                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1763                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1764                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1765                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1766                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1767                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1768                 "mov %c[r10](%[svm]), %%r10 \n\t"
1769                 "mov %c[r11](%[svm]), %%r11 \n\t"
1770                 "mov %c[r12](%[svm]), %%r12 \n\t"
1771                 "mov %c[r13](%[svm]), %%r13 \n\t"
1772                 "mov %c[r14](%[svm]), %%r14 \n\t"
1773                 "mov %c[r15](%[svm]), %%r15 \n\t"
1774 #else
1775                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1776                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1777                 "mov %c[rdx](%[svm]), %%edx \n\t"
1778                 "mov %c[rsi](%[svm]), %%esi \n\t"
1779                 "mov %c[rdi](%[svm]), %%edi \n\t"
1780                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1781 #endif
1782
1783 #ifdef CONFIG_X86_64
1784                 /* Enter guest mode */
1785                 "push %%rax \n\t"
1786                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1787                 __ex(SVM_VMLOAD) "\n\t"
1788                 __ex(SVM_VMRUN) "\n\t"
1789                 __ex(SVM_VMSAVE) "\n\t"
1790                 "pop %%rax \n\t"
1791 #else
1792                 /* Enter guest mode */
1793                 "push %%eax \n\t"
1794                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1795                 __ex(SVM_VMLOAD) "\n\t"
1796                 __ex(SVM_VMRUN) "\n\t"
1797                 __ex(SVM_VMSAVE) "\n\t"
1798                 "pop %%eax \n\t"
1799 #endif
1800
1801                 /* Save guest registers, load host registers */
1802 #ifdef CONFIG_X86_64
1803                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1804                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1805                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1806                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1807                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1808                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1809                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1810                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1811                 "mov %%r10, %c[r10](%[svm]) \n\t"
1812                 "mov %%r11, %c[r11](%[svm]) \n\t"
1813                 "mov %%r12, %c[r12](%[svm]) \n\t"
1814                 "mov %%r13, %c[r13](%[svm]) \n\t"
1815                 "mov %%r14, %c[r14](%[svm]) \n\t"
1816                 "mov %%r15, %c[r15](%[svm]) \n\t"
1817
1818                 "pop  %%rbp; \n\t"
1819 #else
1820                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1821                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1822                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1823                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1824                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1825                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1826
1827                 "pop  %%ebp; \n\t"
1828 #endif
1829                 :
1830                 : [svm]"a"(svm),
1831                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1832                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1833                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1834                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1835                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1836                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1837                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1838 #ifdef CONFIG_X86_64
1839                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1840                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1841                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1842                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1843                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1844                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1845                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1846                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1847 #endif
1848                 : "cc", "memory"
1849 #ifdef CONFIG_X86_64
1850                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1851                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1852 #else
1853                 , "ebx", "ecx", "edx" , "esi", "edi"
1854 #endif
1855                 );
1856
1857         if ((svm->vmcb->save.dr7 & 0xff))
1858                 load_db_regs(svm->host_db_regs);
1859
1860         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1861
1862         write_dr6(svm->host_dr6);
1863         write_dr7(svm->host_dr7);
1864         kvm_write_cr2(svm->host_cr2);
1865
1866         kvm_load_fs(fs_selector);
1867         kvm_load_gs(gs_selector);
1868         kvm_load_ldt(ldt_selector);
1869         load_host_msrs(vcpu);
1870
1871         reload_tss(vcpu);
1872
1873         local_irq_disable();
1874
1875         stgi();
1876
1877         sync_cr8_to_lapic(vcpu);
1878
1879         svm->next_rip = 0;
1880 }
1881
1882 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1883 {
1884         struct vcpu_svm *svm = to_svm(vcpu);
1885
1886         if (npt_enabled) {
1887                 svm->vmcb->control.nested_cr3 = root;
1888                 force_new_asid(vcpu);
1889                 return;
1890         }
1891
1892         svm->vmcb->save.cr3 = root;
1893         force_new_asid(vcpu);
1894
1895         if (vcpu->fpu_active) {
1896                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1897                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1898                 vcpu->fpu_active = 0;
1899         }
1900 }
1901
1902 static int is_disabled(void)
1903 {
1904         u64 vm_cr;
1905
1906         rdmsrl(MSR_VM_CR, vm_cr);
1907         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1908                 return 1;
1909
1910         return 0;
1911 }
1912
1913 static void
1914 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1915 {
1916         /*
1917          * Patch in the VMMCALL instruction:
1918          */
1919         hypercall[0] = 0x0f;
1920         hypercall[1] = 0x01;
1921         hypercall[2] = 0xd9;
1922 }
1923
1924 static void svm_check_processor_compat(void *rtn)
1925 {
1926         *(int *)rtn = 0;
1927 }
1928
1929 static bool svm_cpu_has_accelerated_tpr(void)
1930 {
1931         return false;
1932 }
1933
1934 static int get_npt_level(void)
1935 {
1936 #ifdef CONFIG_X86_64
1937         return PT64_ROOT_LEVEL;
1938 #else
1939         return PT32E_ROOT_LEVEL;
1940 #endif
1941 }
1942
1943 static struct kvm_x86_ops svm_x86_ops = {
1944         .cpu_has_kvm_support = has_svm,
1945         .disabled_by_bios = is_disabled,
1946         .hardware_setup = svm_hardware_setup,
1947         .hardware_unsetup = svm_hardware_unsetup,
1948         .check_processor_compatibility = svm_check_processor_compat,
1949         .hardware_enable = svm_hardware_enable,
1950         .hardware_disable = svm_hardware_disable,
1951         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1952
1953         .vcpu_create = svm_create_vcpu,
1954         .vcpu_free = svm_free_vcpu,
1955         .vcpu_reset = svm_vcpu_reset,
1956
1957         .prepare_guest_switch = svm_prepare_guest_switch,
1958         .vcpu_load = svm_vcpu_load,
1959         .vcpu_put = svm_vcpu_put,
1960
1961         .set_guest_debug = svm_guest_debug,
1962         .get_msr = svm_get_msr,
1963         .set_msr = svm_set_msr,
1964         .get_segment_base = svm_get_segment_base,
1965         .get_segment = svm_get_segment,
1966         .set_segment = svm_set_segment,
1967         .get_cpl = svm_get_cpl,
1968         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1969         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1970         .set_cr0 = svm_set_cr0,
1971         .set_cr3 = svm_set_cr3,
1972         .set_cr4 = svm_set_cr4,
1973         .set_efer = svm_set_efer,
1974         .get_idt = svm_get_idt,
1975         .set_idt = svm_set_idt,
1976         .get_gdt = svm_get_gdt,
1977         .set_gdt = svm_set_gdt,
1978         .get_dr = svm_get_dr,
1979         .set_dr = svm_set_dr,
1980         .cache_regs = svm_cache_regs,
1981         .decache_regs = svm_decache_regs,
1982         .get_rflags = svm_get_rflags,
1983         .set_rflags = svm_set_rflags,
1984
1985         .tlb_flush = svm_flush_tlb,
1986
1987         .run = svm_vcpu_run,
1988         .handle_exit = handle_exit,
1989         .skip_emulated_instruction = skip_emulated_instruction,
1990         .patch_hypercall = svm_patch_hypercall,
1991         .get_irq = svm_get_irq,
1992         .set_irq = svm_set_irq,
1993         .queue_exception = svm_queue_exception,
1994         .exception_injected = svm_exception_injected,
1995         .inject_pending_irq = svm_intr_assist,
1996         .inject_pending_vectors = do_interrupt_requests,
1997
1998         .set_tss_addr = svm_set_tss_addr,
1999         .get_tdp_level = get_npt_level,
2000 };
2001
2002 static int __init svm_init(void)
2003 {
2004         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2005                               THIS_MODULE);
2006 }
2007
2008 static void __exit svm_exit(void)
2009 {
2010         kvm_exit();
2011 }
2012
2013 module_init(svm_init)
2014 module_exit(svm_exit)