arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33
  34 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  35
  36 MODULE_AUTHOR("Qumranet");
  37 MODULE_LICENSE("GPL");
  38
  39 #define IOPM_ALLOC_ORDER 2
  40 #define MSRPM_ALLOC_ORDER 1
  41
  42 #define SEG_TYPE_LDT 2
  43 #define SEG_TYPE_BUSY_TSS16 3
  44
  45 #define SVM_FEATURE_NPT  (1 << 0)
  46 #define SVM_FEATURE_LBRV (1 << 1)
  47 #define SVM_FEATURE_SVML (1 << 2)
  48
  49 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  50
  51 /* Turn on to get debugging output*/
  52 /* #define NESTED_DEBUG */
  53
  54 #ifdef NESTED_DEBUG
  55 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  56 #else
  57 #define nsvm_printk(fmt, args...) do {} while(0)
  58 #endif
  59
  60 /* enable NPT for AMD64 and X86 with PAE */
  61 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  62 static bool npt_enabled = true;
  63 #else
  64 static bool npt_enabled = false;
  65 #endif
  66 static int npt = 1;
  67
  68 module_param(npt, int, S_IRUGO);
  69
  70 static int nested = 0;
  71 module_param(nested, int, S_IRUGO);
  72
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
  76 static int nested_svm_vmexit(struct vcpu_svm *svm);
  77 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
  78                              void *arg2, void *opaque);
  79 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  80                                       bool has_error_code, u32 error_code);
  81
  82 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  83 {
  84         return container_of(vcpu, struct vcpu_svm, vcpu);
  85 }
  86
  87 static inline bool is_nested(struct vcpu_svm *svm)
  88 {
  89         return svm->nested_vmcb;
  90 }
  91
  92 static unsigned long iopm_base;
  93
  94 struct kvm_ldttss_desc {
  95         u16 limit0;
  96         u16 base0;
  97         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  98         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  99         u32 base3;
 100         u32 zero1;
 101 } __attribute__((packed));
 102
 103 struct svm_cpu_data {
 104         int cpu;
 105
 106         u64 asid_generation;
 107         u32 max_asid;
 108         u32 next_asid;
 109         struct kvm_ldttss_desc *tss_desc;
 110
 111         struct page *save_area;
 112 };
 113
 114 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 115 static uint32_t svm_features;
 116
 117 struct svm_init_data {
 118         int cpu;
 119         int r;
 120 };
 121
 122 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 123
 124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 125 #define MSRS_RANGE_SIZE 2048
 126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 127
 128 #define MAX_INST_SIZE 15
 129
 130 static inline u32 svm_has(u32 feat)
 131 {
 132         return svm_features & feat;
 133 }
 134
 135 static inline void clgi(void)
 136 {
 137         asm volatile (__ex(SVM_CLGI));
 138 }
 139
 140 static inline void stgi(void)
 141 {
 142         asm volatile (__ex(SVM_STGI));
 143 }
 144
 145 static inline void invlpga(unsigned long addr, u32 asid)
 146 {
 147         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 148 }
 149
 150 static inline unsigned long kvm_read_cr2(void)
 151 {
 152         unsigned long cr2;
 153
 154         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 155         return cr2;
 156 }
 157
 158 static inline void kvm_write_cr2(unsigned long val)
 159 {
 160         asm volatile ("mov %0, %%cr2" :: "r" (val));
 161 }
 162
 163 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 164 {
 165         to_svm(vcpu)->asid_generation--;
 166 }
 167
 168 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 169 {
 170         force_new_asid(vcpu);
 171 }
 172
 173 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 174 {
 175         if (!npt_enabled && !(efer & EFER_LMA))
 176                 efer &= ~EFER_LME;
 177
 178         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 179         vcpu->arch.shadow_efer = efer;
 180 }
 181
 182 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 183                                 bool has_error_code, u32 error_code)
 184 {
 185         struct vcpu_svm *svm = to_svm(vcpu);
 186
 187         /* If we are within a nested VM we'd better #VMEXIT and let the
 188            guest handle the exception */
 189         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 190                 return;
 191
 192         svm->vmcb->control.event_inj = nr
 193                 | SVM_EVTINJ_VALID
 194                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 195                 | SVM_EVTINJ_TYPE_EXEPT;
 196         svm->vmcb->control.event_inj_err = error_code;
 197 }
 198
 199 static int is_external_interrupt(u32 info)
 200 {
 201         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 202         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 203 }
 204
 205 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 206 {
 207         struct vcpu_svm *svm = to_svm(vcpu);
 208         u32 ret = 0;
 209
 210         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 211                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 212         return ret & mask;
 213 }
 214
 215 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 216 {
 217         struct vcpu_svm *svm = to_svm(vcpu);
 218
 219         if (mask == 0)
 220                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 221         else
 222                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 223
 224 }
 225
 226 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 227 {
 228         struct vcpu_svm *svm = to_svm(vcpu);
 229
 230         if (!svm->next_rip) {
 231                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 232                 return;
 233         }
 234         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 235                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 236                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 237
 238         kvm_rip_write(vcpu, svm->next_rip);
 239         svm_set_interrupt_shadow(vcpu, 0);
 240 }
 241
 242 static int has_svm(void)
 243 {
 244         const char *msg;
 245
 246         if (!cpu_has_svm(&msg)) {
 247                 printk(KERN_INFO "has_svm: %s\n", msg);
 248                 return 0;
 249         }
 250
 251         return 1;
 252 }
 253
 254 static void svm_hardware_disable(void *garbage)
 255 {
 256         cpu_svm_disable();
 257 }
 258
 259 static void svm_hardware_enable(void *garbage)
 260 {
 261
 262         struct svm_cpu_data *svm_data;
 263         uint64_t efer;
 264         struct desc_ptr gdt_descr;
 265         struct desc_struct *gdt;
 266         int me = raw_smp_processor_id();
 267
 268         if (!has_svm()) {
 269                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 270                 return;
 271         }
 272         svm_data = per_cpu(svm_data, me);
 273
 274         if (!svm_data) {
 275                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 276                        me);
 277                 return;
 278         }
 279
 280         svm_data->asid_generation = 1;
 281         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 282         svm_data->next_asid = svm_data->max_asid + 1;
 283
 284         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 285         gdt = (struct desc_struct *)gdt_descr.address;
 286         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 287
 288         rdmsrl(MSR_EFER, efer);
 289         wrmsrl(MSR_EFER, efer | EFER_SVME);
 290
 291         wrmsrl(MSR_VM_HSAVE_PA,
 292                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 293 }
 294
 295 static void svm_cpu_uninit(int cpu)
 296 {
 297         struct svm_cpu_data *svm_data
 298                 = per_cpu(svm_data, raw_smp_processor_id());
 299
 300         if (!svm_data)
 301                 return;
 302
 303         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 304         __free_page(svm_data->save_area);
 305         kfree(svm_data);
 306 }
 307
 308 static int svm_cpu_init(int cpu)
 309 {
 310         struct svm_cpu_data *svm_data;
 311         int r;
 312
 313         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 314         if (!svm_data)
 315                 return -ENOMEM;
 316         svm_data->cpu = cpu;
 317         svm_data->save_area = alloc_page(GFP_KERNEL);
 318         r = -ENOMEM;
 319         if (!svm_data->save_area)
 320                 goto err_1;
 321
 322         per_cpu(svm_data, cpu) = svm_data;
 323
 324         return 0;
 325
 326 err_1:
 327         kfree(svm_data);
 328         return r;
 329
 330 }
 331
 332 static void set_msr_interception(u32 *msrpm, unsigned msr,
 333                                  int read, int write)
 334 {
 335         int i;
 336
 337         for (i = 0; i < NUM_MSR_MAPS; i++) {
 338                 if (msr >= msrpm_ranges[i] &&
 339                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 340                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 341                                           msrpm_ranges[i]) * 2;
 342
 343                         u32 *base = msrpm + (msr_offset / 32);
 344                         u32 msr_shift = msr_offset % 32;
 345                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 346                         *base = (*base & ~(0x3 << msr_shift)) |
 347                                 (mask << msr_shift);
 348                         return;
 349                 }
 350         }
 351         BUG();
 352 }
 353
 354 static void svm_vcpu_init_msrpm(u32 *msrpm)
 355 {
 356         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 357
 358 #ifdef CONFIG_X86_64
 359         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 360         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 361         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 362         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 363         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 364         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 365 #endif
 366         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 367         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 368         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 369         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 370 }
 371
 372 static void svm_enable_lbrv(struct vcpu_svm *svm)
 373 {
 374         u32 *msrpm = svm->msrpm;
 375
 376         svm->vmcb->control.lbr_ctl = 1;
 377         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 378         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 379         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 380         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 381 }
 382
 383 static void svm_disable_lbrv(struct vcpu_svm *svm)
 384 {
 385         u32 *msrpm = svm->msrpm;
 386
 387         svm->vmcb->control.lbr_ctl = 0;
 388         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 389         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 390         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 391         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 392 }
 393
 394 static __init int svm_hardware_setup(void)
 395 {
 396         int cpu;
 397         struct page *iopm_pages;
 398         void *iopm_va;
 399         int r;
 400
 401         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 402
 403         if (!iopm_pages)
 404                 return -ENOMEM;
 405
 406         iopm_va = page_address(iopm_pages);
 407         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 408         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 409
 410         if (boot_cpu_has(X86_FEATURE_NX))
 411                 kvm_enable_efer_bits(EFER_NX);
 412
 413         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 414                 kvm_enable_efer_bits(EFER_FFXSR);
 415
 416         if (nested) {
 417                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 418                 kvm_enable_efer_bits(EFER_SVME);
 419         }
 420
 421         for_each_online_cpu(cpu) {
 422                 r = svm_cpu_init(cpu);
 423                 if (r)
 424                         goto err;
 425         }
 426
 427         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 428
 429         if (!svm_has(SVM_FEATURE_NPT))
 430                 npt_enabled = false;
 431
 432         if (npt_enabled && !npt) {
 433                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 434                 npt_enabled = false;
 435         }
 436
 437         if (npt_enabled) {
 438                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 439                 kvm_enable_tdp();
 440         } else
 441                 kvm_disable_tdp();
 442
 443         return 0;
 444
 445 err:
 446         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 447         iopm_base = 0;
 448         return r;
 449 }
 450
 451 static __exit void svm_hardware_unsetup(void)
 452 {
 453         int cpu;
 454
 455         for_each_online_cpu(cpu)
 456                 svm_cpu_uninit(cpu);
 457
 458         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 459         iopm_base = 0;
 460 }
 461
 462 static void init_seg(struct vmcb_seg *seg)
 463 {
 464         seg->selector = 0;
 465         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 466                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 467         seg->limit = 0xffff;
 468         seg->base = 0;
 469 }
 470
 471 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 472 {
 473         seg->selector = 0;
 474         seg->attrib = SVM_SELECTOR_P_MASK | type;
 475         seg->limit = 0xffff;
 476         seg->base = 0;
 477 }
 478
 479 static void init_vmcb(struct vcpu_svm *svm)
 480 {
 481         struct vmcb_control_area *control = &svm->vmcb->control;
 482         struct vmcb_save_area *save = &svm->vmcb->save;
 483
 484         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 485                                         INTERCEPT_CR3_MASK |
 486                                         INTERCEPT_CR4_MASK;
 487
 488         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 489                                         INTERCEPT_CR3_MASK |
 490                                         INTERCEPT_CR4_MASK |
 491                                         INTERCEPT_CR8_MASK;
 492
 493         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 494                                         INTERCEPT_DR1_MASK |
 495                                         INTERCEPT_DR2_MASK |
 496                                         INTERCEPT_DR3_MASK;
 497
 498         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 499                                         INTERCEPT_DR1_MASK |
 500                                         INTERCEPT_DR2_MASK |
 501                                         INTERCEPT_DR3_MASK |
 502                                         INTERCEPT_DR5_MASK |
 503                                         INTERCEPT_DR7_MASK;
 504
 505         control->intercept_exceptions = (1 << PF_VECTOR) |
 506                                         (1 << UD_VECTOR) |
 507                                         (1 << MC_VECTOR);
 508
 509
 510         control->intercept =    (1ULL << INTERCEPT_INTR) |
 511                                 (1ULL << INTERCEPT_NMI) |
 512                                 (1ULL << INTERCEPT_SMI) |
 513                                 (1ULL << INTERCEPT_CPUID) |
 514                                 (1ULL << INTERCEPT_INVD) |
 515                                 (1ULL << INTERCEPT_HLT) |
 516                                 (1ULL << INTERCEPT_INVLPG) |
 517                                 (1ULL << INTERCEPT_INVLPGA) |
 518                                 (1ULL << INTERCEPT_IOIO_PROT) |
 519                                 (1ULL << INTERCEPT_MSR_PROT) |
 520                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 521                                 (1ULL << INTERCEPT_SHUTDOWN) |
 522                                 (1ULL << INTERCEPT_VMRUN) |
 523                                 (1ULL << INTERCEPT_VMMCALL) |
 524                                 (1ULL << INTERCEPT_VMLOAD) |
 525                                 (1ULL << INTERCEPT_VMSAVE) |
 526                                 (1ULL << INTERCEPT_STGI) |
 527                                 (1ULL << INTERCEPT_CLGI) |
 528                                 (1ULL << INTERCEPT_SKINIT) |
 529                                 (1ULL << INTERCEPT_WBINVD) |
 530                                 (1ULL << INTERCEPT_MONITOR) |
 531                                 (1ULL << INTERCEPT_MWAIT);
 532
 533         control->iopm_base_pa = iopm_base;
 534         control->msrpm_base_pa = __pa(svm->msrpm);
 535         control->tsc_offset = 0;
 536         control->int_ctl = V_INTR_MASKING_MASK;
 537
 538         init_seg(&save->es);
 539         init_seg(&save->ss);
 540         init_seg(&save->ds);
 541         init_seg(&save->fs);
 542         init_seg(&save->gs);
 543
 544         save->cs.selector = 0xf000;
 545         /* Executable/Readable Code Segment */
 546         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 547                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 548         save->cs.limit = 0xffff;
 549         /*
 550          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 551          * be consistent with it.
 552          *
 553          * Replace when we have real mode working for vmx.
 554          */
 555         save->cs.base = 0xf0000;
 556
 557         save->gdtr.limit = 0xffff;
 558         save->idtr.limit = 0xffff;
 559
 560         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 561         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 562
 563         save->efer = EFER_SVME;
 564         save->dr6 = 0xffff0ff0;
 565         save->dr7 = 0x400;
 566         save->rflags = 2;
 567         save->rip = 0x0000fff0;
 568         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 569
 570         /*
 571          * cr0 val on cpu init should be 0x60000010, we enable cpu
 572          * cache by default. the orderly way is to enable cache in bios.
 573          */
 574         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 575         save->cr4 = X86_CR4_PAE;
 576         /* rdx = ?? */
 577
 578         if (npt_enabled) {
 579                 /* Setup VMCB for Nested Paging */
 580                 control->nested_ctl = 1;
 581                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 582                                         (1ULL << INTERCEPT_INVLPG));
 583                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 584                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 585                                                 INTERCEPT_CR3_MASK);
 586                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 587                                                  INTERCEPT_CR3_MASK);
 588                 save->g_pat = 0x0007040600070406ULL;
 589                 /* enable caching because the QEMU Bios doesn't enable it */
 590                 save->cr0 = X86_CR0_ET;
 591                 save->cr3 = 0;
 592                 save->cr4 = 0;
 593         }
 594         force_new_asid(&svm->vcpu);
 595
 596         svm->nested_vmcb = 0;
 597         svm->vcpu.arch.hflags = HF_GIF_MASK;
 598 }
 599
 600 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 601 {
 602         struct vcpu_svm *svm = to_svm(vcpu);
 603
 604         init_vmcb(svm);
 605
 606         if (vcpu->vcpu_id != 0) {
 607                 kvm_rip_write(vcpu, 0);
 608                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 609                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 610         }
 611         vcpu->arch.regs_avail = ~0;
 612         vcpu->arch.regs_dirty = ~0;
 613
 614         return 0;
 615 }
 616
 617 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 618 {
 619         struct vcpu_svm *svm;
 620         struct page *page;
 621         struct page *msrpm_pages;
 622         struct page *hsave_page;
 623         struct page *nested_msrpm_pages;
 624         int err;
 625
 626         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 627         if (!svm) {
 628                 err = -ENOMEM;
 629                 goto out;
 630         }
 631
 632         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 633         if (err)
 634                 goto free_svm;
 635
 636         page = alloc_page(GFP_KERNEL);
 637         if (!page) {
 638                 err = -ENOMEM;
 639                 goto uninit;
 640         }
 641
 642         err = -ENOMEM;
 643         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 644         if (!msrpm_pages)
 645                 goto uninit;
 646
 647         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 648         if (!nested_msrpm_pages)
 649                 goto uninit;
 650
 651         svm->msrpm = page_address(msrpm_pages);
 652         svm_vcpu_init_msrpm(svm->msrpm);
 653
 654         hsave_page = alloc_page(GFP_KERNEL);
 655         if (!hsave_page)
 656                 goto uninit;
 657         svm->hsave = page_address(hsave_page);
 658
 659         svm->nested_msrpm = page_address(nested_msrpm_pages);
 660
 661         svm->vmcb = page_address(page);
 662         clear_page(svm->vmcb);
 663         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 664         svm->asid_generation = 0;
 665         init_vmcb(svm);
 666
 667         fx_init(&svm->vcpu);
 668         svm->vcpu.fpu_active = 1;
 669         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 670         if (svm->vcpu.vcpu_id == 0)
 671                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 672
 673         return &svm->vcpu;
 674
 675 uninit:
 676         kvm_vcpu_uninit(&svm->vcpu);
 677 free_svm:
 678         kmem_cache_free(kvm_vcpu_cache, svm);
 679 out:
 680         return ERR_PTR(err);
 681 }
 682
 683 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 684 {
 685         struct vcpu_svm *svm = to_svm(vcpu);
 686
 687         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 688         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 689         __free_page(virt_to_page(svm->hsave));
 690         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 691         kvm_vcpu_uninit(vcpu);
 692         kmem_cache_free(kvm_vcpu_cache, svm);
 693 }
 694
 695 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 696 {
 697         struct vcpu_svm *svm = to_svm(vcpu);
 698         int i;
 699
 700         if (unlikely(cpu != vcpu->cpu)) {
 701                 u64 tsc_this, delta;
 702
 703                 /*
 704                  * Make sure that the guest sees a monotonically
 705                  * increasing TSC.
 706                  */
 707                 rdtscll(tsc_this);
 708                 delta = vcpu->arch.host_tsc - tsc_this;
 709                 svm->vmcb->control.tsc_offset += delta;
 710                 vcpu->cpu = cpu;
 711                 kvm_migrate_timers(vcpu);
 712         }
 713
 714         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 715                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 716 }
 717
 718 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 719 {
 720         struct vcpu_svm *svm = to_svm(vcpu);
 721         int i;
 722
 723         ++vcpu->stat.host_state_reload;
 724         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 725                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 726
 727         rdtscll(vcpu->arch.host_tsc);
 728 }
 729
 730 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 731 {
 732         return to_svm(vcpu)->vmcb->save.rflags;
 733 }
 734
 735 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 736 {
 737         to_svm(vcpu)->vmcb->save.rflags = rflags;
 738 }
 739
 740 static void svm_set_vintr(struct vcpu_svm *svm)
 741 {
 742         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 743 }
 744
 745 static void svm_clear_vintr(struct vcpu_svm *svm)
 746 {
 747         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 748 }
 749
 750 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 751 {
 752         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 753
 754         switch (seg) {
 755         case VCPU_SREG_CS: return &save->cs;
 756         case VCPU_SREG_DS: return &save->ds;
 757         case VCPU_SREG_ES: return &save->es;
 758         case VCPU_SREG_FS: return &save->fs;
 759         case VCPU_SREG_GS: return &save->gs;
 760         case VCPU_SREG_SS: return &save->ss;
 761         case VCPU_SREG_TR: return &save->tr;
 762         case VCPU_SREG_LDTR: return &save->ldtr;
 763         }
 764         BUG();
 765         return NULL;
 766 }
 767
 768 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 769 {
 770         struct vmcb_seg *s = svm_seg(vcpu, seg);
 771
 772         return s->base;
 773 }
 774
 775 static void svm_get_segment(struct kvm_vcpu *vcpu,
 776                             struct kvm_segment *var, int seg)
 777 {
 778         struct vmcb_seg *s = svm_seg(vcpu, seg);
 779
 780         var->base = s->base;
 781         var->limit = s->limit;
 782         var->selector = s->selector;
 783         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 784         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 785         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 786         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 787         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 788         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 789         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 790         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 791
 792         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 793          * for cross vendor migration purposes by "not present"
 794          */
 795         var->unusable = !var->present || (var->type == 0);
 796
 797         switch (seg) {
 798         case VCPU_SREG_CS:
 799                 /*
 800                  * SVM always stores 0 for the 'G' bit in the CS selector in
 801                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 802                  * Intel's VMENTRY has a check on the 'G' bit.
 803                  */
 804                 var->g = s->limit > 0xfffff;
 805                 break;
 806         case VCPU_SREG_TR:
 807                 /*
 808                  * Work around a bug where the busy flag in the tr selector
 809                  * isn't exposed
 810                  */
 811                 var->type |= 0x2;
 812                 break;
 813         case VCPU_SREG_DS:
 814         case VCPU_SREG_ES:
 815         case VCPU_SREG_FS:
 816         case VCPU_SREG_GS:
 817                 /*
 818                  * The accessed bit must always be set in the segment
 819                  * descriptor cache, although it can be cleared in the
 820                  * descriptor, the cached bit always remains at 1. Since
 821                  * Intel has a check on this, set it here to support
 822                  * cross-vendor migration.
 823                  */
 824                 if (!var->unusable)
 825                         var->type |= 0x1;
 826                 break;
 827         case VCPU_SREG_SS:
 828                 /* On AMD CPUs sometimes the DB bit in the segment
 829                  * descriptor is left as 1, although the whole segment has
 830                  * been made unusable. Clear it here to pass an Intel VMX
 831                  * entry check when cross vendor migrating.
 832                  */
 833                 if (var->unusable)
 834                         var->db = 0;
 835                 break;
 836         }
 837 }
 838
 839 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 840 {
 841         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 842
 843         return save->cpl;
 844 }
 845
 846 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 847 {
 848         struct vcpu_svm *svm = to_svm(vcpu);
 849
 850         dt->limit = svm->vmcb->save.idtr.limit;
 851         dt->base = svm->vmcb->save.idtr.base;
 852 }
 853
 854 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 855 {
 856         struct vcpu_svm *svm = to_svm(vcpu);
 857
 858         svm->vmcb->save.idtr.limit = dt->limit;
 859         svm->vmcb->save.idtr.base = dt->base ;
 860 }
 861
 862 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 863 {
 864         struct vcpu_svm *svm = to_svm(vcpu);
 865
 866         dt->limit = svm->vmcb->save.gdtr.limit;
 867         dt->base = svm->vmcb->save.gdtr.base;
 868 }
 869
 870 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 871 {
 872         struct vcpu_svm *svm = to_svm(vcpu);
 873
 874         svm->vmcb->save.gdtr.limit = dt->limit;
 875         svm->vmcb->save.gdtr.base = dt->base ;
 876 }
 877
 878 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 879 {
 880 }
 881
 882 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 883 {
 884         struct vcpu_svm *svm = to_svm(vcpu);
 885
 886 #ifdef CONFIG_X86_64
 887         if (vcpu->arch.shadow_efer & EFER_LME) {
 888                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 889                         vcpu->arch.shadow_efer |= EFER_LMA;
 890                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 891                 }
 892
 893                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 894                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 895                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 896                 }
 897         }
 898 #endif
 899         if (npt_enabled)
 900                 goto set;
 901
 902         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 903                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 904                 vcpu->fpu_active = 1;
 905         }
 906
 907         vcpu->arch.cr0 = cr0;
 908         cr0 |= X86_CR0_PG | X86_CR0_WP;
 909         if (!vcpu->fpu_active) {
 910                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 911                 cr0 |= X86_CR0_TS;
 912         }
 913 set:
 914         /*
 915          * re-enable caching here because the QEMU bios
 916          * does not do it - this results in some delay at
 917          * reboot
 918          */
 919         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 920         svm->vmcb->save.cr0 = cr0;
 921 }
 922
 923 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 924 {
 925         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 926         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 927
 928         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 929                 force_new_asid(vcpu);
 930
 931         vcpu->arch.cr4 = cr4;
 932         if (!npt_enabled)
 933                 cr4 |= X86_CR4_PAE;
 934         cr4 |= host_cr4_mce;
 935         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 936 }
 937
 938 static void svm_set_segment(struct kvm_vcpu *vcpu,
 939                             struct kvm_segment *var, int seg)
 940 {
 941         struct vcpu_svm *svm = to_svm(vcpu);
 942         struct vmcb_seg *s = svm_seg(vcpu, seg);
 943
 944         s->base = var->base;
 945         s->limit = var->limit;
 946         s->selector = var->selector;
 947         if (var->unusable)
 948                 s->attrib = 0;
 949         else {
 950                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 951                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 952                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 953                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 954                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 955                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 956                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 957                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 958         }
 959         if (seg == VCPU_SREG_CS)
 960                 svm->vmcb->save.cpl
 961                         = (svm->vmcb->save.cs.attrib
 962                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 963
 964 }
 965
 966 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
 967 {
 968         int old_debug = vcpu->guest_debug;
 969         struct vcpu_svm *svm = to_svm(vcpu);
 970
 971         vcpu->guest_debug = dbg->control;
 972
 973         svm->vmcb->control.intercept_exceptions &=
 974                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
 975         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 976                 if (vcpu->guest_debug &
 977                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 978                         svm->vmcb->control.intercept_exceptions |=
 979                                 1 << DB_VECTOR;
 980                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 981                         svm->vmcb->control.intercept_exceptions |=
 982                                 1 << BP_VECTOR;
 983         } else
 984                 vcpu->guest_debug = 0;
 985
 986         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 987                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
 988         else
 989                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
 990
 991         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
 992                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
 993         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
 994                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 995
 996         return 0;
 997 }
 998
 999 static void load_host_msrs(struct kvm_vcpu *vcpu)
1000 {
1001 #ifdef CONFIG_X86_64
1002         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1003 #endif
1004 }
1005
1006 static void save_host_msrs(struct kvm_vcpu *vcpu)
1007 {
1008 #ifdef CONFIG_X86_64
1009         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1010 #endif
1011 }
1012
1013 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1014 {
1015         if (svm_data->next_asid > svm_data->max_asid) {
1016                 ++svm_data->asid_generation;
1017                 svm_data->next_asid = 1;
1018                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1019         }
1020
1021         svm->vcpu.cpu = svm_data->cpu;
1022         svm->asid_generation = svm_data->asid_generation;
1023         svm->vmcb->control.asid = svm_data->next_asid++;
1024 }
1025
1026 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1027 {
1028         struct vcpu_svm *svm = to_svm(vcpu);
1029         unsigned long val;
1030
1031         switch (dr) {
1032         case 0 ... 3:
1033                 val = vcpu->arch.db[dr];
1034                 break;
1035         case 6:
1036                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1037                         val = vcpu->arch.dr6;
1038                 else
1039                         val = svm->vmcb->save.dr6;
1040                 break;
1041         case 7:
1042                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1043                         val = vcpu->arch.dr7;
1044                 else
1045                         val = svm->vmcb->save.dr7;
1046                 break;
1047         default:
1048                 val = 0;
1049         }
1050
1051         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1052         return val;
1053 }
1054
1055 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1056                        int *exception)
1057 {
1058         struct vcpu_svm *svm = to_svm(vcpu);
1059
1060         KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
1061
1062         *exception = 0;
1063
1064         switch (dr) {
1065         case 0 ... 3:
1066                 vcpu->arch.db[dr] = value;
1067                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1068                         vcpu->arch.eff_db[dr] = value;
1069                 return;
1070         case 4 ... 5:
1071                 if (vcpu->arch.cr4 & X86_CR4_DE)
1072                         *exception = UD_VECTOR;
1073                 return;
1074         case 6:
1075                 if (value & 0xffffffff00000000ULL) {
1076                         *exception = GP_VECTOR;
1077                         return;
1078                 }
1079                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1080                 return;
1081         case 7:
1082                 if (value & 0xffffffff00000000ULL) {
1083                         *exception = GP_VECTOR;
1084                         return;
1085                 }
1086                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1087                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1088                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1089                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1090                 }
1091                 return;
1092         default:
1093                 /* FIXME: Possible case? */
1094                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1095                        __func__, dr);
1096                 *exception = UD_VECTOR;
1097                 return;
1098         }
1099 }
1100
1101 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1102 {
1103         u64 fault_address;
1104         u32 error_code;
1105
1106         fault_address  = svm->vmcb->control.exit_info_2;
1107         error_code = svm->vmcb->control.exit_info_1;
1108
1109         if (!npt_enabled)
1110                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1111                             (u32)fault_address, (u32)(fault_address >> 32),
1112                             handler);
1113         else
1114                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1115                             (u32)fault_address, (u32)(fault_address >> 32),
1116                             handler);
1117         /*
1118          * FIXME: Tis shouldn't be necessary here, but there is a flush
1119          * missing in the MMU code. Until we find this bug, flush the
1120          * complete TLB here on an NPF
1121          */
1122         if (npt_enabled)
1123                 svm_flush_tlb(&svm->vcpu);
1124         else {
1125                 if (svm->vcpu.arch.interrupt.pending ||
1126                                 svm->vcpu.arch.exception.pending)
1127                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1128         }
1129         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1130 }
1131
1132 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1133 {
1134         if (!(svm->vcpu.guest_debug &
1135               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1136                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1137                 return 1;
1138         }
1139         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1140         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1141         kvm_run->debug.arch.exception = DB_VECTOR;
1142         return 0;
1143 }
1144
1145 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1146 {
1147         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1148         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1149         kvm_run->debug.arch.exception = BP_VECTOR;
1150         return 0;
1151 }
1152
1153 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1154 {
1155         int er;
1156
1157         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1158         if (er != EMULATE_DONE)
1159                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1160         return 1;
1161 }
1162
1163 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1164 {
1165         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1166         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1167                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1168         svm->vcpu.fpu_active = 1;
1169
1170         return 1;
1171 }
1172
1173 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1174 {
1175         /*
1176          * On an #MC intercept the MCE handler is not called automatically in
1177          * the host. So do it by hand here.
1178          */
1179         asm volatile (
1180                 "int $0x12\n");
1181         /* not sure if we ever come back to this point */
1182
1183         return 1;
1184 }
1185
1186 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1187 {
1188         /*
1189          * VMCB is undefined after a SHUTDOWN intercept
1190          * so reinitialize it.
1191          */
1192         clear_page(svm->vmcb);
1193         init_vmcb(svm);
1194
1195         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1196         return 0;
1197 }
1198
1199 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1200 {
1201         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1202         int size, in, string;
1203         unsigned port;
1204
1205         ++svm->vcpu.stat.io_exits;
1206
1207         svm->next_rip = svm->vmcb->control.exit_info_2;
1208
1209         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1210
1211         if (string) {
1212                 if (emulate_instruction(&svm->vcpu,
1213                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1214                         return 0;
1215                 return 1;
1216         }
1217
1218         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1219         port = io_info >> 16;
1220         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1221
1222         skip_emulated_instruction(&svm->vcpu);
1223         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1224 }
1225
1226 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1227 {
1228         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1229         return 1;
1230 }
1231
1232 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1233 {
1234         ++svm->vcpu.stat.irq_exits;
1235         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1236         return 1;
1237 }
1238
1239 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1240 {
1241         return 1;
1242 }
1243
1244 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1245 {
1246         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1247         skip_emulated_instruction(&svm->vcpu);
1248         return kvm_emulate_halt(&svm->vcpu);
1249 }
1250
1251 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1252 {
1253         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1254         skip_emulated_instruction(&svm->vcpu);
1255         kvm_emulate_hypercall(&svm->vcpu);
1256         return 1;
1257 }
1258
1259 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1260 {
1261         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1262             || !is_paging(&svm->vcpu)) {
1263                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1264                 return 1;
1265         }
1266
1267         if (svm->vmcb->save.cpl) {
1268                 kvm_inject_gp(&svm->vcpu, 0);
1269                 return 1;
1270         }
1271
1272        return 0;
1273 }
1274
1275 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1276                                       bool has_error_code, u32 error_code)
1277 {
1278         if (is_nested(svm)) {
1279                 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1280                 svm->vmcb->control.exit_code_hi = 0;
1281                 svm->vmcb->control.exit_info_1 = error_code;
1282                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1283                 if (nested_svm_exit_handled(svm, false)) {
1284                         nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1285
1286                         nested_svm_vmexit(svm);
1287                         return 1;
1288                 }
1289         }
1290
1291         return 0;
1292 }
1293
1294 static inline int nested_svm_intr(struct vcpu_svm *svm)
1295 {
1296         if (is_nested(svm)) {
1297                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1298                         return 0;
1299
1300                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1301                         return 0;
1302
1303                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1304
1305                 if (nested_svm_exit_handled(svm, false)) {
1306                         nsvm_printk("VMexit -> INTR\n");
1307                         nested_svm_vmexit(svm);
1308                         return 1;
1309                 }
1310         }
1311
1312         return 0;
1313 }
1314
1315 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1316 {
1317         struct page *page;
1318
1319         down_read(&current->mm->mmap_sem);
1320         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1321         up_read(&current->mm->mmap_sem);
1322
1323         if (is_error_page(page)) {
1324                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1325                        __func__, gpa);
1326                 kvm_release_page_clean(page);
1327                 kvm_inject_gp(&svm->vcpu, 0);
1328                 return NULL;
1329         }
1330         return page;
1331 }
1332
1333 static int nested_svm_do(struct vcpu_svm *svm,
1334                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1335                          int (*handler)(struct vcpu_svm *svm,
1336                                         void *arg1,
1337                                         void *arg2,
1338                                         void *opaque))
1339 {
1340         struct page *arg1_page;
1341         struct page *arg2_page = NULL;
1342         void *arg1;
1343         void *arg2 = NULL;
1344         int retval;
1345
1346         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1347         if(arg1_page == NULL)
1348                 return 1;
1349
1350         if (arg2_gpa) {
1351                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1352                 if(arg2_page == NULL) {
1353                         kvm_release_page_clean(arg1_page);
1354                         return 1;
1355                 }
1356         }
1357
1358         arg1 = kmap_atomic(arg1_page, KM_USER0);
1359         if (arg2_gpa)
1360                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1361
1362         retval = handler(svm, arg1, arg2, opaque);
1363
1364         kunmap_atomic(arg1, KM_USER0);
1365         if (arg2_gpa)
1366                 kunmap_atomic(arg2, KM_USER1);
1367
1368         kvm_release_page_dirty(arg1_page);
1369         if (arg2_gpa)
1370                 kvm_release_page_dirty(arg2_page);
1371
1372         return retval;
1373 }
1374
1375 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1376                                         void *arg1,
1377                                         void *arg2,
1378                                         void *opaque)
1379 {
1380         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1381         bool kvm_overrides = *(bool *)opaque;
1382         u32 exit_code = svm->vmcb->control.exit_code;
1383
1384         if (kvm_overrides) {
1385                 switch (exit_code) {
1386                 case SVM_EXIT_INTR:
1387                 case SVM_EXIT_NMI:
1388                         return 0;
1389                 /* For now we are always handling NPFs when using them */
1390                 case SVM_EXIT_NPF:
1391                         if (npt_enabled)
1392                                 return 0;
1393                         break;
1394                 /* When we're shadowing, trap PFs */
1395                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1396                         if (!npt_enabled)
1397                                 return 0;
1398                         break;
1399                 default:
1400                         break;
1401                 }
1402         }
1403
1404         switch (exit_code) {
1405         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1406                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1407                 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1408                         return 1;
1409                 break;
1410         }
1411         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1412                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1413                 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1414                         return 1;
1415                 break;
1416         }
1417         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1418                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1419                 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1420                         return 1;
1421                 break;
1422         }
1423         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1424                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1425                 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1426                         return 1;
1427                 break;
1428         }
1429         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1430                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1431                 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1432                         return 1;
1433                 break;
1434         }
1435         default: {
1436                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1437                 nsvm_printk("exit code: 0x%x\n", exit_code);
1438                 if (nested_vmcb->control.intercept & exit_bits)
1439                         return 1;
1440         }
1441         }
1442
1443         return 0;
1444 }
1445
1446 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1447                                        void *arg1, void *arg2,
1448                                        void *opaque)
1449 {
1450         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1451         u8 *msrpm = (u8 *)arg2;
1452         u32 t0, t1;
1453         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1454         u32 param = svm->vmcb->control.exit_info_1 & 1;
1455
1456         if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1457                 return 0;
1458
1459         switch(msr) {
1460         case 0 ... 0x1fff:
1461                 t0 = (msr * 2) % 8;
1462                 t1 = msr / 8;
1463                 break;
1464         case 0xc0000000 ... 0xc0001fff:
1465                 t0 = (8192 + msr - 0xc0000000) * 2;
1466                 t1 = (t0 / 8);
1467                 t0 %= 8;
1468                 break;
1469         case 0xc0010000 ... 0xc0011fff:
1470                 t0 = (16384 + msr - 0xc0010000) * 2;
1471                 t1 = (t0 / 8);
1472                 t0 %= 8;
1473                 break;
1474         default:
1475                 return 1;
1476                 break;
1477         }
1478         if (msrpm[t1] & ((1 << param) << t0))
1479                 return 1;
1480
1481         return 0;
1482 }
1483
1484 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1485 {
1486         bool k = kvm_override;
1487
1488         switch (svm->vmcb->control.exit_code) {
1489         case SVM_EXIT_MSR:
1490                 return nested_svm_do(svm, svm->nested_vmcb,
1491                                      svm->nested_vmcb_msrpm, NULL,
1492                                      nested_svm_exit_handled_msr);
1493         default: break;
1494         }
1495
1496         return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1497                              nested_svm_exit_handled_real);
1498 }
1499
1500 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1501                                   void *arg2, void *opaque)
1502 {
1503         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1504         struct vmcb *hsave = svm->hsave;
1505         u64 nested_save[] = { nested_vmcb->save.cr0,
1506                               nested_vmcb->save.cr3,
1507                               nested_vmcb->save.cr4,
1508                               nested_vmcb->save.efer,
1509                               nested_vmcb->control.intercept_cr_read,
1510                               nested_vmcb->control.intercept_cr_write,
1511                               nested_vmcb->control.intercept_dr_read,
1512                               nested_vmcb->control.intercept_dr_write,
1513                               nested_vmcb->control.intercept_exceptions,
1514                               nested_vmcb->control.intercept,
1515                               nested_vmcb->control.msrpm_base_pa,
1516                               nested_vmcb->control.iopm_base_pa,
1517                               nested_vmcb->control.tsc_offset };
1518
1519         /* Give the current vmcb to the guest */
1520         memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1521         nested_vmcb->save.cr0 = nested_save[0];
1522         if (!npt_enabled)
1523                 nested_vmcb->save.cr3 = nested_save[1];
1524         nested_vmcb->save.cr4 = nested_save[2];
1525         nested_vmcb->save.efer = nested_save[3];
1526         nested_vmcb->control.intercept_cr_read = nested_save[4];
1527         nested_vmcb->control.intercept_cr_write = nested_save[5];
1528         nested_vmcb->control.intercept_dr_read = nested_save[6];
1529         nested_vmcb->control.intercept_dr_write = nested_save[7];
1530         nested_vmcb->control.intercept_exceptions = nested_save[8];
1531         nested_vmcb->control.intercept = nested_save[9];
1532         nested_vmcb->control.msrpm_base_pa = nested_save[10];
1533         nested_vmcb->control.iopm_base_pa = nested_save[11];
1534         nested_vmcb->control.tsc_offset = nested_save[12];
1535
1536         /* We always set V_INTR_MASKING and remember the old value in hflags */
1537         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1538                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1539
1540         if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1541             (nested_vmcb->control.int_vector)) {
1542                 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1543                                 nested_vmcb->control.int_vector);
1544         }
1545
1546         /* Restore the original control entries */
1547         svm->vmcb->control = hsave->control;
1548
1549         /* Kill any pending exceptions */
1550         if (svm->vcpu.arch.exception.pending == true)
1551                 nsvm_printk("WARNING: Pending Exception\n");
1552         svm->vcpu.arch.exception.pending = false;
1553
1554         /* Restore selected save entries */
1555         svm->vmcb->save.es = hsave->save.es;
1556         svm->vmcb->save.cs = hsave->save.cs;
1557         svm->vmcb->save.ss = hsave->save.ss;
1558         svm->vmcb->save.ds = hsave->save.ds;
1559         svm->vmcb->save.gdtr = hsave->save.gdtr;
1560         svm->vmcb->save.idtr = hsave->save.idtr;
1561         svm->vmcb->save.rflags = hsave->save.rflags;
1562         svm_set_efer(&svm->vcpu, hsave->save.efer);
1563         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1564         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1565         if (npt_enabled) {
1566                 svm->vmcb->save.cr3 = hsave->save.cr3;
1567                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1568         } else {
1569                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1570         }
1571         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1572         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1573         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1574         svm->vmcb->save.dr7 = 0;
1575         svm->vmcb->save.cpl = 0;
1576         svm->vmcb->control.exit_int_info = 0;
1577
1578         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1579         /* Exit nested SVM mode */
1580         svm->nested_vmcb = 0;
1581
1582         return 0;
1583 }
1584
1585 static int nested_svm_vmexit(struct vcpu_svm *svm)
1586 {
1587         nsvm_printk("VMexit\n");
1588         if (nested_svm_do(svm, svm->nested_vmcb, 0,
1589                           NULL, nested_svm_vmexit_real))
1590                 return 1;
1591
1592         kvm_mmu_reset_context(&svm->vcpu);
1593         kvm_mmu_load(&svm->vcpu);
1594
1595         return 0;
1596 }
1597
1598 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1599                                   void *arg2, void *opaque)
1600 {
1601         int i;
1602         u32 *nested_msrpm = (u32*)arg1;
1603         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1604                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1605         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1606
1607         return 0;
1608 }
1609
1610 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1611                             void *arg2, void *opaque)
1612 {
1613         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1614         struct vmcb *hsave = svm->hsave;
1615
1616         /* nested_vmcb is our indicator if nested SVM is activated */
1617         svm->nested_vmcb = svm->vmcb->save.rax;
1618
1619         /* Clear internal status */
1620         svm->vcpu.arch.exception.pending = false;
1621
1622         /* Save the old vmcb, so we don't need to pick what we save, but
1623            can restore everything when a VMEXIT occurs */
1624         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1625         /* We need to remember the original CR3 in the SPT case */
1626         if (!npt_enabled)
1627                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1628         hsave->save.cr4 = svm->vcpu.arch.cr4;
1629         hsave->save.rip = svm->next_rip;
1630
1631         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1632                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1633         else
1634                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1635
1636         /* Load the nested guest state */
1637         svm->vmcb->save.es = nested_vmcb->save.es;
1638         svm->vmcb->save.cs = nested_vmcb->save.cs;
1639         svm->vmcb->save.ss = nested_vmcb->save.ss;
1640         svm->vmcb->save.ds = nested_vmcb->save.ds;
1641         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1642         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1643         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1644         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1645         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1646         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1647         if (npt_enabled) {
1648                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1649                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1650         } else {
1651                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1652                 kvm_mmu_reset_context(&svm->vcpu);
1653         }
1654         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1655         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1656         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1657         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1658         /* In case we don't even reach vcpu_run, the fields are not updated */
1659         svm->vmcb->save.rax = nested_vmcb->save.rax;
1660         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1661         svm->vmcb->save.rip = nested_vmcb->save.rip;
1662         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1663         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1664         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1665
1666         /* We don't want a nested guest to be more powerful than the guest,
1667            so all intercepts are ORed */
1668         svm->vmcb->control.intercept_cr_read |=
1669                 nested_vmcb->control.intercept_cr_read;
1670         svm->vmcb->control.intercept_cr_write |=
1671                 nested_vmcb->control.intercept_cr_write;
1672         svm->vmcb->control.intercept_dr_read |=
1673                 nested_vmcb->control.intercept_dr_read;
1674         svm->vmcb->control.intercept_dr_write |=
1675                 nested_vmcb->control.intercept_dr_write;
1676         svm->vmcb->control.intercept_exceptions |=
1677                 nested_vmcb->control.intercept_exceptions;
1678
1679         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1680
1681         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1682
1683         force_new_asid(&svm->vcpu);
1684         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1685         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1686         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1687         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1688                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1689                                 nested_vmcb->control.int_ctl);
1690         }
1691         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1692                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1693         else
1694                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1695
1696         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1697                         nested_vmcb->control.exit_int_info,
1698                         nested_vmcb->control.int_state);
1699
1700         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1701         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1702         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1703         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1704                 nsvm_printk("Injecting Event: 0x%x\n",
1705                                 nested_vmcb->control.event_inj);
1706         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1707         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1708
1709         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1710
1711         return 0;
1712 }
1713
1714 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1715 {
1716         to_vmcb->save.fs = from_vmcb->save.fs;
1717         to_vmcb->save.gs = from_vmcb->save.gs;
1718         to_vmcb->save.tr = from_vmcb->save.tr;
1719         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1720         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1721         to_vmcb->save.star = from_vmcb->save.star;
1722         to_vmcb->save.lstar = from_vmcb->save.lstar;
1723         to_vmcb->save.cstar = from_vmcb->save.cstar;
1724         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1725         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1726         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1727         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1728
1729         return 1;
1730 }
1731
1732 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1733                              void *arg2, void *opaque)
1734 {
1735         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1736 }
1737
1738 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1739                              void *arg2, void *opaque)
1740 {
1741         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1742 }
1743
1744 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1745 {
1746         if (nested_svm_check_permissions(svm))
1747                 return 1;
1748
1749         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1750         skip_emulated_instruction(&svm->vcpu);
1751
1752         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1753
1754         return 1;
1755 }
1756
1757 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1758 {
1759         if (nested_svm_check_permissions(svm))
1760                 return 1;
1761
1762         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1763         skip_emulated_instruction(&svm->vcpu);
1764
1765         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1766
1767         return 1;
1768 }
1769
1770 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1771 {
1772         nsvm_printk("VMrun\n");
1773         if (nested_svm_check_permissions(svm))
1774                 return 1;
1775
1776         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1777         skip_emulated_instruction(&svm->vcpu);
1778
1779         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1780                           NULL, nested_svm_vmrun))
1781                 return 1;
1782
1783         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1784                       NULL, nested_svm_vmrun_msrpm))
1785                 return 1;
1786
1787         return 1;
1788 }
1789
1790 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1791 {
1792         if (nested_svm_check_permissions(svm))
1793                 return 1;
1794
1795         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1796         skip_emulated_instruction(&svm->vcpu);
1797
1798         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1799
1800         return 1;
1801 }
1802
1803 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1804 {
1805         if (nested_svm_check_permissions(svm))
1806                 return 1;
1807
1808         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1809         skip_emulated_instruction(&svm->vcpu);
1810
1811         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1812
1813         /* After a CLGI no interrupts should come */
1814         svm_clear_vintr(svm);
1815         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1816
1817         return 1;
1818 }
1819
1820 static int invalid_op_interception(struct vcpu_svm *svm,
1821                                    struct kvm_run *kvm_run)
1822 {
1823         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1824         return 1;
1825 }
1826
1827 static int task_switch_interception(struct vcpu_svm *svm,
1828                                     struct kvm_run *kvm_run)
1829 {
1830         u16 tss_selector;
1831         int reason;
1832         int int_type = svm->vmcb->control.exit_int_info &
1833                 SVM_EXITINTINFO_TYPE_MASK;
1834         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1835         uint32_t type =
1836                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1837         uint32_t idt_v =
1838                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1839
1840         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1841
1842         if (svm->vmcb->control.exit_info_2 &
1843             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1844                 reason = TASK_SWITCH_IRET;
1845         else if (svm->vmcb->control.exit_info_2 &
1846                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1847                 reason = TASK_SWITCH_JMP;
1848         else if (idt_v)
1849                 reason = TASK_SWITCH_GATE;
1850         else
1851                 reason = TASK_SWITCH_CALL;
1852
1853         if (reason == TASK_SWITCH_GATE) {
1854                 switch (type) {
1855                 case SVM_EXITINTINFO_TYPE_NMI:
1856                         svm->vcpu.arch.nmi_injected = false;
1857                         break;
1858                 case SVM_EXITINTINFO_TYPE_EXEPT:
1859                         kvm_clear_exception_queue(&svm->vcpu);
1860                         break;
1861                 case SVM_EXITINTINFO_TYPE_INTR:
1862                         kvm_clear_interrupt_queue(&svm->vcpu);
1863                         break;
1864                 default:
1865                         break;
1866                 }
1867         }
1868
1869         if (reason != TASK_SWITCH_GATE ||
1870             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1871             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1872              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
1873                 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0,
1874                                         EMULTYPE_SKIP) != EMULATE_DONE)
1875                         return 0;
1876         }
1877
1878         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
1879 }
1880
1881 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1882 {
1883         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1884         kvm_emulate_cpuid(&svm->vcpu);
1885         return 1;
1886 }
1887
1888 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1889 {
1890         ++svm->vcpu.stat.nmi_window_exits;
1891         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
1892         svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
1893         return 1;
1894 }
1895
1896 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1897 {
1898         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1899                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1900         return 1;
1901 }
1902
1903 static int emulate_on_interception(struct vcpu_svm *svm,
1904                                    struct kvm_run *kvm_run)
1905 {
1906         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1907                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1908         return 1;
1909 }
1910
1911 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1912 {
1913         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
1914         /* instruction emulation calls kvm_set_cr8() */
1915         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1916         if (irqchip_in_kernel(svm->vcpu.kvm)) {
1917                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1918                 return 1;
1919         }
1920         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
1921                 return 1;
1922         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1923         return 0;
1924 }
1925
1926 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1927 {
1928         struct vcpu_svm *svm = to_svm(vcpu);
1929
1930         switch (ecx) {
1931         case MSR_IA32_TIME_STAMP_COUNTER: {
1932                 u64 tsc;
1933
1934                 rdtscll(tsc);
1935                 *data = svm->vmcb->control.tsc_offset + tsc;
1936                 break;
1937         }
1938         case MSR_K6_STAR:
1939                 *data = svm->vmcb->save.star;
1940                 break;
1941 #ifdef CONFIG_X86_64
1942         case MSR_LSTAR:
1943                 *data = svm->vmcb->save.lstar;
1944                 break;
1945         case MSR_CSTAR:
1946                 *data = svm->vmcb->save.cstar;
1947                 break;
1948         case MSR_KERNEL_GS_BASE:
1949                 *data = svm->vmcb->save.kernel_gs_base;
1950                 break;
1951         case MSR_SYSCALL_MASK:
1952                 *data = svm->vmcb->save.sfmask;
1953                 break;
1954 #endif
1955         case MSR_IA32_SYSENTER_CS:
1956                 *data = svm->vmcb->save.sysenter_cs;
1957                 break;
1958         case MSR_IA32_SYSENTER_EIP:
1959                 *data = svm->vmcb->save.sysenter_eip;
1960                 break;
1961         case MSR_IA32_SYSENTER_ESP:
1962                 *data = svm->vmcb->save.sysenter_esp;
1963                 break;
1964         /* Nobody will change the following 5 values in the VMCB so
1965            we can safely return them on rdmsr. They will always be 0
1966            until LBRV is implemented. */
1967         case MSR_IA32_DEBUGCTLMSR:
1968                 *data = svm->vmcb->save.dbgctl;
1969                 break;
1970         case MSR_IA32_LASTBRANCHFROMIP:
1971                 *data = svm->vmcb->save.br_from;
1972                 break;
1973         case MSR_IA32_LASTBRANCHTOIP:
1974                 *data = svm->vmcb->save.br_to;
1975                 break;
1976         case MSR_IA32_LASTINTFROMIP:
1977                 *data = svm->vmcb->save.last_excp_from;
1978                 break;
1979         case MSR_IA32_LASTINTTOIP:
1980                 *data = svm->vmcb->save.last_excp_to;
1981                 break;
1982         case MSR_VM_HSAVE_PA:
1983                 *data = svm->hsave_msr;
1984                 break;
1985         case MSR_VM_CR:
1986                 *data = 0;
1987                 break;
1988         case MSR_IA32_UCODE_REV:
1989                 *data = 0x01000065;
1990                 break;
1991         default:
1992                 return kvm_get_msr_common(vcpu, ecx, data);
1993         }
1994         return 0;
1995 }
1996
1997 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1998 {
1999         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2000         u64 data;
2001
2002         if (svm_get_msr(&svm->vcpu, ecx, &data))
2003                 kvm_inject_gp(&svm->vcpu, 0);
2004         else {
2005                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
2006                             (u32)(data >> 32), handler);
2007
2008                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2009                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2010                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2011                 skip_emulated_instruction(&svm->vcpu);
2012         }
2013         return 1;
2014 }
2015
2016 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2017 {
2018         struct vcpu_svm *svm = to_svm(vcpu);
2019
2020         switch (ecx) {
2021         case MSR_IA32_TIME_STAMP_COUNTER: {
2022                 u64 tsc;
2023
2024                 rdtscll(tsc);
2025                 svm->vmcb->control.tsc_offset = data - tsc;
2026                 break;
2027         }
2028         case MSR_K6_STAR:
2029                 svm->vmcb->save.star = data;
2030                 break;
2031 #ifdef CONFIG_X86_64
2032         case MSR_LSTAR:
2033                 svm->vmcb->save.lstar = data;
2034                 break;
2035         case MSR_CSTAR:
2036                 svm->vmcb->save.cstar = data;
2037                 break;
2038         case MSR_KERNEL_GS_BASE:
2039                 svm->vmcb->save.kernel_gs_base = data;
2040                 break;
2041         case MSR_SYSCALL_MASK:
2042                 svm->vmcb->save.sfmask = data;
2043                 break;
2044 #endif
2045         case MSR_IA32_SYSENTER_CS:
2046                 svm->vmcb->save.sysenter_cs = data;
2047                 break;
2048         case MSR_IA32_SYSENTER_EIP:
2049                 svm->vmcb->save.sysenter_eip = data;
2050                 break;
2051         case MSR_IA32_SYSENTER_ESP:
2052                 svm->vmcb->save.sysenter_esp = data;
2053                 break;
2054         case MSR_IA32_DEBUGCTLMSR:
2055                 if (!svm_has(SVM_FEATURE_LBRV)) {
2056                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2057                                         __func__, data);
2058                         break;
2059                 }
2060                 if (data & DEBUGCTL_RESERVED_BITS)
2061                         return 1;
2062
2063                 svm->vmcb->save.dbgctl = data;
2064                 if (data & (1ULL<<0))
2065                         svm_enable_lbrv(svm);
2066                 else
2067                         svm_disable_lbrv(svm);
2068                 break;
2069         case MSR_K7_EVNTSEL0:
2070         case MSR_K7_EVNTSEL1:
2071         case MSR_K7_EVNTSEL2:
2072         case MSR_K7_EVNTSEL3:
2073         case MSR_K7_PERFCTR0:
2074         case MSR_K7_PERFCTR1:
2075         case MSR_K7_PERFCTR2:
2076         case MSR_K7_PERFCTR3:
2077                 /*
2078                  * Just discard all writes to the performance counters; this
2079                  * should keep both older linux and windows 64-bit guests
2080                  * happy
2081                  */
2082                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2083
2084                 break;
2085         case MSR_VM_HSAVE_PA:
2086                 svm->hsave_msr = data;
2087                 break;
2088         default:
2089                 return kvm_set_msr_common(vcpu, ecx, data);
2090         }
2091         return 0;
2092 }
2093
2094 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2095 {
2096         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2097         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2098                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2099
2100         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2101                     handler);
2102
2103         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2104         if (svm_set_msr(&svm->vcpu, ecx, data))
2105                 kvm_inject_gp(&svm->vcpu, 0);
2106         else
2107                 skip_emulated_instruction(&svm->vcpu);
2108         return 1;
2109 }
2110
2111 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2112 {
2113         if (svm->vmcb->control.exit_info_1)
2114                 return wrmsr_interception(svm, kvm_run);
2115         else
2116                 return rdmsr_interception(svm, kvm_run);
2117 }
2118
2119 static int interrupt_window_interception(struct vcpu_svm *svm,
2120                                    struct kvm_run *kvm_run)
2121 {
2122         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2123
2124         svm_clear_vintr(svm);
2125         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2126         /*
2127          * If the user space waits to inject interrupts, exit as soon as
2128          * possible
2129          */
2130         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2131             kvm_run->request_interrupt_window &&
2132             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2133                 ++svm->vcpu.stat.irq_window_exits;
2134                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2135                 return 0;
2136         }
2137
2138         return 1;
2139 }
2140
2141 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2142                                       struct kvm_run *kvm_run) = {
2143         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2144         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2145         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2146         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2147         /* for now: */
2148         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2149         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2150         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2151         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2152         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2153         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2154         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2155         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2156         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2157         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2158         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2159         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2160         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2161         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2162         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2163         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2164         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2165         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2166         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2167         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2168         [SVM_EXIT_INTR]                         = intr_interception,
2169         [SVM_EXIT_NMI]                          = nmi_interception,
2170         [SVM_EXIT_SMI]                          = nop_on_interception,
2171         [SVM_EXIT_INIT]                         = nop_on_interception,
2172         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2173         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2174         [SVM_EXIT_CPUID]                        = cpuid_interception,
2175         [SVM_EXIT_IRET]                         = iret_interception,
2176         [SVM_EXIT_INVD]                         = emulate_on_interception,
2177         [SVM_EXIT_HLT]                          = halt_interception,
2178         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2179         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
2180         [SVM_EXIT_IOIO]                         = io_interception,
2181         [SVM_EXIT_MSR]                          = msr_interception,
2182         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2183         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2184         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2185         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2186         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2187         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2188         [SVM_EXIT_STGI]                         = stgi_interception,
2189         [SVM_EXIT_CLGI]                         = clgi_interception,
2190         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2191         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2192         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2193         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2194         [SVM_EXIT_NPF]                          = pf_interception,
2195 };
2196
2197 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2198 {
2199         struct vcpu_svm *svm = to_svm(vcpu);
2200         u32 exit_code = svm->vmcb->control.exit_code;
2201
2202         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2203                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2204
2205         if (is_nested(svm)) {
2206                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2207                             exit_code, svm->vmcb->control.exit_info_1,
2208                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2209                 if (nested_svm_exit_handled(svm, true)) {
2210                         nested_svm_vmexit(svm);
2211                         nsvm_printk("-> #VMEXIT\n");
2212                         return 1;
2213                 }
2214         }
2215
2216         if (npt_enabled) {
2217                 int mmu_reload = 0;
2218                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2219                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2220                         mmu_reload = 1;
2221                 }
2222                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2223                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2224                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2225                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2226                                 kvm_inject_gp(vcpu, 0);
2227                                 return 1;
2228                         }
2229                 }
2230                 if (mmu_reload) {
2231                         kvm_mmu_reset_context(vcpu);
2232                         kvm_mmu_load(vcpu);
2233                 }
2234         }
2235
2236
2237         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2238                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2239                 kvm_run->fail_entry.hardware_entry_failure_reason
2240                         = svm->vmcb->control.exit_code;
2241                 return 0;
2242         }
2243
2244         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2245             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2246             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2247                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2248                        "exit_code 0x%x\n",
2249                        __func__, svm->vmcb->control.exit_int_info,
2250                        exit_code);
2251
2252         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2253             || !svm_exit_handlers[exit_code]) {
2254                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2255                 kvm_run->hw.hardware_exit_reason = exit_code;
2256                 return 0;
2257         }
2258
2259         return svm_exit_handlers[exit_code](svm, kvm_run);
2260 }
2261
2262 static void reload_tss(struct kvm_vcpu *vcpu)
2263 {
2264         int cpu = raw_smp_processor_id();
2265
2266         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2267         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2268         load_TR_desc();
2269 }
2270
2271 static void pre_svm_run(struct vcpu_svm *svm)
2272 {
2273         int cpu = raw_smp_processor_id();
2274
2275         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2276
2277         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2278         if (svm->vcpu.cpu != cpu ||
2279             svm->asid_generation != svm_data->asid_generation)
2280                 new_asid(svm, svm_data);
2281 }
2282
2283 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2284 {
2285         struct vcpu_svm *svm = to_svm(vcpu);
2286
2287         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2288         vcpu->arch.hflags |= HF_NMI_MASK;
2289         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2290         ++vcpu->stat.nmi_injections;
2291 }
2292
2293 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2294 {
2295         struct vmcb_control_area *control;
2296
2297         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2298
2299         ++svm->vcpu.stat.irq_injections;
2300         control = &svm->vmcb->control;
2301         control->int_vector = irq;
2302         control->int_ctl &= ~V_INTR_PRIO_MASK;
2303         control->int_ctl |= V_IRQ_MASK |
2304                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2305 }
2306
2307 static void svm_queue_irq(struct kvm_vcpu *vcpu, unsigned nr)
2308 {
2309         struct vcpu_svm *svm = to_svm(vcpu);
2310
2311         svm->vmcb->control.event_inj = nr |
2312                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2313 }
2314
2315 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2316 {
2317         struct vcpu_svm *svm = to_svm(vcpu);
2318
2319         nested_svm_intr(svm);
2320
2321         svm_queue_irq(vcpu, irq);
2322 }
2323
2324 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2325 {
2326         struct vcpu_svm *svm = to_svm(vcpu);
2327
2328         if (irr == -1)
2329                 return;
2330
2331         if (tpr >= irr)
2332                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2333 }
2334
2335 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2336 {
2337         struct vcpu_svm *svm = to_svm(vcpu);
2338         struct vmcb *vmcb = svm->vmcb;
2339         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2340                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2341 }
2342
2343 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2344 {
2345         struct vcpu_svm *svm = to_svm(vcpu);
2346         struct vmcb *vmcb = svm->vmcb;
2347         return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2348                 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2349                 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2350 }
2351
2352 static void enable_irq_window(struct kvm_vcpu *vcpu)
2353 {
2354         svm_set_vintr(to_svm(vcpu));
2355         svm_inject_irq(to_svm(vcpu), 0x0);
2356 }
2357
2358 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2359 {
2360         struct vcpu_svm *svm = to_svm(vcpu);
2361
2362         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
2363                 enable_irq_window(vcpu);
2364 }
2365
2366 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2367 {
2368         return 0;
2369 }
2370
2371 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2372 {
2373         force_new_asid(vcpu);
2374 }
2375
2376 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2377 {
2378 }
2379
2380 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2381 {
2382         struct vcpu_svm *svm = to_svm(vcpu);
2383
2384         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2385                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2386                 kvm_set_cr8(vcpu, cr8);
2387         }
2388 }
2389
2390 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2391 {
2392         struct vcpu_svm *svm = to_svm(vcpu);
2393         u64 cr8;
2394
2395         cr8 = kvm_get_cr8(vcpu);
2396         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2397         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2398 }
2399
2400 static void svm_complete_interrupts(struct vcpu_svm *svm)
2401 {
2402         u8 vector;
2403         int type;
2404         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2405
2406         svm->vcpu.arch.nmi_injected = false;
2407         kvm_clear_exception_queue(&svm->vcpu);
2408         kvm_clear_interrupt_queue(&svm->vcpu);
2409
2410         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2411                 return;
2412
2413         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2414         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2415
2416         switch (type) {
2417         case SVM_EXITINTINFO_TYPE_NMI:
2418                 svm->vcpu.arch.nmi_injected = true;
2419                 break;
2420         case SVM_EXITINTINFO_TYPE_EXEPT:
2421                 /* In case of software exception do not reinject an exception
2422                    vector, but re-execute and instruction instead */
2423                 if (vector == BP_VECTOR || vector == OF_VECTOR)
2424                         break;
2425                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2426                         u32 err = svm->vmcb->control.exit_int_info_err;
2427                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2428
2429                 } else
2430                         kvm_queue_exception(&svm->vcpu, vector);
2431                 break;
2432         case SVM_EXITINTINFO_TYPE_INTR:
2433                 kvm_queue_interrupt(&svm->vcpu, vector);
2434                 break;
2435         default:
2436                 break;
2437         }
2438 }
2439
2440 #ifdef CONFIG_X86_64
2441 #define R "r"
2442 #else
2443 #define R "e"
2444 #endif
2445
2446 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2447 {
2448         struct vcpu_svm *svm = to_svm(vcpu);
2449         u16 fs_selector;
2450         u16 gs_selector;
2451         u16 ldt_selector;
2452
2453         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2454         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2455         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2456
2457         pre_svm_run(svm);
2458
2459         sync_lapic_to_cr8(vcpu);
2460
2461         save_host_msrs(vcpu);
2462         fs_selector = kvm_read_fs();
2463         gs_selector = kvm_read_gs();
2464         ldt_selector = kvm_read_ldt();
2465         svm->host_cr2 = kvm_read_cr2();
2466         if (!is_nested(svm))
2467                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2468         /* required for live migration with NPT */
2469         if (npt_enabled)
2470                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2471
2472         clgi();
2473
2474         local_irq_enable();
2475
2476         asm volatile (
2477                 "push %%"R"bp; \n\t"
2478                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2479                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2480                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2481                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2482                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2483                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2484 #ifdef CONFIG_X86_64
2485                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2486                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2487                 "mov %c[r10](%[svm]), %%r10 \n\t"
2488                 "mov %c[r11](%[svm]), %%r11 \n\t"
2489                 "mov %c[r12](%[svm]), %%r12 \n\t"
2490                 "mov %c[r13](%[svm]), %%r13 \n\t"
2491                 "mov %c[r14](%[svm]), %%r14 \n\t"
2492                 "mov %c[r15](%[svm]), %%r15 \n\t"
2493 #endif
2494
2495                 /* Enter guest mode */
2496                 "push %%"R"ax \n\t"
2497                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2498                 __ex(SVM_VMLOAD) "\n\t"
2499                 __ex(SVM_VMRUN) "\n\t"
2500                 __ex(SVM_VMSAVE) "\n\t"
2501                 "pop %%"R"ax \n\t"
2502
2503                 /* Save guest registers, load host registers */
2504                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2505                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2506                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2507                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2508                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2509                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2510 #ifdef CONFIG_X86_64
2511                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2512                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2513                 "mov %%r10, %c[r10](%[svm]) \n\t"
2514                 "mov %%r11, %c[r11](%[svm]) \n\t"
2515                 "mov %%r12, %c[r12](%[svm]) \n\t"
2516                 "mov %%r13, %c[r13](%[svm]) \n\t"
2517                 "mov %%r14, %c[r14](%[svm]) \n\t"
2518                 "mov %%r15, %c[r15](%[svm]) \n\t"
2519 #endif
2520                 "pop %%"R"bp"
2521                 :
2522                 : [svm]"a"(svm),
2523                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2524                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2525                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2526                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2527                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2528                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2529                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2530 #ifdef CONFIG_X86_64
2531                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2532                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2533                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2534                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2535                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2536                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2537                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2538                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2539 #endif
2540                 : "cc", "memory"
2541                 , R"bx", R"cx", R"dx", R"si", R"di"
2542 #ifdef CONFIG_X86_64
2543                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2544 #endif
2545                 );
2546
2547         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2548         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2549         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2550         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2551
2552         kvm_write_cr2(svm->host_cr2);
2553
2554         kvm_load_fs(fs_selector);
2555         kvm_load_gs(gs_selector);
2556         kvm_load_ldt(ldt_selector);
2557         load_host_msrs(vcpu);
2558
2559         reload_tss(vcpu);
2560
2561         local_irq_disable();
2562
2563         stgi();
2564
2565         sync_cr8_to_lapic(vcpu);
2566
2567         svm->next_rip = 0;
2568
2569         svm_complete_interrupts(svm);
2570 }
2571
2572 #undef R
2573
2574 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2575 {
2576         struct vcpu_svm *svm = to_svm(vcpu);
2577
2578         if (npt_enabled) {
2579                 svm->vmcb->control.nested_cr3 = root;
2580                 force_new_asid(vcpu);
2581                 return;
2582         }
2583
2584         svm->vmcb->save.cr3 = root;
2585         force_new_asid(vcpu);
2586
2587         if (vcpu->fpu_active) {
2588                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2589                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2590                 vcpu->fpu_active = 0;
2591         }
2592 }
2593
2594 static int is_disabled(void)
2595 {
2596         u64 vm_cr;
2597
2598         rdmsrl(MSR_VM_CR, vm_cr);
2599         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2600                 return 1;
2601
2602         return 0;
2603 }
2604
2605 static void
2606 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2607 {
2608         /*
2609          * Patch in the VMMCALL instruction:
2610          */
2611         hypercall[0] = 0x0f;
2612         hypercall[1] = 0x01;
2613         hypercall[2] = 0xd9;
2614 }
2615
2616 static void svm_check_processor_compat(void *rtn)
2617 {
2618         *(int *)rtn = 0;
2619 }
2620
2621 static bool svm_cpu_has_accelerated_tpr(void)
2622 {
2623         return false;
2624 }
2625
2626 static int get_npt_level(void)
2627 {
2628 #ifdef CONFIG_X86_64
2629         return PT64_ROOT_LEVEL;
2630 #else
2631         return PT32E_ROOT_LEVEL;
2632 #endif
2633 }
2634
2635 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2636 {
2637         return 0;
2638 }
2639
2640 static struct kvm_x86_ops svm_x86_ops = {
2641         .cpu_has_kvm_support = has_svm,
2642         .disabled_by_bios = is_disabled,
2643         .hardware_setup = svm_hardware_setup,
2644         .hardware_unsetup = svm_hardware_unsetup,
2645         .check_processor_compatibility = svm_check_processor_compat,
2646         .hardware_enable = svm_hardware_enable,
2647         .hardware_disable = svm_hardware_disable,
2648         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2649
2650         .vcpu_create = svm_create_vcpu,
2651         .vcpu_free = svm_free_vcpu,
2652         .vcpu_reset = svm_vcpu_reset,
2653
2654         .prepare_guest_switch = svm_prepare_guest_switch,
2655         .vcpu_load = svm_vcpu_load,
2656         .vcpu_put = svm_vcpu_put,
2657
2658         .set_guest_debug = svm_guest_debug,
2659         .get_msr = svm_get_msr,
2660         .set_msr = svm_set_msr,
2661         .get_segment_base = svm_get_segment_base,
2662         .get_segment = svm_get_segment,
2663         .set_segment = svm_set_segment,
2664         .get_cpl = svm_get_cpl,
2665         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2666         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2667         .set_cr0 = svm_set_cr0,
2668         .set_cr3 = svm_set_cr3,
2669         .set_cr4 = svm_set_cr4,
2670         .set_efer = svm_set_efer,
2671         .get_idt = svm_get_idt,
2672         .set_idt = svm_set_idt,
2673         .get_gdt = svm_get_gdt,
2674         .set_gdt = svm_set_gdt,
2675         .get_dr = svm_get_dr,
2676         .set_dr = svm_set_dr,
2677         .get_rflags = svm_get_rflags,
2678         .set_rflags = svm_set_rflags,
2679
2680         .tlb_flush = svm_flush_tlb,
2681
2682         .run = svm_vcpu_run,
2683         .handle_exit = handle_exit,
2684         .skip_emulated_instruction = skip_emulated_instruction,
2685         .set_interrupt_shadow = svm_set_interrupt_shadow,
2686         .get_interrupt_shadow = svm_get_interrupt_shadow,
2687         .patch_hypercall = svm_patch_hypercall,
2688         .set_irq = svm_set_irq,
2689         .set_nmi = svm_inject_nmi,
2690         .queue_exception = svm_queue_exception,
2691         .interrupt_allowed = svm_interrupt_allowed,
2692         .nmi_allowed = svm_nmi_allowed,
2693         .enable_nmi_window = enable_nmi_window,
2694         .enable_irq_window = enable_irq_window,
2695         .update_cr8_intercept = update_cr8_intercept,
2696
2697         .set_tss_addr = svm_set_tss_addr,
2698         .get_tdp_level = get_npt_level,
2699         .get_mt_mask = svm_get_mt_mask,
2700 };
2701
2702 static int __init svm_init(void)
2703 {
2704         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2705                               THIS_MODULE);
2706 }
2707
2708 static void __exit svm_exit(void)
2709 {
2710         kvm_exit();
2711 }
2712
2713 module_init(svm_init)
2714 module_exit(svm_exit)