2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
20 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29 #include <linux/slab.h>
33 #include <asm/virtext.h>
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
41 #define IOPM_ALLOC_ORDER 2
42 #define MSRPM_ALLOC_ORDER 1
44 #define SEG_TYPE_LDT 2
45 #define SEG_TYPE_BUSY_TSS16 3
47 #define SVM_FEATURE_NPT (1 << 0)
48 #define SVM_FEATURE_LBRV (1 << 1)
49 #define SVM_FEATURE_SVML (1 << 2)
50 #define SVM_FEATURE_NRIP (1 << 3)
51 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
53 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
57 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
59 static const u32 host_save_user_msrs[] = {
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
67 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
77 /* These are the merged vectors */
80 /* gpa pointers to the real vectors */
83 /* A VMEXIT is required but not yet emulated */
86 /* cache for intercepts of the guest */
87 u16 intercept_cr_read;
88 u16 intercept_cr_write;
89 u16 intercept_dr_read;
90 u16 intercept_dr_write;
91 u32 intercept_exceptions;
96 #define MSRPM_OFFSETS 16
97 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
100 struct kvm_vcpu vcpu;
102 unsigned long vmcb_pa;
103 struct svm_cpu_data *svm_data;
104 uint64_t asid_generation;
105 uint64_t sysenter_esp;
106 uint64_t sysenter_eip;
110 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
115 struct nested_state nested;
119 unsigned int3_injected;
120 unsigned long int3_rip;
123 #define MSR_INVALID 0xffffffffU
125 static struct svm_direct_access_msrs {
126 u32 index; /* Index of the MSR */
127 bool always; /* True if intercept is always on */
128 } direct_access_msrs[] = {
129 { .index = MSR_K6_STAR, .always = true },
130 { .index = MSR_IA32_SYSENTER_CS, .always = true },
132 { .index = MSR_GS_BASE, .always = true },
133 { .index = MSR_FS_BASE, .always = true },
134 { .index = MSR_KERNEL_GS_BASE, .always = true },
135 { .index = MSR_LSTAR, .always = true },
136 { .index = MSR_CSTAR, .always = true },
137 { .index = MSR_SYSCALL_MASK, .always = true },
139 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
140 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
141 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
142 { .index = MSR_IA32_LASTINTTOIP, .always = false },
143 { .index = MSR_INVALID, .always = false },
146 /* enable NPT for AMD64 and X86 with PAE */
147 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
148 static bool npt_enabled = true;
150 static bool npt_enabled;
154 module_param(npt, int, S_IRUGO);
156 static int nested = 1;
157 module_param(nested, int, S_IRUGO);
159 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
160 static void svm_complete_interrupts(struct vcpu_svm *svm);
162 static int nested_svm_exit_handled(struct vcpu_svm *svm);
163 static int nested_svm_intercept(struct vcpu_svm *svm);
164 static int nested_svm_vmexit(struct vcpu_svm *svm);
165 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
166 bool has_error_code, u32 error_code);
168 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
170 return container_of(vcpu, struct vcpu_svm, vcpu);
173 static inline bool is_nested(struct vcpu_svm *svm)
175 return svm->nested.vmcb;
178 static inline void enable_gif(struct vcpu_svm *svm)
180 svm->vcpu.arch.hflags |= HF_GIF_MASK;
183 static inline void disable_gif(struct vcpu_svm *svm)
185 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
188 static inline bool gif_set(struct vcpu_svm *svm)
190 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
193 static unsigned long iopm_base;
195 struct kvm_ldttss_desc {
198 unsigned base1:8, type:5, dpl:2, p:1;
199 unsigned limit1:4, zero0:3, g:1, base2:8;
202 } __attribute__((packed));
204 struct svm_cpu_data {
210 struct kvm_ldttss_desc *tss_desc;
212 struct page *save_area;
215 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
216 static uint32_t svm_features;
218 struct svm_init_data {
223 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
225 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
226 #define MSRS_RANGE_SIZE 2048
227 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
229 static u32 svm_msrpm_offset(u32 msr)
234 for (i = 0; i < NUM_MSR_MAPS; i++) {
235 if (msr < msrpm_ranges[i] ||
236 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
239 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
240 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
242 /* Now we have the u8 offset - but need the u32 offset */
246 /* MSR not in any range */
250 #define MAX_INST_SIZE 15
252 static inline u32 svm_has(u32 feat)
254 return svm_features & feat;
257 static inline void clgi(void)
259 asm volatile (__ex(SVM_CLGI));
262 static inline void stgi(void)
264 asm volatile (__ex(SVM_STGI));
267 static inline void invlpga(unsigned long addr, u32 asid)
269 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
272 static inline void force_new_asid(struct kvm_vcpu *vcpu)
274 to_svm(vcpu)->asid_generation--;
277 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
279 force_new_asid(vcpu);
282 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
284 if (!npt_enabled && !(efer & EFER_LMA))
287 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
288 vcpu->arch.efer = efer;
291 static int is_external_interrupt(u32 info)
293 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
294 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
297 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
299 struct vcpu_svm *svm = to_svm(vcpu);
302 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
303 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
307 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
309 struct vcpu_svm *svm = to_svm(vcpu);
312 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
314 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
318 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
320 struct vcpu_svm *svm = to_svm(vcpu);
322 if (!svm->next_rip) {
323 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
325 printk(KERN_DEBUG "%s: NOP\n", __func__);
328 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
329 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
330 __func__, kvm_rip_read(vcpu), svm->next_rip);
332 kvm_rip_write(vcpu, svm->next_rip);
333 svm_set_interrupt_shadow(vcpu, 0);
336 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
337 bool has_error_code, u32 error_code)
339 struct vcpu_svm *svm = to_svm(vcpu);
342 * If we are within a nested VM we'd better #VMEXIT and let the guest
343 * handle the exception
345 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
348 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
349 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
352 * For guest debugging where we have to reinject #BP if some
353 * INT3 is guest-owned:
354 * Emulate nRIP by moving RIP forward. Will fail if injection
355 * raises a fault that is not intercepted. Still better than
356 * failing in all cases.
358 skip_emulated_instruction(&svm->vcpu);
359 rip = kvm_rip_read(&svm->vcpu);
360 svm->int3_rip = rip + svm->vmcb->save.cs.base;
361 svm->int3_injected = rip - old_rip;
364 svm->vmcb->control.event_inj = nr
366 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
367 | SVM_EVTINJ_TYPE_EXEPT;
368 svm->vmcb->control.event_inj_err = error_code;
371 static int has_svm(void)
375 if (!cpu_has_svm(&msg)) {
376 printk(KERN_INFO "has_svm: %s\n", msg);
383 static void svm_hardware_disable(void *garbage)
388 static int svm_hardware_enable(void *garbage)
391 struct svm_cpu_data *sd;
393 struct desc_ptr gdt_descr;
394 struct desc_struct *gdt;
395 int me = raw_smp_processor_id();
397 rdmsrl(MSR_EFER, efer);
398 if (efer & EFER_SVME)
402 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
406 sd = per_cpu(svm_data, me);
409 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
414 sd->asid_generation = 1;
415 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
416 sd->next_asid = sd->max_asid + 1;
418 native_store_gdt(&gdt_descr);
419 gdt = (struct desc_struct *)gdt_descr.address;
420 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
422 wrmsrl(MSR_EFER, efer | EFER_SVME);
424 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
429 static void svm_cpu_uninit(int cpu)
431 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
436 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
437 __free_page(sd->save_area);
441 static int svm_cpu_init(int cpu)
443 struct svm_cpu_data *sd;
446 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
450 sd->save_area = alloc_page(GFP_KERNEL);
455 per_cpu(svm_data, cpu) = sd;
465 static bool valid_msr_intercept(u32 index)
469 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
470 if (direct_access_msrs[i].index == index)
476 static void set_msr_interception(u32 *msrpm, unsigned msr,
479 u8 bit_read, bit_write;
484 * If this warning triggers extend the direct_access_msrs list at the
485 * beginning of the file
487 WARN_ON(!valid_msr_intercept(msr));
489 offset = svm_msrpm_offset(msr);
490 bit_read = 2 * (msr & 0x0f);
491 bit_write = 2 * (msr & 0x0f) + 1;
494 BUG_ON(offset == MSR_INVALID);
496 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
497 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
502 static void svm_vcpu_init_msrpm(u32 *msrpm)
506 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
508 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
509 if (!direct_access_msrs[i].always)
512 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
516 static void add_msr_offset(u32 offset)
520 for (i = 0; i < MSRPM_OFFSETS; ++i) {
522 /* Offset already in list? */
523 if (msrpm_offsets[i] == offset)
526 /* Slot used by another offset? */
527 if (msrpm_offsets[i] != MSR_INVALID)
530 /* Add offset to list */
531 msrpm_offsets[i] = offset;
537 * If this BUG triggers the msrpm_offsets table has an overflow. Just
538 * increase MSRPM_OFFSETS in this case.
543 static void init_msrpm_offsets(void)
547 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
549 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
552 offset = svm_msrpm_offset(direct_access_msrs[i].index);
553 BUG_ON(offset == MSR_INVALID);
555 add_msr_offset(offset);
559 static void svm_enable_lbrv(struct vcpu_svm *svm)
561 u32 *msrpm = svm->msrpm;
563 svm->vmcb->control.lbr_ctl = 1;
564 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
565 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
566 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
567 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
570 static void svm_disable_lbrv(struct vcpu_svm *svm)
572 u32 *msrpm = svm->msrpm;
574 svm->vmcb->control.lbr_ctl = 0;
575 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
576 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
577 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
578 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
581 static __init int svm_hardware_setup(void)
584 struct page *iopm_pages;
588 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
593 iopm_va = page_address(iopm_pages);
594 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
595 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
597 init_msrpm_offsets();
599 if (boot_cpu_has(X86_FEATURE_NX))
600 kvm_enable_efer_bits(EFER_NX);
602 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
603 kvm_enable_efer_bits(EFER_FFXSR);
606 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
607 kvm_enable_efer_bits(EFER_SVME);
610 for_each_possible_cpu(cpu) {
611 r = svm_cpu_init(cpu);
616 svm_features = cpuid_edx(SVM_CPUID_FUNC);
618 if (!svm_has(SVM_FEATURE_NPT))
621 if (npt_enabled && !npt) {
622 printk(KERN_INFO "kvm: Nested Paging disabled\n");
627 printk(KERN_INFO "kvm: Nested Paging enabled\n");
635 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
640 static __exit void svm_hardware_unsetup(void)
644 for_each_possible_cpu(cpu)
647 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
651 static void init_seg(struct vmcb_seg *seg)
654 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
655 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
660 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
663 seg->attrib = SVM_SELECTOR_P_MASK | type;
668 static void init_vmcb(struct vcpu_svm *svm)
670 struct vmcb_control_area *control = &svm->vmcb->control;
671 struct vmcb_save_area *save = &svm->vmcb->save;
673 svm->vcpu.fpu_active = 1;
675 control->intercept_cr_read = INTERCEPT_CR0_MASK |
679 control->intercept_cr_write = INTERCEPT_CR0_MASK |
684 control->intercept_dr_read = INTERCEPT_DR0_MASK |
693 control->intercept_dr_write = INTERCEPT_DR0_MASK |
702 control->intercept_exceptions = (1 << PF_VECTOR) |
707 control->intercept = (1ULL << INTERCEPT_INTR) |
708 (1ULL << INTERCEPT_NMI) |
709 (1ULL << INTERCEPT_SMI) |
710 (1ULL << INTERCEPT_SELECTIVE_CR0) |
711 (1ULL << INTERCEPT_CPUID) |
712 (1ULL << INTERCEPT_INVD) |
713 (1ULL << INTERCEPT_HLT) |
714 (1ULL << INTERCEPT_INVLPG) |
715 (1ULL << INTERCEPT_INVLPGA) |
716 (1ULL << INTERCEPT_IOIO_PROT) |
717 (1ULL << INTERCEPT_MSR_PROT) |
718 (1ULL << INTERCEPT_TASK_SWITCH) |
719 (1ULL << INTERCEPT_SHUTDOWN) |
720 (1ULL << INTERCEPT_VMRUN) |
721 (1ULL << INTERCEPT_VMMCALL) |
722 (1ULL << INTERCEPT_VMLOAD) |
723 (1ULL << INTERCEPT_VMSAVE) |
724 (1ULL << INTERCEPT_STGI) |
725 (1ULL << INTERCEPT_CLGI) |
726 (1ULL << INTERCEPT_SKINIT) |
727 (1ULL << INTERCEPT_WBINVD) |
728 (1ULL << INTERCEPT_MONITOR) |
729 (1ULL << INTERCEPT_MWAIT);
731 control->iopm_base_pa = iopm_base;
732 control->msrpm_base_pa = __pa(svm->msrpm);
733 control->tsc_offset = 0;
734 control->int_ctl = V_INTR_MASKING_MASK;
742 save->cs.selector = 0xf000;
743 /* Executable/Readable Code Segment */
744 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
745 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
746 save->cs.limit = 0xffff;
748 * cs.base should really be 0xffff0000, but vmx can't handle that, so
749 * be consistent with it.
751 * Replace when we have real mode working for vmx.
753 save->cs.base = 0xf0000;
755 save->gdtr.limit = 0xffff;
756 save->idtr.limit = 0xffff;
758 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
759 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
761 save->efer = EFER_SVME;
762 save->dr6 = 0xffff0ff0;
765 save->rip = 0x0000fff0;
766 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
769 * This is the guest-visible cr0 value.
770 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
772 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
773 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
775 save->cr4 = X86_CR4_PAE;
779 /* Setup VMCB for Nested Paging */
780 control->nested_ctl = 1;
781 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
782 (1ULL << INTERCEPT_INVLPG));
783 control->intercept_exceptions &= ~(1 << PF_VECTOR);
784 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
785 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
786 save->g_pat = 0x0007040600070406ULL;
790 force_new_asid(&svm->vcpu);
792 svm->nested.vmcb = 0;
793 svm->vcpu.arch.hflags = 0;
795 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
796 control->pause_filter_count = 3000;
797 control->intercept |= (1ULL << INTERCEPT_PAUSE);
803 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
805 struct vcpu_svm *svm = to_svm(vcpu);
809 if (!kvm_vcpu_is_bsp(vcpu)) {
810 kvm_rip_write(vcpu, 0);
811 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
812 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
814 vcpu->arch.regs_avail = ~0;
815 vcpu->arch.regs_dirty = ~0;
820 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
822 struct vcpu_svm *svm;
824 struct page *msrpm_pages;
825 struct page *hsave_page;
826 struct page *nested_msrpm_pages;
829 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
835 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
840 page = alloc_page(GFP_KERNEL);
844 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
848 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
849 if (!nested_msrpm_pages)
852 hsave_page = alloc_page(GFP_KERNEL);
856 svm->nested.hsave = page_address(hsave_page);
858 svm->msrpm = page_address(msrpm_pages);
859 svm_vcpu_init_msrpm(svm->msrpm);
861 svm->nested.msrpm = page_address(nested_msrpm_pages);
862 svm_vcpu_init_msrpm(svm->nested.msrpm);
864 svm->vmcb = page_address(page);
865 clear_page(svm->vmcb);
866 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
867 svm->asid_generation = 0;
871 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
872 if (kvm_vcpu_is_bsp(&svm->vcpu))
873 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
878 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
880 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
884 kvm_vcpu_uninit(&svm->vcpu);
886 kmem_cache_free(kvm_vcpu_cache, svm);
891 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
893 struct vcpu_svm *svm = to_svm(vcpu);
895 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
896 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
897 __free_page(virt_to_page(svm->nested.hsave));
898 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
899 kvm_vcpu_uninit(vcpu);
900 kmem_cache_free(kvm_vcpu_cache, svm);
903 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
905 struct vcpu_svm *svm = to_svm(vcpu);
908 if (unlikely(cpu != vcpu->cpu)) {
911 if (check_tsc_unstable()) {
913 * Make sure that the guest sees a monotonically
916 delta = vcpu->arch.host_tsc - native_read_tsc();
917 svm->vmcb->control.tsc_offset += delta;
919 svm->nested.hsave->control.tsc_offset += delta;
922 kvm_migrate_timers(vcpu);
923 svm->asid_generation = 0;
926 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
927 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
930 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
932 struct vcpu_svm *svm = to_svm(vcpu);
935 ++vcpu->stat.host_state_reload;
936 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
937 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
939 vcpu->arch.host_tsc = native_read_tsc();
942 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
944 return to_svm(vcpu)->vmcb->save.rflags;
947 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
949 to_svm(vcpu)->vmcb->save.rflags = rflags;
952 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
955 case VCPU_EXREG_PDPTR:
956 BUG_ON(!npt_enabled);
957 load_pdptrs(vcpu, vcpu->arch.cr3);
964 static void svm_set_vintr(struct vcpu_svm *svm)
966 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
969 static void svm_clear_vintr(struct vcpu_svm *svm)
971 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
974 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
976 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
979 case VCPU_SREG_CS: return &save->cs;
980 case VCPU_SREG_DS: return &save->ds;
981 case VCPU_SREG_ES: return &save->es;
982 case VCPU_SREG_FS: return &save->fs;
983 case VCPU_SREG_GS: return &save->gs;
984 case VCPU_SREG_SS: return &save->ss;
985 case VCPU_SREG_TR: return &save->tr;
986 case VCPU_SREG_LDTR: return &save->ldtr;
992 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
994 struct vmcb_seg *s = svm_seg(vcpu, seg);
999 static void svm_get_segment(struct kvm_vcpu *vcpu,
1000 struct kvm_segment *var, int seg)
1002 struct vmcb_seg *s = svm_seg(vcpu, seg);
1004 var->base = s->base;
1005 var->limit = s->limit;
1006 var->selector = s->selector;
1007 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1008 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1009 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1010 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1011 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1012 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1013 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1014 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1017 * AMD's VMCB does not have an explicit unusable field, so emulate it
1018 * for cross vendor migration purposes by "not present"
1020 var->unusable = !var->present || (var->type == 0);
1025 * SVM always stores 0 for the 'G' bit in the CS selector in
1026 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1027 * Intel's VMENTRY has a check on the 'G' bit.
1029 var->g = s->limit > 0xfffff;
1033 * Work around a bug where the busy flag in the tr selector
1043 * The accessed bit must always be set in the segment
1044 * descriptor cache, although it can be cleared in the
1045 * descriptor, the cached bit always remains at 1. Since
1046 * Intel has a check on this, set it here to support
1047 * cross-vendor migration.
1054 * On AMD CPUs sometimes the DB bit in the segment
1055 * descriptor is left as 1, although the whole segment has
1056 * been made unusable. Clear it here to pass an Intel VMX
1057 * entry check when cross vendor migrating.
1065 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1067 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1072 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1074 struct vcpu_svm *svm = to_svm(vcpu);
1076 dt->size = svm->vmcb->save.idtr.limit;
1077 dt->address = svm->vmcb->save.idtr.base;
1080 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1082 struct vcpu_svm *svm = to_svm(vcpu);
1084 svm->vmcb->save.idtr.limit = dt->size;
1085 svm->vmcb->save.idtr.base = dt->address ;
1088 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1090 struct vcpu_svm *svm = to_svm(vcpu);
1092 dt->size = svm->vmcb->save.gdtr.limit;
1093 dt->address = svm->vmcb->save.gdtr.base;
1096 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1098 struct vcpu_svm *svm = to_svm(vcpu);
1100 svm->vmcb->save.gdtr.limit = dt->size;
1101 svm->vmcb->save.gdtr.base = dt->address ;
1104 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1108 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1112 static void update_cr0_intercept(struct vcpu_svm *svm)
1114 struct vmcb *vmcb = svm->vmcb;
1115 ulong gcr0 = svm->vcpu.arch.cr0;
1116 u64 *hcr0 = &svm->vmcb->save.cr0;
1118 if (!svm->vcpu.fpu_active)
1119 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1121 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1122 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1125 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1126 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1127 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1128 if (is_nested(svm)) {
1129 struct vmcb *hsave = svm->nested.hsave;
1131 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1132 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1133 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1134 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1137 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1138 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1139 if (is_nested(svm)) {
1140 struct vmcb *hsave = svm->nested.hsave;
1142 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1143 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1148 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1150 struct vcpu_svm *svm = to_svm(vcpu);
1152 if (is_nested(svm)) {
1154 * We are here because we run in nested mode, the host kvm
1155 * intercepts cr0 writes but the l1 hypervisor does not.
1156 * But the L1 hypervisor may intercept selective cr0 writes.
1157 * This needs to be checked here.
1159 unsigned long old, new;
1161 /* Remove bits that would trigger a real cr0 write intercept */
1162 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1163 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1166 /* cr0 write with ts and mp unchanged */
1167 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1168 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1173 #ifdef CONFIG_X86_64
1174 if (vcpu->arch.efer & EFER_LME) {
1175 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1176 vcpu->arch.efer |= EFER_LMA;
1177 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1180 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1181 vcpu->arch.efer &= ~EFER_LMA;
1182 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1186 vcpu->arch.cr0 = cr0;
1189 cr0 |= X86_CR0_PG | X86_CR0_WP;
1191 if (!vcpu->fpu_active)
1194 * re-enable caching here because the QEMU bios
1195 * does not do it - this results in some delay at
1198 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1199 svm->vmcb->save.cr0 = cr0;
1200 update_cr0_intercept(svm);
1203 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1205 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1206 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1208 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1209 force_new_asid(vcpu);
1211 vcpu->arch.cr4 = cr4;
1214 cr4 |= host_cr4_mce;
1215 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1218 static void svm_set_segment(struct kvm_vcpu *vcpu,
1219 struct kvm_segment *var, int seg)
1221 struct vcpu_svm *svm = to_svm(vcpu);
1222 struct vmcb_seg *s = svm_seg(vcpu, seg);
1224 s->base = var->base;
1225 s->limit = var->limit;
1226 s->selector = var->selector;
1230 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1231 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1232 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1233 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1234 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1235 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1236 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1237 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1239 if (seg == VCPU_SREG_CS)
1241 = (svm->vmcb->save.cs.attrib
1242 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1246 static void update_db_intercept(struct kvm_vcpu *vcpu)
1248 struct vcpu_svm *svm = to_svm(vcpu);
1250 svm->vmcb->control.intercept_exceptions &=
1251 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1253 if (svm->nmi_singlestep)
1254 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1256 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1257 if (vcpu->guest_debug &
1258 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1259 svm->vmcb->control.intercept_exceptions |=
1261 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1262 svm->vmcb->control.intercept_exceptions |=
1265 vcpu->guest_debug = 0;
1268 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1270 struct vcpu_svm *svm = to_svm(vcpu);
1272 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1273 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1275 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1277 update_db_intercept(vcpu);
1280 static void load_host_msrs(struct kvm_vcpu *vcpu)
1282 #ifdef CONFIG_X86_64
1283 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1287 static void save_host_msrs(struct kvm_vcpu *vcpu)
1289 #ifdef CONFIG_X86_64
1290 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1294 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1296 if (sd->next_asid > sd->max_asid) {
1297 ++sd->asid_generation;
1299 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1302 svm->asid_generation = sd->asid_generation;
1303 svm->vmcb->control.asid = sd->next_asid++;
1306 static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
1308 struct vcpu_svm *svm = to_svm(vcpu);
1312 *dest = vcpu->arch.db[dr];
1315 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1316 return EMULATE_FAIL; /* will re-inject UD */
1319 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1320 *dest = vcpu->arch.dr6;
1322 *dest = svm->vmcb->save.dr6;
1325 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1326 return EMULATE_FAIL; /* will re-inject UD */
1329 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1330 *dest = vcpu->arch.dr7;
1332 *dest = svm->vmcb->save.dr7;
1336 return EMULATE_DONE;
1339 static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
1341 struct vcpu_svm *svm = to_svm(vcpu);
1345 vcpu->arch.db[dr] = value;
1346 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1347 vcpu->arch.eff_db[dr] = value;
1350 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1351 return EMULATE_FAIL; /* will re-inject UD */
1354 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1357 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1358 return EMULATE_FAIL; /* will re-inject UD */
1361 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1362 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1363 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1364 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1369 return EMULATE_DONE;
1372 static int pf_interception(struct vcpu_svm *svm)
1377 fault_address = svm->vmcb->control.exit_info_2;
1378 error_code = svm->vmcb->control.exit_info_1;
1380 trace_kvm_page_fault(fault_address, error_code);
1381 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1382 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1383 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1386 static int db_interception(struct vcpu_svm *svm)
1388 struct kvm_run *kvm_run = svm->vcpu.run;
1390 if (!(svm->vcpu.guest_debug &
1391 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1392 !svm->nmi_singlestep) {
1393 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1397 if (svm->nmi_singlestep) {
1398 svm->nmi_singlestep = false;
1399 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1400 svm->vmcb->save.rflags &=
1401 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1402 update_db_intercept(&svm->vcpu);
1405 if (svm->vcpu.guest_debug &
1406 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1407 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1408 kvm_run->debug.arch.pc =
1409 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1410 kvm_run->debug.arch.exception = DB_VECTOR;
1417 static int bp_interception(struct vcpu_svm *svm)
1419 struct kvm_run *kvm_run = svm->vcpu.run;
1421 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1422 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1423 kvm_run->debug.arch.exception = BP_VECTOR;
1427 static int ud_interception(struct vcpu_svm *svm)
1431 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1432 if (er != EMULATE_DONE)
1433 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1437 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1439 struct vcpu_svm *svm = to_svm(vcpu);
1442 if (is_nested(svm)) {
1445 h_excp = svm->nested.hsave->control.intercept_exceptions;
1446 n_excp = svm->nested.intercept_exceptions;
1447 h_excp &= ~(1 << NM_VECTOR);
1448 excp = h_excp | n_excp;
1450 excp = svm->vmcb->control.intercept_exceptions;
1451 excp &= ~(1 << NM_VECTOR);
1454 svm->vmcb->control.intercept_exceptions = excp;
1456 svm->vcpu.fpu_active = 1;
1457 update_cr0_intercept(svm);
1460 static int nm_interception(struct vcpu_svm *svm)
1462 svm_fpu_activate(&svm->vcpu);
1466 static int mc_interception(struct vcpu_svm *svm)
1469 * On an #MC intercept the MCE handler is not called automatically in
1470 * the host. So do it by hand here.
1474 /* not sure if we ever come back to this point */
1479 static int shutdown_interception(struct vcpu_svm *svm)
1481 struct kvm_run *kvm_run = svm->vcpu.run;
1484 * VMCB is undefined after a SHUTDOWN intercept
1485 * so reinitialize it.
1487 clear_page(svm->vmcb);
1490 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1494 static int io_interception(struct vcpu_svm *svm)
1496 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1497 int size, in, string;
1500 ++svm->vcpu.stat.io_exits;
1502 svm->next_rip = svm->vmcb->control.exit_info_2;
1504 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1507 if (emulate_instruction(&svm->vcpu,
1508 0, 0, 0) == EMULATE_DO_MMIO)
1513 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1514 port = io_info >> 16;
1515 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1517 skip_emulated_instruction(&svm->vcpu);
1518 return kvm_emulate_pio(&svm->vcpu, in, size, port);
1521 static int nmi_interception(struct vcpu_svm *svm)
1526 static int intr_interception(struct vcpu_svm *svm)
1528 ++svm->vcpu.stat.irq_exits;
1532 static int nop_on_interception(struct vcpu_svm *svm)
1537 static int halt_interception(struct vcpu_svm *svm)
1539 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1540 skip_emulated_instruction(&svm->vcpu);
1541 return kvm_emulate_halt(&svm->vcpu);
1544 static int vmmcall_interception(struct vcpu_svm *svm)
1546 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1547 skip_emulated_instruction(&svm->vcpu);
1548 kvm_emulate_hypercall(&svm->vcpu);
1552 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1554 if (!(svm->vcpu.arch.efer & EFER_SVME)
1555 || !is_paging(&svm->vcpu)) {
1556 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1560 if (svm->vmcb->save.cpl) {
1561 kvm_inject_gp(&svm->vcpu, 0);
1568 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1569 bool has_error_code, u32 error_code)
1573 if (!is_nested(svm))
1576 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1577 svm->vmcb->control.exit_code_hi = 0;
1578 svm->vmcb->control.exit_info_1 = error_code;
1579 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1581 vmexit = nested_svm_intercept(svm);
1582 if (vmexit == NESTED_EXIT_DONE)
1583 svm->nested.exit_required = true;
1588 /* This function returns true if it is save to enable the irq window */
1589 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1591 if (!is_nested(svm))
1594 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1597 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1600 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1601 svm->vmcb->control.exit_info_1 = 0;
1602 svm->vmcb->control.exit_info_2 = 0;
1604 if (svm->nested.intercept & 1ULL) {
1606 * The #vmexit can't be emulated here directly because this
1607 * code path runs with irqs and preemtion disabled. A
1608 * #vmexit emulation might sleep. Only signal request for
1611 svm->nested.exit_required = true;
1612 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1619 /* This function returns true if it is save to enable the nmi window */
1620 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1622 if (!is_nested(svm))
1625 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1628 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1629 svm->nested.exit_required = true;
1634 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1640 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1641 if (is_error_page(page))
1649 kvm_release_page_clean(page);
1650 kvm_inject_gp(&svm->vcpu, 0);
1655 static void nested_svm_unmap(struct page *page)
1658 kvm_release_page_dirty(page);
1661 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1663 u32 offset, msr, value;
1666 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1667 return NESTED_EXIT_HOST;
1669 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1670 offset = svm_msrpm_offset(msr);
1671 write = svm->vmcb->control.exit_info_1 & 1;
1672 mask = 1 << ((2 * (msr & 0xf)) + write);
1674 if (offset == MSR_INVALID)
1675 return NESTED_EXIT_DONE;
1677 /* Offset is in 32 bit units but need in 8 bit units */
1680 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1681 return NESTED_EXIT_DONE;
1683 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1686 static int nested_svm_exit_special(struct vcpu_svm *svm)
1688 u32 exit_code = svm->vmcb->control.exit_code;
1690 switch (exit_code) {
1693 return NESTED_EXIT_HOST;
1695 /* For now we are always handling NPFs when using them */
1697 return NESTED_EXIT_HOST;
1699 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1700 /* When we're shadowing, trap PFs */
1702 return NESTED_EXIT_HOST;
1704 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1705 nm_interception(svm);
1711 return NESTED_EXIT_CONTINUE;
1715 * If this function returns true, this #vmexit was already handled
1717 static int nested_svm_intercept(struct vcpu_svm *svm)
1719 u32 exit_code = svm->vmcb->control.exit_code;
1720 int vmexit = NESTED_EXIT_HOST;
1722 switch (exit_code) {
1724 vmexit = nested_svm_exit_handled_msr(svm);
1726 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1727 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1728 if (svm->nested.intercept_cr_read & cr_bits)
1729 vmexit = NESTED_EXIT_DONE;
1732 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1733 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1734 if (svm->nested.intercept_cr_write & cr_bits)
1735 vmexit = NESTED_EXIT_DONE;
1738 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1739 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1740 if (svm->nested.intercept_dr_read & dr_bits)
1741 vmexit = NESTED_EXIT_DONE;
1744 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1745 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1746 if (svm->nested.intercept_dr_write & dr_bits)
1747 vmexit = NESTED_EXIT_DONE;
1750 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1751 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1752 if (svm->nested.intercept_exceptions & excp_bits)
1753 vmexit = NESTED_EXIT_DONE;
1757 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1758 if (svm->nested.intercept & exit_bits)
1759 vmexit = NESTED_EXIT_DONE;
1766 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1770 vmexit = nested_svm_intercept(svm);
1772 if (vmexit == NESTED_EXIT_DONE)
1773 nested_svm_vmexit(svm);
1778 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1780 struct vmcb_control_area *dst = &dst_vmcb->control;
1781 struct vmcb_control_area *from = &from_vmcb->control;
1783 dst->intercept_cr_read = from->intercept_cr_read;
1784 dst->intercept_cr_write = from->intercept_cr_write;
1785 dst->intercept_dr_read = from->intercept_dr_read;
1786 dst->intercept_dr_write = from->intercept_dr_write;
1787 dst->intercept_exceptions = from->intercept_exceptions;
1788 dst->intercept = from->intercept;
1789 dst->iopm_base_pa = from->iopm_base_pa;
1790 dst->msrpm_base_pa = from->msrpm_base_pa;
1791 dst->tsc_offset = from->tsc_offset;
1792 dst->asid = from->asid;
1793 dst->tlb_ctl = from->tlb_ctl;
1794 dst->int_ctl = from->int_ctl;
1795 dst->int_vector = from->int_vector;
1796 dst->int_state = from->int_state;
1797 dst->exit_code = from->exit_code;
1798 dst->exit_code_hi = from->exit_code_hi;
1799 dst->exit_info_1 = from->exit_info_1;
1800 dst->exit_info_2 = from->exit_info_2;
1801 dst->exit_int_info = from->exit_int_info;
1802 dst->exit_int_info_err = from->exit_int_info_err;
1803 dst->nested_ctl = from->nested_ctl;
1804 dst->event_inj = from->event_inj;
1805 dst->event_inj_err = from->event_inj_err;
1806 dst->nested_cr3 = from->nested_cr3;
1807 dst->lbr_ctl = from->lbr_ctl;
1810 static int nested_svm_vmexit(struct vcpu_svm *svm)
1812 struct vmcb *nested_vmcb;
1813 struct vmcb *hsave = svm->nested.hsave;
1814 struct vmcb *vmcb = svm->vmcb;
1817 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1818 vmcb->control.exit_info_1,
1819 vmcb->control.exit_info_2,
1820 vmcb->control.exit_int_info,
1821 vmcb->control.exit_int_info_err);
1823 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1827 /* Exit nested SVM mode */
1828 svm->nested.vmcb = 0;
1830 /* Give the current vmcb to the guest */
1833 nested_vmcb->save.es = vmcb->save.es;
1834 nested_vmcb->save.cs = vmcb->save.cs;
1835 nested_vmcb->save.ss = vmcb->save.ss;
1836 nested_vmcb->save.ds = vmcb->save.ds;
1837 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1838 nested_vmcb->save.idtr = vmcb->save.idtr;
1839 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
1841 nested_vmcb->save.cr3 = vmcb->save.cr3;
1843 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
1844 nested_vmcb->save.cr2 = vmcb->save.cr2;
1845 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
1846 nested_vmcb->save.rflags = vmcb->save.rflags;
1847 nested_vmcb->save.rip = vmcb->save.rip;
1848 nested_vmcb->save.rsp = vmcb->save.rsp;
1849 nested_vmcb->save.rax = vmcb->save.rax;
1850 nested_vmcb->save.dr7 = vmcb->save.dr7;
1851 nested_vmcb->save.dr6 = vmcb->save.dr6;
1852 nested_vmcb->save.cpl = vmcb->save.cpl;
1854 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1855 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1856 nested_vmcb->control.int_state = vmcb->control.int_state;
1857 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1858 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1859 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1860 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1861 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1862 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1865 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1866 * to make sure that we do not lose injected events. So check event_inj
1867 * here and copy it to exit_int_info if it is valid.
1868 * Exit_int_info and event_inj can't be both valid because the case
1869 * below only happens on a VMRUN instruction intercept which has
1870 * no valid exit_int_info set.
1872 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1873 struct vmcb_control_area *nc = &nested_vmcb->control;
1875 nc->exit_int_info = vmcb->control.event_inj;
1876 nc->exit_int_info_err = vmcb->control.event_inj_err;
1879 nested_vmcb->control.tlb_ctl = 0;
1880 nested_vmcb->control.event_inj = 0;
1881 nested_vmcb->control.event_inj_err = 0;
1883 /* We always set V_INTR_MASKING and remember the old value in hflags */
1884 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1885 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1887 /* Restore the original control entries */
1888 copy_vmcb_control_area(vmcb, hsave);
1890 kvm_clear_exception_queue(&svm->vcpu);
1891 kvm_clear_interrupt_queue(&svm->vcpu);
1893 /* Restore selected save entries */
1894 svm->vmcb->save.es = hsave->save.es;
1895 svm->vmcb->save.cs = hsave->save.cs;
1896 svm->vmcb->save.ss = hsave->save.ss;
1897 svm->vmcb->save.ds = hsave->save.ds;
1898 svm->vmcb->save.gdtr = hsave->save.gdtr;
1899 svm->vmcb->save.idtr = hsave->save.idtr;
1900 svm->vmcb->save.rflags = hsave->save.rflags;
1901 svm_set_efer(&svm->vcpu, hsave->save.efer);
1902 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1903 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1905 svm->vmcb->save.cr3 = hsave->save.cr3;
1906 svm->vcpu.arch.cr3 = hsave->save.cr3;
1908 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1910 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1911 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1912 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1913 svm->vmcb->save.dr7 = 0;
1914 svm->vmcb->save.cpl = 0;
1915 svm->vmcb->control.exit_int_info = 0;
1917 nested_svm_unmap(page);
1919 kvm_mmu_reset_context(&svm->vcpu);
1920 kvm_mmu_load(&svm->vcpu);
1925 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1928 * This function merges the msr permission bitmaps of kvm and the
1929 * nested vmcb. It is omptimized in that it only merges the parts where
1930 * the kvm msr permission bitmap may contain zero bits
1934 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1937 for (i = 0; i < MSRPM_OFFSETS; i++) {
1941 if (msrpm_offsets[i] == 0xffffffff)
1944 p = msrpm_offsets[i];
1945 offset = svm->nested.vmcb_msrpm + (p * 4);
1947 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
1950 svm->nested.msrpm[p] = svm->msrpm[p] | value;
1953 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1958 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1960 struct vmcb *nested_vmcb;
1961 struct vmcb *hsave = svm->nested.hsave;
1962 struct vmcb *vmcb = svm->vmcb;
1966 vmcb_gpa = svm->vmcb->save.rax;
1968 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1972 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
1973 nested_vmcb->save.rip,
1974 nested_vmcb->control.int_ctl,
1975 nested_vmcb->control.event_inj,
1976 nested_vmcb->control.nested_ctl);
1978 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
1979 nested_vmcb->control.intercept_cr_write,
1980 nested_vmcb->control.intercept_exceptions,
1981 nested_vmcb->control.intercept);
1983 /* Clear internal status */
1984 kvm_clear_exception_queue(&svm->vcpu);
1985 kvm_clear_interrupt_queue(&svm->vcpu);
1988 * Save the old vmcb, so we don't need to pick what we save, but can
1989 * restore everything when a VMEXIT occurs
1991 hsave->save.es = vmcb->save.es;
1992 hsave->save.cs = vmcb->save.cs;
1993 hsave->save.ss = vmcb->save.ss;
1994 hsave->save.ds = vmcb->save.ds;
1995 hsave->save.gdtr = vmcb->save.gdtr;
1996 hsave->save.idtr = vmcb->save.idtr;
1997 hsave->save.efer = svm->vcpu.arch.efer;
1998 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
1999 hsave->save.cr4 = svm->vcpu.arch.cr4;
2000 hsave->save.rflags = vmcb->save.rflags;
2001 hsave->save.rip = svm->next_rip;
2002 hsave->save.rsp = vmcb->save.rsp;
2003 hsave->save.rax = vmcb->save.rax;
2005 hsave->save.cr3 = vmcb->save.cr3;
2007 hsave->save.cr3 = svm->vcpu.arch.cr3;
2009 copy_vmcb_control_area(hsave, vmcb);
2011 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2012 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2014 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2016 /* Load the nested guest state */
2017 svm->vmcb->save.es = nested_vmcb->save.es;
2018 svm->vmcb->save.cs = nested_vmcb->save.cs;
2019 svm->vmcb->save.ss = nested_vmcb->save.ss;
2020 svm->vmcb->save.ds = nested_vmcb->save.ds;
2021 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2022 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2023 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2024 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2025 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2026 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2028 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2029 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2031 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2033 /* Guest paging mode is active - reset mmu */
2034 kvm_mmu_reset_context(&svm->vcpu);
2036 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2037 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2038 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2039 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2041 /* In case we don't even reach vcpu_run, the fields are not updated */
2042 svm->vmcb->save.rax = nested_vmcb->save.rax;
2043 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2044 svm->vmcb->save.rip = nested_vmcb->save.rip;
2045 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2046 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2047 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2049 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
2051 /* cache intercepts */
2052 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2053 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2054 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2055 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2056 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2057 svm->nested.intercept = nested_vmcb->control.intercept;
2059 force_new_asid(&svm->vcpu);
2060 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2061 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2062 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2064 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2066 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2067 /* We only want the cr8 intercept bits of the guest */
2068 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2069 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2073 * We don't want a nested guest to be more powerful than the guest, so
2074 * all intercepts are ORed
2076 svm->vmcb->control.intercept_cr_read |=
2077 nested_vmcb->control.intercept_cr_read;
2078 svm->vmcb->control.intercept_cr_write |=
2079 nested_vmcb->control.intercept_cr_write;
2080 svm->vmcb->control.intercept_dr_read |=
2081 nested_vmcb->control.intercept_dr_read;
2082 svm->vmcb->control.intercept_dr_write |=
2083 nested_vmcb->control.intercept_dr_write;
2084 svm->vmcb->control.intercept_exceptions |=
2085 nested_vmcb->control.intercept_exceptions;
2087 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2089 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2090 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2091 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2092 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2093 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2094 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2096 nested_svm_unmap(page);
2098 /* nested_vmcb is our indicator if nested SVM is activated */
2099 svm->nested.vmcb = vmcb_gpa;
2106 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2108 to_vmcb->save.fs = from_vmcb->save.fs;
2109 to_vmcb->save.gs = from_vmcb->save.gs;
2110 to_vmcb->save.tr = from_vmcb->save.tr;
2111 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2112 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2113 to_vmcb->save.star = from_vmcb->save.star;
2114 to_vmcb->save.lstar = from_vmcb->save.lstar;
2115 to_vmcb->save.cstar = from_vmcb->save.cstar;
2116 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2117 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2118 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2119 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2122 static int vmload_interception(struct vcpu_svm *svm)
2124 struct vmcb *nested_vmcb;
2127 if (nested_svm_check_permissions(svm))
2130 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2131 skip_emulated_instruction(&svm->vcpu);
2133 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2137 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2138 nested_svm_unmap(page);
2143 static int vmsave_interception(struct vcpu_svm *svm)
2145 struct vmcb *nested_vmcb;
2148 if (nested_svm_check_permissions(svm))
2151 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2152 skip_emulated_instruction(&svm->vcpu);
2154 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2158 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2159 nested_svm_unmap(page);
2164 static int vmrun_interception(struct vcpu_svm *svm)
2166 if (nested_svm_check_permissions(svm))
2169 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2170 skip_emulated_instruction(&svm->vcpu);
2172 if (!nested_svm_vmrun(svm))
2175 if (!nested_svm_vmrun_msrpm(svm))
2182 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2183 svm->vmcb->control.exit_code_hi = 0;
2184 svm->vmcb->control.exit_info_1 = 0;
2185 svm->vmcb->control.exit_info_2 = 0;
2187 nested_svm_vmexit(svm);
2192 static int stgi_interception(struct vcpu_svm *svm)
2194 if (nested_svm_check_permissions(svm))
2197 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2198 skip_emulated_instruction(&svm->vcpu);
2205 static int clgi_interception(struct vcpu_svm *svm)
2207 if (nested_svm_check_permissions(svm))
2210 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2211 skip_emulated_instruction(&svm->vcpu);
2215 /* After a CLGI no interrupts should come */
2216 svm_clear_vintr(svm);
2217 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2222 static int invlpga_interception(struct vcpu_svm *svm)
2224 struct kvm_vcpu *vcpu = &svm->vcpu;
2226 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2227 vcpu->arch.regs[VCPU_REGS_RAX]);
2229 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2230 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2232 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2233 skip_emulated_instruction(&svm->vcpu);
2237 static int skinit_interception(struct vcpu_svm *svm)
2239 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2241 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2245 static int invalid_op_interception(struct vcpu_svm *svm)
2247 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2251 static int task_switch_interception(struct vcpu_svm *svm)
2255 int int_type = svm->vmcb->control.exit_int_info &
2256 SVM_EXITINTINFO_TYPE_MASK;
2257 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2259 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2261 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2263 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2265 if (svm->vmcb->control.exit_info_2 &
2266 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2267 reason = TASK_SWITCH_IRET;
2268 else if (svm->vmcb->control.exit_info_2 &
2269 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2270 reason = TASK_SWITCH_JMP;
2272 reason = TASK_SWITCH_GATE;
2274 reason = TASK_SWITCH_CALL;
2276 if (reason == TASK_SWITCH_GATE) {
2278 case SVM_EXITINTINFO_TYPE_NMI:
2279 svm->vcpu.arch.nmi_injected = false;
2281 case SVM_EXITINTINFO_TYPE_EXEPT:
2282 kvm_clear_exception_queue(&svm->vcpu);
2284 case SVM_EXITINTINFO_TYPE_INTR:
2285 kvm_clear_interrupt_queue(&svm->vcpu);
2292 if (reason != TASK_SWITCH_GATE ||
2293 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2294 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2295 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2296 skip_emulated_instruction(&svm->vcpu);
2298 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2301 static int cpuid_interception(struct vcpu_svm *svm)
2303 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2304 kvm_emulate_cpuid(&svm->vcpu);
2308 static int iret_interception(struct vcpu_svm *svm)
2310 ++svm->vcpu.stat.nmi_window_exits;
2311 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2312 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2316 static int invlpg_interception(struct vcpu_svm *svm)
2318 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2319 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2323 static int emulate_on_interception(struct vcpu_svm *svm)
2325 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2326 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2330 static int cr8_write_interception(struct vcpu_svm *svm)
2332 struct kvm_run *kvm_run = svm->vcpu.run;
2334 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2335 /* instruction emulation calls kvm_set_cr8() */
2336 emulate_instruction(&svm->vcpu, 0, 0, 0);
2337 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2338 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2341 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2343 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2347 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2349 struct vcpu_svm *svm = to_svm(vcpu);
2352 case MSR_IA32_TSC: {
2356 tsc_offset = svm->nested.hsave->control.tsc_offset;
2358 tsc_offset = svm->vmcb->control.tsc_offset;
2360 *data = tsc_offset + native_read_tsc();
2364 *data = svm->vmcb->save.star;
2366 #ifdef CONFIG_X86_64
2368 *data = svm->vmcb->save.lstar;
2371 *data = svm->vmcb->save.cstar;
2373 case MSR_KERNEL_GS_BASE:
2374 *data = svm->vmcb->save.kernel_gs_base;
2376 case MSR_SYSCALL_MASK:
2377 *data = svm->vmcb->save.sfmask;
2380 case MSR_IA32_SYSENTER_CS:
2381 *data = svm->vmcb->save.sysenter_cs;
2383 case MSR_IA32_SYSENTER_EIP:
2384 *data = svm->sysenter_eip;
2386 case MSR_IA32_SYSENTER_ESP:
2387 *data = svm->sysenter_esp;
2390 * Nobody will change the following 5 values in the VMCB so we can
2391 * safely return them on rdmsr. They will always be 0 until LBRV is
2394 case MSR_IA32_DEBUGCTLMSR:
2395 *data = svm->vmcb->save.dbgctl;
2397 case MSR_IA32_LASTBRANCHFROMIP:
2398 *data = svm->vmcb->save.br_from;
2400 case MSR_IA32_LASTBRANCHTOIP:
2401 *data = svm->vmcb->save.br_to;
2403 case MSR_IA32_LASTINTFROMIP:
2404 *data = svm->vmcb->save.last_excp_from;
2406 case MSR_IA32_LASTINTTOIP:
2407 *data = svm->vmcb->save.last_excp_to;
2409 case MSR_VM_HSAVE_PA:
2410 *data = svm->nested.hsave_msr;
2413 *data = svm->nested.vm_cr_msr;
2415 case MSR_IA32_UCODE_REV:
2419 return kvm_get_msr_common(vcpu, ecx, data);
2424 static int rdmsr_interception(struct vcpu_svm *svm)
2426 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2429 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2430 trace_kvm_msr_read_ex(ecx);
2431 kvm_inject_gp(&svm->vcpu, 0);
2433 trace_kvm_msr_read(ecx, data);
2435 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2436 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2437 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2438 skip_emulated_instruction(&svm->vcpu);
2443 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2445 struct vcpu_svm *svm = to_svm(vcpu);
2446 int svm_dis, chg_mask;
2448 if (data & ~SVM_VM_CR_VALID_MASK)
2451 chg_mask = SVM_VM_CR_VALID_MASK;
2453 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2454 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2456 svm->nested.vm_cr_msr &= ~chg_mask;
2457 svm->nested.vm_cr_msr |= (data & chg_mask);
2459 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2461 /* check for svm_disable while efer.svme is set */
2462 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2468 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2470 struct vcpu_svm *svm = to_svm(vcpu);
2473 case MSR_IA32_TSC: {
2474 u64 tsc_offset = data - native_read_tsc();
2475 u64 g_tsc_offset = 0;
2477 if (is_nested(svm)) {
2478 g_tsc_offset = svm->vmcb->control.tsc_offset -
2479 svm->nested.hsave->control.tsc_offset;
2480 svm->nested.hsave->control.tsc_offset = tsc_offset;
2483 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2488 svm->vmcb->save.star = data;
2490 #ifdef CONFIG_X86_64
2492 svm->vmcb->save.lstar = data;
2495 svm->vmcb->save.cstar = data;
2497 case MSR_KERNEL_GS_BASE:
2498 svm->vmcb->save.kernel_gs_base = data;
2500 case MSR_SYSCALL_MASK:
2501 svm->vmcb->save.sfmask = data;
2504 case MSR_IA32_SYSENTER_CS:
2505 svm->vmcb->save.sysenter_cs = data;
2507 case MSR_IA32_SYSENTER_EIP:
2508 svm->sysenter_eip = data;
2509 svm->vmcb->save.sysenter_eip = data;
2511 case MSR_IA32_SYSENTER_ESP:
2512 svm->sysenter_esp = data;
2513 svm->vmcb->save.sysenter_esp = data;
2515 case MSR_IA32_DEBUGCTLMSR:
2516 if (!svm_has(SVM_FEATURE_LBRV)) {
2517 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2521 if (data & DEBUGCTL_RESERVED_BITS)
2524 svm->vmcb->save.dbgctl = data;
2525 if (data & (1ULL<<0))
2526 svm_enable_lbrv(svm);
2528 svm_disable_lbrv(svm);
2530 case MSR_VM_HSAVE_PA:
2531 svm->nested.hsave_msr = data;
2534 return svm_set_vm_cr(vcpu, data);
2536 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2539 return kvm_set_msr_common(vcpu, ecx, data);
2544 static int wrmsr_interception(struct vcpu_svm *svm)
2546 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2547 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2548 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2551 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2552 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2553 trace_kvm_msr_write_ex(ecx, data);
2554 kvm_inject_gp(&svm->vcpu, 0);
2556 trace_kvm_msr_write(ecx, data);
2557 skip_emulated_instruction(&svm->vcpu);
2562 static int msr_interception(struct vcpu_svm *svm)
2564 if (svm->vmcb->control.exit_info_1)
2565 return wrmsr_interception(svm);
2567 return rdmsr_interception(svm);
2570 static int interrupt_window_interception(struct vcpu_svm *svm)
2572 struct kvm_run *kvm_run = svm->vcpu.run;
2574 svm_clear_vintr(svm);
2575 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2577 * If the user space waits to inject interrupts, exit as soon as
2580 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2581 kvm_run->request_interrupt_window &&
2582 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2583 ++svm->vcpu.stat.irq_window_exits;
2584 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2591 static int pause_interception(struct vcpu_svm *svm)
2593 kvm_vcpu_on_spin(&(svm->vcpu));
2597 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2598 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2599 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2600 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2601 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2602 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2603 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2604 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2605 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2606 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2607 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2608 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2609 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2610 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2611 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2612 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2613 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2614 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2615 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2616 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2617 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2618 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2619 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2620 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2621 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2622 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2623 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2624 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2625 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2626 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2627 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2628 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2629 [SVM_EXIT_INTR] = intr_interception,
2630 [SVM_EXIT_NMI] = nmi_interception,
2631 [SVM_EXIT_SMI] = nop_on_interception,
2632 [SVM_EXIT_INIT] = nop_on_interception,
2633 [SVM_EXIT_VINTR] = interrupt_window_interception,
2634 [SVM_EXIT_CPUID] = cpuid_interception,
2635 [SVM_EXIT_IRET] = iret_interception,
2636 [SVM_EXIT_INVD] = emulate_on_interception,
2637 [SVM_EXIT_PAUSE] = pause_interception,
2638 [SVM_EXIT_HLT] = halt_interception,
2639 [SVM_EXIT_INVLPG] = invlpg_interception,
2640 [SVM_EXIT_INVLPGA] = invlpga_interception,
2641 [SVM_EXIT_IOIO] = io_interception,
2642 [SVM_EXIT_MSR] = msr_interception,
2643 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2644 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2645 [SVM_EXIT_VMRUN] = vmrun_interception,
2646 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2647 [SVM_EXIT_VMLOAD] = vmload_interception,
2648 [SVM_EXIT_VMSAVE] = vmsave_interception,
2649 [SVM_EXIT_STGI] = stgi_interception,
2650 [SVM_EXIT_CLGI] = clgi_interception,
2651 [SVM_EXIT_SKINIT] = skinit_interception,
2652 [SVM_EXIT_WBINVD] = emulate_on_interception,
2653 [SVM_EXIT_MONITOR] = invalid_op_interception,
2654 [SVM_EXIT_MWAIT] = invalid_op_interception,
2655 [SVM_EXIT_NPF] = pf_interception,
2658 static int handle_exit(struct kvm_vcpu *vcpu)
2660 struct vcpu_svm *svm = to_svm(vcpu);
2661 struct kvm_run *kvm_run = vcpu->run;
2662 u32 exit_code = svm->vmcb->control.exit_code;
2664 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2666 if (unlikely(svm->nested.exit_required)) {
2667 nested_svm_vmexit(svm);
2668 svm->nested.exit_required = false;
2673 if (is_nested(svm)) {
2676 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2677 svm->vmcb->control.exit_info_1,
2678 svm->vmcb->control.exit_info_2,
2679 svm->vmcb->control.exit_int_info,
2680 svm->vmcb->control.exit_int_info_err);
2682 vmexit = nested_svm_exit_special(svm);
2684 if (vmexit == NESTED_EXIT_CONTINUE)
2685 vmexit = nested_svm_exit_handled(svm);
2687 if (vmexit == NESTED_EXIT_DONE)
2691 svm_complete_interrupts(svm);
2693 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2694 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2696 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2698 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2699 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2700 kvm_run->fail_entry.hardware_entry_failure_reason
2701 = svm->vmcb->control.exit_code;
2705 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2706 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2707 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2708 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2710 __func__, svm->vmcb->control.exit_int_info,
2713 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2714 || !svm_exit_handlers[exit_code]) {
2715 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2716 kvm_run->hw.hardware_exit_reason = exit_code;
2720 return svm_exit_handlers[exit_code](svm);
2723 static void reload_tss(struct kvm_vcpu *vcpu)
2725 int cpu = raw_smp_processor_id();
2727 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2728 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2732 static void pre_svm_run(struct vcpu_svm *svm)
2734 int cpu = raw_smp_processor_id();
2736 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2738 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2739 /* FIXME: handle wraparound of asid_generation */
2740 if (svm->asid_generation != sd->asid_generation)
2744 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2746 struct vcpu_svm *svm = to_svm(vcpu);
2748 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2749 vcpu->arch.hflags |= HF_NMI_MASK;
2750 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2751 ++vcpu->stat.nmi_injections;
2754 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2756 struct vmcb_control_area *control;
2758 trace_kvm_inj_virq(irq);
2760 ++svm->vcpu.stat.irq_injections;
2761 control = &svm->vmcb->control;
2762 control->int_vector = irq;
2763 control->int_ctl &= ~V_INTR_PRIO_MASK;
2764 control->int_ctl |= V_IRQ_MASK |
2765 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2768 static void svm_set_irq(struct kvm_vcpu *vcpu)
2770 struct vcpu_svm *svm = to_svm(vcpu);
2772 BUG_ON(!(gif_set(svm)));
2774 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2775 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2778 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2780 struct vcpu_svm *svm = to_svm(vcpu);
2782 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2789 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2792 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2794 struct vcpu_svm *svm = to_svm(vcpu);
2795 struct vmcb *vmcb = svm->vmcb;
2796 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2797 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2800 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2802 struct vcpu_svm *svm = to_svm(vcpu);
2804 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2807 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2809 struct vcpu_svm *svm = to_svm(vcpu);
2812 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2813 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2815 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2816 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2820 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2822 struct vcpu_svm *svm = to_svm(vcpu);
2823 struct vmcb *vmcb = svm->vmcb;
2826 if (!gif_set(svm) ||
2827 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2830 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2833 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2838 static void enable_irq_window(struct kvm_vcpu *vcpu)
2840 struct vcpu_svm *svm = to_svm(vcpu);
2843 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2844 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2845 * get that intercept, this function will be called again though and
2846 * we'll get the vintr intercept.
2848 if (gif_set(svm) && nested_svm_intr(svm)) {
2850 svm_inject_irq(svm, 0x0);
2854 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2856 struct vcpu_svm *svm = to_svm(vcpu);
2858 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2860 return; /* IRET will cause a vm exit */
2863 * Something prevents NMI from been injected. Single step over possible
2864 * problem (IRET or exception injection or interrupt shadow)
2866 if (gif_set(svm) && nested_svm_nmi(svm)) {
2867 svm->nmi_singlestep = true;
2868 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2869 update_db_intercept(vcpu);
2873 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2878 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2880 force_new_asid(vcpu);
2883 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2887 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2889 struct vcpu_svm *svm = to_svm(vcpu);
2891 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2894 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2895 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2896 kvm_set_cr8(vcpu, cr8);
2900 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2902 struct vcpu_svm *svm = to_svm(vcpu);
2905 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2908 cr8 = kvm_get_cr8(vcpu);
2909 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2910 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2913 static void svm_complete_interrupts(struct vcpu_svm *svm)
2917 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2918 unsigned int3_injected = svm->int3_injected;
2920 svm->int3_injected = 0;
2922 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2923 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2925 svm->vcpu.arch.nmi_injected = false;
2926 kvm_clear_exception_queue(&svm->vcpu);
2927 kvm_clear_interrupt_queue(&svm->vcpu);
2929 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2932 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2933 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2936 case SVM_EXITINTINFO_TYPE_NMI:
2937 svm->vcpu.arch.nmi_injected = true;
2939 case SVM_EXITINTINFO_TYPE_EXEPT:
2943 * In case of software exceptions, do not reinject the vector,
2944 * but re-execute the instruction instead. Rewind RIP first
2945 * if we emulated INT3 before.
2947 if (kvm_exception_is_soft(vector)) {
2948 if (vector == BP_VECTOR && int3_injected &&
2949 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2950 kvm_rip_write(&svm->vcpu,
2951 kvm_rip_read(&svm->vcpu) -
2955 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2956 u32 err = svm->vmcb->control.exit_int_info_err;
2957 kvm_queue_exception_e(&svm->vcpu, vector, err);
2960 kvm_queue_exception(&svm->vcpu, vector);
2962 case SVM_EXITINTINFO_TYPE_INTR:
2963 kvm_queue_interrupt(&svm->vcpu, vector, false);
2970 #ifdef CONFIG_X86_64
2976 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2978 struct vcpu_svm *svm = to_svm(vcpu);
2984 * A vmexit emulation is required before the vcpu can be executed
2987 if (unlikely(svm->nested.exit_required))
2990 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2991 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2992 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2996 sync_lapic_to_cr8(vcpu);
2998 save_host_msrs(vcpu);
2999 fs_selector = kvm_read_fs();
3000 gs_selector = kvm_read_gs();
3001 ldt_selector = kvm_read_ldt();
3002 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3003 /* required for live migration with NPT */
3005 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3012 "push %%"R"bp; \n\t"
3013 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3014 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3015 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3016 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3017 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3018 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3019 #ifdef CONFIG_X86_64
3020 "mov %c[r8](%[svm]), %%r8 \n\t"
3021 "mov %c[r9](%[svm]), %%r9 \n\t"
3022 "mov %c[r10](%[svm]), %%r10 \n\t"
3023 "mov %c[r11](%[svm]), %%r11 \n\t"
3024 "mov %c[r12](%[svm]), %%r12 \n\t"
3025 "mov %c[r13](%[svm]), %%r13 \n\t"
3026 "mov %c[r14](%[svm]), %%r14 \n\t"
3027 "mov %c[r15](%[svm]), %%r15 \n\t"
3030 /* Enter guest mode */
3032 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3033 __ex(SVM_VMLOAD) "\n\t"
3034 __ex(SVM_VMRUN) "\n\t"
3035 __ex(SVM_VMSAVE) "\n\t"
3038 /* Save guest registers, load host registers */
3039 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3040 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3041 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3042 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3043 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3044 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3045 #ifdef CONFIG_X86_64
3046 "mov %%r8, %c[r8](%[svm]) \n\t"
3047 "mov %%r9, %c[r9](%[svm]) \n\t"
3048 "mov %%r10, %c[r10](%[svm]) \n\t"
3049 "mov %%r11, %c[r11](%[svm]) \n\t"
3050 "mov %%r12, %c[r12](%[svm]) \n\t"
3051 "mov %%r13, %c[r13](%[svm]) \n\t"
3052 "mov %%r14, %c[r14](%[svm]) \n\t"
3053 "mov %%r15, %c[r15](%[svm]) \n\t"
3058 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3059 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3060 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3061 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3062 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3063 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3064 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3065 #ifdef CONFIG_X86_64
3066 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3067 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3068 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3069 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3070 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3071 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3072 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3073 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3076 , R"bx", R"cx", R"dx", R"si", R"di"
3077 #ifdef CONFIG_X86_64
3078 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3082 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3083 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3084 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3085 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3087 kvm_load_fs(fs_selector);
3088 kvm_load_gs(gs_selector);
3089 kvm_load_ldt(ldt_selector);
3090 load_host_msrs(vcpu);
3094 local_irq_disable();
3098 sync_cr8_to_lapic(vcpu);
3103 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3104 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3110 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3112 struct vcpu_svm *svm = to_svm(vcpu);
3115 svm->vmcb->control.nested_cr3 = root;
3116 force_new_asid(vcpu);
3120 svm->vmcb->save.cr3 = root;
3121 force_new_asid(vcpu);
3124 static int is_disabled(void)
3128 rdmsrl(MSR_VM_CR, vm_cr);
3129 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3136 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3139 * Patch in the VMMCALL instruction:
3141 hypercall[0] = 0x0f;
3142 hypercall[1] = 0x01;
3143 hypercall[2] = 0xd9;
3146 static void svm_check_processor_compat(void *rtn)
3151 static bool svm_cpu_has_accelerated_tpr(void)
3156 static int get_npt_level(void)
3158 #ifdef CONFIG_X86_64
3159 return PT64_ROOT_LEVEL;
3161 return PT32E_ROOT_LEVEL;
3165 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3170 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3174 static const struct trace_print_flags svm_exit_reasons_str[] = {
3175 { SVM_EXIT_READ_CR0, "read_cr0" },
3176 { SVM_EXIT_READ_CR3, "read_cr3" },
3177 { SVM_EXIT_READ_CR4, "read_cr4" },
3178 { SVM_EXIT_READ_CR8, "read_cr8" },
3179 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3180 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3181 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3182 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3183 { SVM_EXIT_READ_DR0, "read_dr0" },
3184 { SVM_EXIT_READ_DR1, "read_dr1" },
3185 { SVM_EXIT_READ_DR2, "read_dr2" },
3186 { SVM_EXIT_READ_DR3, "read_dr3" },
3187 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3188 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3189 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3190 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3191 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3192 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3193 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3194 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3195 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3196 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3197 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3198 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3199 { SVM_EXIT_INTR, "interrupt" },
3200 { SVM_EXIT_NMI, "nmi" },
3201 { SVM_EXIT_SMI, "smi" },
3202 { SVM_EXIT_INIT, "init" },
3203 { SVM_EXIT_VINTR, "vintr" },
3204 { SVM_EXIT_CPUID, "cpuid" },
3205 { SVM_EXIT_INVD, "invd" },
3206 { SVM_EXIT_HLT, "hlt" },
3207 { SVM_EXIT_INVLPG, "invlpg" },
3208 { SVM_EXIT_INVLPGA, "invlpga" },
3209 { SVM_EXIT_IOIO, "io" },
3210 { SVM_EXIT_MSR, "msr" },
3211 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3212 { SVM_EXIT_SHUTDOWN, "shutdown" },
3213 { SVM_EXIT_VMRUN, "vmrun" },
3214 { SVM_EXIT_VMMCALL, "hypercall" },
3215 { SVM_EXIT_VMLOAD, "vmload" },
3216 { SVM_EXIT_VMSAVE, "vmsave" },
3217 { SVM_EXIT_STGI, "stgi" },
3218 { SVM_EXIT_CLGI, "clgi" },
3219 { SVM_EXIT_SKINIT, "skinit" },
3220 { SVM_EXIT_WBINVD, "wbinvd" },
3221 { SVM_EXIT_MONITOR, "monitor" },
3222 { SVM_EXIT_MWAIT, "mwait" },
3223 { SVM_EXIT_NPF, "npf" },
3227 static int svm_get_lpage_level(void)
3229 return PT_PDPE_LEVEL;
3232 static bool svm_rdtscp_supported(void)
3237 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3239 struct vcpu_svm *svm = to_svm(vcpu);
3241 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3243 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3244 update_cr0_intercept(svm);
3247 static struct kvm_x86_ops svm_x86_ops = {
3248 .cpu_has_kvm_support = has_svm,
3249 .disabled_by_bios = is_disabled,
3250 .hardware_setup = svm_hardware_setup,
3251 .hardware_unsetup = svm_hardware_unsetup,
3252 .check_processor_compatibility = svm_check_processor_compat,
3253 .hardware_enable = svm_hardware_enable,
3254 .hardware_disable = svm_hardware_disable,
3255 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3257 .vcpu_create = svm_create_vcpu,
3258 .vcpu_free = svm_free_vcpu,
3259 .vcpu_reset = svm_vcpu_reset,
3261 .prepare_guest_switch = svm_prepare_guest_switch,
3262 .vcpu_load = svm_vcpu_load,
3263 .vcpu_put = svm_vcpu_put,
3265 .set_guest_debug = svm_guest_debug,
3266 .get_msr = svm_get_msr,
3267 .set_msr = svm_set_msr,
3268 .get_segment_base = svm_get_segment_base,
3269 .get_segment = svm_get_segment,
3270 .set_segment = svm_set_segment,
3271 .get_cpl = svm_get_cpl,
3272 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3273 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3274 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3275 .set_cr0 = svm_set_cr0,
3276 .set_cr3 = svm_set_cr3,
3277 .set_cr4 = svm_set_cr4,
3278 .set_efer = svm_set_efer,
3279 .get_idt = svm_get_idt,
3280 .set_idt = svm_set_idt,
3281 .get_gdt = svm_get_gdt,
3282 .set_gdt = svm_set_gdt,
3283 .get_dr = svm_get_dr,
3284 .set_dr = svm_set_dr,
3285 .cache_reg = svm_cache_reg,
3286 .get_rflags = svm_get_rflags,
3287 .set_rflags = svm_set_rflags,
3288 .fpu_activate = svm_fpu_activate,
3289 .fpu_deactivate = svm_fpu_deactivate,
3291 .tlb_flush = svm_flush_tlb,
3293 .run = svm_vcpu_run,
3294 .handle_exit = handle_exit,
3295 .skip_emulated_instruction = skip_emulated_instruction,
3296 .set_interrupt_shadow = svm_set_interrupt_shadow,
3297 .get_interrupt_shadow = svm_get_interrupt_shadow,
3298 .patch_hypercall = svm_patch_hypercall,
3299 .set_irq = svm_set_irq,
3300 .set_nmi = svm_inject_nmi,
3301 .queue_exception = svm_queue_exception,
3302 .interrupt_allowed = svm_interrupt_allowed,
3303 .nmi_allowed = svm_nmi_allowed,
3304 .get_nmi_mask = svm_get_nmi_mask,
3305 .set_nmi_mask = svm_set_nmi_mask,
3306 .enable_nmi_window = enable_nmi_window,
3307 .enable_irq_window = enable_irq_window,
3308 .update_cr8_intercept = update_cr8_intercept,
3310 .set_tss_addr = svm_set_tss_addr,
3311 .get_tdp_level = get_npt_level,
3312 .get_mt_mask = svm_get_mt_mask,
3314 .exit_reasons_str = svm_exit_reasons_str,
3315 .get_lpage_level = svm_get_lpage_level,
3317 .cpuid_update = svm_cpuid_update,
3319 .rdtscp_supported = svm_rdtscp_supported,
3322 static int __init svm_init(void)
3324 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3328 static void __exit svm_exit(void)
3333 module_init(svm_init)
3334 module_exit(svm_exit)