arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30
  31 #include <asm/desc.h>
  32
  33 #include <asm/virtext.h>
  34 #include "trace.h"
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 #define IOPM_ALLOC_ORDER 2
  42 #define MSRPM_ALLOC_ORDER 1
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT  (1 << 0)
  48 #define SVM_FEATURE_LBRV (1 << 1)
  49 #define SVM_FEATURE_SVML (1 << 2)
  50 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
  51
  52 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  53 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  54 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  55
  56 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  57
  58 static const u32 host_save_user_msrs[] = {
  59 #ifdef CONFIG_X86_64
  60         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  61         MSR_FS_BASE,
  62 #endif
  63         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  64 };
  65
  66 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  67
  68 struct kvm_vcpu;
  69
  70 struct nested_state {
  71         struct vmcb *hsave;
  72         u64 hsave_msr;
  73         u64 vmcb;
  74
  75         /* These are the merged vectors */
  76         u32 *msrpm;
  77
  78         /* gpa pointers to the real vectors */
  79         u64 vmcb_msrpm;
  80
  81         /* A VMEXIT is required but not yet emulated */
  82         bool exit_required;
  83
  84         /* cache for intercepts of the guest */
  85         u16 intercept_cr_read;
  86         u16 intercept_cr_write;
  87         u16 intercept_dr_read;
  88         u16 intercept_dr_write;
  89         u32 intercept_exceptions;
  90         u64 intercept;
  91
  92 };
  93
  94 struct vcpu_svm {
  95         struct kvm_vcpu vcpu;
  96         struct vmcb *vmcb;
  97         unsigned long vmcb_pa;
  98         struct svm_cpu_data *svm_data;
  99         uint64_t asid_generation;
 100         uint64_t sysenter_esp;
 101         uint64_t sysenter_eip;
 102
 103         u64 next_rip;
 104
 105         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 106         u64 host_gs_base;
 107
 108         u32 *msrpm;
 109
 110         struct nested_state nested;
 111
 112         bool nmi_singlestep;
 113 };
 114
 115 /* enable NPT for AMD64 and X86 with PAE */
 116 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 117 static bool npt_enabled = true;
 118 #else
 119 static bool npt_enabled = false;
 120 #endif
 121 static int npt = 1;
 122
 123 module_param(npt, int, S_IRUGO);
 124
 125 static int nested = 1;
 126 module_param(nested, int, S_IRUGO);
 127
 128 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 129 static void svm_complete_interrupts(struct vcpu_svm *svm);
 130
 131 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 132 static int nested_svm_intercept(struct vcpu_svm *svm);
 133 static int nested_svm_vmexit(struct vcpu_svm *svm);
 134 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 135                                       bool has_error_code, u32 error_code);
 136
 137 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 138 {
 139         return container_of(vcpu, struct vcpu_svm, vcpu);
 140 }
 141
 142 static inline bool is_nested(struct vcpu_svm *svm)
 143 {
 144         return svm->nested.vmcb;
 145 }
 146
 147 static inline void enable_gif(struct vcpu_svm *svm)
 148 {
 149         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 150 }
 151
 152 static inline void disable_gif(struct vcpu_svm *svm)
 153 {
 154         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 155 }
 156
 157 static inline bool gif_set(struct vcpu_svm *svm)
 158 {
 159         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 160 }
 161
 162 static unsigned long iopm_base;
 163
 164 struct kvm_ldttss_desc {
 165         u16 limit0;
 166         u16 base0;
 167         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 168         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 169         u32 base3;
 170         u32 zero1;
 171 } __attribute__((packed));
 172
 173 struct svm_cpu_data {
 174         int cpu;
 175
 176         u64 asid_generation;
 177         u32 max_asid;
 178         u32 next_asid;
 179         struct kvm_ldttss_desc *tss_desc;
 180
 181         struct page *save_area;
 182 };
 183
 184 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 185 static uint32_t svm_features;
 186
 187 struct svm_init_data {
 188         int cpu;
 189         int r;
 190 };
 191
 192 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 193
 194 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 195 #define MSRS_RANGE_SIZE 2048
 196 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 197
 198 #define MAX_INST_SIZE 15
 199
 200 static inline u32 svm_has(u32 feat)
 201 {
 202         return svm_features & feat;
 203 }
 204
 205 static inline void clgi(void)
 206 {
 207         asm volatile (__ex(SVM_CLGI));
 208 }
 209
 210 static inline void stgi(void)
 211 {
 212         asm volatile (__ex(SVM_STGI));
 213 }
 214
 215 static inline void invlpga(unsigned long addr, u32 asid)
 216 {
 217         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 218 }
 219
 220 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 221 {
 222         to_svm(vcpu)->asid_generation--;
 223 }
 224
 225 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 226 {
 227         force_new_asid(vcpu);
 228 }
 229
 230 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 231 {
 232         if (!npt_enabled && !(efer & EFER_LMA))
 233                 efer &= ~EFER_LME;
 234
 235         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 236         vcpu->arch.efer = efer;
 237 }
 238
 239 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 240                                 bool has_error_code, u32 error_code)
 241 {
 242         struct vcpu_svm *svm = to_svm(vcpu);
 243
 244         /* If we are within a nested VM we'd better #VMEXIT and let the
 245            guest handle the exception */
 246         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 247                 return;
 248
 249         svm->vmcb->control.event_inj = nr
 250                 | SVM_EVTINJ_VALID
 251                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 252                 | SVM_EVTINJ_TYPE_EXEPT;
 253         svm->vmcb->control.event_inj_err = error_code;
 254 }
 255
 256 static int is_external_interrupt(u32 info)
 257 {
 258         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 259         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 260 }
 261
 262 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 263 {
 264         struct vcpu_svm *svm = to_svm(vcpu);
 265         u32 ret = 0;
 266
 267         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 268                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 269         return ret & mask;
 270 }
 271
 272 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 273 {
 274         struct vcpu_svm *svm = to_svm(vcpu);
 275
 276         if (mask == 0)
 277                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 278         else
 279                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 280
 281 }
 282
 283 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 284 {
 285         struct vcpu_svm *svm = to_svm(vcpu);
 286
 287         if (!svm->next_rip) {
 288                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 289                                 EMULATE_DONE)
 290                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 291                 return;
 292         }
 293         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 294                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 295                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 296
 297         kvm_rip_write(vcpu, svm->next_rip);
 298         svm_set_interrupt_shadow(vcpu, 0);
 299 }
 300
 301 static int has_svm(void)
 302 {
 303         const char *msg;
 304
 305         if (!cpu_has_svm(&msg)) {
 306                 printk(KERN_INFO "has_svm: %s\n", msg);
 307                 return 0;
 308         }
 309
 310         return 1;
 311 }
 312
 313 static void svm_hardware_disable(void *garbage)
 314 {
 315         cpu_svm_disable();
 316 }
 317
 318 static int svm_hardware_enable(void *garbage)
 319 {
 320
 321         struct svm_cpu_data *sd;
 322         uint64_t efer;
 323         struct desc_ptr gdt_descr;
 324         struct desc_struct *gdt;
 325         int me = raw_smp_processor_id();
 326
 327         rdmsrl(MSR_EFER, efer);
 328         if (efer & EFER_SVME)
 329                 return -EBUSY;
 330
 331         if (!has_svm()) {
 332                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 333                        me);
 334                 return -EINVAL;
 335         }
 336         sd = per_cpu(svm_data, me);
 337
 338         if (!sd) {
 339                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 340                        me);
 341                 return -EINVAL;
 342         }
 343
 344         sd->asid_generation = 1;
 345         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 346         sd->next_asid = sd->max_asid + 1;
 347
 348         kvm_get_gdt(&gdt_descr);
 349         gdt = (struct desc_struct *)gdt_descr.address;
 350         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 351
 352         wrmsrl(MSR_EFER, efer | EFER_SVME);
 353
 354         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 355
 356         return 0;
 357 }
 358
 359 static void svm_cpu_uninit(int cpu)
 360 {
 361         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 362
 363         if (!sd)
 364                 return;
 365
 366         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 367         __free_page(sd->save_area);
 368         kfree(sd);
 369 }
 370
 371 static int svm_cpu_init(int cpu)
 372 {
 373         struct svm_cpu_data *sd;
 374         int r;
 375
 376         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 377         if (!sd)
 378                 return -ENOMEM;
 379         sd->cpu = cpu;
 380         sd->save_area = alloc_page(GFP_KERNEL);
 381         r = -ENOMEM;
 382         if (!sd->save_area)
 383                 goto err_1;
 384
 385         per_cpu(svm_data, cpu) = sd;
 386
 387         return 0;
 388
 389 err_1:
 390         kfree(sd);
 391         return r;
 392
 393 }
 394
 395 static void set_msr_interception(u32 *msrpm, unsigned msr,
 396                                  int read, int write)
 397 {
 398         int i;
 399
 400         for (i = 0; i < NUM_MSR_MAPS; i++) {
 401                 if (msr >= msrpm_ranges[i] &&
 402                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 403                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 404                                           msrpm_ranges[i]) * 2;
 405
 406                         u32 *base = msrpm + (msr_offset / 32);
 407                         u32 msr_shift = msr_offset % 32;
 408                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 409                         *base = (*base & ~(0x3 << msr_shift)) |
 410                                 (mask << msr_shift);
 411                         return;
 412                 }
 413         }
 414         BUG();
 415 }
 416
 417 static void svm_vcpu_init_msrpm(u32 *msrpm)
 418 {
 419         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 420
 421 #ifdef CONFIG_X86_64
 422         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 423         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 424         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 425         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 426         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 427         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 428 #endif
 429         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 430         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 431 }
 432
 433 static void svm_enable_lbrv(struct vcpu_svm *svm)
 434 {
 435         u32 *msrpm = svm->msrpm;
 436
 437         svm->vmcb->control.lbr_ctl = 1;
 438         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 439         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 440         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 441         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 442 }
 443
 444 static void svm_disable_lbrv(struct vcpu_svm *svm)
 445 {
 446         u32 *msrpm = svm->msrpm;
 447
 448         svm->vmcb->control.lbr_ctl = 0;
 449         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 450         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 451         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 452         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 453 }
 454
 455 static __init int svm_hardware_setup(void)
 456 {
 457         int cpu;
 458         struct page *iopm_pages;
 459         void *iopm_va;
 460         int r;
 461
 462         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 463
 464         if (!iopm_pages)
 465                 return -ENOMEM;
 466
 467         iopm_va = page_address(iopm_pages);
 468         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 469         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 470
 471         if (boot_cpu_has(X86_FEATURE_NX))
 472                 kvm_enable_efer_bits(EFER_NX);
 473
 474         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 475                 kvm_enable_efer_bits(EFER_FFXSR);
 476
 477         if (nested) {
 478                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 479                 kvm_enable_efer_bits(EFER_SVME);
 480         }
 481
 482         for_each_possible_cpu(cpu) {
 483                 r = svm_cpu_init(cpu);
 484                 if (r)
 485                         goto err;
 486         }
 487
 488         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 489
 490         if (!svm_has(SVM_FEATURE_NPT))
 491                 npt_enabled = false;
 492
 493         if (npt_enabled && !npt) {
 494                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 495                 npt_enabled = false;
 496         }
 497
 498         if (npt_enabled) {
 499                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 500                 kvm_enable_tdp();
 501         } else
 502                 kvm_disable_tdp();
 503
 504         return 0;
 505
 506 err:
 507         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 508         iopm_base = 0;
 509         return r;
 510 }
 511
 512 static __exit void svm_hardware_unsetup(void)
 513 {
 514         int cpu;
 515
 516         for_each_possible_cpu(cpu)
 517                 svm_cpu_uninit(cpu);
 518
 519         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 520         iopm_base = 0;
 521 }
 522
 523 static void init_seg(struct vmcb_seg *seg)
 524 {
 525         seg->selector = 0;
 526         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 527                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 528         seg->limit = 0xffff;
 529         seg->base = 0;
 530 }
 531
 532 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 533 {
 534         seg->selector = 0;
 535         seg->attrib = SVM_SELECTOR_P_MASK | type;
 536         seg->limit = 0xffff;
 537         seg->base = 0;
 538 }
 539
 540 static void init_vmcb(struct vcpu_svm *svm)
 541 {
 542         struct vmcb_control_area *control = &svm->vmcb->control;
 543         struct vmcb_save_area *save = &svm->vmcb->save;
 544
 545         svm->vcpu.fpu_active = 1;
 546
 547         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 548                                         INTERCEPT_CR3_MASK |
 549                                         INTERCEPT_CR4_MASK;
 550
 551         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 552                                         INTERCEPT_CR3_MASK |
 553                                         INTERCEPT_CR4_MASK |
 554                                         INTERCEPT_CR8_MASK;
 555
 556         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 557                                         INTERCEPT_DR1_MASK |
 558                                         INTERCEPT_DR2_MASK |
 559                                         INTERCEPT_DR3_MASK |
 560                                         INTERCEPT_DR4_MASK |
 561                                         INTERCEPT_DR5_MASK |
 562                                         INTERCEPT_DR6_MASK |
 563                                         INTERCEPT_DR7_MASK;
 564
 565         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 566                                         INTERCEPT_DR1_MASK |
 567                                         INTERCEPT_DR2_MASK |
 568                                         INTERCEPT_DR3_MASK |
 569                                         INTERCEPT_DR4_MASK |
 570                                         INTERCEPT_DR5_MASK |
 571                                         INTERCEPT_DR6_MASK |
 572                                         INTERCEPT_DR7_MASK;
 573
 574         control->intercept_exceptions = (1 << PF_VECTOR) |
 575                                         (1 << UD_VECTOR) |
 576                                         (1 << MC_VECTOR);
 577
 578
 579         control->intercept =    (1ULL << INTERCEPT_INTR) |
 580                                 (1ULL << INTERCEPT_NMI) |
 581                                 (1ULL << INTERCEPT_SMI) |
 582                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 583                                 (1ULL << INTERCEPT_CPUID) |
 584                                 (1ULL << INTERCEPT_INVD) |
 585                                 (1ULL << INTERCEPT_HLT) |
 586                                 (1ULL << INTERCEPT_INVLPG) |
 587                                 (1ULL << INTERCEPT_INVLPGA) |
 588                                 (1ULL << INTERCEPT_IOIO_PROT) |
 589                                 (1ULL << INTERCEPT_MSR_PROT) |
 590                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 591                                 (1ULL << INTERCEPT_SHUTDOWN) |
 592                                 (1ULL << INTERCEPT_VMRUN) |
 593                                 (1ULL << INTERCEPT_VMMCALL) |
 594                                 (1ULL << INTERCEPT_VMLOAD) |
 595                                 (1ULL << INTERCEPT_VMSAVE) |
 596                                 (1ULL << INTERCEPT_STGI) |
 597                                 (1ULL << INTERCEPT_CLGI) |
 598                                 (1ULL << INTERCEPT_SKINIT) |
 599                                 (1ULL << INTERCEPT_WBINVD) |
 600                                 (1ULL << INTERCEPT_MONITOR) |
 601                                 (1ULL << INTERCEPT_MWAIT);
 602
 603         control->iopm_base_pa = iopm_base;
 604         control->msrpm_base_pa = __pa(svm->msrpm);
 605         control->tsc_offset = 0;
 606         control->int_ctl = V_INTR_MASKING_MASK;
 607
 608         init_seg(&save->es);
 609         init_seg(&save->ss);
 610         init_seg(&save->ds);
 611         init_seg(&save->fs);
 612         init_seg(&save->gs);
 613
 614         save->cs.selector = 0xf000;
 615         /* Executable/Readable Code Segment */
 616         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 617                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 618         save->cs.limit = 0xffff;
 619         /*
 620          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 621          * be consistent with it.
 622          *
 623          * Replace when we have real mode working for vmx.
 624          */
 625         save->cs.base = 0xf0000;
 626
 627         save->gdtr.limit = 0xffff;
 628         save->idtr.limit = 0xffff;
 629
 630         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 631         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 632
 633         save->efer = EFER_SVME;
 634         save->dr6 = 0xffff0ff0;
 635         save->dr7 = 0x400;
 636         save->rflags = 2;
 637         save->rip = 0x0000fff0;
 638         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 639
 640         /* This is the guest-visible cr0 value.
 641          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 642          */
 643         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 644         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 645
 646         save->cr4 = X86_CR4_PAE;
 647         /* rdx = ?? */
 648
 649         if (npt_enabled) {
 650                 /* Setup VMCB for Nested Paging */
 651                 control->nested_ctl = 1;
 652                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 653                                         (1ULL << INTERCEPT_INVLPG));
 654                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 655                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 656                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 657                 save->g_pat = 0x0007040600070406ULL;
 658                 save->cr3 = 0;
 659                 save->cr4 = 0;
 660         }
 661         force_new_asid(&svm->vcpu);
 662
 663         svm->nested.vmcb = 0;
 664         svm->vcpu.arch.hflags = 0;
 665
 666         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 667                 control->pause_filter_count = 3000;
 668                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 669         }
 670
 671         enable_gif(svm);
 672 }
 673
 674 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 675 {
 676         struct vcpu_svm *svm = to_svm(vcpu);
 677
 678         init_vmcb(svm);
 679
 680         if (!kvm_vcpu_is_bsp(vcpu)) {
 681                 kvm_rip_write(vcpu, 0);
 682                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 683                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 684         }
 685         vcpu->arch.regs_avail = ~0;
 686         vcpu->arch.regs_dirty = ~0;
 687
 688         return 0;
 689 }
 690
 691 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 692 {
 693         struct vcpu_svm *svm;
 694         struct page *page;
 695         struct page *msrpm_pages;
 696         struct page *hsave_page;
 697         struct page *nested_msrpm_pages;
 698         int err;
 699
 700         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 701         if (!svm) {
 702                 err = -ENOMEM;
 703                 goto out;
 704         }
 705
 706         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 707         if (err)
 708                 goto free_svm;
 709
 710         err = -ENOMEM;
 711         page = alloc_page(GFP_KERNEL);
 712         if (!page)
 713                 goto uninit;
 714
 715         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 716         if (!msrpm_pages)
 717                 goto free_page1;
 718
 719         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 720         if (!nested_msrpm_pages)
 721                 goto free_page2;
 722
 723         hsave_page = alloc_page(GFP_KERNEL);
 724         if (!hsave_page)
 725                 goto free_page3;
 726
 727         svm->nested.hsave = page_address(hsave_page);
 728
 729         svm->msrpm = page_address(msrpm_pages);
 730         svm_vcpu_init_msrpm(svm->msrpm);
 731
 732         svm->nested.msrpm = page_address(nested_msrpm_pages);
 733
 734         svm->vmcb = page_address(page);
 735         clear_page(svm->vmcb);
 736         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 737         svm->asid_generation = 0;
 738         init_vmcb(svm);
 739
 740         fx_init(&svm->vcpu);
 741         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 742         if (kvm_vcpu_is_bsp(&svm->vcpu))
 743                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 744
 745         return &svm->vcpu;
 746
 747 free_page3:
 748         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 749 free_page2:
 750         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 751 free_page1:
 752         __free_page(page);
 753 uninit:
 754         kvm_vcpu_uninit(&svm->vcpu);
 755 free_svm:
 756         kmem_cache_free(kvm_vcpu_cache, svm);
 757 out:
 758         return ERR_PTR(err);
 759 }
 760
 761 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 762 {
 763         struct vcpu_svm *svm = to_svm(vcpu);
 764
 765         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 766         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 767         __free_page(virt_to_page(svm->nested.hsave));
 768         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 769         kvm_vcpu_uninit(vcpu);
 770         kmem_cache_free(kvm_vcpu_cache, svm);
 771 }
 772
 773 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 774 {
 775         struct vcpu_svm *svm = to_svm(vcpu);
 776         int i;
 777
 778         if (unlikely(cpu != vcpu->cpu)) {
 779                 u64 delta;
 780
 781                 if (check_tsc_unstable()) {
 782                         /*
 783                          * Make sure that the guest sees a monotonically
 784                          * increasing TSC.
 785                          */
 786                         delta = vcpu->arch.host_tsc - native_read_tsc();
 787                         svm->vmcb->control.tsc_offset += delta;
 788                         if (is_nested(svm))
 789                                 svm->nested.hsave->control.tsc_offset += delta;
 790                 }
 791                 vcpu->cpu = cpu;
 792                 kvm_migrate_timers(vcpu);
 793                 svm->asid_generation = 0;
 794         }
 795
 796         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 797                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 798 }
 799
 800 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 801 {
 802         struct vcpu_svm *svm = to_svm(vcpu);
 803         int i;
 804
 805         ++vcpu->stat.host_state_reload;
 806         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 807                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 808
 809         vcpu->arch.host_tsc = native_read_tsc();
 810 }
 811
 812 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 813 {
 814         return to_svm(vcpu)->vmcb->save.rflags;
 815 }
 816
 817 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 818 {
 819         to_svm(vcpu)->vmcb->save.rflags = rflags;
 820 }
 821
 822 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 823 {
 824         switch (reg) {
 825         case VCPU_EXREG_PDPTR:
 826                 BUG_ON(!npt_enabled);
 827                 load_pdptrs(vcpu, vcpu->arch.cr3);
 828                 break;
 829         default:
 830                 BUG();
 831         }
 832 }
 833
 834 static void svm_set_vintr(struct vcpu_svm *svm)
 835 {
 836         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 837 }
 838
 839 static void svm_clear_vintr(struct vcpu_svm *svm)
 840 {
 841         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 842 }
 843
 844 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 845 {
 846         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 847
 848         switch (seg) {
 849         case VCPU_SREG_CS: return &save->cs;
 850         case VCPU_SREG_DS: return &save->ds;
 851         case VCPU_SREG_ES: return &save->es;
 852         case VCPU_SREG_FS: return &save->fs;
 853         case VCPU_SREG_GS: return &save->gs;
 854         case VCPU_SREG_SS: return &save->ss;
 855         case VCPU_SREG_TR: return &save->tr;
 856         case VCPU_SREG_LDTR: return &save->ldtr;
 857         }
 858         BUG();
 859         return NULL;
 860 }
 861
 862 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 863 {
 864         struct vmcb_seg *s = svm_seg(vcpu, seg);
 865
 866         return s->base;
 867 }
 868
 869 static void svm_get_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg)
 871 {
 872         struct vmcb_seg *s = svm_seg(vcpu, seg);
 873
 874         var->base = s->base;
 875         var->limit = s->limit;
 876         var->selector = s->selector;
 877         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 878         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 879         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 880         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 881         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 882         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 883         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 884         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 885
 886         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 887          * for cross vendor migration purposes by "not present"
 888          */
 889         var->unusable = !var->present || (var->type == 0);
 890
 891         switch (seg) {
 892         case VCPU_SREG_CS:
 893                 /*
 894                  * SVM always stores 0 for the 'G' bit in the CS selector in
 895                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 896                  * Intel's VMENTRY has a check on the 'G' bit.
 897                  */
 898                 var->g = s->limit > 0xfffff;
 899                 break;
 900         case VCPU_SREG_TR:
 901                 /*
 902                  * Work around a bug where the busy flag in the tr selector
 903                  * isn't exposed
 904                  */
 905                 var->type |= 0x2;
 906                 break;
 907         case VCPU_SREG_DS:
 908         case VCPU_SREG_ES:
 909         case VCPU_SREG_FS:
 910         case VCPU_SREG_GS:
 911                 /*
 912                  * The accessed bit must always be set in the segment
 913                  * descriptor cache, although it can be cleared in the
 914                  * descriptor, the cached bit always remains at 1. Since
 915                  * Intel has a check on this, set it here to support
 916                  * cross-vendor migration.
 917                  */
 918                 if (!var->unusable)
 919                         var->type |= 0x1;
 920                 break;
 921         case VCPU_SREG_SS:
 922                 /* On AMD CPUs sometimes the DB bit in the segment
 923                  * descriptor is left as 1, although the whole segment has
 924                  * been made unusable. Clear it here to pass an Intel VMX
 925                  * entry check when cross vendor migrating.
 926                  */
 927                 if (var->unusable)
 928                         var->db = 0;
 929                 break;
 930         }
 931 }
 932
 933 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 934 {
 935         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 936
 937         return save->cpl;
 938 }
 939
 940 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 941 {
 942         struct vcpu_svm *svm = to_svm(vcpu);
 943
 944         dt->size = svm->vmcb->save.idtr.limit;
 945         dt->address = svm->vmcb->save.idtr.base;
 946 }
 947
 948 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 949 {
 950         struct vcpu_svm *svm = to_svm(vcpu);
 951
 952         svm->vmcb->save.idtr.limit = dt->size;
 953         svm->vmcb->save.idtr.base = dt->address ;
 954 }
 955
 956 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 957 {
 958         struct vcpu_svm *svm = to_svm(vcpu);
 959
 960         dt->size = svm->vmcb->save.gdtr.limit;
 961         dt->address = svm->vmcb->save.gdtr.base;
 962 }
 963
 964 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
 965 {
 966         struct vcpu_svm *svm = to_svm(vcpu);
 967
 968         svm->vmcb->save.gdtr.limit = dt->size;
 969         svm->vmcb->save.gdtr.base = dt->address ;
 970 }
 971
 972 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
 973 {
 974 }
 975
 976 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 977 {
 978 }
 979
 980 static void update_cr0_intercept(struct vcpu_svm *svm)
 981 {
 982         ulong gcr0 = svm->vcpu.arch.cr0;
 983         u64 *hcr0 = &svm->vmcb->save.cr0;
 984
 985         if (!svm->vcpu.fpu_active)
 986                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
 987         else
 988                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
 989                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
 990
 991
 992         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
 993                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
 994                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
 995         } else {
 996                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
 997                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
 998         }
 999 }
1000
1001 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1002 {
1003         struct vcpu_svm *svm = to_svm(vcpu);
1004
1005 #ifdef CONFIG_X86_64
1006         if (vcpu->arch.efer & EFER_LME) {
1007                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1008                         vcpu->arch.efer |= EFER_LMA;
1009                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1010                 }
1011
1012                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1013                         vcpu->arch.efer &= ~EFER_LMA;
1014                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1015                 }
1016         }
1017 #endif
1018         vcpu->arch.cr0 = cr0;
1019
1020         if (!npt_enabled)
1021                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1022
1023         if (!vcpu->fpu_active)
1024                 cr0 |= X86_CR0_TS;
1025         /*
1026          * re-enable caching here because the QEMU bios
1027          * does not do it - this results in some delay at
1028          * reboot
1029          */
1030         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1031         svm->vmcb->save.cr0 = cr0;
1032         update_cr0_intercept(svm);
1033 }
1034
1035 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1036 {
1037         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1038         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1039
1040         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1041                 force_new_asid(vcpu);
1042
1043         vcpu->arch.cr4 = cr4;
1044         if (!npt_enabled)
1045                 cr4 |= X86_CR4_PAE;
1046         cr4 |= host_cr4_mce;
1047         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1048 }
1049
1050 static void svm_set_segment(struct kvm_vcpu *vcpu,
1051                             struct kvm_segment *var, int seg)
1052 {
1053         struct vcpu_svm *svm = to_svm(vcpu);
1054         struct vmcb_seg *s = svm_seg(vcpu, seg);
1055
1056         s->base = var->base;
1057         s->limit = var->limit;
1058         s->selector = var->selector;
1059         if (var->unusable)
1060                 s->attrib = 0;
1061         else {
1062                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1063                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1064                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1065                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1066                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1067                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1068                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1069                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1070         }
1071         if (seg == VCPU_SREG_CS)
1072                 svm->vmcb->save.cpl
1073                         = (svm->vmcb->save.cs.attrib
1074                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1075
1076 }
1077
1078 static void update_db_intercept(struct kvm_vcpu *vcpu)
1079 {
1080         struct vcpu_svm *svm = to_svm(vcpu);
1081
1082         svm->vmcb->control.intercept_exceptions &=
1083                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1084
1085         if (svm->nmi_singlestep)
1086                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1087
1088         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1089                 if (vcpu->guest_debug &
1090                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1091                         svm->vmcb->control.intercept_exceptions |=
1092                                 1 << DB_VECTOR;
1093                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1094                         svm->vmcb->control.intercept_exceptions |=
1095                                 1 << BP_VECTOR;
1096         } else
1097                 vcpu->guest_debug = 0;
1098 }
1099
1100 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1101 {
1102         struct vcpu_svm *svm = to_svm(vcpu);
1103
1104         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1105                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1106         else
1107                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1108
1109         update_db_intercept(vcpu);
1110 }
1111
1112 static void load_host_msrs(struct kvm_vcpu *vcpu)
1113 {
1114 #ifdef CONFIG_X86_64
1115         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1116 #endif
1117 }
1118
1119 static void save_host_msrs(struct kvm_vcpu *vcpu)
1120 {
1121 #ifdef CONFIG_X86_64
1122         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1123 #endif
1124 }
1125
1126 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1127 {
1128         if (sd->next_asid > sd->max_asid) {
1129                 ++sd->asid_generation;
1130                 sd->next_asid = 1;
1131                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1132         }
1133
1134         svm->asid_generation = sd->asid_generation;
1135         svm->vmcb->control.asid = sd->next_asid++;
1136 }
1137
1138 static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
1139 {
1140         struct vcpu_svm *svm = to_svm(vcpu);
1141
1142         switch (dr) {
1143         case 0 ... 3:
1144                 *dest = vcpu->arch.db[dr];
1145                 break;
1146         case 4:
1147                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1148                         return EMULATE_FAIL; /* will re-inject UD */
1149                 /* fall through */
1150         case 6:
1151                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1152                         *dest = vcpu->arch.dr6;
1153                 else
1154                         *dest = svm->vmcb->save.dr6;
1155                 break;
1156         case 5:
1157                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1158                         return EMULATE_FAIL; /* will re-inject UD */
1159                 /* fall through */
1160         case 7:
1161                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1162                         *dest = vcpu->arch.dr7;
1163                 else
1164                         *dest = svm->vmcb->save.dr7;
1165                 break;
1166         }
1167
1168         return EMULATE_DONE;
1169 }
1170
1171 static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
1172 {
1173         struct vcpu_svm *svm = to_svm(vcpu);
1174
1175         switch (dr) {
1176         case 0 ... 3:
1177                 vcpu->arch.db[dr] = value;
1178                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1179                         vcpu->arch.eff_db[dr] = value;
1180                 break;
1181         case 4:
1182                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1183                         return EMULATE_FAIL; /* will re-inject UD */
1184                 /* fall through */
1185         case 6:
1186                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1187                 break;
1188         case 5:
1189                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1190                         return EMULATE_FAIL; /* will re-inject UD */
1191                 /* fall through */
1192         case 7:
1193                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1194                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1195                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1196                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1197                 }
1198                 break;
1199         }
1200
1201         return EMULATE_DONE;
1202 }
1203
1204 static int pf_interception(struct vcpu_svm *svm)
1205 {
1206         u64 fault_address;
1207         u32 error_code;
1208
1209         fault_address  = svm->vmcb->control.exit_info_2;
1210         error_code = svm->vmcb->control.exit_info_1;
1211
1212         trace_kvm_page_fault(fault_address, error_code);
1213         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1214                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1215         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1216 }
1217
1218 static int db_interception(struct vcpu_svm *svm)
1219 {
1220         struct kvm_run *kvm_run = svm->vcpu.run;
1221
1222         if (!(svm->vcpu.guest_debug &
1223               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1224                 !svm->nmi_singlestep) {
1225                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1226                 return 1;
1227         }
1228
1229         if (svm->nmi_singlestep) {
1230                 svm->nmi_singlestep = false;
1231                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1232                         svm->vmcb->save.rflags &=
1233                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1234                 update_db_intercept(&svm->vcpu);
1235         }
1236
1237         if (svm->vcpu.guest_debug &
1238             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1239                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1240                 kvm_run->debug.arch.pc =
1241                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1242                 kvm_run->debug.arch.exception = DB_VECTOR;
1243                 return 0;
1244         }
1245
1246         return 1;
1247 }
1248
1249 static int bp_interception(struct vcpu_svm *svm)
1250 {
1251         struct kvm_run *kvm_run = svm->vcpu.run;
1252
1253         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1254         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1255         kvm_run->debug.arch.exception = BP_VECTOR;
1256         return 0;
1257 }
1258
1259 static int ud_interception(struct vcpu_svm *svm)
1260 {
1261         int er;
1262
1263         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1264         if (er != EMULATE_DONE)
1265                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1266         return 1;
1267 }
1268
1269 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1270 {
1271         struct vcpu_svm *svm = to_svm(vcpu);
1272         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1273         svm->vcpu.fpu_active = 1;
1274         update_cr0_intercept(svm);
1275 }
1276
1277 static int nm_interception(struct vcpu_svm *svm)
1278 {
1279         svm_fpu_activate(&svm->vcpu);
1280         return 1;
1281 }
1282
1283 static int mc_interception(struct vcpu_svm *svm)
1284 {
1285         /*
1286          * On an #MC intercept the MCE handler is not called automatically in
1287          * the host. So do it by hand here.
1288          */
1289         asm volatile (
1290                 "int $0x12\n");
1291         /* not sure if we ever come back to this point */
1292
1293         return 1;
1294 }
1295
1296 static int shutdown_interception(struct vcpu_svm *svm)
1297 {
1298         struct kvm_run *kvm_run = svm->vcpu.run;
1299
1300         /*
1301          * VMCB is undefined after a SHUTDOWN intercept
1302          * so reinitialize it.
1303          */
1304         clear_page(svm->vmcb);
1305         init_vmcb(svm);
1306
1307         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1308         return 0;
1309 }
1310
1311 static int io_interception(struct vcpu_svm *svm)
1312 {
1313         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1314         int size, in, string;
1315         unsigned port;
1316
1317         ++svm->vcpu.stat.io_exits;
1318
1319         svm->next_rip = svm->vmcb->control.exit_info_2;
1320
1321         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1322
1323         if (string) {
1324                 if (emulate_instruction(&svm->vcpu,
1325                                         0, 0, 0) == EMULATE_DO_MMIO)
1326                         return 0;
1327                 return 1;
1328         }
1329
1330         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1331         port = io_info >> 16;
1332         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1333
1334         skip_emulated_instruction(&svm->vcpu);
1335         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1336 }
1337
1338 static int nmi_interception(struct vcpu_svm *svm)
1339 {
1340         return 1;
1341 }
1342
1343 static int intr_interception(struct vcpu_svm *svm)
1344 {
1345         ++svm->vcpu.stat.irq_exits;
1346         return 1;
1347 }
1348
1349 static int nop_on_interception(struct vcpu_svm *svm)
1350 {
1351         return 1;
1352 }
1353
1354 static int halt_interception(struct vcpu_svm *svm)
1355 {
1356         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1357         skip_emulated_instruction(&svm->vcpu);
1358         return kvm_emulate_halt(&svm->vcpu);
1359 }
1360
1361 static int vmmcall_interception(struct vcpu_svm *svm)
1362 {
1363         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1364         skip_emulated_instruction(&svm->vcpu);
1365         kvm_emulate_hypercall(&svm->vcpu);
1366         return 1;
1367 }
1368
1369 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1370 {
1371         if (!(svm->vcpu.arch.efer & EFER_SVME)
1372             || !is_paging(&svm->vcpu)) {
1373                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1374                 return 1;
1375         }
1376
1377         if (svm->vmcb->save.cpl) {
1378                 kvm_inject_gp(&svm->vcpu, 0);
1379                 return 1;
1380         }
1381
1382        return 0;
1383 }
1384
1385 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1386                                       bool has_error_code, u32 error_code)
1387 {
1388         int vmexit;
1389
1390         if (!is_nested(svm))
1391                 return 0;
1392
1393         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1394         svm->vmcb->control.exit_code_hi = 0;
1395         svm->vmcb->control.exit_info_1 = error_code;
1396         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1397
1398         vmexit = nested_svm_intercept(svm);
1399         if (vmexit == NESTED_EXIT_DONE)
1400                 svm->nested.exit_required = true;
1401
1402         return vmexit;
1403 }
1404
1405 static inline int nested_svm_intr(struct vcpu_svm *svm)
1406 {
1407         if (!is_nested(svm))
1408                 return 0;
1409
1410         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1411                 return 0;
1412
1413         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1414                 return 0;
1415
1416         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1417
1418         if (svm->nested.intercept & 1ULL) {
1419                 /*
1420                  * The #vmexit can't be emulated here directly because this
1421                  * code path runs with irqs and preemtion disabled. A
1422                  * #vmexit emulation might sleep. Only signal request for
1423                  * the #vmexit here.
1424                  */
1425                 svm->nested.exit_required = true;
1426                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1427                 return 1;
1428         }
1429
1430         return 0;
1431 }
1432
1433 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1434 {
1435         struct page *page;
1436
1437         might_sleep();
1438
1439         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1440         if (is_error_page(page))
1441                 goto error;
1442
1443         *_page = page;
1444
1445         return kmap(page);
1446
1447 error:
1448         kvm_release_page_clean(page);
1449         kvm_inject_gp(&svm->vcpu, 0);
1450
1451         return NULL;
1452 }
1453
1454 static void nested_svm_unmap(struct page *page)
1455 {
1456         kunmap(page);
1457         kvm_release_page_dirty(page);
1458 }
1459
1460 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1461 {
1462         u32 param = svm->vmcb->control.exit_info_1 & 1;
1463         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1464         struct page *page;
1465         bool ret = false;
1466         u32 t0, t1;
1467         u8 *msrpm;
1468
1469         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1470                 return false;
1471
1472         msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
1473
1474         if (!msrpm)
1475                 goto out;
1476
1477         switch (msr) {
1478         case 0 ... 0x1fff:
1479                 t0 = (msr * 2) % 8;
1480                 t1 = msr / 8;
1481                 break;
1482         case 0xc0000000 ... 0xc0001fff:
1483                 t0 = (8192 + msr - 0xc0000000) * 2;
1484                 t1 = (t0 / 8);
1485                 t0 %= 8;
1486                 break;
1487         case 0xc0010000 ... 0xc0011fff:
1488                 t0 = (16384 + msr - 0xc0010000) * 2;
1489                 t1 = (t0 / 8);
1490                 t0 %= 8;
1491                 break;
1492         default:
1493                 ret = true;
1494                 goto out;
1495         }
1496
1497         ret = msrpm[t1] & ((1 << param) << t0);
1498
1499 out:
1500         nested_svm_unmap(page);
1501
1502         return ret;
1503 }
1504
1505 static int nested_svm_exit_special(struct vcpu_svm *svm)
1506 {
1507         u32 exit_code = svm->vmcb->control.exit_code;
1508
1509         switch (exit_code) {
1510         case SVM_EXIT_INTR:
1511         case SVM_EXIT_NMI:
1512                 return NESTED_EXIT_HOST;
1513                 /* For now we are always handling NPFs when using them */
1514         case SVM_EXIT_NPF:
1515                 if (npt_enabled)
1516                         return NESTED_EXIT_HOST;
1517                 break;
1518         /* When we're shadowing, trap PFs */
1519         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1520                 if (!npt_enabled)
1521                         return NESTED_EXIT_HOST;
1522                 break;
1523         default:
1524                 break;
1525         }
1526
1527         return NESTED_EXIT_CONTINUE;
1528 }
1529
1530 /*
1531  * If this function returns true, this #vmexit was already handled
1532  */
1533 static int nested_svm_intercept(struct vcpu_svm *svm)
1534 {
1535         u32 exit_code = svm->vmcb->control.exit_code;
1536         int vmexit = NESTED_EXIT_HOST;
1537
1538         switch (exit_code) {
1539         case SVM_EXIT_MSR:
1540                 vmexit = nested_svm_exit_handled_msr(svm);
1541                 break;
1542         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1543                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1544                 if (svm->nested.intercept_cr_read & cr_bits)
1545                         vmexit = NESTED_EXIT_DONE;
1546                 break;
1547         }
1548         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1549                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1550                 if (svm->nested.intercept_cr_write & cr_bits)
1551                         vmexit = NESTED_EXIT_DONE;
1552                 break;
1553         }
1554         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1555                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1556                 if (svm->nested.intercept_dr_read & dr_bits)
1557                         vmexit = NESTED_EXIT_DONE;
1558                 break;
1559         }
1560         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1561                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1562                 if (svm->nested.intercept_dr_write & dr_bits)
1563                         vmexit = NESTED_EXIT_DONE;
1564                 break;
1565         }
1566         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1567                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1568                 if (svm->nested.intercept_exceptions & excp_bits)
1569                         vmexit = NESTED_EXIT_DONE;
1570                 break;
1571         }
1572         default: {
1573                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1574                 if (svm->nested.intercept & exit_bits)
1575                         vmexit = NESTED_EXIT_DONE;
1576         }
1577         }
1578
1579         return vmexit;
1580 }
1581
1582 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1583 {
1584         int vmexit;
1585
1586         vmexit = nested_svm_intercept(svm);
1587
1588         if (vmexit == NESTED_EXIT_DONE)
1589                 nested_svm_vmexit(svm);
1590
1591         return vmexit;
1592 }
1593
1594 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1595 {
1596         struct vmcb_control_area *dst  = &dst_vmcb->control;
1597         struct vmcb_control_area *from = &from_vmcb->control;
1598
1599         dst->intercept_cr_read    = from->intercept_cr_read;
1600         dst->intercept_cr_write   = from->intercept_cr_write;
1601         dst->intercept_dr_read    = from->intercept_dr_read;
1602         dst->intercept_dr_write   = from->intercept_dr_write;
1603         dst->intercept_exceptions = from->intercept_exceptions;
1604         dst->intercept            = from->intercept;
1605         dst->iopm_base_pa         = from->iopm_base_pa;
1606         dst->msrpm_base_pa        = from->msrpm_base_pa;
1607         dst->tsc_offset           = from->tsc_offset;
1608         dst->asid                 = from->asid;
1609         dst->tlb_ctl              = from->tlb_ctl;
1610         dst->int_ctl              = from->int_ctl;
1611         dst->int_vector           = from->int_vector;
1612         dst->int_state            = from->int_state;
1613         dst->exit_code            = from->exit_code;
1614         dst->exit_code_hi         = from->exit_code_hi;
1615         dst->exit_info_1          = from->exit_info_1;
1616         dst->exit_info_2          = from->exit_info_2;
1617         dst->exit_int_info        = from->exit_int_info;
1618         dst->exit_int_info_err    = from->exit_int_info_err;
1619         dst->nested_ctl           = from->nested_ctl;
1620         dst->event_inj            = from->event_inj;
1621         dst->event_inj_err        = from->event_inj_err;
1622         dst->nested_cr3           = from->nested_cr3;
1623         dst->lbr_ctl              = from->lbr_ctl;
1624 }
1625
1626 static int nested_svm_vmexit(struct vcpu_svm *svm)
1627 {
1628         struct vmcb *nested_vmcb;
1629         struct vmcb *hsave = svm->nested.hsave;
1630         struct vmcb *vmcb = svm->vmcb;
1631         struct page *page;
1632
1633         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1634                                        vmcb->control.exit_info_1,
1635                                        vmcb->control.exit_info_2,
1636                                        vmcb->control.exit_int_info,
1637                                        vmcb->control.exit_int_info_err);
1638
1639         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1640         if (!nested_vmcb)
1641                 return 1;
1642
1643         /* Give the current vmcb to the guest */
1644         disable_gif(svm);
1645
1646         nested_vmcb->save.es     = vmcb->save.es;
1647         nested_vmcb->save.cs     = vmcb->save.cs;
1648         nested_vmcb->save.ss     = vmcb->save.ss;
1649         nested_vmcb->save.ds     = vmcb->save.ds;
1650         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1651         nested_vmcb->save.idtr   = vmcb->save.idtr;
1652         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1653         if (npt_enabled)
1654                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1655         else
1656                 nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1657         nested_vmcb->save.cr2    = vmcb->save.cr2;
1658         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1659         nested_vmcb->save.rflags = vmcb->save.rflags;
1660         nested_vmcb->save.rip    = vmcb->save.rip;
1661         nested_vmcb->save.rsp    = vmcb->save.rsp;
1662         nested_vmcb->save.rax    = vmcb->save.rax;
1663         nested_vmcb->save.dr7    = vmcb->save.dr7;
1664         nested_vmcb->save.dr6    = vmcb->save.dr6;
1665         nested_vmcb->save.cpl    = vmcb->save.cpl;
1666
1667         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1668         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1669         nested_vmcb->control.int_state         = vmcb->control.int_state;
1670         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1671         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1672         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1673         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1674         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1675         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1676
1677         /*
1678          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1679          * to make sure that we do not lose injected events. So check event_inj
1680          * here and copy it to exit_int_info if it is valid.
1681          * Exit_int_info and event_inj can't be both valid because the case
1682          * below only happens on a VMRUN instruction intercept which has
1683          * no valid exit_int_info set.
1684          */
1685         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1686                 struct vmcb_control_area *nc = &nested_vmcb->control;
1687
1688                 nc->exit_int_info     = vmcb->control.event_inj;
1689                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1690         }
1691
1692         nested_vmcb->control.tlb_ctl           = 0;
1693         nested_vmcb->control.event_inj         = 0;
1694         nested_vmcb->control.event_inj_err     = 0;
1695
1696         /* We always set V_INTR_MASKING and remember the old value in hflags */
1697         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1698                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1699
1700         /* Restore the original control entries */
1701         copy_vmcb_control_area(vmcb, hsave);
1702
1703         kvm_clear_exception_queue(&svm->vcpu);
1704         kvm_clear_interrupt_queue(&svm->vcpu);
1705
1706         /* Restore selected save entries */
1707         svm->vmcb->save.es = hsave->save.es;
1708         svm->vmcb->save.cs = hsave->save.cs;
1709         svm->vmcb->save.ss = hsave->save.ss;
1710         svm->vmcb->save.ds = hsave->save.ds;
1711         svm->vmcb->save.gdtr = hsave->save.gdtr;
1712         svm->vmcb->save.idtr = hsave->save.idtr;
1713         svm->vmcb->save.rflags = hsave->save.rflags;
1714         svm_set_efer(&svm->vcpu, hsave->save.efer);
1715         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1716         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1717         if (npt_enabled) {
1718                 svm->vmcb->save.cr3 = hsave->save.cr3;
1719                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1720         } else {
1721                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1722         }
1723         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1724         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1725         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1726         svm->vmcb->save.dr7 = 0;
1727         svm->vmcb->save.cpl = 0;
1728         svm->vmcb->control.exit_int_info = 0;
1729
1730         /* Exit nested SVM mode */
1731         svm->nested.vmcb = 0;
1732
1733         nested_svm_unmap(page);
1734
1735         kvm_mmu_reset_context(&svm->vcpu);
1736         kvm_mmu_load(&svm->vcpu);
1737
1738         return 0;
1739 }
1740
1741 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1742 {
1743         u32 *nested_msrpm;
1744         struct page *page;
1745         int i;
1746
1747         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
1748         if (!nested_msrpm)
1749                 return false;
1750
1751         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1752                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1753
1754         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1755
1756         nested_svm_unmap(page);
1757
1758         return true;
1759 }
1760
1761 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1762 {
1763         struct vmcb *nested_vmcb;
1764         struct vmcb *hsave = svm->nested.hsave;
1765         struct vmcb *vmcb = svm->vmcb;
1766         struct page *page;
1767
1768         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1769         if (!nested_vmcb)
1770                 return false;
1771
1772         /* nested_vmcb is our indicator if nested SVM is activated */
1773         svm->nested.vmcb = svm->vmcb->save.rax;
1774
1775         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1776                                nested_vmcb->save.rip,
1777                                nested_vmcb->control.int_ctl,
1778                                nested_vmcb->control.event_inj,
1779                                nested_vmcb->control.nested_ctl);
1780
1781         /* Clear internal status */
1782         kvm_clear_exception_queue(&svm->vcpu);
1783         kvm_clear_interrupt_queue(&svm->vcpu);
1784
1785         /* Save the old vmcb, so we don't need to pick what we save, but
1786            can restore everything when a VMEXIT occurs */
1787         hsave->save.es     = vmcb->save.es;
1788         hsave->save.cs     = vmcb->save.cs;
1789         hsave->save.ss     = vmcb->save.ss;
1790         hsave->save.ds     = vmcb->save.ds;
1791         hsave->save.gdtr   = vmcb->save.gdtr;
1792         hsave->save.idtr   = vmcb->save.idtr;
1793         hsave->save.efer   = svm->vcpu.arch.efer;
1794         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
1795         hsave->save.cr4    = svm->vcpu.arch.cr4;
1796         hsave->save.rflags = vmcb->save.rflags;
1797         hsave->save.rip    = svm->next_rip;
1798         hsave->save.rsp    = vmcb->save.rsp;
1799         hsave->save.rax    = vmcb->save.rax;
1800         if (npt_enabled)
1801                 hsave->save.cr3    = vmcb->save.cr3;
1802         else
1803                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1804
1805         copy_vmcb_control_area(hsave, vmcb);
1806
1807         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1808                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1809         else
1810                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1811
1812         /* Load the nested guest state */
1813         svm->vmcb->save.es = nested_vmcb->save.es;
1814         svm->vmcb->save.cs = nested_vmcb->save.cs;
1815         svm->vmcb->save.ss = nested_vmcb->save.ss;
1816         svm->vmcb->save.ds = nested_vmcb->save.ds;
1817         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1818         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1819         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1820         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1821         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1822         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1823         if (npt_enabled) {
1824                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1825                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1826         } else {
1827                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1828                 kvm_mmu_reset_context(&svm->vcpu);
1829         }
1830         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1831         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1832         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1833         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1834         /* In case we don't even reach vcpu_run, the fields are not updated */
1835         svm->vmcb->save.rax = nested_vmcb->save.rax;
1836         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1837         svm->vmcb->save.rip = nested_vmcb->save.rip;
1838         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1839         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1840         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1841
1842         /* We don't want a nested guest to be more powerful than the guest,
1843            so all intercepts are ORed */
1844         svm->vmcb->control.intercept_cr_read |=
1845                 nested_vmcb->control.intercept_cr_read;
1846         svm->vmcb->control.intercept_cr_write |=
1847                 nested_vmcb->control.intercept_cr_write;
1848         svm->vmcb->control.intercept_dr_read |=
1849                 nested_vmcb->control.intercept_dr_read;
1850         svm->vmcb->control.intercept_dr_write |=
1851                 nested_vmcb->control.intercept_dr_write;
1852         svm->vmcb->control.intercept_exceptions |=
1853                 nested_vmcb->control.intercept_exceptions;
1854
1855         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1856
1857         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1858
1859         /* cache intercepts */
1860         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1861         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1862         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1863         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1864         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1865         svm->nested.intercept            = nested_vmcb->control.intercept;
1866
1867         force_new_asid(&svm->vcpu);
1868         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1869         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1870                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1871         else
1872                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1873
1874         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1875         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1876         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1877         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1878         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1879
1880         nested_svm_unmap(page);
1881
1882         enable_gif(svm);
1883
1884         return true;
1885 }
1886
1887 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1888 {
1889         to_vmcb->save.fs = from_vmcb->save.fs;
1890         to_vmcb->save.gs = from_vmcb->save.gs;
1891         to_vmcb->save.tr = from_vmcb->save.tr;
1892         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1893         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1894         to_vmcb->save.star = from_vmcb->save.star;
1895         to_vmcb->save.lstar = from_vmcb->save.lstar;
1896         to_vmcb->save.cstar = from_vmcb->save.cstar;
1897         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1898         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1899         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1900         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1901 }
1902
1903 static int vmload_interception(struct vcpu_svm *svm)
1904 {
1905         struct vmcb *nested_vmcb;
1906         struct page *page;
1907
1908         if (nested_svm_check_permissions(svm))
1909                 return 1;
1910
1911         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1912         skip_emulated_instruction(&svm->vcpu);
1913
1914         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1915         if (!nested_vmcb)
1916                 return 1;
1917
1918         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1919         nested_svm_unmap(page);
1920
1921         return 1;
1922 }
1923
1924 static int vmsave_interception(struct vcpu_svm *svm)
1925 {
1926         struct vmcb *nested_vmcb;
1927         struct page *page;
1928
1929         if (nested_svm_check_permissions(svm))
1930                 return 1;
1931
1932         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1933         skip_emulated_instruction(&svm->vcpu);
1934
1935         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1936         if (!nested_vmcb)
1937                 return 1;
1938
1939         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1940         nested_svm_unmap(page);
1941
1942         return 1;
1943 }
1944
1945 static int vmrun_interception(struct vcpu_svm *svm)
1946 {
1947         if (nested_svm_check_permissions(svm))
1948                 return 1;
1949
1950         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1951         skip_emulated_instruction(&svm->vcpu);
1952
1953         if (!nested_svm_vmrun(svm))
1954                 return 1;
1955
1956         if (!nested_svm_vmrun_msrpm(svm))
1957                 goto failed;
1958
1959         return 1;
1960
1961 failed:
1962
1963         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
1964         svm->vmcb->control.exit_code_hi = 0;
1965         svm->vmcb->control.exit_info_1  = 0;
1966         svm->vmcb->control.exit_info_2  = 0;
1967
1968         nested_svm_vmexit(svm);
1969
1970         return 1;
1971 }
1972
1973 static int stgi_interception(struct vcpu_svm *svm)
1974 {
1975         if (nested_svm_check_permissions(svm))
1976                 return 1;
1977
1978         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1979         skip_emulated_instruction(&svm->vcpu);
1980
1981         enable_gif(svm);
1982
1983         return 1;
1984 }
1985
1986 static int clgi_interception(struct vcpu_svm *svm)
1987 {
1988         if (nested_svm_check_permissions(svm))
1989                 return 1;
1990
1991         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1992         skip_emulated_instruction(&svm->vcpu);
1993
1994         disable_gif(svm);
1995
1996         /* After a CLGI no interrupts should come */
1997         svm_clear_vintr(svm);
1998         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1999
2000         return 1;
2001 }
2002
2003 static int invlpga_interception(struct vcpu_svm *svm)
2004 {
2005         struct kvm_vcpu *vcpu = &svm->vcpu;
2006
2007         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2008                           vcpu->arch.regs[VCPU_REGS_RAX]);
2009
2010         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2011         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2012
2013         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2014         skip_emulated_instruction(&svm->vcpu);
2015         return 1;
2016 }
2017
2018 static int skinit_interception(struct vcpu_svm *svm)
2019 {
2020         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2021
2022         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2023         return 1;
2024 }
2025
2026 static int invalid_op_interception(struct vcpu_svm *svm)
2027 {
2028         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2029         return 1;
2030 }
2031
2032 static int task_switch_interception(struct vcpu_svm *svm)
2033 {
2034         u16 tss_selector;
2035         int reason;
2036         int int_type = svm->vmcb->control.exit_int_info &
2037                 SVM_EXITINTINFO_TYPE_MASK;
2038         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2039         uint32_t type =
2040                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2041         uint32_t idt_v =
2042                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2043
2044         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2045
2046         if (svm->vmcb->control.exit_info_2 &
2047             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2048                 reason = TASK_SWITCH_IRET;
2049         else if (svm->vmcb->control.exit_info_2 &
2050                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2051                 reason = TASK_SWITCH_JMP;
2052         else if (idt_v)
2053                 reason = TASK_SWITCH_GATE;
2054         else
2055                 reason = TASK_SWITCH_CALL;
2056
2057         if (reason == TASK_SWITCH_GATE) {
2058                 switch (type) {
2059                 case SVM_EXITINTINFO_TYPE_NMI:
2060                         svm->vcpu.arch.nmi_injected = false;
2061                         break;
2062                 case SVM_EXITINTINFO_TYPE_EXEPT:
2063                         kvm_clear_exception_queue(&svm->vcpu);
2064                         break;
2065                 case SVM_EXITINTINFO_TYPE_INTR:
2066                         kvm_clear_interrupt_queue(&svm->vcpu);
2067                         break;
2068                 default:
2069                         break;
2070                 }
2071         }
2072
2073         if (reason != TASK_SWITCH_GATE ||
2074             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2075             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2076              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2077                 skip_emulated_instruction(&svm->vcpu);
2078
2079         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2080 }
2081
2082 static int cpuid_interception(struct vcpu_svm *svm)
2083 {
2084         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2085         kvm_emulate_cpuid(&svm->vcpu);
2086         return 1;
2087 }
2088
2089 static int iret_interception(struct vcpu_svm *svm)
2090 {
2091         ++svm->vcpu.stat.nmi_window_exits;
2092         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2093         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2094         return 1;
2095 }
2096
2097 static int invlpg_interception(struct vcpu_svm *svm)
2098 {
2099         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2100                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2101         return 1;
2102 }
2103
2104 static int emulate_on_interception(struct vcpu_svm *svm)
2105 {
2106         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2107                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2108         return 1;
2109 }
2110
2111 static int cr8_write_interception(struct vcpu_svm *svm)
2112 {
2113         struct kvm_run *kvm_run = svm->vcpu.run;
2114
2115         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2116         /* instruction emulation calls kvm_set_cr8() */
2117         emulate_instruction(&svm->vcpu, 0, 0, 0);
2118         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2119                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2120                 return 1;
2121         }
2122         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2123                 return 1;
2124         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2125         return 0;
2126 }
2127
2128 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2129 {
2130         struct vcpu_svm *svm = to_svm(vcpu);
2131
2132         switch (ecx) {
2133         case MSR_IA32_TSC: {
2134                 u64 tsc_offset;
2135
2136                 if (is_nested(svm))
2137                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2138                 else
2139                         tsc_offset = svm->vmcb->control.tsc_offset;
2140
2141                 *data = tsc_offset + native_read_tsc();
2142                 break;
2143         }
2144         case MSR_K6_STAR:
2145                 *data = svm->vmcb->save.star;
2146                 break;
2147 #ifdef CONFIG_X86_64
2148         case MSR_LSTAR:
2149                 *data = svm->vmcb->save.lstar;
2150                 break;
2151         case MSR_CSTAR:
2152                 *data = svm->vmcb->save.cstar;
2153                 break;
2154         case MSR_KERNEL_GS_BASE:
2155                 *data = svm->vmcb->save.kernel_gs_base;
2156                 break;
2157         case MSR_SYSCALL_MASK:
2158                 *data = svm->vmcb->save.sfmask;
2159                 break;
2160 #endif
2161         case MSR_IA32_SYSENTER_CS:
2162                 *data = svm->vmcb->save.sysenter_cs;
2163                 break;
2164         case MSR_IA32_SYSENTER_EIP:
2165                 *data = svm->sysenter_eip;
2166                 break;
2167         case MSR_IA32_SYSENTER_ESP:
2168                 *data = svm->sysenter_esp;
2169                 break;
2170         /* Nobody will change the following 5 values in the VMCB so
2171            we can safely return them on rdmsr. They will always be 0
2172            until LBRV is implemented. */
2173         case MSR_IA32_DEBUGCTLMSR:
2174                 *data = svm->vmcb->save.dbgctl;
2175                 break;
2176         case MSR_IA32_LASTBRANCHFROMIP:
2177                 *data = svm->vmcb->save.br_from;
2178                 break;
2179         case MSR_IA32_LASTBRANCHTOIP:
2180                 *data = svm->vmcb->save.br_to;
2181                 break;
2182         case MSR_IA32_LASTINTFROMIP:
2183                 *data = svm->vmcb->save.last_excp_from;
2184                 break;
2185         case MSR_IA32_LASTINTTOIP:
2186                 *data = svm->vmcb->save.last_excp_to;
2187                 break;
2188         case MSR_VM_HSAVE_PA:
2189                 *data = svm->nested.hsave_msr;
2190                 break;
2191         case MSR_VM_CR:
2192                 *data = 0;
2193                 break;
2194         case MSR_IA32_UCODE_REV:
2195                 *data = 0x01000065;
2196                 break;
2197         default:
2198                 return kvm_get_msr_common(vcpu, ecx, data);
2199         }
2200         return 0;
2201 }
2202
2203 static int rdmsr_interception(struct vcpu_svm *svm)
2204 {
2205         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2206         u64 data;
2207
2208         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2209                 trace_kvm_msr_read_ex(ecx);
2210                 kvm_inject_gp(&svm->vcpu, 0);
2211         } else {
2212                 trace_kvm_msr_read(ecx, data);
2213
2214                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2215                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2216                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2217                 skip_emulated_instruction(&svm->vcpu);
2218         }
2219         return 1;
2220 }
2221
2222 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2223 {
2224         struct vcpu_svm *svm = to_svm(vcpu);
2225
2226         switch (ecx) {
2227         case MSR_IA32_TSC: {
2228                 u64 tsc_offset = data - native_read_tsc();
2229                 u64 g_tsc_offset = 0;
2230
2231                 if (is_nested(svm)) {
2232                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2233                                        svm->nested.hsave->control.tsc_offset;
2234                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2235                 }
2236
2237                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2238
2239                 break;
2240         }
2241         case MSR_K6_STAR:
2242                 svm->vmcb->save.star = data;
2243                 break;
2244 #ifdef CONFIG_X86_64
2245         case MSR_LSTAR:
2246                 svm->vmcb->save.lstar = data;
2247                 break;
2248         case MSR_CSTAR:
2249                 svm->vmcb->save.cstar = data;
2250                 break;
2251         case MSR_KERNEL_GS_BASE:
2252                 svm->vmcb->save.kernel_gs_base = data;
2253                 break;
2254         case MSR_SYSCALL_MASK:
2255                 svm->vmcb->save.sfmask = data;
2256                 break;
2257 #endif
2258         case MSR_IA32_SYSENTER_CS:
2259                 svm->vmcb->save.sysenter_cs = data;
2260                 break;
2261         case MSR_IA32_SYSENTER_EIP:
2262                 svm->sysenter_eip = data;
2263                 svm->vmcb->save.sysenter_eip = data;
2264                 break;
2265         case MSR_IA32_SYSENTER_ESP:
2266                 svm->sysenter_esp = data;
2267                 svm->vmcb->save.sysenter_esp = data;
2268                 break;
2269         case MSR_IA32_DEBUGCTLMSR:
2270                 if (!svm_has(SVM_FEATURE_LBRV)) {
2271                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2272                                         __func__, data);
2273                         break;
2274                 }
2275                 if (data & DEBUGCTL_RESERVED_BITS)
2276                         return 1;
2277
2278                 svm->vmcb->save.dbgctl = data;
2279                 if (data & (1ULL<<0))
2280                         svm_enable_lbrv(svm);
2281                 else
2282                         svm_disable_lbrv(svm);
2283                 break;
2284         case MSR_VM_HSAVE_PA:
2285                 svm->nested.hsave_msr = data;
2286                 break;
2287         case MSR_VM_CR:
2288         case MSR_VM_IGNNE:
2289                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2290                 break;
2291         default:
2292                 return kvm_set_msr_common(vcpu, ecx, data);
2293         }
2294         return 0;
2295 }
2296
2297 static int wrmsr_interception(struct vcpu_svm *svm)
2298 {
2299         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2300         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2301                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2302
2303
2304         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2305         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2306                 trace_kvm_msr_write_ex(ecx, data);
2307                 kvm_inject_gp(&svm->vcpu, 0);
2308         } else {
2309                 trace_kvm_msr_write(ecx, data);
2310                 skip_emulated_instruction(&svm->vcpu);
2311         }
2312         return 1;
2313 }
2314
2315 static int msr_interception(struct vcpu_svm *svm)
2316 {
2317         if (svm->vmcb->control.exit_info_1)
2318                 return wrmsr_interception(svm);
2319         else
2320                 return rdmsr_interception(svm);
2321 }
2322
2323 static int interrupt_window_interception(struct vcpu_svm *svm)
2324 {
2325         struct kvm_run *kvm_run = svm->vcpu.run;
2326
2327         svm_clear_vintr(svm);
2328         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2329         /*
2330          * If the user space waits to inject interrupts, exit as soon as
2331          * possible
2332          */
2333         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2334             kvm_run->request_interrupt_window &&
2335             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2336                 ++svm->vcpu.stat.irq_window_exits;
2337                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2338                 return 0;
2339         }
2340
2341         return 1;
2342 }
2343
2344 static int pause_interception(struct vcpu_svm *svm)
2345 {
2346         kvm_vcpu_on_spin(&(svm->vcpu));
2347         return 1;
2348 }
2349
2350 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2351         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2352         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2353         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2354         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2355         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2356         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2357         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2358         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2359         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2360         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2361         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2362         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2363         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2364         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2365         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2366         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2367         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2368         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2369         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2370         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2371         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2372         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2373         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2374         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2375         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2376         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2377         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2378         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2379         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2380         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2381         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2382         [SVM_EXIT_INTR]                         = intr_interception,
2383         [SVM_EXIT_NMI]                          = nmi_interception,
2384         [SVM_EXIT_SMI]                          = nop_on_interception,
2385         [SVM_EXIT_INIT]                         = nop_on_interception,
2386         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2387         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2388         [SVM_EXIT_CPUID]                        = cpuid_interception,
2389         [SVM_EXIT_IRET]                         = iret_interception,
2390         [SVM_EXIT_INVD]                         = emulate_on_interception,
2391         [SVM_EXIT_PAUSE]                        = pause_interception,
2392         [SVM_EXIT_HLT]                          = halt_interception,
2393         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2394         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2395         [SVM_EXIT_IOIO]                         = io_interception,
2396         [SVM_EXIT_MSR]                          = msr_interception,
2397         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2398         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2399         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2400         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2401         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2402         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2403         [SVM_EXIT_STGI]                         = stgi_interception,
2404         [SVM_EXIT_CLGI]                         = clgi_interception,
2405         [SVM_EXIT_SKINIT]                       = skinit_interception,
2406         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2407         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2408         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2409         [SVM_EXIT_NPF]                          = pf_interception,
2410 };
2411
2412 static int handle_exit(struct kvm_vcpu *vcpu)
2413 {
2414         struct vcpu_svm *svm = to_svm(vcpu);
2415         struct kvm_run *kvm_run = vcpu->run;
2416         u32 exit_code = svm->vmcb->control.exit_code;
2417
2418         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2419
2420         if (unlikely(svm->nested.exit_required)) {
2421                 nested_svm_vmexit(svm);
2422                 svm->nested.exit_required = false;
2423
2424                 return 1;
2425         }
2426
2427         if (is_nested(svm)) {
2428                 int vmexit;
2429
2430                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2431                                         svm->vmcb->control.exit_info_1,
2432                                         svm->vmcb->control.exit_info_2,
2433                                         svm->vmcb->control.exit_int_info,
2434                                         svm->vmcb->control.exit_int_info_err);
2435
2436                 vmexit = nested_svm_exit_special(svm);
2437
2438                 if (vmexit == NESTED_EXIT_CONTINUE)
2439                         vmexit = nested_svm_exit_handled(svm);
2440
2441                 if (vmexit == NESTED_EXIT_DONE)
2442                         return 1;
2443         }
2444
2445         svm_complete_interrupts(svm);
2446
2447         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2448                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2449         if (npt_enabled)
2450                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2451
2452         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2453                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2454                 kvm_run->fail_entry.hardware_entry_failure_reason
2455                         = svm->vmcb->control.exit_code;
2456                 return 0;
2457         }
2458
2459         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2460             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2461             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2462                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2463                        "exit_code 0x%x\n",
2464                        __func__, svm->vmcb->control.exit_int_info,
2465                        exit_code);
2466
2467         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2468             || !svm_exit_handlers[exit_code]) {
2469                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2470                 kvm_run->hw.hardware_exit_reason = exit_code;
2471                 return 0;
2472         }
2473
2474         return svm_exit_handlers[exit_code](svm);
2475 }
2476
2477 static void reload_tss(struct kvm_vcpu *vcpu)
2478 {
2479         int cpu = raw_smp_processor_id();
2480
2481         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2482         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2483         load_TR_desc();
2484 }
2485
2486 static void pre_svm_run(struct vcpu_svm *svm)
2487 {
2488         int cpu = raw_smp_processor_id();
2489
2490         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2491
2492         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2493         /* FIXME: handle wraparound of asid_generation */
2494         if (svm->asid_generation != sd->asid_generation)
2495                 new_asid(svm, sd);
2496 }
2497
2498 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2499 {
2500         struct vcpu_svm *svm = to_svm(vcpu);
2501
2502         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2503         vcpu->arch.hflags |= HF_NMI_MASK;
2504         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2505         ++vcpu->stat.nmi_injections;
2506 }
2507
2508 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2509 {
2510         struct vmcb_control_area *control;
2511
2512         trace_kvm_inj_virq(irq);
2513
2514         ++svm->vcpu.stat.irq_injections;
2515         control = &svm->vmcb->control;
2516         control->int_vector = irq;
2517         control->int_ctl &= ~V_INTR_PRIO_MASK;
2518         control->int_ctl |= V_IRQ_MASK |
2519                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2520 }
2521
2522 static void svm_set_irq(struct kvm_vcpu *vcpu)
2523 {
2524         struct vcpu_svm *svm = to_svm(vcpu);
2525
2526         BUG_ON(!(gif_set(svm)));
2527
2528         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2529                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2530 }
2531
2532 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2533 {
2534         struct vcpu_svm *svm = to_svm(vcpu);
2535
2536         if (irr == -1)
2537                 return;
2538
2539         if (tpr >= irr)
2540                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2541 }
2542
2543 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2544 {
2545         struct vcpu_svm *svm = to_svm(vcpu);
2546         struct vmcb *vmcb = svm->vmcb;
2547         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2548                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2549 }
2550
2551 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2552 {
2553         struct vcpu_svm *svm = to_svm(vcpu);
2554
2555         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2556 }
2557
2558 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2559 {
2560         struct vcpu_svm *svm = to_svm(vcpu);
2561
2562         if (masked) {
2563                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2564                 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2565         } else {
2566                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2567                 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2568         }
2569 }
2570
2571 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2572 {
2573         struct vcpu_svm *svm = to_svm(vcpu);
2574         struct vmcb *vmcb = svm->vmcb;
2575         int ret;
2576
2577         if (!gif_set(svm) ||
2578              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2579                 return 0;
2580
2581         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2582
2583         if (is_nested(svm))
2584                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2585
2586         return ret;
2587 }
2588
2589 static void enable_irq_window(struct kvm_vcpu *vcpu)
2590 {
2591         struct vcpu_svm *svm = to_svm(vcpu);
2592
2593         nested_svm_intr(svm);
2594
2595         /* In case GIF=0 we can't rely on the CPU to tell us when
2596          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2597          * The next time we get that intercept, this function will be
2598          * called again though and we'll get the vintr intercept. */
2599         if (gif_set(svm)) {
2600                 svm_set_vintr(svm);
2601                 svm_inject_irq(svm, 0x0);
2602         }
2603 }
2604
2605 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2606 {
2607         struct vcpu_svm *svm = to_svm(vcpu);
2608
2609         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2610             == HF_NMI_MASK)
2611                 return; /* IRET will cause a vm exit */
2612
2613         /* Something prevents NMI from been injected. Single step over
2614            possible problem (IRET or exception injection or interrupt
2615            shadow) */
2616         svm->nmi_singlestep = true;
2617         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2618         update_db_intercept(vcpu);
2619 }
2620
2621 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2622 {
2623         return 0;
2624 }
2625
2626 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2627 {
2628         force_new_asid(vcpu);
2629 }
2630
2631 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2632 {
2633 }
2634
2635 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2636 {
2637         struct vcpu_svm *svm = to_svm(vcpu);
2638
2639         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2640                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2641                 kvm_set_cr8(vcpu, cr8);
2642         }
2643 }
2644
2645 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2646 {
2647         struct vcpu_svm *svm = to_svm(vcpu);
2648         u64 cr8;
2649
2650         cr8 = kvm_get_cr8(vcpu);
2651         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2652         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2653 }
2654
2655 static void svm_complete_interrupts(struct vcpu_svm *svm)
2656 {
2657         u8 vector;
2658         int type;
2659         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2660
2661         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2662                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2663
2664         svm->vcpu.arch.nmi_injected = false;
2665         kvm_clear_exception_queue(&svm->vcpu);
2666         kvm_clear_interrupt_queue(&svm->vcpu);
2667
2668         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2669                 return;
2670
2671         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2672         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2673
2674         switch (type) {
2675         case SVM_EXITINTINFO_TYPE_NMI:
2676                 svm->vcpu.arch.nmi_injected = true;
2677                 break;
2678         case SVM_EXITINTINFO_TYPE_EXEPT:
2679                 /* In case of software exception do not reinject an exception
2680                    vector, but re-execute and instruction instead */
2681                 if (is_nested(svm))
2682                         break;
2683                 if (kvm_exception_is_soft(vector))
2684                         break;
2685                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2686                         u32 err = svm->vmcb->control.exit_int_info_err;
2687                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2688
2689                 } else
2690                         kvm_queue_exception(&svm->vcpu, vector);
2691                 break;
2692         case SVM_EXITINTINFO_TYPE_INTR:
2693                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2694                 break;
2695         default:
2696                 break;
2697         }
2698 }
2699
2700 #ifdef CONFIG_X86_64
2701 #define R "r"
2702 #else
2703 #define R "e"
2704 #endif
2705
2706 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2707 {
2708         struct vcpu_svm *svm = to_svm(vcpu);
2709         u16 fs_selector;
2710         u16 gs_selector;
2711         u16 ldt_selector;
2712
2713         /*
2714          * A vmexit emulation is required before the vcpu can be executed
2715          * again.
2716          */
2717         if (unlikely(svm->nested.exit_required))
2718                 return;
2719
2720         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2721         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2722         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2723
2724         pre_svm_run(svm);
2725
2726         sync_lapic_to_cr8(vcpu);
2727
2728         save_host_msrs(vcpu);
2729         fs_selector = kvm_read_fs();
2730         gs_selector = kvm_read_gs();
2731         ldt_selector = kvm_read_ldt();
2732         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2733         /* required for live migration with NPT */
2734         if (npt_enabled)
2735                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2736
2737         clgi();
2738
2739         local_irq_enable();
2740
2741         asm volatile (
2742                 "push %%"R"bp; \n\t"
2743                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2744                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2745                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2746                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2747                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2748                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2749 #ifdef CONFIG_X86_64
2750                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2751                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2752                 "mov %c[r10](%[svm]), %%r10 \n\t"
2753                 "mov %c[r11](%[svm]), %%r11 \n\t"
2754                 "mov %c[r12](%[svm]), %%r12 \n\t"
2755                 "mov %c[r13](%[svm]), %%r13 \n\t"
2756                 "mov %c[r14](%[svm]), %%r14 \n\t"
2757                 "mov %c[r15](%[svm]), %%r15 \n\t"
2758 #endif
2759
2760                 /* Enter guest mode */
2761                 "push %%"R"ax \n\t"
2762                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2763                 __ex(SVM_VMLOAD) "\n\t"
2764                 __ex(SVM_VMRUN) "\n\t"
2765                 __ex(SVM_VMSAVE) "\n\t"
2766                 "pop %%"R"ax \n\t"
2767
2768                 /* Save guest registers, load host registers */
2769                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2770                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2771                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2772                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2773                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2774                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2775 #ifdef CONFIG_X86_64
2776                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2777                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2778                 "mov %%r10, %c[r10](%[svm]) \n\t"
2779                 "mov %%r11, %c[r11](%[svm]) \n\t"
2780                 "mov %%r12, %c[r12](%[svm]) \n\t"
2781                 "mov %%r13, %c[r13](%[svm]) \n\t"
2782                 "mov %%r14, %c[r14](%[svm]) \n\t"
2783                 "mov %%r15, %c[r15](%[svm]) \n\t"
2784 #endif
2785                 "pop %%"R"bp"
2786                 :
2787                 : [svm]"a"(svm),
2788                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2789                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2790                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2791                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2792                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2793                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2794                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2795 #ifdef CONFIG_X86_64
2796                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2797                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2798                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2799                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2800                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2801                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2802                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2803                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2804 #endif
2805                 : "cc", "memory"
2806                 , R"bx", R"cx", R"dx", R"si", R"di"
2807 #ifdef CONFIG_X86_64
2808                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2809 #endif
2810                 );
2811
2812         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2813         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2814         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2815         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2816
2817         kvm_load_fs(fs_selector);
2818         kvm_load_gs(gs_selector);
2819         kvm_load_ldt(ldt_selector);
2820         load_host_msrs(vcpu);
2821
2822         reload_tss(vcpu);
2823
2824         local_irq_disable();
2825
2826         stgi();
2827
2828         sync_cr8_to_lapic(vcpu);
2829
2830         svm->next_rip = 0;
2831
2832         if (npt_enabled) {
2833                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2834                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2835         }
2836 }
2837
2838 #undef R
2839
2840 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2841 {
2842         struct vcpu_svm *svm = to_svm(vcpu);
2843
2844         if (npt_enabled) {
2845                 svm->vmcb->control.nested_cr3 = root;
2846                 force_new_asid(vcpu);
2847                 return;
2848         }
2849
2850         svm->vmcb->save.cr3 = root;
2851         force_new_asid(vcpu);
2852 }
2853
2854 static int is_disabled(void)
2855 {
2856         u64 vm_cr;
2857
2858         rdmsrl(MSR_VM_CR, vm_cr);
2859         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2860                 return 1;
2861
2862         return 0;
2863 }
2864
2865 static void
2866 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2867 {
2868         /*
2869          * Patch in the VMMCALL instruction:
2870          */
2871         hypercall[0] = 0x0f;
2872         hypercall[1] = 0x01;
2873         hypercall[2] = 0xd9;
2874 }
2875
2876 static void svm_check_processor_compat(void *rtn)
2877 {
2878         *(int *)rtn = 0;
2879 }
2880
2881 static bool svm_cpu_has_accelerated_tpr(void)
2882 {
2883         return false;
2884 }
2885
2886 static int get_npt_level(void)
2887 {
2888 #ifdef CONFIG_X86_64
2889         return PT64_ROOT_LEVEL;
2890 #else
2891         return PT32E_ROOT_LEVEL;
2892 #endif
2893 }
2894
2895 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2896 {
2897         return 0;
2898 }
2899
2900 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2901 {
2902 }
2903
2904 static const struct trace_print_flags svm_exit_reasons_str[] = {
2905         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2906         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2907         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2908         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2909         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2910         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2911         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2912         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2913         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2914         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2915         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2916         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2917         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2918         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2919         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2920         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2921         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2922         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2923         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2924         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2925         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2926         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2927         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2928         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2929         { SVM_EXIT_INTR,                        "interrupt" },
2930         { SVM_EXIT_NMI,                         "nmi" },
2931         { SVM_EXIT_SMI,                         "smi" },
2932         { SVM_EXIT_INIT,                        "init" },
2933         { SVM_EXIT_VINTR,                       "vintr" },
2934         { SVM_EXIT_CPUID,                       "cpuid" },
2935         { SVM_EXIT_INVD,                        "invd" },
2936         { SVM_EXIT_HLT,                         "hlt" },
2937         { SVM_EXIT_INVLPG,                      "invlpg" },
2938         { SVM_EXIT_INVLPGA,                     "invlpga" },
2939         { SVM_EXIT_IOIO,                        "io" },
2940         { SVM_EXIT_MSR,                         "msr" },
2941         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2942         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2943         { SVM_EXIT_VMRUN,                       "vmrun" },
2944         { SVM_EXIT_VMMCALL,                     "hypercall" },
2945         { SVM_EXIT_VMLOAD,                      "vmload" },
2946         { SVM_EXIT_VMSAVE,                      "vmsave" },
2947         { SVM_EXIT_STGI,                        "stgi" },
2948         { SVM_EXIT_CLGI,                        "clgi" },
2949         { SVM_EXIT_SKINIT,                      "skinit" },
2950         { SVM_EXIT_WBINVD,                      "wbinvd" },
2951         { SVM_EXIT_MONITOR,                     "monitor" },
2952         { SVM_EXIT_MWAIT,                       "mwait" },
2953         { SVM_EXIT_NPF,                         "npf" },
2954         { -1, NULL }
2955 };
2956
2957 static int svm_get_lpage_level(void)
2958 {
2959         return PT_PDPE_LEVEL;
2960 }
2961
2962 static bool svm_rdtscp_supported(void)
2963 {
2964         return false;
2965 }
2966
2967 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2968 {
2969         struct vcpu_svm *svm = to_svm(vcpu);
2970
2971         update_cr0_intercept(svm);
2972         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
2973 }
2974
2975 static struct kvm_x86_ops svm_x86_ops = {
2976         .cpu_has_kvm_support = has_svm,
2977         .disabled_by_bios = is_disabled,
2978         .hardware_setup = svm_hardware_setup,
2979         .hardware_unsetup = svm_hardware_unsetup,
2980         .check_processor_compatibility = svm_check_processor_compat,
2981         .hardware_enable = svm_hardware_enable,
2982         .hardware_disable = svm_hardware_disable,
2983         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2984
2985         .vcpu_create = svm_create_vcpu,
2986         .vcpu_free = svm_free_vcpu,
2987         .vcpu_reset = svm_vcpu_reset,
2988
2989         .prepare_guest_switch = svm_prepare_guest_switch,
2990         .vcpu_load = svm_vcpu_load,
2991         .vcpu_put = svm_vcpu_put,
2992
2993         .set_guest_debug = svm_guest_debug,
2994         .get_msr = svm_get_msr,
2995         .set_msr = svm_set_msr,
2996         .get_segment_base = svm_get_segment_base,
2997         .get_segment = svm_get_segment,
2998         .set_segment = svm_set_segment,
2999         .get_cpl = svm_get_cpl,
3000         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3001         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3002         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3003         .set_cr0 = svm_set_cr0,
3004         .set_cr3 = svm_set_cr3,
3005         .set_cr4 = svm_set_cr4,
3006         .set_efer = svm_set_efer,
3007         .get_idt = svm_get_idt,
3008         .set_idt = svm_set_idt,
3009         .get_gdt = svm_get_gdt,
3010         .set_gdt = svm_set_gdt,
3011         .get_dr = svm_get_dr,
3012         .set_dr = svm_set_dr,
3013         .cache_reg = svm_cache_reg,
3014         .get_rflags = svm_get_rflags,
3015         .set_rflags = svm_set_rflags,
3016         .fpu_activate = svm_fpu_activate,
3017         .fpu_deactivate = svm_fpu_deactivate,
3018
3019         .tlb_flush = svm_flush_tlb,
3020
3021         .run = svm_vcpu_run,
3022         .handle_exit = handle_exit,
3023         .skip_emulated_instruction = skip_emulated_instruction,
3024         .set_interrupt_shadow = svm_set_interrupt_shadow,
3025         .get_interrupt_shadow = svm_get_interrupt_shadow,
3026         .patch_hypercall = svm_patch_hypercall,
3027         .set_irq = svm_set_irq,
3028         .set_nmi = svm_inject_nmi,
3029         .queue_exception = svm_queue_exception,
3030         .interrupt_allowed = svm_interrupt_allowed,
3031         .nmi_allowed = svm_nmi_allowed,
3032         .get_nmi_mask = svm_get_nmi_mask,
3033         .set_nmi_mask = svm_set_nmi_mask,
3034         .enable_nmi_window = enable_nmi_window,
3035         .enable_irq_window = enable_irq_window,
3036         .update_cr8_intercept = update_cr8_intercept,
3037
3038         .set_tss_addr = svm_set_tss_addr,
3039         .get_tdp_level = get_npt_level,
3040         .get_mt_mask = svm_get_mt_mask,
3041
3042         .exit_reasons_str = svm_exit_reasons_str,
3043         .get_lpage_level = svm_get_lpage_level,
3044
3045         .cpuid_update = svm_cpuid_update,
3046
3047         .rdtscp_supported = svm_rdtscp_supported,
3048 };
3049
3050 static int __init svm_init(void)
3051 {
3052         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3053                               THIS_MODULE);
3054 }
3055
3056 static void __exit svm_exit(void)
3057 {
3058         kvm_exit();
3059 }
3060
3061 module_init(svm_init)
3062 module_exit(svm_exit)