2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
34 #include <asm/kvm_para.h>
36 #include <asm/virtext.h>
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_TSC_RATE (1 << 4)
55 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
56 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
57 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
58 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
60 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
61 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
62 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
66 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
67 #define TSC_RATIO_MIN 0x0000000000000001ULL
68 #define TSC_RATIO_MAX 0x000000ffffffffffULL
70 static bool erratum_383_found __read_mostly;
72 static const u32 host_save_user_msrs[] = {
74 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
77 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
80 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
90 /* These are the merged vectors */
93 /* gpa pointers to the real vectors */
97 /* A VMEXIT is required but not yet emulated */
100 /* cache for intercepts of the guest */
103 u32 intercept_exceptions;
106 /* Nested Paging related state */
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
114 struct kvm_vcpu vcpu;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
136 struct nested_state nested;
140 unsigned int3_injected;
141 unsigned long int3_rip;
147 static DEFINE_PER_CPU(u64, current_tsc_ratio);
148 #define TSC_RATIO_DEFAULT 0x0100000000ULL
150 #define MSR_INVALID 0xffffffffU
152 static struct svm_direct_access_msrs {
153 u32 index; /* Index of the MSR */
154 bool always; /* True if intercept is always on */
155 } direct_access_msrs[] = {
156 { .index = MSR_STAR, .always = true },
157 { .index = MSR_IA32_SYSENTER_CS, .always = true },
159 { .index = MSR_GS_BASE, .always = true },
160 { .index = MSR_FS_BASE, .always = true },
161 { .index = MSR_KERNEL_GS_BASE, .always = true },
162 { .index = MSR_LSTAR, .always = true },
163 { .index = MSR_CSTAR, .always = true },
164 { .index = MSR_SYSCALL_MASK, .always = true },
166 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
167 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
168 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
169 { .index = MSR_IA32_LASTINTTOIP, .always = false },
170 { .index = MSR_INVALID, .always = false },
173 /* enable NPT for AMD64 and X86 with PAE */
174 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
175 static bool npt_enabled = true;
177 static bool npt_enabled;
181 module_param(npt, int, S_IRUGO);
183 static int nested = 1;
184 module_param(nested, int, S_IRUGO);
186 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
187 static void svm_complete_interrupts(struct vcpu_svm *svm);
189 static int nested_svm_exit_handled(struct vcpu_svm *svm);
190 static int nested_svm_intercept(struct vcpu_svm *svm);
191 static int nested_svm_vmexit(struct vcpu_svm *svm);
192 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
193 bool has_error_code, u32 error_code);
194 static u64 __scale_tsc(u64 ratio, u64 tsc);
197 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
198 pause filter count */
199 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
200 VMCB_ASID, /* ASID */
201 VMCB_INTR, /* int_ctl, int_vector */
202 VMCB_NPT, /* npt_en, nCR3, gPAT */
203 VMCB_CR, /* CR0, CR3, CR4, EFER */
204 VMCB_DR, /* DR6, DR7 */
205 VMCB_DT, /* GDT, IDT */
206 VMCB_SEG, /* CS, DS, SS, ES, CPL */
207 VMCB_CR2, /* CR2 only */
208 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
212 /* TPR and CR2 are always written before VMRUN */
213 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
215 static inline void mark_all_dirty(struct vmcb *vmcb)
217 vmcb->control.clean = 0;
220 static inline void mark_all_clean(struct vmcb *vmcb)
222 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
223 & ~VMCB_ALWAYS_DIRTY_MASK;
226 static inline void mark_dirty(struct vmcb *vmcb, int bit)
228 vmcb->control.clean &= ~(1 << bit);
231 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
233 return container_of(vcpu, struct vcpu_svm, vcpu);
236 static void recalc_intercepts(struct vcpu_svm *svm)
238 struct vmcb_control_area *c, *h;
239 struct nested_state *g;
241 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
243 if (!is_guest_mode(&svm->vcpu))
246 c = &svm->vmcb->control;
247 h = &svm->nested.hsave->control;
250 c->intercept_cr = h->intercept_cr | g->intercept_cr;
251 c->intercept_dr = h->intercept_dr | g->intercept_dr;
252 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
253 c->intercept = h->intercept | g->intercept;
256 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
258 if (is_guest_mode(&svm->vcpu))
259 return svm->nested.hsave;
264 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
266 struct vmcb *vmcb = get_host_vmcb(svm);
268 vmcb->control.intercept_cr |= (1U << bit);
270 recalc_intercepts(svm);
273 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
275 struct vmcb *vmcb = get_host_vmcb(svm);
277 vmcb->control.intercept_cr &= ~(1U << bit);
279 recalc_intercepts(svm);
282 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
284 struct vmcb *vmcb = get_host_vmcb(svm);
286 return vmcb->control.intercept_cr & (1U << bit);
289 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
291 struct vmcb *vmcb = get_host_vmcb(svm);
293 vmcb->control.intercept_dr |= (1U << bit);
295 recalc_intercepts(svm);
298 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
300 struct vmcb *vmcb = get_host_vmcb(svm);
302 vmcb->control.intercept_dr &= ~(1U << bit);
304 recalc_intercepts(svm);
307 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
309 struct vmcb *vmcb = get_host_vmcb(svm);
311 vmcb->control.intercept_exceptions |= (1U << bit);
313 recalc_intercepts(svm);
316 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
318 struct vmcb *vmcb = get_host_vmcb(svm);
320 vmcb->control.intercept_exceptions &= ~(1U << bit);
322 recalc_intercepts(svm);
325 static inline void set_intercept(struct vcpu_svm *svm, int bit)
327 struct vmcb *vmcb = get_host_vmcb(svm);
329 vmcb->control.intercept |= (1ULL << bit);
331 recalc_intercepts(svm);
334 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
336 struct vmcb *vmcb = get_host_vmcb(svm);
338 vmcb->control.intercept &= ~(1ULL << bit);
340 recalc_intercepts(svm);
343 static inline void enable_gif(struct vcpu_svm *svm)
345 svm->vcpu.arch.hflags |= HF_GIF_MASK;
348 static inline void disable_gif(struct vcpu_svm *svm)
350 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
353 static inline bool gif_set(struct vcpu_svm *svm)
355 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
358 static unsigned long iopm_base;
360 struct kvm_ldttss_desc {
363 unsigned base1:8, type:5, dpl:2, p:1;
364 unsigned limit1:4, zero0:3, g:1, base2:8;
367 } __attribute__((packed));
369 struct svm_cpu_data {
375 struct kvm_ldttss_desc *tss_desc;
377 struct page *save_area;
380 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
382 struct svm_init_data {
387 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
389 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
390 #define MSRS_RANGE_SIZE 2048
391 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
393 static u32 svm_msrpm_offset(u32 msr)
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr < msrpm_ranges[i] ||
400 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
403 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
404 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
406 /* Now we have the u8 offset - but need the u32 offset */
410 /* MSR not in any range */
414 #define MAX_INST_SIZE 15
416 static inline void clgi(void)
418 asm volatile (__ex(SVM_CLGI));
421 static inline void stgi(void)
423 asm volatile (__ex(SVM_STGI));
426 static inline void invlpga(unsigned long addr, u32 asid)
428 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
431 static int get_npt_level(void)
434 return PT64_ROOT_LEVEL;
436 return PT32E_ROOT_LEVEL;
440 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
442 vcpu->arch.efer = efer;
443 if (!npt_enabled && !(efer & EFER_LMA))
446 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
447 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
450 static int is_external_interrupt(u32 info)
452 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
453 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
456 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
458 struct vcpu_svm *svm = to_svm(vcpu);
461 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
462 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
466 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
468 struct vcpu_svm *svm = to_svm(vcpu);
471 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
473 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
477 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
479 struct vcpu_svm *svm = to_svm(vcpu);
481 if (svm->vmcb->control.next_rip != 0)
482 svm->next_rip = svm->vmcb->control.next_rip;
484 if (!svm->next_rip) {
485 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
487 printk(KERN_DEBUG "%s: NOP\n", __func__);
490 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
491 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
492 __func__, kvm_rip_read(vcpu), svm->next_rip);
494 kvm_rip_write(vcpu, svm->next_rip);
495 svm_set_interrupt_shadow(vcpu, 0);
498 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
499 bool has_error_code, u32 error_code,
502 struct vcpu_svm *svm = to_svm(vcpu);
505 * If we are within a nested VM we'd better #VMEXIT and let the guest
506 * handle the exception
509 nested_svm_check_exception(svm, nr, has_error_code, error_code))
512 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
513 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
516 * For guest debugging where we have to reinject #BP if some
517 * INT3 is guest-owned:
518 * Emulate nRIP by moving RIP forward. Will fail if injection
519 * raises a fault that is not intercepted. Still better than
520 * failing in all cases.
522 skip_emulated_instruction(&svm->vcpu);
523 rip = kvm_rip_read(&svm->vcpu);
524 svm->int3_rip = rip + svm->vmcb->save.cs.base;
525 svm->int3_injected = rip - old_rip;
528 svm->vmcb->control.event_inj = nr
530 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
531 | SVM_EVTINJ_TYPE_EXEPT;
532 svm->vmcb->control.event_inj_err = error_code;
535 static void svm_init_erratum_383(void)
541 if (!cpu_has_amd_erratum(amd_erratum_383))
544 /* Use _safe variants to not break nested virtualization */
545 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
551 low = lower_32_bits(val);
552 high = upper_32_bits(val);
554 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
556 erratum_383_found = true;
559 static int has_svm(void)
563 if (!cpu_has_svm(&msg)) {
564 printk(KERN_INFO "has_svm: %s\n", msg);
571 static void svm_hardware_disable(void *garbage)
573 /* Make sure we clean up behind us */
574 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
575 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
580 static int svm_hardware_enable(void *garbage)
583 struct svm_cpu_data *sd;
585 struct desc_ptr gdt_descr;
586 struct desc_struct *gdt;
587 int me = raw_smp_processor_id();
589 rdmsrl(MSR_EFER, efer);
590 if (efer & EFER_SVME)
594 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
598 sd = per_cpu(svm_data, me);
601 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
606 sd->asid_generation = 1;
607 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
608 sd->next_asid = sd->max_asid + 1;
610 native_store_gdt(&gdt_descr);
611 gdt = (struct desc_struct *)gdt_descr.address;
612 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
614 wrmsrl(MSR_EFER, efer | EFER_SVME);
616 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
618 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
619 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
620 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
623 svm_init_erratum_383();
628 static void svm_cpu_uninit(int cpu)
630 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
635 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
636 __free_page(sd->save_area);
640 static int svm_cpu_init(int cpu)
642 struct svm_cpu_data *sd;
645 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
649 sd->save_area = alloc_page(GFP_KERNEL);
654 per_cpu(svm_data, cpu) = sd;
664 static bool valid_msr_intercept(u32 index)
668 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
669 if (direct_access_msrs[i].index == index)
675 static void set_msr_interception(u32 *msrpm, unsigned msr,
678 u8 bit_read, bit_write;
683 * If this warning triggers extend the direct_access_msrs list at the
684 * beginning of the file
686 WARN_ON(!valid_msr_intercept(msr));
688 offset = svm_msrpm_offset(msr);
689 bit_read = 2 * (msr & 0x0f);
690 bit_write = 2 * (msr & 0x0f) + 1;
693 BUG_ON(offset == MSR_INVALID);
695 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
696 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
701 static void svm_vcpu_init_msrpm(u32 *msrpm)
705 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
707 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
708 if (!direct_access_msrs[i].always)
711 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
715 static void add_msr_offset(u32 offset)
719 for (i = 0; i < MSRPM_OFFSETS; ++i) {
721 /* Offset already in list? */
722 if (msrpm_offsets[i] == offset)
725 /* Slot used by another offset? */
726 if (msrpm_offsets[i] != MSR_INVALID)
729 /* Add offset to list */
730 msrpm_offsets[i] = offset;
736 * If this BUG triggers the msrpm_offsets table has an overflow. Just
737 * increase MSRPM_OFFSETS in this case.
742 static void init_msrpm_offsets(void)
746 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
748 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
751 offset = svm_msrpm_offset(direct_access_msrs[i].index);
752 BUG_ON(offset == MSR_INVALID);
754 add_msr_offset(offset);
758 static void svm_enable_lbrv(struct vcpu_svm *svm)
760 u32 *msrpm = svm->msrpm;
762 svm->vmcb->control.lbr_ctl = 1;
763 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
764 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
765 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
766 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
769 static void svm_disable_lbrv(struct vcpu_svm *svm)
771 u32 *msrpm = svm->msrpm;
773 svm->vmcb->control.lbr_ctl = 0;
774 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
775 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
776 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
777 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
780 static __init int svm_hardware_setup(void)
783 struct page *iopm_pages;
787 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
792 iopm_va = page_address(iopm_pages);
793 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
794 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
796 init_msrpm_offsets();
798 if (boot_cpu_has(X86_FEATURE_NX))
799 kvm_enable_efer_bits(EFER_NX);
801 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
802 kvm_enable_efer_bits(EFER_FFXSR);
804 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
807 kvm_has_tsc_control = true;
810 * Make sure the user can only configure tsc_khz values that
811 * fit into a signed integer.
812 * A min value is not calculated needed because it will always
813 * be 1 on all machines and a value of 0 is used to disable
814 * tsc-scaling for the vcpu.
816 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
818 kvm_max_guest_tsc_khz = max;
822 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
823 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
826 for_each_possible_cpu(cpu) {
827 r = svm_cpu_init(cpu);
832 if (!boot_cpu_has(X86_FEATURE_NPT))
835 if (npt_enabled && !npt) {
836 printk(KERN_INFO "kvm: Nested Paging disabled\n");
841 printk(KERN_INFO "kvm: Nested Paging enabled\n");
849 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
854 static __exit void svm_hardware_unsetup(void)
858 for_each_possible_cpu(cpu)
861 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
865 static void init_seg(struct vmcb_seg *seg)
868 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
869 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
874 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
877 seg->attrib = SVM_SELECTOR_P_MASK | type;
882 static u64 __scale_tsc(u64 ratio, u64 tsc)
884 u64 mult, frac, _tsc;
887 frac = ratio & ((1ULL << 32) - 1);
891 _tsc += (tsc >> 32) * frac;
892 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
897 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
899 struct vcpu_svm *svm = to_svm(vcpu);
902 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
903 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
908 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
910 struct vcpu_svm *svm = to_svm(vcpu);
914 /* TSC scaling supported? */
915 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR))
918 /* TSC-Scaling disabled or guest TSC same frequency as host TSC? */
919 if (user_tsc_khz == 0) {
920 vcpu->arch.virtual_tsc_khz = 0;
921 svm->tsc_ratio = TSC_RATIO_DEFAULT;
927 /* TSC scaling required - calculate ratio */
929 do_div(ratio, tsc_khz);
931 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
932 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
936 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
937 svm->tsc_ratio = ratio;
940 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
942 struct vcpu_svm *svm = to_svm(vcpu);
943 u64 g_tsc_offset = 0;
945 if (is_guest_mode(vcpu)) {
946 g_tsc_offset = svm->vmcb->control.tsc_offset -
947 svm->nested.hsave->control.tsc_offset;
948 svm->nested.hsave->control.tsc_offset = offset;
951 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
953 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
956 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
958 struct vcpu_svm *svm = to_svm(vcpu);
960 svm->vmcb->control.tsc_offset += adjustment;
961 if (is_guest_mode(vcpu))
962 svm->nested.hsave->control.tsc_offset += adjustment;
963 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
966 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
970 tsc = svm_scale_tsc(vcpu, native_read_tsc());
972 return target_tsc - tsc;
975 static void init_vmcb(struct vcpu_svm *svm)
977 struct vmcb_control_area *control = &svm->vmcb->control;
978 struct vmcb_save_area *save = &svm->vmcb->save;
980 svm->vcpu.fpu_active = 1;
981 svm->vcpu.arch.hflags = 0;
983 set_cr_intercept(svm, INTERCEPT_CR0_READ);
984 set_cr_intercept(svm, INTERCEPT_CR3_READ);
985 set_cr_intercept(svm, INTERCEPT_CR4_READ);
986 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
987 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
988 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
989 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
991 set_dr_intercept(svm, INTERCEPT_DR0_READ);
992 set_dr_intercept(svm, INTERCEPT_DR1_READ);
993 set_dr_intercept(svm, INTERCEPT_DR2_READ);
994 set_dr_intercept(svm, INTERCEPT_DR3_READ);
995 set_dr_intercept(svm, INTERCEPT_DR4_READ);
996 set_dr_intercept(svm, INTERCEPT_DR5_READ);
997 set_dr_intercept(svm, INTERCEPT_DR6_READ);
998 set_dr_intercept(svm, INTERCEPT_DR7_READ);
1000 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1001 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1002 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1003 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1004 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1005 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1006 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1007 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1009 set_exception_intercept(svm, PF_VECTOR);
1010 set_exception_intercept(svm, UD_VECTOR);
1011 set_exception_intercept(svm, MC_VECTOR);
1013 set_intercept(svm, INTERCEPT_INTR);
1014 set_intercept(svm, INTERCEPT_NMI);
1015 set_intercept(svm, INTERCEPT_SMI);
1016 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1017 set_intercept(svm, INTERCEPT_CPUID);
1018 set_intercept(svm, INTERCEPT_INVD);
1019 set_intercept(svm, INTERCEPT_HLT);
1020 set_intercept(svm, INTERCEPT_INVLPG);
1021 set_intercept(svm, INTERCEPT_INVLPGA);
1022 set_intercept(svm, INTERCEPT_IOIO_PROT);
1023 set_intercept(svm, INTERCEPT_MSR_PROT);
1024 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1025 set_intercept(svm, INTERCEPT_SHUTDOWN);
1026 set_intercept(svm, INTERCEPT_VMRUN);
1027 set_intercept(svm, INTERCEPT_VMMCALL);
1028 set_intercept(svm, INTERCEPT_VMLOAD);
1029 set_intercept(svm, INTERCEPT_VMSAVE);
1030 set_intercept(svm, INTERCEPT_STGI);
1031 set_intercept(svm, INTERCEPT_CLGI);
1032 set_intercept(svm, INTERCEPT_SKINIT);
1033 set_intercept(svm, INTERCEPT_WBINVD);
1034 set_intercept(svm, INTERCEPT_MONITOR);
1035 set_intercept(svm, INTERCEPT_MWAIT);
1036 set_intercept(svm, INTERCEPT_XSETBV);
1038 control->iopm_base_pa = iopm_base;
1039 control->msrpm_base_pa = __pa(svm->msrpm);
1040 control->int_ctl = V_INTR_MASKING_MASK;
1042 init_seg(&save->es);
1043 init_seg(&save->ss);
1044 init_seg(&save->ds);
1045 init_seg(&save->fs);
1046 init_seg(&save->gs);
1048 save->cs.selector = 0xf000;
1049 /* Executable/Readable Code Segment */
1050 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1051 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1052 save->cs.limit = 0xffff;
1054 * cs.base should really be 0xffff0000, but vmx can't handle that, so
1055 * be consistent with it.
1057 * Replace when we have real mode working for vmx.
1059 save->cs.base = 0xf0000;
1061 save->gdtr.limit = 0xffff;
1062 save->idtr.limit = 0xffff;
1064 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1065 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1067 svm_set_efer(&svm->vcpu, 0);
1068 save->dr6 = 0xffff0ff0;
1070 kvm_set_rflags(&svm->vcpu, 2);
1071 save->rip = 0x0000fff0;
1072 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1075 * This is the guest-visible cr0 value.
1076 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1078 svm->vcpu.arch.cr0 = 0;
1079 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1081 save->cr4 = X86_CR4_PAE;
1085 /* Setup VMCB for Nested Paging */
1086 control->nested_ctl = 1;
1087 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
1088 clr_intercept(svm, INTERCEPT_INVLPG);
1089 clr_exception_intercept(svm, PF_VECTOR);
1090 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1091 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1092 save->g_pat = 0x0007040600070406ULL;
1096 svm->asid_generation = 0;
1098 svm->nested.vmcb = 0;
1099 svm->vcpu.arch.hflags = 0;
1101 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1102 control->pause_filter_count = 3000;
1103 set_intercept(svm, INTERCEPT_PAUSE);
1106 mark_all_dirty(svm->vmcb);
1111 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1113 struct vcpu_svm *svm = to_svm(vcpu);
1117 if (!kvm_vcpu_is_bsp(vcpu)) {
1118 kvm_rip_write(vcpu, 0);
1119 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1120 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1122 vcpu->arch.regs_avail = ~0;
1123 vcpu->arch.regs_dirty = ~0;
1128 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1130 struct vcpu_svm *svm;
1132 struct page *msrpm_pages;
1133 struct page *hsave_page;
1134 struct page *nested_msrpm_pages;
1137 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1143 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1145 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1150 page = alloc_page(GFP_KERNEL);
1154 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1158 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1159 if (!nested_msrpm_pages)
1162 hsave_page = alloc_page(GFP_KERNEL);
1166 svm->nested.hsave = page_address(hsave_page);
1168 svm->msrpm = page_address(msrpm_pages);
1169 svm_vcpu_init_msrpm(svm->msrpm);
1171 svm->nested.msrpm = page_address(nested_msrpm_pages);
1172 svm_vcpu_init_msrpm(svm->nested.msrpm);
1174 svm->vmcb = page_address(page);
1175 clear_page(svm->vmcb);
1176 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1177 svm->asid_generation = 0;
1179 kvm_write_tsc(&svm->vcpu, 0);
1181 err = fx_init(&svm->vcpu);
1185 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1186 if (kvm_vcpu_is_bsp(&svm->vcpu))
1187 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1192 __free_page(hsave_page);
1194 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1196 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1200 kvm_vcpu_uninit(&svm->vcpu);
1202 kmem_cache_free(kvm_vcpu_cache, svm);
1204 return ERR_PTR(err);
1207 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1209 struct vcpu_svm *svm = to_svm(vcpu);
1211 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1212 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1213 __free_page(virt_to_page(svm->nested.hsave));
1214 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1215 kvm_vcpu_uninit(vcpu);
1216 kmem_cache_free(kvm_vcpu_cache, svm);
1219 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1221 struct vcpu_svm *svm = to_svm(vcpu);
1224 if (unlikely(cpu != vcpu->cpu)) {
1225 svm->asid_generation = 0;
1226 mark_all_dirty(svm->vmcb);
1229 #ifdef CONFIG_X86_64
1230 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1232 savesegment(fs, svm->host.fs);
1233 savesegment(gs, svm->host.gs);
1234 svm->host.ldt = kvm_read_ldt();
1236 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1237 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1239 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1240 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1241 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1242 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1246 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1248 struct vcpu_svm *svm = to_svm(vcpu);
1251 ++vcpu->stat.host_state_reload;
1252 kvm_load_ldt(svm->host.ldt);
1253 #ifdef CONFIG_X86_64
1254 loadsegment(fs, svm->host.fs);
1255 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1256 load_gs_index(svm->host.gs);
1258 #ifdef CONFIG_X86_32_LAZY_GS
1259 loadsegment(gs, svm->host.gs);
1262 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1263 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1266 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1268 return to_svm(vcpu)->vmcb->save.rflags;
1271 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1273 to_svm(vcpu)->vmcb->save.rflags = rflags;
1276 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1279 case VCPU_EXREG_PDPTR:
1280 BUG_ON(!npt_enabled);
1281 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1288 static void svm_set_vintr(struct vcpu_svm *svm)
1290 set_intercept(svm, INTERCEPT_VINTR);
1293 static void svm_clear_vintr(struct vcpu_svm *svm)
1295 clr_intercept(svm, INTERCEPT_VINTR);
1298 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1300 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1303 case VCPU_SREG_CS: return &save->cs;
1304 case VCPU_SREG_DS: return &save->ds;
1305 case VCPU_SREG_ES: return &save->es;
1306 case VCPU_SREG_FS: return &save->fs;
1307 case VCPU_SREG_GS: return &save->gs;
1308 case VCPU_SREG_SS: return &save->ss;
1309 case VCPU_SREG_TR: return &save->tr;
1310 case VCPU_SREG_LDTR: return &save->ldtr;
1316 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1318 struct vmcb_seg *s = svm_seg(vcpu, seg);
1323 static void svm_get_segment(struct kvm_vcpu *vcpu,
1324 struct kvm_segment *var, int seg)
1326 struct vmcb_seg *s = svm_seg(vcpu, seg);
1328 var->base = s->base;
1329 var->limit = s->limit;
1330 var->selector = s->selector;
1331 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1332 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1333 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1334 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1335 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1336 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1337 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1338 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1341 * AMD's VMCB does not have an explicit unusable field, so emulate it
1342 * for cross vendor migration purposes by "not present"
1344 var->unusable = !var->present || (var->type == 0);
1349 * SVM always stores 0 for the 'G' bit in the CS selector in
1350 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1351 * Intel's VMENTRY has a check on the 'G' bit.
1353 var->g = s->limit > 0xfffff;
1357 * Work around a bug where the busy flag in the tr selector
1367 * The accessed bit must always be set in the segment
1368 * descriptor cache, although it can be cleared in the
1369 * descriptor, the cached bit always remains at 1. Since
1370 * Intel has a check on this, set it here to support
1371 * cross-vendor migration.
1378 * On AMD CPUs sometimes the DB bit in the segment
1379 * descriptor is left as 1, although the whole segment has
1380 * been made unusable. Clear it here to pass an Intel VMX
1381 * entry check when cross vendor migrating.
1389 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1391 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1396 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1398 struct vcpu_svm *svm = to_svm(vcpu);
1400 dt->size = svm->vmcb->save.idtr.limit;
1401 dt->address = svm->vmcb->save.idtr.base;
1404 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1406 struct vcpu_svm *svm = to_svm(vcpu);
1408 svm->vmcb->save.idtr.limit = dt->size;
1409 svm->vmcb->save.idtr.base = dt->address ;
1410 mark_dirty(svm->vmcb, VMCB_DT);
1413 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1415 struct vcpu_svm *svm = to_svm(vcpu);
1417 dt->size = svm->vmcb->save.gdtr.limit;
1418 dt->address = svm->vmcb->save.gdtr.base;
1421 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1423 struct vcpu_svm *svm = to_svm(vcpu);
1425 svm->vmcb->save.gdtr.limit = dt->size;
1426 svm->vmcb->save.gdtr.base = dt->address ;
1427 mark_dirty(svm->vmcb, VMCB_DT);
1430 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1434 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1438 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1442 static void update_cr0_intercept(struct vcpu_svm *svm)
1444 ulong gcr0 = svm->vcpu.arch.cr0;
1445 u64 *hcr0 = &svm->vmcb->save.cr0;
1447 if (!svm->vcpu.fpu_active)
1448 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1450 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1451 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1453 mark_dirty(svm->vmcb, VMCB_CR);
1455 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1456 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1457 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1459 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1460 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1464 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1466 struct vcpu_svm *svm = to_svm(vcpu);
1468 #ifdef CONFIG_X86_64
1469 if (vcpu->arch.efer & EFER_LME) {
1470 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1471 vcpu->arch.efer |= EFER_LMA;
1472 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1475 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1476 vcpu->arch.efer &= ~EFER_LMA;
1477 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1481 vcpu->arch.cr0 = cr0;
1484 cr0 |= X86_CR0_PG | X86_CR0_WP;
1486 if (!vcpu->fpu_active)
1489 * re-enable caching here because the QEMU bios
1490 * does not do it - this results in some delay at
1493 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1494 svm->vmcb->save.cr0 = cr0;
1495 mark_dirty(svm->vmcb, VMCB_CR);
1496 update_cr0_intercept(svm);
1499 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1501 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1502 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1504 if (cr4 & X86_CR4_VMXE)
1507 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1508 svm_flush_tlb(vcpu);
1510 vcpu->arch.cr4 = cr4;
1513 cr4 |= host_cr4_mce;
1514 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1515 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1519 static void svm_set_segment(struct kvm_vcpu *vcpu,
1520 struct kvm_segment *var, int seg)
1522 struct vcpu_svm *svm = to_svm(vcpu);
1523 struct vmcb_seg *s = svm_seg(vcpu, seg);
1525 s->base = var->base;
1526 s->limit = var->limit;
1527 s->selector = var->selector;
1531 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1532 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1533 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1534 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1535 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1536 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1537 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1538 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1540 if (seg == VCPU_SREG_CS)
1542 = (svm->vmcb->save.cs.attrib
1543 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1545 mark_dirty(svm->vmcb, VMCB_SEG);
1548 static void update_db_intercept(struct kvm_vcpu *vcpu)
1550 struct vcpu_svm *svm = to_svm(vcpu);
1552 clr_exception_intercept(svm, DB_VECTOR);
1553 clr_exception_intercept(svm, BP_VECTOR);
1555 if (svm->nmi_singlestep)
1556 set_exception_intercept(svm, DB_VECTOR);
1558 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1559 if (vcpu->guest_debug &
1560 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1561 set_exception_intercept(svm, DB_VECTOR);
1562 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1563 set_exception_intercept(svm, BP_VECTOR);
1565 vcpu->guest_debug = 0;
1568 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1570 struct vcpu_svm *svm = to_svm(vcpu);
1572 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1573 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1575 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1577 mark_dirty(svm->vmcb, VMCB_DR);
1579 update_db_intercept(vcpu);
1582 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1584 if (sd->next_asid > sd->max_asid) {
1585 ++sd->asid_generation;
1587 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1590 svm->asid_generation = sd->asid_generation;
1591 svm->vmcb->control.asid = sd->next_asid++;
1593 mark_dirty(svm->vmcb, VMCB_ASID);
1596 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1598 struct vcpu_svm *svm = to_svm(vcpu);
1600 svm->vmcb->save.dr7 = value;
1601 mark_dirty(svm->vmcb, VMCB_DR);
1604 static int pf_interception(struct vcpu_svm *svm)
1606 u64 fault_address = svm->vmcb->control.exit_info_2;
1610 switch (svm->apf_reason) {
1612 error_code = svm->vmcb->control.exit_info_1;
1614 trace_kvm_page_fault(fault_address, error_code);
1615 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1616 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1617 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1618 svm->vmcb->control.insn_bytes,
1619 svm->vmcb->control.insn_len);
1621 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1622 svm->apf_reason = 0;
1623 local_irq_disable();
1624 kvm_async_pf_task_wait(fault_address);
1627 case KVM_PV_REASON_PAGE_READY:
1628 svm->apf_reason = 0;
1629 local_irq_disable();
1630 kvm_async_pf_task_wake(fault_address);
1637 static int db_interception(struct vcpu_svm *svm)
1639 struct kvm_run *kvm_run = svm->vcpu.run;
1641 if (!(svm->vcpu.guest_debug &
1642 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1643 !svm->nmi_singlestep) {
1644 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1648 if (svm->nmi_singlestep) {
1649 svm->nmi_singlestep = false;
1650 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1651 svm->vmcb->save.rflags &=
1652 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1653 update_db_intercept(&svm->vcpu);
1656 if (svm->vcpu.guest_debug &
1657 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1658 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1659 kvm_run->debug.arch.pc =
1660 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1661 kvm_run->debug.arch.exception = DB_VECTOR;
1668 static int bp_interception(struct vcpu_svm *svm)
1670 struct kvm_run *kvm_run = svm->vcpu.run;
1672 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1673 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1674 kvm_run->debug.arch.exception = BP_VECTOR;
1678 static int ud_interception(struct vcpu_svm *svm)
1682 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1683 if (er != EMULATE_DONE)
1684 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1688 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1690 struct vcpu_svm *svm = to_svm(vcpu);
1692 clr_exception_intercept(svm, NM_VECTOR);
1694 svm->vcpu.fpu_active = 1;
1695 update_cr0_intercept(svm);
1698 static int nm_interception(struct vcpu_svm *svm)
1700 svm_fpu_activate(&svm->vcpu);
1704 static bool is_erratum_383(void)
1709 if (!erratum_383_found)
1712 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1716 /* Bit 62 may or may not be set for this mce */
1717 value &= ~(1ULL << 62);
1719 if (value != 0xb600000000010015ULL)
1722 /* Clear MCi_STATUS registers */
1723 for (i = 0; i < 6; ++i)
1724 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1726 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1730 value &= ~(1ULL << 2);
1731 low = lower_32_bits(value);
1732 high = upper_32_bits(value);
1734 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1737 /* Flush tlb to evict multi-match entries */
1743 static void svm_handle_mce(struct vcpu_svm *svm)
1745 if (is_erratum_383()) {
1747 * Erratum 383 triggered. Guest state is corrupt so kill the
1750 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1752 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1758 * On an #MC intercept the MCE handler is not called automatically in
1759 * the host. So do it by hand here.
1763 /* not sure if we ever come back to this point */
1768 static int mc_interception(struct vcpu_svm *svm)
1773 static int shutdown_interception(struct vcpu_svm *svm)
1775 struct kvm_run *kvm_run = svm->vcpu.run;
1778 * VMCB is undefined after a SHUTDOWN intercept
1779 * so reinitialize it.
1781 clear_page(svm->vmcb);
1784 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1788 static int io_interception(struct vcpu_svm *svm)
1790 struct kvm_vcpu *vcpu = &svm->vcpu;
1791 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1792 int size, in, string;
1795 ++svm->vcpu.stat.io_exits;
1796 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1797 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1799 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1801 port = io_info >> 16;
1802 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1803 svm->next_rip = svm->vmcb->control.exit_info_2;
1804 skip_emulated_instruction(&svm->vcpu);
1806 return kvm_fast_pio_out(vcpu, size, port);
1809 static int nmi_interception(struct vcpu_svm *svm)
1814 static int intr_interception(struct vcpu_svm *svm)
1816 ++svm->vcpu.stat.irq_exits;
1820 static int nop_on_interception(struct vcpu_svm *svm)
1825 static int halt_interception(struct vcpu_svm *svm)
1827 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1828 skip_emulated_instruction(&svm->vcpu);
1829 return kvm_emulate_halt(&svm->vcpu);
1832 static int vmmcall_interception(struct vcpu_svm *svm)
1834 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1835 skip_emulated_instruction(&svm->vcpu);
1836 kvm_emulate_hypercall(&svm->vcpu);
1840 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1842 struct vcpu_svm *svm = to_svm(vcpu);
1844 return svm->nested.nested_cr3;
1847 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1850 struct vcpu_svm *svm = to_svm(vcpu);
1852 svm->vmcb->control.nested_cr3 = root;
1853 mark_dirty(svm->vmcb, VMCB_NPT);
1854 svm_flush_tlb(vcpu);
1857 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1858 struct x86_exception *fault)
1860 struct vcpu_svm *svm = to_svm(vcpu);
1862 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1863 svm->vmcb->control.exit_code_hi = 0;
1864 svm->vmcb->control.exit_info_1 = fault->error_code;
1865 svm->vmcb->control.exit_info_2 = fault->address;
1867 nested_svm_vmexit(svm);
1870 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1874 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1876 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1877 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1878 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1879 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1880 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1885 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1887 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1890 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1892 if (!(svm->vcpu.arch.efer & EFER_SVME)
1893 || !is_paging(&svm->vcpu)) {
1894 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1898 if (svm->vmcb->save.cpl) {
1899 kvm_inject_gp(&svm->vcpu, 0);
1906 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1907 bool has_error_code, u32 error_code)
1911 if (!is_guest_mode(&svm->vcpu))
1914 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1915 svm->vmcb->control.exit_code_hi = 0;
1916 svm->vmcb->control.exit_info_1 = error_code;
1917 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1919 vmexit = nested_svm_intercept(svm);
1920 if (vmexit == NESTED_EXIT_DONE)
1921 svm->nested.exit_required = true;
1926 /* This function returns true if it is save to enable the irq window */
1927 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1929 if (!is_guest_mode(&svm->vcpu))
1932 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1935 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1939 * if vmexit was already requested (by intercepted exception
1940 * for instance) do not overwrite it with "external interrupt"
1943 if (svm->nested.exit_required)
1946 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1947 svm->vmcb->control.exit_info_1 = 0;
1948 svm->vmcb->control.exit_info_2 = 0;
1950 if (svm->nested.intercept & 1ULL) {
1952 * The #vmexit can't be emulated here directly because this
1953 * code path runs with irqs and preemtion disabled. A
1954 * #vmexit emulation might sleep. Only signal request for
1957 svm->nested.exit_required = true;
1958 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1965 /* This function returns true if it is save to enable the nmi window */
1966 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1968 if (!is_guest_mode(&svm->vcpu))
1971 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1974 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1975 svm->nested.exit_required = true;
1980 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1986 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1987 if (is_error_page(page))
1995 kvm_release_page_clean(page);
1996 kvm_inject_gp(&svm->vcpu, 0);
2001 static void nested_svm_unmap(struct page *page)
2004 kvm_release_page_dirty(page);
2007 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2013 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2014 return NESTED_EXIT_HOST;
2016 port = svm->vmcb->control.exit_info_1 >> 16;
2017 gpa = svm->nested.vmcb_iopm + (port / 8);
2021 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2024 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2027 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2029 u32 offset, msr, value;
2032 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2033 return NESTED_EXIT_HOST;
2035 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2036 offset = svm_msrpm_offset(msr);
2037 write = svm->vmcb->control.exit_info_1 & 1;
2038 mask = 1 << ((2 * (msr & 0xf)) + write);
2040 if (offset == MSR_INVALID)
2041 return NESTED_EXIT_DONE;
2043 /* Offset is in 32 bit units but need in 8 bit units */
2046 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2047 return NESTED_EXIT_DONE;
2049 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2052 static int nested_svm_exit_special(struct vcpu_svm *svm)
2054 u32 exit_code = svm->vmcb->control.exit_code;
2056 switch (exit_code) {
2059 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2060 return NESTED_EXIT_HOST;
2062 /* For now we are always handling NPFs when using them */
2064 return NESTED_EXIT_HOST;
2066 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2067 /* When we're shadowing, trap PFs, but not async PF */
2068 if (!npt_enabled && svm->apf_reason == 0)
2069 return NESTED_EXIT_HOST;
2071 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2072 nm_interception(svm);
2078 return NESTED_EXIT_CONTINUE;
2082 * If this function returns true, this #vmexit was already handled
2084 static int nested_svm_intercept(struct vcpu_svm *svm)
2086 u32 exit_code = svm->vmcb->control.exit_code;
2087 int vmexit = NESTED_EXIT_HOST;
2089 switch (exit_code) {
2091 vmexit = nested_svm_exit_handled_msr(svm);
2094 vmexit = nested_svm_intercept_ioio(svm);
2096 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2097 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2098 if (svm->nested.intercept_cr & bit)
2099 vmexit = NESTED_EXIT_DONE;
2102 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2103 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2104 if (svm->nested.intercept_dr & bit)
2105 vmexit = NESTED_EXIT_DONE;
2108 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2109 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2110 if (svm->nested.intercept_exceptions & excp_bits)
2111 vmexit = NESTED_EXIT_DONE;
2112 /* async page fault always cause vmexit */
2113 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2114 svm->apf_reason != 0)
2115 vmexit = NESTED_EXIT_DONE;
2118 case SVM_EXIT_ERR: {
2119 vmexit = NESTED_EXIT_DONE;
2123 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2124 if (svm->nested.intercept & exit_bits)
2125 vmexit = NESTED_EXIT_DONE;
2132 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2136 vmexit = nested_svm_intercept(svm);
2138 if (vmexit == NESTED_EXIT_DONE)
2139 nested_svm_vmexit(svm);
2144 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2146 struct vmcb_control_area *dst = &dst_vmcb->control;
2147 struct vmcb_control_area *from = &from_vmcb->control;
2149 dst->intercept_cr = from->intercept_cr;
2150 dst->intercept_dr = from->intercept_dr;
2151 dst->intercept_exceptions = from->intercept_exceptions;
2152 dst->intercept = from->intercept;
2153 dst->iopm_base_pa = from->iopm_base_pa;
2154 dst->msrpm_base_pa = from->msrpm_base_pa;
2155 dst->tsc_offset = from->tsc_offset;
2156 dst->asid = from->asid;
2157 dst->tlb_ctl = from->tlb_ctl;
2158 dst->int_ctl = from->int_ctl;
2159 dst->int_vector = from->int_vector;
2160 dst->int_state = from->int_state;
2161 dst->exit_code = from->exit_code;
2162 dst->exit_code_hi = from->exit_code_hi;
2163 dst->exit_info_1 = from->exit_info_1;
2164 dst->exit_info_2 = from->exit_info_2;
2165 dst->exit_int_info = from->exit_int_info;
2166 dst->exit_int_info_err = from->exit_int_info_err;
2167 dst->nested_ctl = from->nested_ctl;
2168 dst->event_inj = from->event_inj;
2169 dst->event_inj_err = from->event_inj_err;
2170 dst->nested_cr3 = from->nested_cr3;
2171 dst->lbr_ctl = from->lbr_ctl;
2174 static int nested_svm_vmexit(struct vcpu_svm *svm)
2176 struct vmcb *nested_vmcb;
2177 struct vmcb *hsave = svm->nested.hsave;
2178 struct vmcb *vmcb = svm->vmcb;
2181 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2182 vmcb->control.exit_info_1,
2183 vmcb->control.exit_info_2,
2184 vmcb->control.exit_int_info,
2185 vmcb->control.exit_int_info_err,
2188 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2192 /* Exit Guest-Mode */
2193 leave_guest_mode(&svm->vcpu);
2194 svm->nested.vmcb = 0;
2196 /* Give the current vmcb to the guest */
2199 nested_vmcb->save.es = vmcb->save.es;
2200 nested_vmcb->save.cs = vmcb->save.cs;
2201 nested_vmcb->save.ss = vmcb->save.ss;
2202 nested_vmcb->save.ds = vmcb->save.ds;
2203 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2204 nested_vmcb->save.idtr = vmcb->save.idtr;
2205 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2206 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2207 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2208 nested_vmcb->save.cr2 = vmcb->save.cr2;
2209 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2210 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2211 nested_vmcb->save.rip = vmcb->save.rip;
2212 nested_vmcb->save.rsp = vmcb->save.rsp;
2213 nested_vmcb->save.rax = vmcb->save.rax;
2214 nested_vmcb->save.dr7 = vmcb->save.dr7;
2215 nested_vmcb->save.dr6 = vmcb->save.dr6;
2216 nested_vmcb->save.cpl = vmcb->save.cpl;
2218 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2219 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2220 nested_vmcb->control.int_state = vmcb->control.int_state;
2221 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2222 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2223 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2224 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2225 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2226 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2227 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2230 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2231 * to make sure that we do not lose injected events. So check event_inj
2232 * here and copy it to exit_int_info if it is valid.
2233 * Exit_int_info and event_inj can't be both valid because the case
2234 * below only happens on a VMRUN instruction intercept which has
2235 * no valid exit_int_info set.
2237 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2238 struct vmcb_control_area *nc = &nested_vmcb->control;
2240 nc->exit_int_info = vmcb->control.event_inj;
2241 nc->exit_int_info_err = vmcb->control.event_inj_err;
2244 nested_vmcb->control.tlb_ctl = 0;
2245 nested_vmcb->control.event_inj = 0;
2246 nested_vmcb->control.event_inj_err = 0;
2248 /* We always set V_INTR_MASKING and remember the old value in hflags */
2249 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2250 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2252 /* Restore the original control entries */
2253 copy_vmcb_control_area(vmcb, hsave);
2255 kvm_clear_exception_queue(&svm->vcpu);
2256 kvm_clear_interrupt_queue(&svm->vcpu);
2258 svm->nested.nested_cr3 = 0;
2260 /* Restore selected save entries */
2261 svm->vmcb->save.es = hsave->save.es;
2262 svm->vmcb->save.cs = hsave->save.cs;
2263 svm->vmcb->save.ss = hsave->save.ss;
2264 svm->vmcb->save.ds = hsave->save.ds;
2265 svm->vmcb->save.gdtr = hsave->save.gdtr;
2266 svm->vmcb->save.idtr = hsave->save.idtr;
2267 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2268 svm_set_efer(&svm->vcpu, hsave->save.efer);
2269 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2270 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2272 svm->vmcb->save.cr3 = hsave->save.cr3;
2273 svm->vcpu.arch.cr3 = hsave->save.cr3;
2275 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2277 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2278 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2279 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2280 svm->vmcb->save.dr7 = 0;
2281 svm->vmcb->save.cpl = 0;
2282 svm->vmcb->control.exit_int_info = 0;
2284 mark_all_dirty(svm->vmcb);
2286 nested_svm_unmap(page);
2288 nested_svm_uninit_mmu_context(&svm->vcpu);
2289 kvm_mmu_reset_context(&svm->vcpu);
2290 kvm_mmu_load(&svm->vcpu);
2295 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2298 * This function merges the msr permission bitmaps of kvm and the
2299 * nested vmcb. It is omptimized in that it only merges the parts where
2300 * the kvm msr permission bitmap may contain zero bits
2304 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2307 for (i = 0; i < MSRPM_OFFSETS; i++) {
2311 if (msrpm_offsets[i] == 0xffffffff)
2314 p = msrpm_offsets[i];
2315 offset = svm->nested.vmcb_msrpm + (p * 4);
2317 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2320 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2323 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2328 static bool nested_vmcb_checks(struct vmcb *vmcb)
2330 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2333 if (vmcb->control.asid == 0)
2336 if (vmcb->control.nested_ctl && !npt_enabled)
2342 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2344 struct vmcb *nested_vmcb;
2345 struct vmcb *hsave = svm->nested.hsave;
2346 struct vmcb *vmcb = svm->vmcb;
2350 vmcb_gpa = svm->vmcb->save.rax;
2352 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2356 if (!nested_vmcb_checks(nested_vmcb)) {
2357 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2358 nested_vmcb->control.exit_code_hi = 0;
2359 nested_vmcb->control.exit_info_1 = 0;
2360 nested_vmcb->control.exit_info_2 = 0;
2362 nested_svm_unmap(page);
2367 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2368 nested_vmcb->save.rip,
2369 nested_vmcb->control.int_ctl,
2370 nested_vmcb->control.event_inj,
2371 nested_vmcb->control.nested_ctl);
2373 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2374 nested_vmcb->control.intercept_cr >> 16,
2375 nested_vmcb->control.intercept_exceptions,
2376 nested_vmcb->control.intercept);
2378 /* Clear internal status */
2379 kvm_clear_exception_queue(&svm->vcpu);
2380 kvm_clear_interrupt_queue(&svm->vcpu);
2383 * Save the old vmcb, so we don't need to pick what we save, but can
2384 * restore everything when a VMEXIT occurs
2386 hsave->save.es = vmcb->save.es;
2387 hsave->save.cs = vmcb->save.cs;
2388 hsave->save.ss = vmcb->save.ss;
2389 hsave->save.ds = vmcb->save.ds;
2390 hsave->save.gdtr = vmcb->save.gdtr;
2391 hsave->save.idtr = vmcb->save.idtr;
2392 hsave->save.efer = svm->vcpu.arch.efer;
2393 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2394 hsave->save.cr4 = svm->vcpu.arch.cr4;
2395 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2396 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2397 hsave->save.rsp = vmcb->save.rsp;
2398 hsave->save.rax = vmcb->save.rax;
2400 hsave->save.cr3 = vmcb->save.cr3;
2402 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2404 copy_vmcb_control_area(hsave, vmcb);
2406 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2407 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2409 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2411 if (nested_vmcb->control.nested_ctl) {
2412 kvm_mmu_unload(&svm->vcpu);
2413 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2414 nested_svm_init_mmu_context(&svm->vcpu);
2417 /* Load the nested guest state */
2418 svm->vmcb->save.es = nested_vmcb->save.es;
2419 svm->vmcb->save.cs = nested_vmcb->save.cs;
2420 svm->vmcb->save.ss = nested_vmcb->save.ss;
2421 svm->vmcb->save.ds = nested_vmcb->save.ds;
2422 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2423 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2424 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2425 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2426 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2427 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2429 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2430 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2432 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2434 /* Guest paging mode is active - reset mmu */
2435 kvm_mmu_reset_context(&svm->vcpu);
2437 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2438 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2439 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2440 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2442 /* In case we don't even reach vcpu_run, the fields are not updated */
2443 svm->vmcb->save.rax = nested_vmcb->save.rax;
2444 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2445 svm->vmcb->save.rip = nested_vmcb->save.rip;
2446 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2447 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2448 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2450 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2451 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2453 /* cache intercepts */
2454 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2455 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2456 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2457 svm->nested.intercept = nested_vmcb->control.intercept;
2459 svm_flush_tlb(&svm->vcpu);
2460 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2461 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2462 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2464 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2466 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2467 /* We only want the cr8 intercept bits of the guest */
2468 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2469 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2472 /* We don't want to see VMMCALLs from a nested guest */
2473 clr_intercept(svm, INTERCEPT_VMMCALL);
2475 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2476 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2477 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2478 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2479 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2480 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2482 nested_svm_unmap(page);
2484 /* Enter Guest-Mode */
2485 enter_guest_mode(&svm->vcpu);
2488 * Merge guest and host intercepts - must be called with vcpu in
2489 * guest-mode to take affect here
2491 recalc_intercepts(svm);
2493 svm->nested.vmcb = vmcb_gpa;
2497 mark_all_dirty(svm->vmcb);
2502 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2504 to_vmcb->save.fs = from_vmcb->save.fs;
2505 to_vmcb->save.gs = from_vmcb->save.gs;
2506 to_vmcb->save.tr = from_vmcb->save.tr;
2507 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2508 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2509 to_vmcb->save.star = from_vmcb->save.star;
2510 to_vmcb->save.lstar = from_vmcb->save.lstar;
2511 to_vmcb->save.cstar = from_vmcb->save.cstar;
2512 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2513 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2514 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2515 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2518 static int vmload_interception(struct vcpu_svm *svm)
2520 struct vmcb *nested_vmcb;
2523 if (nested_svm_check_permissions(svm))
2526 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2530 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2531 skip_emulated_instruction(&svm->vcpu);
2533 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2534 nested_svm_unmap(page);
2539 static int vmsave_interception(struct vcpu_svm *svm)
2541 struct vmcb *nested_vmcb;
2544 if (nested_svm_check_permissions(svm))
2547 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2551 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2552 skip_emulated_instruction(&svm->vcpu);
2554 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2555 nested_svm_unmap(page);
2560 static int vmrun_interception(struct vcpu_svm *svm)
2562 if (nested_svm_check_permissions(svm))
2565 /* Save rip after vmrun instruction */
2566 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2568 if (!nested_svm_vmrun(svm))
2571 if (!nested_svm_vmrun_msrpm(svm))
2578 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2579 svm->vmcb->control.exit_code_hi = 0;
2580 svm->vmcb->control.exit_info_1 = 0;
2581 svm->vmcb->control.exit_info_2 = 0;
2583 nested_svm_vmexit(svm);
2588 static int stgi_interception(struct vcpu_svm *svm)
2590 if (nested_svm_check_permissions(svm))
2593 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2594 skip_emulated_instruction(&svm->vcpu);
2595 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2602 static int clgi_interception(struct vcpu_svm *svm)
2604 if (nested_svm_check_permissions(svm))
2607 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2608 skip_emulated_instruction(&svm->vcpu);
2612 /* After a CLGI no interrupts should come */
2613 svm_clear_vintr(svm);
2614 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2616 mark_dirty(svm->vmcb, VMCB_INTR);
2621 static int invlpga_interception(struct vcpu_svm *svm)
2623 struct kvm_vcpu *vcpu = &svm->vcpu;
2625 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2626 vcpu->arch.regs[VCPU_REGS_RAX]);
2628 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2629 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2631 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2632 skip_emulated_instruction(&svm->vcpu);
2636 static int skinit_interception(struct vcpu_svm *svm)
2638 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2640 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2644 static int xsetbv_interception(struct vcpu_svm *svm)
2646 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2647 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2649 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2650 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2651 skip_emulated_instruction(&svm->vcpu);
2657 static int invalid_op_interception(struct vcpu_svm *svm)
2659 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2663 static int task_switch_interception(struct vcpu_svm *svm)
2667 int int_type = svm->vmcb->control.exit_int_info &
2668 SVM_EXITINTINFO_TYPE_MASK;
2669 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2671 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2673 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2674 bool has_error_code = false;
2677 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2679 if (svm->vmcb->control.exit_info_2 &
2680 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2681 reason = TASK_SWITCH_IRET;
2682 else if (svm->vmcb->control.exit_info_2 &
2683 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2684 reason = TASK_SWITCH_JMP;
2686 reason = TASK_SWITCH_GATE;
2688 reason = TASK_SWITCH_CALL;
2690 if (reason == TASK_SWITCH_GATE) {
2692 case SVM_EXITINTINFO_TYPE_NMI:
2693 svm->vcpu.arch.nmi_injected = false;
2695 case SVM_EXITINTINFO_TYPE_EXEPT:
2696 if (svm->vmcb->control.exit_info_2 &
2697 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2698 has_error_code = true;
2700 (u32)svm->vmcb->control.exit_info_2;
2702 kvm_clear_exception_queue(&svm->vcpu);
2704 case SVM_EXITINTINFO_TYPE_INTR:
2705 kvm_clear_interrupt_queue(&svm->vcpu);
2712 if (reason != TASK_SWITCH_GATE ||
2713 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2714 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2715 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2716 skip_emulated_instruction(&svm->vcpu);
2718 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2719 has_error_code, error_code) == EMULATE_FAIL) {
2720 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2721 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2722 svm->vcpu.run->internal.ndata = 0;
2728 static int cpuid_interception(struct vcpu_svm *svm)
2730 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2731 kvm_emulate_cpuid(&svm->vcpu);
2735 static int iret_interception(struct vcpu_svm *svm)
2737 ++svm->vcpu.stat.nmi_window_exits;
2738 clr_intercept(svm, INTERCEPT_IRET);
2739 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2740 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2744 static int invlpg_interception(struct vcpu_svm *svm)
2746 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2747 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2749 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2750 skip_emulated_instruction(&svm->vcpu);
2754 static int emulate_on_interception(struct vcpu_svm *svm)
2756 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2759 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2761 unsigned long cr0 = svm->vcpu.arch.cr0;
2765 intercept = svm->nested.intercept;
2767 if (!is_guest_mode(&svm->vcpu) ||
2768 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2771 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2772 val &= ~SVM_CR0_SELECTIVE_MASK;
2775 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2776 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2782 #define CR_VALID (1ULL << 63)
2784 static int cr_interception(struct vcpu_svm *svm)
2790 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2791 return emulate_on_interception(svm);
2793 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2794 return emulate_on_interception(svm);
2796 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2797 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2800 if (cr >= 16) { /* mov to cr */
2802 val = kvm_register_read(&svm->vcpu, reg);
2805 if (!check_selective_cr0_intercepted(svm, val))
2806 err = kvm_set_cr0(&svm->vcpu, val);
2812 err = kvm_set_cr3(&svm->vcpu, val);
2815 err = kvm_set_cr4(&svm->vcpu, val);
2818 err = kvm_set_cr8(&svm->vcpu, val);
2821 WARN(1, "unhandled write to CR%d", cr);
2822 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2825 } else { /* mov from cr */
2828 val = kvm_read_cr0(&svm->vcpu);
2831 val = svm->vcpu.arch.cr2;
2834 val = kvm_read_cr3(&svm->vcpu);
2837 val = kvm_read_cr4(&svm->vcpu);
2840 val = kvm_get_cr8(&svm->vcpu);
2843 WARN(1, "unhandled read from CR%d", cr);
2844 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2847 kvm_register_write(&svm->vcpu, reg, val);
2849 kvm_complete_insn_gp(&svm->vcpu, err);
2854 static int dr_interception(struct vcpu_svm *svm)
2860 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2861 return emulate_on_interception(svm);
2863 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2864 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2866 if (dr >= 16) { /* mov to DRn */
2867 val = kvm_register_read(&svm->vcpu, reg);
2868 kvm_set_dr(&svm->vcpu, dr - 16, val);
2870 err = kvm_get_dr(&svm->vcpu, dr, &val);
2872 kvm_register_write(&svm->vcpu, reg, val);
2875 skip_emulated_instruction(&svm->vcpu);
2880 static int cr8_write_interception(struct vcpu_svm *svm)
2882 struct kvm_run *kvm_run = svm->vcpu.run;
2885 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2886 /* instruction emulation calls kvm_set_cr8() */
2887 r = cr_interception(svm);
2888 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2889 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2892 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2894 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2898 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2900 struct vcpu_svm *svm = to_svm(vcpu);
2903 case MSR_IA32_TSC: {
2904 struct vmcb *vmcb = get_host_vmcb(svm);
2906 *data = vmcb->control.tsc_offset +
2907 svm_scale_tsc(vcpu, native_read_tsc());
2912 *data = svm->vmcb->save.star;
2914 #ifdef CONFIG_X86_64
2916 *data = svm->vmcb->save.lstar;
2919 *data = svm->vmcb->save.cstar;
2921 case MSR_KERNEL_GS_BASE:
2922 *data = svm->vmcb->save.kernel_gs_base;
2924 case MSR_SYSCALL_MASK:
2925 *data = svm->vmcb->save.sfmask;
2928 case MSR_IA32_SYSENTER_CS:
2929 *data = svm->vmcb->save.sysenter_cs;
2931 case MSR_IA32_SYSENTER_EIP:
2932 *data = svm->sysenter_eip;
2934 case MSR_IA32_SYSENTER_ESP:
2935 *data = svm->sysenter_esp;
2938 * Nobody will change the following 5 values in the VMCB so we can
2939 * safely return them on rdmsr. They will always be 0 until LBRV is
2942 case MSR_IA32_DEBUGCTLMSR:
2943 *data = svm->vmcb->save.dbgctl;
2945 case MSR_IA32_LASTBRANCHFROMIP:
2946 *data = svm->vmcb->save.br_from;
2948 case MSR_IA32_LASTBRANCHTOIP:
2949 *data = svm->vmcb->save.br_to;
2951 case MSR_IA32_LASTINTFROMIP:
2952 *data = svm->vmcb->save.last_excp_from;
2954 case MSR_IA32_LASTINTTOIP:
2955 *data = svm->vmcb->save.last_excp_to;
2957 case MSR_VM_HSAVE_PA:
2958 *data = svm->nested.hsave_msr;
2961 *data = svm->nested.vm_cr_msr;
2963 case MSR_IA32_UCODE_REV:
2967 return kvm_get_msr_common(vcpu, ecx, data);
2972 static int rdmsr_interception(struct vcpu_svm *svm)
2974 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2977 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2978 trace_kvm_msr_read_ex(ecx);
2979 kvm_inject_gp(&svm->vcpu, 0);
2981 trace_kvm_msr_read(ecx, data);
2983 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2984 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2985 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2986 skip_emulated_instruction(&svm->vcpu);
2991 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2993 struct vcpu_svm *svm = to_svm(vcpu);
2994 int svm_dis, chg_mask;
2996 if (data & ~SVM_VM_CR_VALID_MASK)
2999 chg_mask = SVM_VM_CR_VALID_MASK;
3001 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3002 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3004 svm->nested.vm_cr_msr &= ~chg_mask;
3005 svm->nested.vm_cr_msr |= (data & chg_mask);
3007 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3009 /* check for svm_disable while efer.svme is set */
3010 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3016 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
3018 struct vcpu_svm *svm = to_svm(vcpu);
3022 kvm_write_tsc(vcpu, data);
3025 svm->vmcb->save.star = data;
3027 #ifdef CONFIG_X86_64
3029 svm->vmcb->save.lstar = data;
3032 svm->vmcb->save.cstar = data;
3034 case MSR_KERNEL_GS_BASE:
3035 svm->vmcb->save.kernel_gs_base = data;
3037 case MSR_SYSCALL_MASK:
3038 svm->vmcb->save.sfmask = data;
3041 case MSR_IA32_SYSENTER_CS:
3042 svm->vmcb->save.sysenter_cs = data;
3044 case MSR_IA32_SYSENTER_EIP:
3045 svm->sysenter_eip = data;
3046 svm->vmcb->save.sysenter_eip = data;
3048 case MSR_IA32_SYSENTER_ESP:
3049 svm->sysenter_esp = data;
3050 svm->vmcb->save.sysenter_esp = data;
3052 case MSR_IA32_DEBUGCTLMSR:
3053 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3054 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3058 if (data & DEBUGCTL_RESERVED_BITS)
3061 svm->vmcb->save.dbgctl = data;
3062 mark_dirty(svm->vmcb, VMCB_LBR);
3063 if (data & (1ULL<<0))
3064 svm_enable_lbrv(svm);
3066 svm_disable_lbrv(svm);
3068 case MSR_VM_HSAVE_PA:
3069 svm->nested.hsave_msr = data;
3072 return svm_set_vm_cr(vcpu, data);
3074 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3077 return kvm_set_msr_common(vcpu, ecx, data);
3082 static int wrmsr_interception(struct vcpu_svm *svm)
3084 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3085 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3086 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3089 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3090 if (svm_set_msr(&svm->vcpu, ecx, data)) {
3091 trace_kvm_msr_write_ex(ecx, data);
3092 kvm_inject_gp(&svm->vcpu, 0);
3094 trace_kvm_msr_write(ecx, data);
3095 skip_emulated_instruction(&svm->vcpu);
3100 static int msr_interception(struct vcpu_svm *svm)
3102 if (svm->vmcb->control.exit_info_1)
3103 return wrmsr_interception(svm);
3105 return rdmsr_interception(svm);
3108 static int interrupt_window_interception(struct vcpu_svm *svm)
3110 struct kvm_run *kvm_run = svm->vcpu.run;
3112 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3113 svm_clear_vintr(svm);
3114 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3115 mark_dirty(svm->vmcb, VMCB_INTR);
3117 * If the user space waits to inject interrupts, exit as soon as
3120 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3121 kvm_run->request_interrupt_window &&
3122 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3123 ++svm->vcpu.stat.irq_window_exits;
3124 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3131 static int pause_interception(struct vcpu_svm *svm)
3133 kvm_vcpu_on_spin(&(svm->vcpu));
3137 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3138 [SVM_EXIT_READ_CR0] = cr_interception,
3139 [SVM_EXIT_READ_CR3] = cr_interception,
3140 [SVM_EXIT_READ_CR4] = cr_interception,
3141 [SVM_EXIT_READ_CR8] = cr_interception,
3142 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3143 [SVM_EXIT_WRITE_CR0] = cr_interception,
3144 [SVM_EXIT_WRITE_CR3] = cr_interception,
3145 [SVM_EXIT_WRITE_CR4] = cr_interception,
3146 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3147 [SVM_EXIT_READ_DR0] = dr_interception,
3148 [SVM_EXIT_READ_DR1] = dr_interception,
3149 [SVM_EXIT_READ_DR2] = dr_interception,
3150 [SVM_EXIT_READ_DR3] = dr_interception,
3151 [SVM_EXIT_READ_DR4] = dr_interception,
3152 [SVM_EXIT_READ_DR5] = dr_interception,
3153 [SVM_EXIT_READ_DR6] = dr_interception,
3154 [SVM_EXIT_READ_DR7] = dr_interception,
3155 [SVM_EXIT_WRITE_DR0] = dr_interception,
3156 [SVM_EXIT_WRITE_DR1] = dr_interception,
3157 [SVM_EXIT_WRITE_DR2] = dr_interception,
3158 [SVM_EXIT_WRITE_DR3] = dr_interception,
3159 [SVM_EXIT_WRITE_DR4] = dr_interception,
3160 [SVM_EXIT_WRITE_DR5] = dr_interception,
3161 [SVM_EXIT_WRITE_DR6] = dr_interception,
3162 [SVM_EXIT_WRITE_DR7] = dr_interception,
3163 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3164 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3165 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3166 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3167 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3168 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3169 [SVM_EXIT_INTR] = intr_interception,
3170 [SVM_EXIT_NMI] = nmi_interception,
3171 [SVM_EXIT_SMI] = nop_on_interception,
3172 [SVM_EXIT_INIT] = nop_on_interception,
3173 [SVM_EXIT_VINTR] = interrupt_window_interception,
3174 [SVM_EXIT_CPUID] = cpuid_interception,
3175 [SVM_EXIT_IRET] = iret_interception,
3176 [SVM_EXIT_INVD] = emulate_on_interception,
3177 [SVM_EXIT_PAUSE] = pause_interception,
3178 [SVM_EXIT_HLT] = halt_interception,
3179 [SVM_EXIT_INVLPG] = invlpg_interception,
3180 [SVM_EXIT_INVLPGA] = invlpga_interception,
3181 [SVM_EXIT_IOIO] = io_interception,
3182 [SVM_EXIT_MSR] = msr_interception,
3183 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3184 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3185 [SVM_EXIT_VMRUN] = vmrun_interception,
3186 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3187 [SVM_EXIT_VMLOAD] = vmload_interception,
3188 [SVM_EXIT_VMSAVE] = vmsave_interception,
3189 [SVM_EXIT_STGI] = stgi_interception,
3190 [SVM_EXIT_CLGI] = clgi_interception,
3191 [SVM_EXIT_SKINIT] = skinit_interception,
3192 [SVM_EXIT_WBINVD] = emulate_on_interception,
3193 [SVM_EXIT_MONITOR] = invalid_op_interception,
3194 [SVM_EXIT_MWAIT] = invalid_op_interception,
3195 [SVM_EXIT_XSETBV] = xsetbv_interception,
3196 [SVM_EXIT_NPF] = pf_interception,
3199 static void dump_vmcb(struct kvm_vcpu *vcpu)
3201 struct vcpu_svm *svm = to_svm(vcpu);
3202 struct vmcb_control_area *control = &svm->vmcb->control;
3203 struct vmcb_save_area *save = &svm->vmcb->save;
3205 pr_err("VMCB Control Area:\n");
3206 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3207 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3208 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3209 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3210 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3211 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3212 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3213 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3214 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3215 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3216 pr_err("%-20s%d\n", "asid:", control->asid);
3217 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3218 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3219 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3220 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3221 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3222 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3223 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3224 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3225 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3226 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3227 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3228 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3229 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3230 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3231 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3232 pr_err("VMCB State Save Area:\n");
3233 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3235 save->es.selector, save->es.attrib,
3236 save->es.limit, save->es.base);
3237 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3239 save->cs.selector, save->cs.attrib,
3240 save->cs.limit, save->cs.base);
3241 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3243 save->ss.selector, save->ss.attrib,
3244 save->ss.limit, save->ss.base);
3245 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3247 save->ds.selector, save->ds.attrib,
3248 save->ds.limit, save->ds.base);
3249 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3251 save->fs.selector, save->fs.attrib,
3252 save->fs.limit, save->fs.base);
3253 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3255 save->gs.selector, save->gs.attrib,
3256 save->gs.limit, save->gs.base);
3257 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3259 save->gdtr.selector, save->gdtr.attrib,
3260 save->gdtr.limit, save->gdtr.base);
3261 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3263 save->ldtr.selector, save->ldtr.attrib,
3264 save->ldtr.limit, save->ldtr.base);
3265 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3267 save->idtr.selector, save->idtr.attrib,
3268 save->idtr.limit, save->idtr.base);
3269 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3271 save->tr.selector, save->tr.attrib,
3272 save->tr.limit, save->tr.base);
3273 pr_err("cpl: %d efer: %016llx\n",
3274 save->cpl, save->efer);
3275 pr_err("%-15s %016llx %-13s %016llx\n",
3276 "cr0:", save->cr0, "cr2:", save->cr2);
3277 pr_err("%-15s %016llx %-13s %016llx\n",
3278 "cr3:", save->cr3, "cr4:", save->cr4);
3279 pr_err("%-15s %016llx %-13s %016llx\n",
3280 "dr6:", save->dr6, "dr7:", save->dr7);
3281 pr_err("%-15s %016llx %-13s %016llx\n",
3282 "rip:", save->rip, "rflags:", save->rflags);
3283 pr_err("%-15s %016llx %-13s %016llx\n",
3284 "rsp:", save->rsp, "rax:", save->rax);
3285 pr_err("%-15s %016llx %-13s %016llx\n",
3286 "star:", save->star, "lstar:", save->lstar);
3287 pr_err("%-15s %016llx %-13s %016llx\n",
3288 "cstar:", save->cstar, "sfmask:", save->sfmask);
3289 pr_err("%-15s %016llx %-13s %016llx\n",
3290 "kernel_gs_base:", save->kernel_gs_base,
3291 "sysenter_cs:", save->sysenter_cs);
3292 pr_err("%-15s %016llx %-13s %016llx\n",
3293 "sysenter_esp:", save->sysenter_esp,
3294 "sysenter_eip:", save->sysenter_eip);
3295 pr_err("%-15s %016llx %-13s %016llx\n",
3296 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3297 pr_err("%-15s %016llx %-13s %016llx\n",
3298 "br_from:", save->br_from, "br_to:", save->br_to);
3299 pr_err("%-15s %016llx %-13s %016llx\n",
3300 "excp_from:", save->last_excp_from,
3301 "excp_to:", save->last_excp_to);
3304 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3306 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3308 *info1 = control->exit_info_1;
3309 *info2 = control->exit_info_2;
3312 static int handle_exit(struct kvm_vcpu *vcpu)
3314 struct vcpu_svm *svm = to_svm(vcpu);
3315 struct kvm_run *kvm_run = vcpu->run;
3316 u32 exit_code = svm->vmcb->control.exit_code;
3318 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3320 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3321 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3323 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3325 if (unlikely(svm->nested.exit_required)) {
3326 nested_svm_vmexit(svm);
3327 svm->nested.exit_required = false;
3332 if (is_guest_mode(vcpu)) {
3335 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3336 svm->vmcb->control.exit_info_1,
3337 svm->vmcb->control.exit_info_2,
3338 svm->vmcb->control.exit_int_info,
3339 svm->vmcb->control.exit_int_info_err,
3342 vmexit = nested_svm_exit_special(svm);
3344 if (vmexit == NESTED_EXIT_CONTINUE)
3345 vmexit = nested_svm_exit_handled(svm);
3347 if (vmexit == NESTED_EXIT_DONE)
3351 svm_complete_interrupts(svm);
3353 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3354 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3355 kvm_run->fail_entry.hardware_entry_failure_reason
3356 = svm->vmcb->control.exit_code;
3357 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3362 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3363 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3364 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3365 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3366 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3368 __func__, svm->vmcb->control.exit_int_info,
3371 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3372 || !svm_exit_handlers[exit_code]) {
3373 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3374 kvm_run->hw.hardware_exit_reason = exit_code;
3378 return svm_exit_handlers[exit_code](svm);
3381 static void reload_tss(struct kvm_vcpu *vcpu)
3383 int cpu = raw_smp_processor_id();
3385 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3386 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3390 static void pre_svm_run(struct vcpu_svm *svm)
3392 int cpu = raw_smp_processor_id();
3394 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3396 /* FIXME: handle wraparound of asid_generation */
3397 if (svm->asid_generation != sd->asid_generation)
3401 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3403 struct vcpu_svm *svm = to_svm(vcpu);
3405 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3406 vcpu->arch.hflags |= HF_NMI_MASK;
3407 set_intercept(svm, INTERCEPT_IRET);
3408 ++vcpu->stat.nmi_injections;
3411 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3413 struct vmcb_control_area *control;
3415 control = &svm->vmcb->control;
3416 control->int_vector = irq;
3417 control->int_ctl &= ~V_INTR_PRIO_MASK;
3418 control->int_ctl |= V_IRQ_MASK |
3419 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3420 mark_dirty(svm->vmcb, VMCB_INTR);
3423 static void svm_set_irq(struct kvm_vcpu *vcpu)
3425 struct vcpu_svm *svm = to_svm(vcpu);
3427 BUG_ON(!(gif_set(svm)));
3429 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3430 ++vcpu->stat.irq_injections;
3432 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3433 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3436 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3438 struct vcpu_svm *svm = to_svm(vcpu);
3440 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3447 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3450 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3452 struct vcpu_svm *svm = to_svm(vcpu);
3453 struct vmcb *vmcb = svm->vmcb;
3455 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3456 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3457 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3462 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3464 struct vcpu_svm *svm = to_svm(vcpu);
3466 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3469 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3471 struct vcpu_svm *svm = to_svm(vcpu);
3474 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3475 set_intercept(svm, INTERCEPT_IRET);
3477 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3478 clr_intercept(svm, INTERCEPT_IRET);
3482 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3484 struct vcpu_svm *svm = to_svm(vcpu);
3485 struct vmcb *vmcb = svm->vmcb;
3488 if (!gif_set(svm) ||
3489 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3492 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3494 if (is_guest_mode(vcpu))
3495 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3500 static void enable_irq_window(struct kvm_vcpu *vcpu)
3502 struct vcpu_svm *svm = to_svm(vcpu);
3505 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3506 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3507 * get that intercept, this function will be called again though and
3508 * we'll get the vintr intercept.
3510 if (gif_set(svm) && nested_svm_intr(svm)) {
3512 svm_inject_irq(svm, 0x0);
3516 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3518 struct vcpu_svm *svm = to_svm(vcpu);
3520 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3522 return; /* IRET will cause a vm exit */
3525 * Something prevents NMI from been injected. Single step over possible
3526 * problem (IRET or exception injection or interrupt shadow)
3528 svm->nmi_singlestep = true;
3529 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3530 update_db_intercept(vcpu);
3533 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3538 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3540 struct vcpu_svm *svm = to_svm(vcpu);
3542 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3543 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3545 svm->asid_generation--;
3548 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3552 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3554 struct vcpu_svm *svm = to_svm(vcpu);
3556 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3559 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3560 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3561 kvm_set_cr8(vcpu, cr8);
3565 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3567 struct vcpu_svm *svm = to_svm(vcpu);
3570 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3573 cr8 = kvm_get_cr8(vcpu);
3574 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3575 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3578 static void svm_complete_interrupts(struct vcpu_svm *svm)
3582 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3583 unsigned int3_injected = svm->int3_injected;
3585 svm->int3_injected = 0;
3588 * If we've made progress since setting HF_IRET_MASK, we've
3589 * executed an IRET and can allow NMI injection.
3591 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3592 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3593 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3594 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3597 svm->vcpu.arch.nmi_injected = false;
3598 kvm_clear_exception_queue(&svm->vcpu);
3599 kvm_clear_interrupt_queue(&svm->vcpu);
3601 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3604 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3606 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3607 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3610 case SVM_EXITINTINFO_TYPE_NMI:
3611 svm->vcpu.arch.nmi_injected = true;
3613 case SVM_EXITINTINFO_TYPE_EXEPT:
3615 * In case of software exceptions, do not reinject the vector,
3616 * but re-execute the instruction instead. Rewind RIP first
3617 * if we emulated INT3 before.
3619 if (kvm_exception_is_soft(vector)) {
3620 if (vector == BP_VECTOR && int3_injected &&
3621 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3622 kvm_rip_write(&svm->vcpu,
3623 kvm_rip_read(&svm->vcpu) -
3627 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3628 u32 err = svm->vmcb->control.exit_int_info_err;
3629 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3632 kvm_requeue_exception(&svm->vcpu, vector);
3634 case SVM_EXITINTINFO_TYPE_INTR:
3635 kvm_queue_interrupt(&svm->vcpu, vector, false);
3642 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3644 struct vcpu_svm *svm = to_svm(vcpu);
3645 struct vmcb_control_area *control = &svm->vmcb->control;
3647 control->exit_int_info = control->event_inj;
3648 control->exit_int_info_err = control->event_inj_err;
3649 control->event_inj = 0;
3650 svm_complete_interrupts(svm);
3653 #ifdef CONFIG_X86_64
3659 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3661 struct vcpu_svm *svm = to_svm(vcpu);
3663 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3664 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3665 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3668 * A vmexit emulation is required before the vcpu can be executed
3671 if (unlikely(svm->nested.exit_required))
3676 sync_lapic_to_cr8(vcpu);
3678 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3685 "push %%"R"bp; \n\t"
3686 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3687 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3688 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3689 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3690 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3691 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3692 #ifdef CONFIG_X86_64
3693 "mov %c[r8](%[svm]), %%r8 \n\t"
3694 "mov %c[r9](%[svm]), %%r9 \n\t"
3695 "mov %c[r10](%[svm]), %%r10 \n\t"
3696 "mov %c[r11](%[svm]), %%r11 \n\t"
3697 "mov %c[r12](%[svm]), %%r12 \n\t"
3698 "mov %c[r13](%[svm]), %%r13 \n\t"
3699 "mov %c[r14](%[svm]), %%r14 \n\t"
3700 "mov %c[r15](%[svm]), %%r15 \n\t"
3703 /* Enter guest mode */
3705 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3706 __ex(SVM_VMLOAD) "\n\t"
3707 __ex(SVM_VMRUN) "\n\t"
3708 __ex(SVM_VMSAVE) "\n\t"
3711 /* Save guest registers, load host registers */
3712 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3713 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3714 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3715 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3716 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3717 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3718 #ifdef CONFIG_X86_64
3719 "mov %%r8, %c[r8](%[svm]) \n\t"
3720 "mov %%r9, %c[r9](%[svm]) \n\t"
3721 "mov %%r10, %c[r10](%[svm]) \n\t"
3722 "mov %%r11, %c[r11](%[svm]) \n\t"
3723 "mov %%r12, %c[r12](%[svm]) \n\t"
3724 "mov %%r13, %c[r13](%[svm]) \n\t"
3725 "mov %%r14, %c[r14](%[svm]) \n\t"
3726 "mov %%r15, %c[r15](%[svm]) \n\t"
3731 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3732 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3733 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3734 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3735 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3736 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3737 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3738 #ifdef CONFIG_X86_64
3739 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3740 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3741 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3742 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3743 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3744 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3745 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3746 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3749 , R"bx", R"cx", R"dx", R"si", R"di"
3750 #ifdef CONFIG_X86_64
3751 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3755 #ifdef CONFIG_X86_64
3756 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3758 loadsegment(fs, svm->host.fs);
3759 #ifndef CONFIG_X86_32_LAZY_GS
3760 loadsegment(gs, svm->host.gs);
3766 local_irq_disable();
3768 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3769 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3770 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3771 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3773 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3774 kvm_before_handle_nmi(&svm->vcpu);
3778 /* Any pending NMI will happen here */
3780 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3781 kvm_after_handle_nmi(&svm->vcpu);
3783 sync_cr8_to_lapic(vcpu);
3787 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3789 /* if exit due to PF check for async PF */
3790 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3791 svm->apf_reason = kvm_read_and_reset_pf_reason();
3794 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3795 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3799 * We need to handle MC intercepts here before the vcpu has a chance to
3800 * change the physical cpu
3802 if (unlikely(svm->vmcb->control.exit_code ==
3803 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3804 svm_handle_mce(svm);
3806 mark_all_clean(svm->vmcb);
3811 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3813 struct vcpu_svm *svm = to_svm(vcpu);
3815 svm->vmcb->save.cr3 = root;
3816 mark_dirty(svm->vmcb, VMCB_CR);
3817 svm_flush_tlb(vcpu);
3820 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3822 struct vcpu_svm *svm = to_svm(vcpu);
3824 svm->vmcb->control.nested_cr3 = root;
3825 mark_dirty(svm->vmcb, VMCB_NPT);
3827 /* Also sync guest cr3 here in case we live migrate */
3828 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3829 mark_dirty(svm->vmcb, VMCB_CR);
3831 svm_flush_tlb(vcpu);
3834 static int is_disabled(void)
3838 rdmsrl(MSR_VM_CR, vm_cr);
3839 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3846 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3849 * Patch in the VMMCALL instruction:
3851 hypercall[0] = 0x0f;
3852 hypercall[1] = 0x01;
3853 hypercall[2] = 0xd9;
3856 static void svm_check_processor_compat(void *rtn)
3861 static bool svm_cpu_has_accelerated_tpr(void)
3866 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3871 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3875 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3880 entry->ecx |= (1 << 2); /* Set SVM bit */
3883 entry->eax = 1; /* SVM revision 1 */
3884 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3885 ASID emulation to nested SVM */
3886 entry->ecx = 0; /* Reserved */
3887 entry->edx = 0; /* Per default do not support any
3888 additional features */
3890 /* Support next_rip if host supports it */
3891 if (boot_cpu_has(X86_FEATURE_NRIPS))
3892 entry->edx |= SVM_FEATURE_NRIP;
3894 /* Support NPT for the guest if enabled */
3896 entry->edx |= SVM_FEATURE_NPT;
3902 static int svm_get_lpage_level(void)
3904 return PT_PDPE_LEVEL;
3907 static bool svm_rdtscp_supported(void)
3912 static bool svm_has_wbinvd_exit(void)
3917 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3919 struct vcpu_svm *svm = to_svm(vcpu);
3921 set_exception_intercept(svm, NM_VECTOR);
3922 update_cr0_intercept(svm);
3925 #define PRE_EX(exit) { .exit_code = (exit), \
3926 .stage = X86_ICPT_PRE_EXCEPT, }
3927 #define POST_EX(exit) { .exit_code = (exit), \
3928 .stage = X86_ICPT_POST_EXCEPT, }
3929 #define POST_MEM(exit) { .exit_code = (exit), \
3930 .stage = X86_ICPT_POST_MEMACCESS, }
3932 static struct __x86_intercept {
3934 enum x86_intercept_stage stage;
3935 } x86_intercept_map[] = {
3936 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3937 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3938 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3939 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3940 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3941 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3942 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
3943 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3944 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3945 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3946 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3947 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3948 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3949 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3950 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
3951 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3952 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3953 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3954 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3955 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3956 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3957 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3958 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
3959 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3960 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3961 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
3962 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3963 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3964 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3965 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3966 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3967 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3968 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3969 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3970 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
3971 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3972 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3973 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3974 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3975 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3976 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3977 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
3978 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3979 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3980 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
3981 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
3988 static int svm_check_intercept(struct kvm_vcpu *vcpu,
3989 struct x86_instruction_info *info,
3990 enum x86_intercept_stage stage)
3992 struct vcpu_svm *svm = to_svm(vcpu);
3993 int vmexit, ret = X86EMUL_CONTINUE;
3994 struct __x86_intercept icpt_info;
3995 struct vmcb *vmcb = svm->vmcb;
3997 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4000 icpt_info = x86_intercept_map[info->intercept];
4002 if (stage != icpt_info.stage)
4005 switch (icpt_info.exit_code) {
4006 case SVM_EXIT_READ_CR0:
4007 if (info->intercept == x86_intercept_cr_read)
4008 icpt_info.exit_code += info->modrm_reg;
4010 case SVM_EXIT_WRITE_CR0: {
4011 unsigned long cr0, val;
4014 if (info->intercept == x86_intercept_cr_write)
4015 icpt_info.exit_code += info->modrm_reg;
4017 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4020 intercept = svm->nested.intercept;
4022 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4025 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4026 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4028 if (info->intercept == x86_intercept_lmsw) {
4031 /* lmsw can't clear PE - catch this here */
4032 if (cr0 & X86_CR0_PE)
4037 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4041 case SVM_EXIT_READ_DR0:
4042 case SVM_EXIT_WRITE_DR0:
4043 icpt_info.exit_code += info->modrm_reg;
4046 if (info->intercept == x86_intercept_wrmsr)
4047 vmcb->control.exit_info_1 = 1;
4049 vmcb->control.exit_info_1 = 0;
4051 case SVM_EXIT_PAUSE:
4053 * We get this for NOP only, but pause
4054 * is rep not, check this here
4056 if (info->rep_prefix != REPE_PREFIX)
4058 case SVM_EXIT_IOIO: {
4062 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4064 if (info->intercept == x86_intercept_in ||
4065 info->intercept == x86_intercept_ins) {
4066 exit_info |= SVM_IOIO_TYPE_MASK;
4067 bytes = info->src_bytes;
4069 bytes = info->dst_bytes;
4072 if (info->intercept == x86_intercept_outs ||
4073 info->intercept == x86_intercept_ins)
4074 exit_info |= SVM_IOIO_STR_MASK;
4076 if (info->rep_prefix)
4077 exit_info |= SVM_IOIO_REP_MASK;
4079 bytes = min(bytes, 4u);
4081 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4083 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4085 vmcb->control.exit_info_1 = exit_info;
4086 vmcb->control.exit_info_2 = info->next_rip;
4094 vmcb->control.next_rip = info->next_rip;
4095 vmcb->control.exit_code = icpt_info.exit_code;
4096 vmexit = nested_svm_exit_handled(svm);
4098 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4105 static struct kvm_x86_ops svm_x86_ops = {
4106 .cpu_has_kvm_support = has_svm,
4107 .disabled_by_bios = is_disabled,
4108 .hardware_setup = svm_hardware_setup,
4109 .hardware_unsetup = svm_hardware_unsetup,
4110 .check_processor_compatibility = svm_check_processor_compat,
4111 .hardware_enable = svm_hardware_enable,
4112 .hardware_disable = svm_hardware_disable,
4113 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4115 .vcpu_create = svm_create_vcpu,
4116 .vcpu_free = svm_free_vcpu,
4117 .vcpu_reset = svm_vcpu_reset,
4119 .prepare_guest_switch = svm_prepare_guest_switch,
4120 .vcpu_load = svm_vcpu_load,
4121 .vcpu_put = svm_vcpu_put,
4123 .set_guest_debug = svm_guest_debug,
4124 .get_msr = svm_get_msr,
4125 .set_msr = svm_set_msr,
4126 .get_segment_base = svm_get_segment_base,
4127 .get_segment = svm_get_segment,
4128 .set_segment = svm_set_segment,
4129 .get_cpl = svm_get_cpl,
4130 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4131 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4132 .decache_cr3 = svm_decache_cr3,
4133 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4134 .set_cr0 = svm_set_cr0,
4135 .set_cr3 = svm_set_cr3,
4136 .set_cr4 = svm_set_cr4,
4137 .set_efer = svm_set_efer,
4138 .get_idt = svm_get_idt,
4139 .set_idt = svm_set_idt,
4140 .get_gdt = svm_get_gdt,
4141 .set_gdt = svm_set_gdt,
4142 .set_dr7 = svm_set_dr7,
4143 .cache_reg = svm_cache_reg,
4144 .get_rflags = svm_get_rflags,
4145 .set_rflags = svm_set_rflags,
4146 .fpu_activate = svm_fpu_activate,
4147 .fpu_deactivate = svm_fpu_deactivate,
4149 .tlb_flush = svm_flush_tlb,
4151 .run = svm_vcpu_run,
4152 .handle_exit = handle_exit,
4153 .skip_emulated_instruction = skip_emulated_instruction,
4154 .set_interrupt_shadow = svm_set_interrupt_shadow,
4155 .get_interrupt_shadow = svm_get_interrupt_shadow,
4156 .patch_hypercall = svm_patch_hypercall,
4157 .set_irq = svm_set_irq,
4158 .set_nmi = svm_inject_nmi,
4159 .queue_exception = svm_queue_exception,
4160 .cancel_injection = svm_cancel_injection,
4161 .interrupt_allowed = svm_interrupt_allowed,
4162 .nmi_allowed = svm_nmi_allowed,
4163 .get_nmi_mask = svm_get_nmi_mask,
4164 .set_nmi_mask = svm_set_nmi_mask,
4165 .enable_nmi_window = enable_nmi_window,
4166 .enable_irq_window = enable_irq_window,
4167 .update_cr8_intercept = update_cr8_intercept,
4169 .set_tss_addr = svm_set_tss_addr,
4170 .get_tdp_level = get_npt_level,
4171 .get_mt_mask = svm_get_mt_mask,
4173 .get_exit_info = svm_get_exit_info,
4175 .get_lpage_level = svm_get_lpage_level,
4177 .cpuid_update = svm_cpuid_update,
4179 .rdtscp_supported = svm_rdtscp_supported,
4181 .set_supported_cpuid = svm_set_supported_cpuid,
4183 .has_wbinvd_exit = svm_has_wbinvd_exit,
4185 .set_tsc_khz = svm_set_tsc_khz,
4186 .write_tsc_offset = svm_write_tsc_offset,
4187 .adjust_tsc_offset = svm_adjust_tsc_offset,
4188 .compute_tsc_offset = svm_compute_tsc_offset,
4190 .set_tdp_cr3 = set_tdp_cr3,
4192 .check_intercept = svm_check_intercept,
4195 static int __init svm_init(void)
4197 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4198 __alignof__(struct vcpu_svm), THIS_MODULE);
4201 static void __exit svm_exit(void)
4206 module_init(svm_init)
4207 module_exit(svm_exit)