arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 MODULE_AUTHOR("Qumranet");
  31 MODULE_LICENSE("GPL");
  32
  33 #define IOPM_ALLOC_ORDER 2
  34 #define MSRPM_ALLOC_ORDER 1
  35
  36 #define DB_VECTOR 1
  37 #define UD_VECTOR 6
  38 #define GP_VECTOR 13
  39
  40 #define DR7_GD_MASK (1 << 13)
  41 #define DR6_BD_MASK (1 << 13)
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_DEATURE_SVML (1 << 2)
  49
  50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  51
  52 /* enable NPT for AMD64 and X86 with PAE */
  53 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  54 static bool npt_enabled = true;
  55 #else
  56 static bool npt_enabled = false;
  57 #endif
  58 static int npt = 1;
  59
  60 module_param(npt, int, S_IRUGO);
  61
  62 static void kvm_reput_irq(struct vcpu_svm *svm);
  63
  64 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  65 {
  66         return container_of(vcpu, struct vcpu_svm, vcpu);
  67 }
  68
  69 static unsigned long iopm_base;
  70
  71 struct kvm_ldttss_desc {
  72         u16 limit0;
  73         u16 base0;
  74         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  75         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  76         u32 base3;
  77         u32 zero1;
  78 } __attribute__((packed));
  79
  80 struct svm_cpu_data {
  81         int cpu;
  82
  83         u64 asid_generation;
  84         u32 max_asid;
  85         u32 next_asid;
  86         struct kvm_ldttss_desc *tss_desc;
  87
  88         struct page *save_area;
  89 };
  90
  91 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  92 static uint32_t svm_features;
  93
  94 struct svm_init_data {
  95         int cpu;
  96         int r;
  97 };
  98
  99 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 100
 101 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 102 #define MSRS_RANGE_SIZE 2048
 103 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 104
 105 #define MAX_INST_SIZE 15
 106
 107 static inline u32 svm_has(u32 feat)
 108 {
 109         return svm_features & feat;
 110 }
 111
 112 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 113 {
 114         int word_index = __ffs(vcpu->arch.irq_summary);
 115         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 116         int irq = word_index * BITS_PER_LONG + bit_index;
 117
 118         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 119         if (!vcpu->arch.irq_pending[word_index])
 120                 clear_bit(word_index, &vcpu->arch.irq_summary);
 121         return irq;
 122 }
 123
 124 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 125 {
 126         set_bit(irq, vcpu->arch.irq_pending);
 127         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 128 }
 129
 130 static inline void clgi(void)
 131 {
 132         asm volatile (SVM_CLGI);
 133 }
 134
 135 static inline void stgi(void)
 136 {
 137         asm volatile (SVM_STGI);
 138 }
 139
 140 static inline void invlpga(unsigned long addr, u32 asid)
 141 {
 142         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 143 }
 144
 145 static inline unsigned long kvm_read_cr2(void)
 146 {
 147         unsigned long cr2;
 148
 149         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 150         return cr2;
 151 }
 152
 153 static inline void kvm_write_cr2(unsigned long val)
 154 {
 155         asm volatile ("mov %0, %%cr2" :: "r" (val));
 156 }
 157
 158 static inline unsigned long read_dr6(void)
 159 {
 160         unsigned long dr6;
 161
 162         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 163         return dr6;
 164 }
 165
 166 static inline void write_dr6(unsigned long val)
 167 {
 168         asm volatile ("mov %0, %%dr6" :: "r" (val));
 169 }
 170
 171 static inline unsigned long read_dr7(void)
 172 {
 173         unsigned long dr7;
 174
 175         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 176         return dr7;
 177 }
 178
 179 static inline void write_dr7(unsigned long val)
 180 {
 181         asm volatile ("mov %0, %%dr7" :: "r" (val));
 182 }
 183
 184 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 185 {
 186         to_svm(vcpu)->asid_generation--;
 187 }
 188
 189 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 190 {
 191         force_new_asid(vcpu);
 192 }
 193
 194 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 195 {
 196         if (!npt_enabled && !(efer & EFER_LMA))
 197                 efer &= ~EFER_LME;
 198
 199         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 200         vcpu->arch.shadow_efer = efer;
 201 }
 202
 203 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 204                                 bool has_error_code, u32 error_code)
 205 {
 206         struct vcpu_svm *svm = to_svm(vcpu);
 207
 208         svm->vmcb->control.event_inj = nr
 209                 | SVM_EVTINJ_VALID
 210                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 211                 | SVM_EVTINJ_TYPE_EXEPT;
 212         svm->vmcb->control.event_inj_err = error_code;
 213 }
 214
 215 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 216 {
 217         struct vcpu_svm *svm = to_svm(vcpu);
 218
 219         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 220 }
 221
 222 static int is_external_interrupt(u32 info)
 223 {
 224         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 225         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 226 }
 227
 228 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 229 {
 230         struct vcpu_svm *svm = to_svm(vcpu);
 231
 232         if (!svm->next_rip) {
 233                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 234                 return;
 235         }
 236         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 237                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 238                        __func__,
 239                        svm->vmcb->save.rip,
 240                        svm->next_rip);
 241
 242         vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 243         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 244
 245         vcpu->arch.interrupt_window_open = 1;
 246 }
 247
 248 static int has_svm(void)
 249 {
 250         uint32_t eax, ebx, ecx, edx;
 251
 252         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 253                 printk(KERN_INFO "has_svm: not amd\n");
 254                 return 0;
 255         }
 256
 257         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 258         if (eax < SVM_CPUID_FUNC) {
 259                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 260                 return 0;
 261         }
 262
 263         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 264         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 265                 printk(KERN_DEBUG "has_svm: svm not available\n");
 266                 return 0;
 267         }
 268         return 1;
 269 }
 270
 271 static void svm_hardware_disable(void *garbage)
 272 {
 273         struct svm_cpu_data *svm_data
 274                 = per_cpu(svm_data, raw_smp_processor_id());
 275
 276         if (svm_data) {
 277                 uint64_t efer;
 278
 279                 wrmsrl(MSR_VM_HSAVE_PA, 0);
 280                 rdmsrl(MSR_EFER, efer);
 281                 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 282                 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 283                 __free_page(svm_data->save_area);
 284                 kfree(svm_data);
 285         }
 286 }
 287
 288 static void svm_hardware_enable(void *garbage)
 289 {
 290
 291         struct svm_cpu_data *svm_data;
 292         uint64_t efer;
 293         struct desc_ptr gdt_descr;
 294         struct desc_struct *gdt;
 295         int me = raw_smp_processor_id();
 296
 297         if (!has_svm()) {
 298                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 299                 return;
 300         }
 301         svm_data = per_cpu(svm_data, me);
 302
 303         if (!svm_data) {
 304                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 305                        me);
 306                 return;
 307         }
 308
 309         svm_data->asid_generation = 1;
 310         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 311         svm_data->next_asid = svm_data->max_asid + 1;
 312
 313         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 314         gdt = (struct desc_struct *)gdt_descr.address;
 315         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 316
 317         rdmsrl(MSR_EFER, efer);
 318         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 319
 320         wrmsrl(MSR_VM_HSAVE_PA,
 321                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 322 }
 323
 324 static int svm_cpu_init(int cpu)
 325 {
 326         struct svm_cpu_data *svm_data;
 327         int r;
 328
 329         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 330         if (!svm_data)
 331                 return -ENOMEM;
 332         svm_data->cpu = cpu;
 333         svm_data->save_area = alloc_page(GFP_KERNEL);
 334         r = -ENOMEM;
 335         if (!svm_data->save_area)
 336                 goto err_1;
 337
 338         per_cpu(svm_data, cpu) = svm_data;
 339
 340         return 0;
 341
 342 err_1:
 343         kfree(svm_data);
 344         return r;
 345
 346 }
 347
 348 static void set_msr_interception(u32 *msrpm, unsigned msr,
 349                                  int read, int write)
 350 {
 351         int i;
 352
 353         for (i = 0; i < NUM_MSR_MAPS; i++) {
 354                 if (msr >= msrpm_ranges[i] &&
 355                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 356                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 357                                           msrpm_ranges[i]) * 2;
 358
 359                         u32 *base = msrpm + (msr_offset / 32);
 360                         u32 msr_shift = msr_offset % 32;
 361                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 362                         *base = (*base & ~(0x3 << msr_shift)) |
 363                                 (mask << msr_shift);
 364                         return;
 365                 }
 366         }
 367         BUG();
 368 }
 369
 370 static void svm_vcpu_init_msrpm(u32 *msrpm)
 371 {
 372         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 373
 374 #ifdef CONFIG_X86_64
 375         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 376         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 377         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 378         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 379         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 380         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 381 #endif
 382         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 383         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 384         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 385         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 386 }
 387
 388 static void svm_enable_lbrv(struct vcpu_svm *svm)
 389 {
 390         u32 *msrpm = svm->msrpm;
 391
 392         svm->vmcb->control.lbr_ctl = 1;
 393         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 394         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 395         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 396         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 397 }
 398
 399 static void svm_disable_lbrv(struct vcpu_svm *svm)
 400 {
 401         u32 *msrpm = svm->msrpm;
 402
 403         svm->vmcb->control.lbr_ctl = 0;
 404         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 405         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 406         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 407         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 408 }
 409
 410 static __init int svm_hardware_setup(void)
 411 {
 412         int cpu;
 413         struct page *iopm_pages;
 414         void *iopm_va;
 415         int r;
 416
 417         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 418
 419         if (!iopm_pages)
 420                 return -ENOMEM;
 421
 422         iopm_va = page_address(iopm_pages);
 423         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 424         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 425         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 426
 427         if (boot_cpu_has(X86_FEATURE_NX))
 428                 kvm_enable_efer_bits(EFER_NX);
 429
 430         for_each_online_cpu(cpu) {
 431                 r = svm_cpu_init(cpu);
 432                 if (r)
 433                         goto err;
 434         }
 435
 436         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 437
 438         if (!svm_has(SVM_FEATURE_NPT))
 439                 npt_enabled = false;
 440
 441         if (npt_enabled && !npt) {
 442                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 443                 npt_enabled = false;
 444         }
 445
 446         if (npt_enabled) {
 447                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 448                 kvm_enable_tdp();
 449         }
 450
 451         return 0;
 452
 453 err:
 454         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 455         iopm_base = 0;
 456         return r;
 457 }
 458
 459 static __exit void svm_hardware_unsetup(void)
 460 {
 461         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 462         iopm_base = 0;
 463 }
 464
 465 static void init_seg(struct vmcb_seg *seg)
 466 {
 467         seg->selector = 0;
 468         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 469                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 470         seg->limit = 0xffff;
 471         seg->base = 0;
 472 }
 473
 474 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 475 {
 476         seg->selector = 0;
 477         seg->attrib = SVM_SELECTOR_P_MASK | type;
 478         seg->limit = 0xffff;
 479         seg->base = 0;
 480 }
 481
 482 static void init_vmcb(struct vcpu_svm *svm)
 483 {
 484         struct vmcb_control_area *control = &svm->vmcb->control;
 485         struct vmcb_save_area *save = &svm->vmcb->save;
 486
 487         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 488                                         INTERCEPT_CR3_MASK |
 489                                         INTERCEPT_CR4_MASK;
 490
 491         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 492                                         INTERCEPT_CR3_MASK |
 493                                         INTERCEPT_CR4_MASK |
 494                                         INTERCEPT_CR8_MASK;
 495
 496         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 497                                         INTERCEPT_DR1_MASK |
 498                                         INTERCEPT_DR2_MASK |
 499                                         INTERCEPT_DR3_MASK;
 500
 501         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 502                                         INTERCEPT_DR1_MASK |
 503                                         INTERCEPT_DR2_MASK |
 504                                         INTERCEPT_DR3_MASK |
 505                                         INTERCEPT_DR5_MASK |
 506                                         INTERCEPT_DR7_MASK;
 507
 508         control->intercept_exceptions = (1 << PF_VECTOR) |
 509                                         (1 << UD_VECTOR) |
 510                                         (1 << MC_VECTOR);
 511
 512
 513         control->intercept =    (1ULL << INTERCEPT_INTR) |
 514                                 (1ULL << INTERCEPT_NMI) |
 515                                 (1ULL << INTERCEPT_SMI) |
 516                                 (1ULL << INTERCEPT_CPUID) |
 517                                 (1ULL << INTERCEPT_INVD) |
 518                                 (1ULL << INTERCEPT_HLT) |
 519                                 (1ULL << INTERCEPT_INVLPGA) |
 520                                 (1ULL << INTERCEPT_IOIO_PROT) |
 521                                 (1ULL << INTERCEPT_MSR_PROT) |
 522                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 523                                 (1ULL << INTERCEPT_SHUTDOWN) |
 524                                 (1ULL << INTERCEPT_VMRUN) |
 525                                 (1ULL << INTERCEPT_VMMCALL) |
 526                                 (1ULL << INTERCEPT_VMLOAD) |
 527                                 (1ULL << INTERCEPT_VMSAVE) |
 528                                 (1ULL << INTERCEPT_STGI) |
 529                                 (1ULL << INTERCEPT_CLGI) |
 530                                 (1ULL << INTERCEPT_SKINIT) |
 531                                 (1ULL << INTERCEPT_WBINVD) |
 532                                 (1ULL << INTERCEPT_MONITOR) |
 533                                 (1ULL << INTERCEPT_MWAIT);
 534
 535         control->iopm_base_pa = iopm_base;
 536         control->msrpm_base_pa = __pa(svm->msrpm);
 537         control->tsc_offset = 0;
 538         control->int_ctl = V_INTR_MASKING_MASK;
 539
 540         init_seg(&save->es);
 541         init_seg(&save->ss);
 542         init_seg(&save->ds);
 543         init_seg(&save->fs);
 544         init_seg(&save->gs);
 545
 546         save->cs.selector = 0xf000;
 547         /* Executable/Readable Code Segment */
 548         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 549                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 550         save->cs.limit = 0xffff;
 551         /*
 552          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 553          * be consistent with it.
 554          *
 555          * Replace when we have real mode working for vmx.
 556          */
 557         save->cs.base = 0xf0000;
 558
 559         save->gdtr.limit = 0xffff;
 560         save->idtr.limit = 0xffff;
 561
 562         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 563         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 564
 565         save->efer = MSR_EFER_SVME_MASK;
 566         save->dr6 = 0xffff0ff0;
 567         save->dr7 = 0x400;
 568         save->rflags = 2;
 569         save->rip = 0x0000fff0;
 570
 571         /*
 572          * cr0 val on cpu init should be 0x60000010, we enable cpu
 573          * cache by default. the orderly way is to enable cache in bios.
 574          */
 575         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 576         save->cr4 = X86_CR4_PAE;
 577         /* rdx = ?? */
 578
 579         if (npt_enabled) {
 580                 /* Setup VMCB for Nested Paging */
 581                 control->nested_ctl = 1;
 582                 control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH);
 583                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 584                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 585                                                 INTERCEPT_CR3_MASK);
 586                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 587                                                  INTERCEPT_CR3_MASK);
 588                 save->g_pat = 0x0007040600070406ULL;
 589                 /* enable caching because the QEMU Bios doesn't enable it */
 590                 save->cr0 = X86_CR0_ET;
 591                 save->cr3 = 0;
 592                 save->cr4 = 0;
 593         }
 594         force_new_asid(&svm->vcpu);
 595 }
 596
 597 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 598 {
 599         struct vcpu_svm *svm = to_svm(vcpu);
 600
 601         init_vmcb(svm);
 602
 603         if (vcpu->vcpu_id != 0) {
 604                 svm->vmcb->save.rip = 0;
 605                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 606                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 607         }
 608
 609         return 0;
 610 }
 611
 612 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 613 {
 614         struct vcpu_svm *svm;
 615         struct page *page;
 616         struct page *msrpm_pages;
 617         int err;
 618
 619         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 620         if (!svm) {
 621                 err = -ENOMEM;
 622                 goto out;
 623         }
 624
 625         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 626         if (err)
 627                 goto free_svm;
 628
 629         page = alloc_page(GFP_KERNEL);
 630         if (!page) {
 631                 err = -ENOMEM;
 632                 goto uninit;
 633         }
 634
 635         err = -ENOMEM;
 636         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 637         if (!msrpm_pages)
 638                 goto uninit;
 639         svm->msrpm = page_address(msrpm_pages);
 640         svm_vcpu_init_msrpm(svm->msrpm);
 641
 642         svm->vmcb = page_address(page);
 643         clear_page(svm->vmcb);
 644         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 645         svm->asid_generation = 0;
 646         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 647         init_vmcb(svm);
 648
 649         fx_init(&svm->vcpu);
 650         svm->vcpu.fpu_active = 1;
 651         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 652         if (svm->vcpu.vcpu_id == 0)
 653                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 654
 655         return &svm->vcpu;
 656
 657 uninit:
 658         kvm_vcpu_uninit(&svm->vcpu);
 659 free_svm:
 660         kmem_cache_free(kvm_vcpu_cache, svm);
 661 out:
 662         return ERR_PTR(err);
 663 }
 664
 665 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 666 {
 667         struct vcpu_svm *svm = to_svm(vcpu);
 668
 669         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 670         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 671         kvm_vcpu_uninit(vcpu);
 672         kmem_cache_free(kvm_vcpu_cache, svm);
 673 }
 674
 675 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 676 {
 677         struct vcpu_svm *svm = to_svm(vcpu);
 678         int i;
 679
 680         if (unlikely(cpu != vcpu->cpu)) {
 681                 u64 tsc_this, delta;
 682
 683                 /*
 684                  * Make sure that the guest sees a monotonically
 685                  * increasing TSC.
 686                  */
 687                 rdtscll(tsc_this);
 688                 delta = vcpu->arch.host_tsc - tsc_this;
 689                 svm->vmcb->control.tsc_offset += delta;
 690                 vcpu->cpu = cpu;
 691                 kvm_migrate_timers(vcpu);
 692         }
 693
 694         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 695                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 696 }
 697
 698 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 699 {
 700         struct vcpu_svm *svm = to_svm(vcpu);
 701         int i;
 702
 703         ++vcpu->stat.host_state_reload;
 704         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 705                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 706
 707         rdtscll(vcpu->arch.host_tsc);
 708 }
 709
 710 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 711 {
 712 }
 713
 714 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 715 {
 716         struct vcpu_svm *svm = to_svm(vcpu);
 717
 718         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 719         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 720         vcpu->arch.rip = svm->vmcb->save.rip;
 721 }
 722
 723 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 724 {
 725         struct vcpu_svm *svm = to_svm(vcpu);
 726         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 727         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 728         svm->vmcb->save.rip = vcpu->arch.rip;
 729 }
 730
 731 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 732 {
 733         return to_svm(vcpu)->vmcb->save.rflags;
 734 }
 735
 736 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 737 {
 738         to_svm(vcpu)->vmcb->save.rflags = rflags;
 739 }
 740
 741 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 742 {
 743         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 744
 745         switch (seg) {
 746         case VCPU_SREG_CS: return &save->cs;
 747         case VCPU_SREG_DS: return &save->ds;
 748         case VCPU_SREG_ES: return &save->es;
 749         case VCPU_SREG_FS: return &save->fs;
 750         case VCPU_SREG_GS: return &save->gs;
 751         case VCPU_SREG_SS: return &save->ss;
 752         case VCPU_SREG_TR: return &save->tr;
 753         case VCPU_SREG_LDTR: return &save->ldtr;
 754         }
 755         BUG();
 756         return NULL;
 757 }
 758
 759 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 760 {
 761         struct vmcb_seg *s = svm_seg(vcpu, seg);
 762
 763         return s->base;
 764 }
 765
 766 static void svm_get_segment(struct kvm_vcpu *vcpu,
 767                             struct kvm_segment *var, int seg)
 768 {
 769         struct vmcb_seg *s = svm_seg(vcpu, seg);
 770
 771         var->base = s->base;
 772         var->limit = s->limit;
 773         var->selector = s->selector;
 774         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 775         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 776         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 777         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 778         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 779         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 780         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 781         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 782         var->unusable = !var->present;
 783 }
 784
 785 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 786 {
 787         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 788
 789         return save->cpl;
 790 }
 791
 792 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 793 {
 794         struct vcpu_svm *svm = to_svm(vcpu);
 795
 796         dt->limit = svm->vmcb->save.idtr.limit;
 797         dt->base = svm->vmcb->save.idtr.base;
 798 }
 799
 800 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 801 {
 802         struct vcpu_svm *svm = to_svm(vcpu);
 803
 804         svm->vmcb->save.idtr.limit = dt->limit;
 805         svm->vmcb->save.idtr.base = dt->base ;
 806 }
 807
 808 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 809 {
 810         struct vcpu_svm *svm = to_svm(vcpu);
 811
 812         dt->limit = svm->vmcb->save.gdtr.limit;
 813         dt->base = svm->vmcb->save.gdtr.base;
 814 }
 815
 816 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 817 {
 818         struct vcpu_svm *svm = to_svm(vcpu);
 819
 820         svm->vmcb->save.gdtr.limit = dt->limit;
 821         svm->vmcb->save.gdtr.base = dt->base ;
 822 }
 823
 824 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 825 {
 826 }
 827
 828 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 829 {
 830         struct vcpu_svm *svm = to_svm(vcpu);
 831
 832 #ifdef CONFIG_X86_64
 833         if (vcpu->arch.shadow_efer & EFER_LME) {
 834                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 835                         vcpu->arch.shadow_efer |= EFER_LMA;
 836                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 837                 }
 838
 839                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 840                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 841                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 842                 }
 843         }
 844 #endif
 845         if (npt_enabled)
 846                 goto set;
 847
 848         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 849                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 850                 vcpu->fpu_active = 1;
 851         }
 852
 853         vcpu->arch.cr0 = cr0;
 854         cr0 |= X86_CR0_PG | X86_CR0_WP;
 855         if (!vcpu->fpu_active) {
 856                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 857                 cr0 |= X86_CR0_TS;
 858         }
 859 set:
 860         /*
 861          * re-enable caching here because the QEMU bios
 862          * does not do it - this results in some delay at
 863          * reboot
 864          */
 865         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 866         svm->vmcb->save.cr0 = cr0;
 867 }
 868
 869 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 870 {
 871         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 872
 873         vcpu->arch.cr4 = cr4;
 874         if (!npt_enabled)
 875                 cr4 |= X86_CR4_PAE;
 876         cr4 |= host_cr4_mce;
 877         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 878 }
 879
 880 static void svm_set_segment(struct kvm_vcpu *vcpu,
 881                             struct kvm_segment *var, int seg)
 882 {
 883         struct vcpu_svm *svm = to_svm(vcpu);
 884         struct vmcb_seg *s = svm_seg(vcpu, seg);
 885
 886         s->base = var->base;
 887         s->limit = var->limit;
 888         s->selector = var->selector;
 889         if (var->unusable)
 890                 s->attrib = 0;
 891         else {
 892                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 893                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 894                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 895                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 896                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 897                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 898                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 899                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 900         }
 901         if (seg == VCPU_SREG_CS)
 902                 svm->vmcb->save.cpl
 903                         = (svm->vmcb->save.cs.attrib
 904                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 905
 906 }
 907
 908 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 909 {
 910         return -EOPNOTSUPP;
 911 }
 912
 913 static int svm_get_irq(struct kvm_vcpu *vcpu)
 914 {
 915         struct vcpu_svm *svm = to_svm(vcpu);
 916         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 917
 918         if (is_external_interrupt(exit_int_info))
 919                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 920         return -1;
 921 }
 922
 923 static void load_host_msrs(struct kvm_vcpu *vcpu)
 924 {
 925 #ifdef CONFIG_X86_64
 926         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 927 #endif
 928 }
 929
 930 static void save_host_msrs(struct kvm_vcpu *vcpu)
 931 {
 932 #ifdef CONFIG_X86_64
 933         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 934 #endif
 935 }
 936
 937 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 938 {
 939         if (svm_data->next_asid > svm_data->max_asid) {
 940                 ++svm_data->asid_generation;
 941                 svm_data->next_asid = 1;
 942                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 943         }
 944
 945         svm->vcpu.cpu = svm_data->cpu;
 946         svm->asid_generation = svm_data->asid_generation;
 947         svm->vmcb->control.asid = svm_data->next_asid++;
 948 }
 949
 950 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 951 {
 952         unsigned long val = to_svm(vcpu)->db_regs[dr];
 953         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 954         return val;
 955 }
 956
 957 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 958                        int *exception)
 959 {
 960         struct vcpu_svm *svm = to_svm(vcpu);
 961
 962         *exception = 0;
 963
 964         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 965                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 966                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 967                 *exception = DB_VECTOR;
 968                 return;
 969         }
 970
 971         switch (dr) {
 972         case 0 ... 3:
 973                 svm->db_regs[dr] = value;
 974                 return;
 975         case 4 ... 5:
 976                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 977                         *exception = UD_VECTOR;
 978                         return;
 979                 }
 980         case 7: {
 981                 if (value & ~((1ULL << 32) - 1)) {
 982                         *exception = GP_VECTOR;
 983                         return;
 984                 }
 985                 svm->vmcb->save.dr7 = value;
 986                 return;
 987         }
 988         default:
 989                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 990                        __func__, dr);
 991                 *exception = UD_VECTOR;
 992                 return;
 993         }
 994 }
 995
 996 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 997 {
 998         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 999         struct kvm *kvm = svm->vcpu.kvm;
1000         u64 fault_address;
1001         u32 error_code;
1002
1003         if (!irqchip_in_kernel(kvm) &&
1004                 is_external_interrupt(exit_int_info))
1005                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1006
1007         fault_address  = svm->vmcb->control.exit_info_2;
1008         error_code = svm->vmcb->control.exit_info_1;
1009
1010         if (!npt_enabled)
1011                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1012                             (u32)fault_address, (u32)(fault_address >> 32),
1013                             handler);
1014         else
1015                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1016                             (u32)fault_address, (u32)(fault_address >> 32),
1017                             handler);
1018
1019         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1020 }
1021
1022 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1023 {
1024         int er;
1025
1026         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1027         if (er != EMULATE_DONE)
1028                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1029         return 1;
1030 }
1031
1032 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1033 {
1034         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1035         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1036                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1037         svm->vcpu.fpu_active = 1;
1038
1039         return 1;
1040 }
1041
1042 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1043 {
1044         /*
1045          * On an #MC intercept the MCE handler is not called automatically in
1046          * the host. So do it by hand here.
1047          */
1048         asm volatile (
1049                 "int $0x12\n");
1050         /* not sure if we ever come back to this point */
1051
1052         return 1;
1053 }
1054
1055 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1056 {
1057         /*
1058          * VMCB is undefined after a SHUTDOWN intercept
1059          * so reinitialize it.
1060          */
1061         clear_page(svm->vmcb);
1062         init_vmcb(svm);
1063
1064         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1065         return 0;
1066 }
1067
1068 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1069 {
1070         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1071         int size, down, in, string, rep;
1072         unsigned port;
1073
1074         ++svm->vcpu.stat.io_exits;
1075
1076         svm->next_rip = svm->vmcb->control.exit_info_2;
1077
1078         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1079
1080         if (string) {
1081                 if (emulate_instruction(&svm->vcpu,
1082                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1083                         return 0;
1084                 return 1;
1085         }
1086
1087         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1088         port = io_info >> 16;
1089         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1090         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1091         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1092
1093         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1094 }
1095
1096 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1097 {
1098         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1099         return 1;
1100 }
1101
1102 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1103 {
1104         ++svm->vcpu.stat.irq_exits;
1105         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1106         return 1;
1107 }
1108
1109 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1110 {
1111         return 1;
1112 }
1113
1114 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1115 {
1116         svm->next_rip = svm->vmcb->save.rip + 1;
1117         skip_emulated_instruction(&svm->vcpu);
1118         return kvm_emulate_halt(&svm->vcpu);
1119 }
1120
1121 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1122 {
1123         svm->next_rip = svm->vmcb->save.rip + 3;
1124         skip_emulated_instruction(&svm->vcpu);
1125         kvm_emulate_hypercall(&svm->vcpu);
1126         return 1;
1127 }
1128
1129 static int invalid_op_interception(struct vcpu_svm *svm,
1130                                    struct kvm_run *kvm_run)
1131 {
1132         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1133         return 1;
1134 }
1135
1136 static int task_switch_interception(struct vcpu_svm *svm,
1137                                     struct kvm_run *kvm_run)
1138 {
1139         u16 tss_selector;
1140
1141         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1142         if (svm->vmcb->control.exit_info_2 &
1143             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1144                 return kvm_task_switch(&svm->vcpu, tss_selector,
1145                                        TASK_SWITCH_IRET);
1146         if (svm->vmcb->control.exit_info_2 &
1147             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1148                 return kvm_task_switch(&svm->vcpu, tss_selector,
1149                                        TASK_SWITCH_JMP);
1150         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1151 }
1152
1153 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1154 {
1155         svm->next_rip = svm->vmcb->save.rip + 2;
1156         kvm_emulate_cpuid(&svm->vcpu);
1157         return 1;
1158 }
1159
1160 static int emulate_on_interception(struct vcpu_svm *svm,
1161                                    struct kvm_run *kvm_run)
1162 {
1163         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1164                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1165         return 1;
1166 }
1167
1168 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1169 {
1170         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1171         if (irqchip_in_kernel(svm->vcpu.kvm))
1172                 return 1;
1173         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1174         return 0;
1175 }
1176
1177 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1178 {
1179         struct vcpu_svm *svm = to_svm(vcpu);
1180
1181         switch (ecx) {
1182         case MSR_IA32_TIME_STAMP_COUNTER: {
1183                 u64 tsc;
1184
1185                 rdtscll(tsc);
1186                 *data = svm->vmcb->control.tsc_offset + tsc;
1187                 break;
1188         }
1189         case MSR_K6_STAR:
1190                 *data = svm->vmcb->save.star;
1191                 break;
1192 #ifdef CONFIG_X86_64
1193         case MSR_LSTAR:
1194                 *data = svm->vmcb->save.lstar;
1195                 break;
1196         case MSR_CSTAR:
1197                 *data = svm->vmcb->save.cstar;
1198                 break;
1199         case MSR_KERNEL_GS_BASE:
1200                 *data = svm->vmcb->save.kernel_gs_base;
1201                 break;
1202         case MSR_SYSCALL_MASK:
1203                 *data = svm->vmcb->save.sfmask;
1204                 break;
1205 #endif
1206         case MSR_IA32_SYSENTER_CS:
1207                 *data = svm->vmcb->save.sysenter_cs;
1208                 break;
1209         case MSR_IA32_SYSENTER_EIP:
1210                 *data = svm->vmcb->save.sysenter_eip;
1211                 break;
1212         case MSR_IA32_SYSENTER_ESP:
1213                 *data = svm->vmcb->save.sysenter_esp;
1214                 break;
1215         /* Nobody will change the following 5 values in the VMCB so
1216            we can safely return them on rdmsr. They will always be 0
1217            until LBRV is implemented. */
1218         case MSR_IA32_DEBUGCTLMSR:
1219                 *data = svm->vmcb->save.dbgctl;
1220                 break;
1221         case MSR_IA32_LASTBRANCHFROMIP:
1222                 *data = svm->vmcb->save.br_from;
1223                 break;
1224         case MSR_IA32_LASTBRANCHTOIP:
1225                 *data = svm->vmcb->save.br_to;
1226                 break;
1227         case MSR_IA32_LASTINTFROMIP:
1228                 *data = svm->vmcb->save.last_excp_from;
1229                 break;
1230         case MSR_IA32_LASTINTTOIP:
1231                 *data = svm->vmcb->save.last_excp_to;
1232                 break;
1233         default:
1234                 return kvm_get_msr_common(vcpu, ecx, data);
1235         }
1236         return 0;
1237 }
1238
1239 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1240 {
1241         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1242         u64 data;
1243
1244         if (svm_get_msr(&svm->vcpu, ecx, &data))
1245                 kvm_inject_gp(&svm->vcpu, 0);
1246         else {
1247                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1248                             (u32)(data >> 32), handler);
1249
1250                 svm->vmcb->save.rax = data & 0xffffffff;
1251                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1252                 svm->next_rip = svm->vmcb->save.rip + 2;
1253                 skip_emulated_instruction(&svm->vcpu);
1254         }
1255         return 1;
1256 }
1257
1258 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1259 {
1260         struct vcpu_svm *svm = to_svm(vcpu);
1261
1262         switch (ecx) {
1263         case MSR_IA32_TIME_STAMP_COUNTER: {
1264                 u64 tsc;
1265
1266                 rdtscll(tsc);
1267                 svm->vmcb->control.tsc_offset = data - tsc;
1268                 break;
1269         }
1270         case MSR_K6_STAR:
1271                 svm->vmcb->save.star = data;
1272                 break;
1273 #ifdef CONFIG_X86_64
1274         case MSR_LSTAR:
1275                 svm->vmcb->save.lstar = data;
1276                 break;
1277         case MSR_CSTAR:
1278                 svm->vmcb->save.cstar = data;
1279                 break;
1280         case MSR_KERNEL_GS_BASE:
1281                 svm->vmcb->save.kernel_gs_base = data;
1282                 break;
1283         case MSR_SYSCALL_MASK:
1284                 svm->vmcb->save.sfmask = data;
1285                 break;
1286 #endif
1287         case MSR_IA32_SYSENTER_CS:
1288                 svm->vmcb->save.sysenter_cs = data;
1289                 break;
1290         case MSR_IA32_SYSENTER_EIP:
1291                 svm->vmcb->save.sysenter_eip = data;
1292                 break;
1293         case MSR_IA32_SYSENTER_ESP:
1294                 svm->vmcb->save.sysenter_esp = data;
1295                 break;
1296         case MSR_IA32_DEBUGCTLMSR:
1297                 if (!svm_has(SVM_FEATURE_LBRV)) {
1298                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1299                                         __func__, data);
1300                         break;
1301                 }
1302                 if (data & DEBUGCTL_RESERVED_BITS)
1303                         return 1;
1304
1305                 svm->vmcb->save.dbgctl = data;
1306                 if (data & (1ULL<<0))
1307                         svm_enable_lbrv(svm);
1308                 else
1309                         svm_disable_lbrv(svm);
1310                 break;
1311         case MSR_K7_EVNTSEL0:
1312         case MSR_K7_EVNTSEL1:
1313         case MSR_K7_EVNTSEL2:
1314         case MSR_K7_EVNTSEL3:
1315                 /*
1316                  * only support writing 0 to the performance counters for now
1317                  * to make Windows happy. Should be replaced by a real
1318                  * performance counter emulation later.
1319                  */
1320                 if (data != 0)
1321                         goto unhandled;
1322                 break;
1323         default:
1324         unhandled:
1325                 return kvm_set_msr_common(vcpu, ecx, data);
1326         }
1327         return 0;
1328 }
1329
1330 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1331 {
1332         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1333         u64 data = (svm->vmcb->save.rax & -1u)
1334                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1335
1336         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1337                     handler);
1338
1339         svm->next_rip = svm->vmcb->save.rip + 2;
1340         if (svm_set_msr(&svm->vcpu, ecx, data))
1341                 kvm_inject_gp(&svm->vcpu, 0);
1342         else
1343                 skip_emulated_instruction(&svm->vcpu);
1344         return 1;
1345 }
1346
1347 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1348 {
1349         if (svm->vmcb->control.exit_info_1)
1350                 return wrmsr_interception(svm, kvm_run);
1351         else
1352                 return rdmsr_interception(svm, kvm_run);
1353 }
1354
1355 static int interrupt_window_interception(struct vcpu_svm *svm,
1356                                    struct kvm_run *kvm_run)
1357 {
1358         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1359
1360         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1361         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1362         /*
1363          * If the user space waits to inject interrupts, exit as soon as
1364          * possible
1365          */
1366         if (kvm_run->request_interrupt_window &&
1367             !svm->vcpu.arch.irq_summary) {
1368                 ++svm->vcpu.stat.irq_window_exits;
1369                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1370                 return 0;
1371         }
1372
1373         return 1;
1374 }
1375
1376 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1377                                       struct kvm_run *kvm_run) = {
1378         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1379         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1380         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1381         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1382         /* for now: */
1383         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1384         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1385         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1386         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1387         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1388         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1389         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1390         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1391         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1392         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1393         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1394         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1395         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1396         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1397         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1398         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1399         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1400         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1401         [SVM_EXIT_INTR]                         = intr_interception,
1402         [SVM_EXIT_NMI]                          = nmi_interception,
1403         [SVM_EXIT_SMI]                          = nop_on_interception,
1404         [SVM_EXIT_INIT]                         = nop_on_interception,
1405         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1406         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1407         [SVM_EXIT_CPUID]                        = cpuid_interception,
1408         [SVM_EXIT_INVD]                         = emulate_on_interception,
1409         [SVM_EXIT_HLT]                          = halt_interception,
1410         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1411         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1412         [SVM_EXIT_IOIO]                         = io_interception,
1413         [SVM_EXIT_MSR]                          = msr_interception,
1414         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1415         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1416         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1417         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1418         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1419         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1420         [SVM_EXIT_STGI]                         = invalid_op_interception,
1421         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1422         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1423         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1424         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1425         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1426         [SVM_EXIT_NPF]                          = pf_interception,
1427 };
1428
1429 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1430 {
1431         struct vcpu_svm *svm = to_svm(vcpu);
1432         u32 exit_code = svm->vmcb->control.exit_code;
1433
1434         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1435                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1436
1437         if (npt_enabled) {
1438                 int mmu_reload = 0;
1439                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1440                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1441                         mmu_reload = 1;
1442                 }
1443                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1444                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1445                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1446                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1447                                 kvm_inject_gp(vcpu, 0);
1448                                 return 1;
1449                         }
1450                 }
1451                 if (mmu_reload) {
1452                         kvm_mmu_reset_context(vcpu);
1453                         kvm_mmu_load(vcpu);
1454                 }
1455         }
1456
1457         kvm_reput_irq(svm);
1458
1459         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1460                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1461                 kvm_run->fail_entry.hardware_entry_failure_reason
1462                         = svm->vmcb->control.exit_code;
1463                 return 0;
1464         }
1465
1466         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1467             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1468             exit_code != SVM_EXIT_NPF)
1469                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1470                        "exit_code 0x%x\n",
1471                        __func__, svm->vmcb->control.exit_int_info,
1472                        exit_code);
1473
1474         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1475             || !svm_exit_handlers[exit_code]) {
1476                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1477                 kvm_run->hw.hardware_exit_reason = exit_code;
1478                 return 0;
1479         }
1480
1481         return svm_exit_handlers[exit_code](svm, kvm_run);
1482 }
1483
1484 static void reload_tss(struct kvm_vcpu *vcpu)
1485 {
1486         int cpu = raw_smp_processor_id();
1487
1488         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1489         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1490         load_TR_desc();
1491 }
1492
1493 static void pre_svm_run(struct vcpu_svm *svm)
1494 {
1495         int cpu = raw_smp_processor_id();
1496
1497         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1498
1499         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1500         if (svm->vcpu.cpu != cpu ||
1501             svm->asid_generation != svm_data->asid_generation)
1502                 new_asid(svm, svm_data);
1503 }
1504
1505
1506 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1507 {
1508         struct vmcb_control_area *control;
1509
1510         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1511
1512         control = &svm->vmcb->control;
1513         control->int_vector = irq;
1514         control->int_ctl &= ~V_INTR_PRIO_MASK;
1515         control->int_ctl |= V_IRQ_MASK |
1516                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1517 }
1518
1519 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1520 {
1521         struct vcpu_svm *svm = to_svm(vcpu);
1522
1523         svm_inject_irq(svm, irq);
1524 }
1525
1526 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1527 {
1528         struct vcpu_svm *svm = to_svm(vcpu);
1529         struct vmcb *vmcb = svm->vmcb;
1530         int max_irr, tpr;
1531
1532         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1533                 return;
1534
1535         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1536
1537         max_irr = kvm_lapic_find_highest_irr(vcpu);
1538         if (max_irr == -1)
1539                 return;
1540
1541         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1542
1543         if (tpr >= (max_irr & 0xf0))
1544                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1545 }
1546
1547 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1548 {
1549         struct vcpu_svm *svm = to_svm(vcpu);
1550         struct vmcb *vmcb = svm->vmcb;
1551         int intr_vector = -1;
1552
1553         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1554             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1555                 intr_vector = vmcb->control.exit_int_info &
1556                               SVM_EVTINJ_VEC_MASK;
1557                 vmcb->control.exit_int_info = 0;
1558                 svm_inject_irq(svm, intr_vector);
1559                 goto out;
1560         }
1561
1562         if (vmcb->control.int_ctl & V_IRQ_MASK)
1563                 goto out;
1564
1565         if (!kvm_cpu_has_interrupt(vcpu))
1566                 goto out;
1567
1568         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1569             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1570             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1571                 /* unable to deliver irq, set pending irq */
1572                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1573                 svm_inject_irq(svm, 0x0);
1574                 goto out;
1575         }
1576         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1577         intr_vector = kvm_cpu_get_interrupt(vcpu);
1578         svm_inject_irq(svm, intr_vector);
1579         kvm_timer_intr_post(vcpu, intr_vector);
1580 out:
1581         update_cr8_intercept(vcpu);
1582 }
1583
1584 static void kvm_reput_irq(struct vcpu_svm *svm)
1585 {
1586         struct vmcb_control_area *control = &svm->vmcb->control;
1587
1588         if ((control->int_ctl & V_IRQ_MASK)
1589             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1590                 control->int_ctl &= ~V_IRQ_MASK;
1591                 push_irq(&svm->vcpu, control->int_vector);
1592         }
1593
1594         svm->vcpu.arch.interrupt_window_open =
1595                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1596 }
1597
1598 static void svm_do_inject_vector(struct vcpu_svm *svm)
1599 {
1600         struct kvm_vcpu *vcpu = &svm->vcpu;
1601         int word_index = __ffs(vcpu->arch.irq_summary);
1602         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1603         int irq = word_index * BITS_PER_LONG + bit_index;
1604
1605         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1606         if (!vcpu->arch.irq_pending[word_index])
1607                 clear_bit(word_index, &vcpu->arch.irq_summary);
1608         svm_inject_irq(svm, irq);
1609 }
1610
1611 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1612                                        struct kvm_run *kvm_run)
1613 {
1614         struct vcpu_svm *svm = to_svm(vcpu);
1615         struct vmcb_control_area *control = &svm->vmcb->control;
1616
1617         svm->vcpu.arch.interrupt_window_open =
1618                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1619                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1620
1621         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1622                 /*
1623                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1624                  */
1625                 svm_do_inject_vector(svm);
1626
1627         /*
1628          * Interrupts blocked.  Wait for unblock.
1629          */
1630         if (!svm->vcpu.arch.interrupt_window_open &&
1631             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1632                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1633          else
1634                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1635 }
1636
1637 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1638 {
1639         return 0;
1640 }
1641
1642 static void save_db_regs(unsigned long *db_regs)
1643 {
1644         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1645         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1646         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1647         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1648 }
1649
1650 static void load_db_regs(unsigned long *db_regs)
1651 {
1652         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1653         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1654         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1655         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1656 }
1657
1658 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1659 {
1660         force_new_asid(vcpu);
1661 }
1662
1663 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1664 {
1665 }
1666
1667 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1668 {
1669         struct vcpu_svm *svm = to_svm(vcpu);
1670
1671         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1672                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1673                 kvm_lapic_set_tpr(vcpu, cr8);
1674         }
1675 }
1676
1677 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1678 {
1679         struct vcpu_svm *svm = to_svm(vcpu);
1680         u64 cr8;
1681
1682         if (!irqchip_in_kernel(vcpu->kvm))
1683                 return;
1684
1685         cr8 = kvm_get_cr8(vcpu);
1686         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1687         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1688 }
1689
1690 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1691 {
1692         struct vcpu_svm *svm = to_svm(vcpu);
1693         u16 fs_selector;
1694         u16 gs_selector;
1695         u16 ldt_selector;
1696
1697         pre_svm_run(svm);
1698
1699         sync_lapic_to_cr8(vcpu);
1700
1701         save_host_msrs(vcpu);
1702         fs_selector = read_fs();
1703         gs_selector = read_gs();
1704         ldt_selector = read_ldt();
1705         svm->host_cr2 = kvm_read_cr2();
1706         svm->host_dr6 = read_dr6();
1707         svm->host_dr7 = read_dr7();
1708         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1709         /* required for live migration with NPT */
1710         if (npt_enabled)
1711                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1712
1713         if (svm->vmcb->save.dr7 & 0xff) {
1714                 write_dr7(0);
1715                 save_db_regs(svm->host_db_regs);
1716                 load_db_regs(svm->db_regs);
1717         }
1718
1719         clgi();
1720
1721         local_irq_enable();
1722
1723         asm volatile (
1724 #ifdef CONFIG_X86_64
1725                 "push %%rbp; \n\t"
1726 #else
1727                 "push %%ebp; \n\t"
1728 #endif
1729
1730 #ifdef CONFIG_X86_64
1731                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1732                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1733                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1734                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1735                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1736                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1737                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1738                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1739                 "mov %c[r10](%[svm]), %%r10 \n\t"
1740                 "mov %c[r11](%[svm]), %%r11 \n\t"
1741                 "mov %c[r12](%[svm]), %%r12 \n\t"
1742                 "mov %c[r13](%[svm]), %%r13 \n\t"
1743                 "mov %c[r14](%[svm]), %%r14 \n\t"
1744                 "mov %c[r15](%[svm]), %%r15 \n\t"
1745 #else
1746                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1747                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1748                 "mov %c[rdx](%[svm]), %%edx \n\t"
1749                 "mov %c[rsi](%[svm]), %%esi \n\t"
1750                 "mov %c[rdi](%[svm]), %%edi \n\t"
1751                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1752 #endif
1753
1754 #ifdef CONFIG_X86_64
1755                 /* Enter guest mode */
1756                 "push %%rax \n\t"
1757                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1758                 SVM_VMLOAD "\n\t"
1759                 SVM_VMRUN "\n\t"
1760                 SVM_VMSAVE "\n\t"
1761                 "pop %%rax \n\t"
1762 #else
1763                 /* Enter guest mode */
1764                 "push %%eax \n\t"
1765                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1766                 SVM_VMLOAD "\n\t"
1767                 SVM_VMRUN "\n\t"
1768                 SVM_VMSAVE "\n\t"
1769                 "pop %%eax \n\t"
1770 #endif
1771
1772                 /* Save guest registers, load host registers */
1773 #ifdef CONFIG_X86_64
1774                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1775                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1776                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1777                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1778                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1779                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1780                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1781                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1782                 "mov %%r10, %c[r10](%[svm]) \n\t"
1783                 "mov %%r11, %c[r11](%[svm]) \n\t"
1784                 "mov %%r12, %c[r12](%[svm]) \n\t"
1785                 "mov %%r13, %c[r13](%[svm]) \n\t"
1786                 "mov %%r14, %c[r14](%[svm]) \n\t"
1787                 "mov %%r15, %c[r15](%[svm]) \n\t"
1788
1789                 "pop  %%rbp; \n\t"
1790 #else
1791                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1792                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1793                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1794                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1795                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1796                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1797
1798                 "pop  %%ebp; \n\t"
1799 #endif
1800                 :
1801                 : [svm]"a"(svm),
1802                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1803                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1804                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1805                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1806                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1807                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1808                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1809 #ifdef CONFIG_X86_64
1810                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1811                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1812                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1813                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1814                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1815                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1816                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1817                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1818 #endif
1819                 : "cc", "memory"
1820 #ifdef CONFIG_X86_64
1821                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1822                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1823 #else
1824                 , "ebx", "ecx", "edx" , "esi", "edi"
1825 #endif
1826                 );
1827
1828         if ((svm->vmcb->save.dr7 & 0xff))
1829                 load_db_regs(svm->host_db_regs);
1830
1831         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1832
1833         write_dr6(svm->host_dr6);
1834         write_dr7(svm->host_dr7);
1835         kvm_write_cr2(svm->host_cr2);
1836
1837         load_fs(fs_selector);
1838         load_gs(gs_selector);
1839         load_ldt(ldt_selector);
1840         load_host_msrs(vcpu);
1841
1842         reload_tss(vcpu);
1843
1844         local_irq_disable();
1845
1846         stgi();
1847
1848         sync_cr8_to_lapic(vcpu);
1849
1850         svm->next_rip = 0;
1851 }
1852
1853 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1854 {
1855         struct vcpu_svm *svm = to_svm(vcpu);
1856
1857         if (npt_enabled) {
1858                 svm->vmcb->control.nested_cr3 = root;
1859                 force_new_asid(vcpu);
1860                 return;
1861         }
1862
1863         svm->vmcb->save.cr3 = root;
1864         force_new_asid(vcpu);
1865
1866         if (vcpu->fpu_active) {
1867                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1868                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1869                 vcpu->fpu_active = 0;
1870         }
1871 }
1872
1873 static int is_disabled(void)
1874 {
1875         u64 vm_cr;
1876
1877         rdmsrl(MSR_VM_CR, vm_cr);
1878         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1879                 return 1;
1880
1881         return 0;
1882 }
1883
1884 static void
1885 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1886 {
1887         /*
1888          * Patch in the VMMCALL instruction:
1889          */
1890         hypercall[0] = 0x0f;
1891         hypercall[1] = 0x01;
1892         hypercall[2] = 0xd9;
1893 }
1894
1895 static void svm_check_processor_compat(void *rtn)
1896 {
1897         *(int *)rtn = 0;
1898 }
1899
1900 static bool svm_cpu_has_accelerated_tpr(void)
1901 {
1902         return false;
1903 }
1904
1905 static int get_npt_level(void)
1906 {
1907 #ifdef CONFIG_X86_64
1908         return PT64_ROOT_LEVEL;
1909 #else
1910         return PT32E_ROOT_LEVEL;
1911 #endif
1912 }
1913
1914 static struct kvm_x86_ops svm_x86_ops = {
1915         .cpu_has_kvm_support = has_svm,
1916         .disabled_by_bios = is_disabled,
1917         .hardware_setup = svm_hardware_setup,
1918         .hardware_unsetup = svm_hardware_unsetup,
1919         .check_processor_compatibility = svm_check_processor_compat,
1920         .hardware_enable = svm_hardware_enable,
1921         .hardware_disable = svm_hardware_disable,
1922         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1923
1924         .vcpu_create = svm_create_vcpu,
1925         .vcpu_free = svm_free_vcpu,
1926         .vcpu_reset = svm_vcpu_reset,
1927
1928         .prepare_guest_switch = svm_prepare_guest_switch,
1929         .vcpu_load = svm_vcpu_load,
1930         .vcpu_put = svm_vcpu_put,
1931         .vcpu_decache = svm_vcpu_decache,
1932
1933         .set_guest_debug = svm_guest_debug,
1934         .get_msr = svm_get_msr,
1935         .set_msr = svm_set_msr,
1936         .get_segment_base = svm_get_segment_base,
1937         .get_segment = svm_get_segment,
1938         .set_segment = svm_set_segment,
1939         .get_cpl = svm_get_cpl,
1940         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1941         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1942         .set_cr0 = svm_set_cr0,
1943         .set_cr3 = svm_set_cr3,
1944         .set_cr4 = svm_set_cr4,
1945         .set_efer = svm_set_efer,
1946         .get_idt = svm_get_idt,
1947         .set_idt = svm_set_idt,
1948         .get_gdt = svm_get_gdt,
1949         .set_gdt = svm_set_gdt,
1950         .get_dr = svm_get_dr,
1951         .set_dr = svm_set_dr,
1952         .cache_regs = svm_cache_regs,
1953         .decache_regs = svm_decache_regs,
1954         .get_rflags = svm_get_rflags,
1955         .set_rflags = svm_set_rflags,
1956
1957         .tlb_flush = svm_flush_tlb,
1958
1959         .run = svm_vcpu_run,
1960         .handle_exit = handle_exit,
1961         .skip_emulated_instruction = skip_emulated_instruction,
1962         .patch_hypercall = svm_patch_hypercall,
1963         .get_irq = svm_get_irq,
1964         .set_irq = svm_set_irq,
1965         .queue_exception = svm_queue_exception,
1966         .exception_injected = svm_exception_injected,
1967         .inject_pending_irq = svm_intr_assist,
1968         .inject_pending_vectors = do_interrupt_requests,
1969
1970         .set_tss_addr = svm_set_tss_addr,
1971         .get_tdp_level = get_npt_level,
1972 };
1973
1974 static int __init svm_init(void)
1975 {
1976         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1977                               THIS_MODULE);
1978 }
1979
1980 static void __exit svm_exit(void)
1981 {
1982         kvm_exit();
1983 }
1984
1985 module_init(svm_init)
1986 module_exit(svm_exit)