2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define CMPXCHG cmpxchg
54 #error Invalid PTTYPE value
57 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
58 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
61 * The guest_walker structure emulates the behavior of the hardware page
66 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
67 pt_element_t ptes[PT_MAX_FULL_LEVELS];
68 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
69 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
73 struct x86_exception fault;
76 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
78 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
81 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
82 gfn_t table_gfn, unsigned index,
83 pt_element_t orig_pte, pt_element_t new_pte)
89 page = gfn_to_page(kvm, table_gfn);
91 table = kmap_atomic(page, KM_USER0);
92 ret = CMPXCHG(&table[index], orig_pte, new_pte);
93 kunmap_atomic(table, KM_USER0);
95 kvm_release_page_dirty(page);
97 return (ret != orig_pte);
100 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
104 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
106 if (vcpu->arch.mmu.nx)
107 access &= ~(gpte >> PT64_NX_SHIFT);
113 * Fetch a guest pte for a guest virtual address
115 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
116 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
117 gva_t addr, u32 access)
121 unsigned index, pt_access, uninitialized_var(pte_access);
123 bool eperm, present, rsvd_fault;
124 int offset, write_fault, user_fault, fetch_fault;
126 write_fault = access & PFERR_WRITE_MASK;
127 user_fault = access & PFERR_USER_MASK;
128 fetch_fault = access & PFERR_FETCH_MASK;
130 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
134 eperm = rsvd_fault = false;
135 walker->level = mmu->root_level;
136 pte = mmu->get_cr3(vcpu);
139 if (walker->level == PT32E_ROOT_LEVEL) {
140 pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3);
141 trace_kvm_mmu_paging_element(pte, walker->level);
142 if (!is_present_gpte(pte)) {
149 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
150 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
155 index = PT_INDEX(addr, walker->level);
157 table_gfn = gpte_to_gfn(pte);
158 offset = index * sizeof(pt_element_t);
159 pte_gpa = gfn_to_gpa(table_gfn) + offset;
160 walker->table_gfn[walker->level - 1] = table_gfn;
161 walker->pte_gpa[walker->level - 1] = pte_gpa;
163 if (kvm_read_guest_page_mmu(vcpu, mmu, table_gfn, &pte,
165 PFERR_USER_MASK|PFERR_WRITE_MASK)) {
170 trace_kvm_mmu_paging_element(pte, walker->level);
172 if (!is_present_gpte(pte)) {
177 if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) {
182 if (write_fault && !is_writable_pte(pte))
183 if (user_fault || is_write_protection(vcpu))
186 if (user_fault && !(pte & PT_USER_MASK))
190 if (fetch_fault && (pte & PT64_NX_MASK))
194 if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) {
195 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
197 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
198 index, pte, pte|PT_ACCESSED_MASK))
200 mark_page_dirty(vcpu->kvm, table_gfn);
201 pte |= PT_ACCESSED_MASK;
204 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
206 walker->ptes[walker->level - 1] = pte;
208 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
209 ((walker->level == PT_DIRECTORY_LEVEL) &&
211 (PTTYPE == 64 || is_pse(vcpu))) ||
212 ((walker->level == PT_PDPE_LEVEL) &&
214 mmu->root_level == PT64_ROOT_LEVEL)) {
215 int lvl = walker->level;
220 gfn = gpte_to_gfn_lvl(pte, lvl);
221 gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
224 walker->level == PT_DIRECTORY_LEVEL &&
226 gfn += pse36_gfn_delta(pte);
228 ac = write_fault | fetch_fault | user_fault;
230 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
232 if (real_gpa == UNMAPPED_GVA)
235 walker->gfn = real_gpa >> PAGE_SHIFT;
240 pt_access = pte_access;
244 if (!present || eperm || rsvd_fault)
247 if (write_fault && !is_dirty_gpte(pte)) {
250 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
251 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
255 mark_page_dirty(vcpu->kvm, table_gfn);
256 pte |= PT_DIRTY_MASK;
257 walker->ptes[walker->level - 1] = pte;
260 walker->pt_access = pt_access;
261 walker->pte_access = pte_access;
262 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
263 __func__, (u64)pte, pte_access, pt_access);
267 walker->fault.vector = PF_VECTOR;
268 walker->fault.error_code_valid = true;
269 walker->fault.error_code = 0;
271 walker->fault.error_code |= PFERR_PRESENT_MASK;
273 walker->fault.error_code |= write_fault | user_fault;
275 if (fetch_fault && mmu->nx)
276 walker->fault.error_code |= PFERR_FETCH_MASK;
278 walker->fault.error_code |= PFERR_RSVD_MASK;
280 walker->fault.address = addr;
281 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
283 trace_kvm_mmu_walker_error(walker->fault.error_code);
287 static int FNAME(walk_addr)(struct guest_walker *walker,
288 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
290 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
294 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
295 struct kvm_vcpu *vcpu, gva_t addr,
298 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
302 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
303 struct kvm_mmu_page *sp, u64 *spte,
306 u64 nonpresent = shadow_trap_nonpresent_pte;
308 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
311 if (!is_present_gpte(gpte)) {
313 nonpresent = shadow_notrap_nonpresent_pte;
317 if (!(gpte & PT_ACCESSED_MASK))
323 drop_spte(vcpu->kvm, spte, nonpresent);
327 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
328 u64 *spte, const void *pte)
334 gpte = *(const pt_element_t *)pte;
335 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
338 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
339 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
340 pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte));
341 if (is_error_pfn(pfn)) {
342 kvm_release_pfn_clean(pfn);
347 * we call mmu_set_spte() with host_writable = true because that
348 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
350 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
351 is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
352 gpte_to_gfn(gpte), pfn, true, true);
355 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
356 struct guest_walker *gw, int level)
358 pt_element_t curr_pte;
359 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
363 if (level == PT_PAGE_TABLE_LEVEL) {
364 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
365 base_gpa = pte_gpa & ~mask;
366 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
368 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
369 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
370 curr_pte = gw->prefetch_ptes[index];
372 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
373 &curr_pte, sizeof(curr_pte));
375 return r || curr_pte != gw->ptes[level - 1];
378 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
381 struct kvm_mmu_page *sp;
382 pt_element_t *gptep = gw->prefetch_ptes;
386 sp = page_header(__pa(sptep));
388 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
392 return __direct_pte_prefetch(vcpu, sp, sptep);
394 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
397 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
407 if (*spte != shadow_trap_nonpresent_pte)
412 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
415 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
416 gfn = gpte_to_gfn(gpte);
417 dirty = is_dirty_gpte(gpte);
418 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
419 (pte_access & ACC_WRITE_MASK) && dirty);
420 if (is_error_pfn(pfn)) {
421 kvm_release_pfn_clean(pfn);
425 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
426 dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn,
432 * Fetch a shadow pte for a specific level in the paging hierarchy.
434 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
435 struct guest_walker *gw,
436 int user_fault, int write_fault, int hlevel,
437 int *ptwrite, pfn_t pfn, bool map_writable,
440 unsigned access = gw->pt_access;
441 struct kvm_mmu_page *sp = NULL;
442 bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
444 unsigned direct_access;
445 struct kvm_shadow_walk_iterator it;
447 if (!is_present_gpte(gw->ptes[gw->level - 1]))
450 direct_access = gw->pt_access & gw->pte_access;
452 direct_access &= ~ACC_WRITE_MASK;
454 top_level = vcpu->arch.mmu.root_level;
455 if (top_level == PT32E_ROOT_LEVEL)
456 top_level = PT32_ROOT_LEVEL;
458 * Verify that the top-level gpte is still there. Since the page
459 * is a root page, it is either write protected (and cannot be
460 * changed from now on) or it is invalid (in which case, we don't
461 * really care if it changes underneath us after this point).
463 if (FNAME(gpte_changed)(vcpu, gw, top_level))
464 goto out_gpte_changed;
466 for (shadow_walk_init(&it, vcpu, addr);
467 shadow_walk_okay(&it) && it.level > gw->level;
468 shadow_walk_next(&it)) {
471 drop_large_spte(vcpu, it.sptep);
474 if (!is_shadow_present_pte(*it.sptep)) {
475 table_gfn = gw->table_gfn[it.level - 2];
476 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
477 false, access, it.sptep);
481 * Verify that the gpte in the page we've just write
482 * protected is still there.
484 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
485 goto out_gpte_changed;
488 link_shadow_page(it.sptep, sp);
492 shadow_walk_okay(&it) && it.level > hlevel;
493 shadow_walk_next(&it)) {
496 validate_direct_spte(vcpu, it.sptep, direct_access);
498 drop_large_spte(vcpu, it.sptep);
500 if (is_shadow_present_pte(*it.sptep))
503 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
505 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
506 true, direct_access, it.sptep);
507 link_shadow_page(it.sptep, sp);
510 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access,
511 user_fault, write_fault, dirty, ptwrite, it.level,
512 gw->gfn, pfn, prefault, map_writable);
513 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
519 kvm_mmu_put_page(sp, it.sptep);
520 kvm_release_pfn_clean(pfn);
525 * Page fault handler. There are several causes for a page fault:
526 * - there is no shadow pte for the guest pte
527 * - write access through a shadow pte marked read only so that we can set
529 * - write access to a shadow pte marked read only so we can update the page
530 * dirty bitmap, when userspace requests it
531 * - mmio access; in this case we will never install a present shadow pte
532 * - normal guest page fault due to the guest pte marked not present, not
533 * writable, or not executable
535 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
536 * a negative value on error.
538 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
541 int write_fault = error_code & PFERR_WRITE_MASK;
542 int user_fault = error_code & PFERR_USER_MASK;
543 struct guest_walker walker;
548 int level = PT_PAGE_TABLE_LEVEL;
550 unsigned long mmu_seq;
553 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
555 r = mmu_topup_memory_caches(vcpu);
560 * Look up the guest pte for the faulting address.
562 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
565 * The page is not mapped by the guest. Let the guest handle it.
568 pgprintk("%s: guest page fault\n", __func__);
570 inject_page_fault(vcpu, &walker.fault);
571 /* reset fork detector */
572 vcpu->arch.last_pt_write_count = 0;
577 if (walker.level >= PT_DIRECTORY_LEVEL)
578 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn);
581 if (!force_pt_level) {
582 level = min(walker.level, mapping_level(vcpu, walker.gfn));
583 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
586 mmu_seq = vcpu->kvm->mmu_notifier_seq;
589 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
594 if (is_error_pfn(pfn))
595 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
597 spin_lock(&vcpu->kvm->mmu_lock);
598 if (mmu_notifier_retry(vcpu, mmu_seq))
601 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
602 kvm_mmu_free_some_pages(vcpu);
604 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
605 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
606 level, &write_pt, pfn, map_writable, prefault);
608 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
609 sptep, *sptep, write_pt);
612 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
614 ++vcpu->stat.pf_fixed;
615 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
616 spin_unlock(&vcpu->kvm->mmu_lock);
621 spin_unlock(&vcpu->kvm->mmu_lock);
622 kvm_release_pfn_clean(pfn);
626 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
628 struct kvm_shadow_walk_iterator iterator;
629 struct kvm_mmu_page *sp;
635 spin_lock(&vcpu->kvm->mmu_lock);
637 for_each_shadow_entry(vcpu, gva, iterator) {
638 level = iterator.level;
639 sptep = iterator.sptep;
641 sp = page_header(__pa(sptep));
642 if (is_last_spte(*sptep, level)) {
649 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
650 offset = sp->role.quadrant << shift;
652 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
653 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
655 if (is_shadow_present_pte(*sptep)) {
656 if (is_large_pte(*sptep))
657 --vcpu->kvm->stat.lpages;
658 drop_spte(vcpu->kvm, sptep,
659 shadow_trap_nonpresent_pte);
662 __set_spte(sptep, shadow_trap_nonpresent_pte);
666 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
671 kvm_flush_remote_tlbs(vcpu->kvm);
673 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
675 spin_unlock(&vcpu->kvm->mmu_lock);
680 if (mmu_topup_memory_caches(vcpu))
682 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
685 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
686 struct x86_exception *exception)
688 struct guest_walker walker;
689 gpa_t gpa = UNMAPPED_GVA;
692 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
695 gpa = gfn_to_gpa(walker.gfn);
696 gpa |= vaddr & ~PAGE_MASK;
697 } else if (exception)
698 *exception = walker.fault;
703 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
705 struct x86_exception *exception)
707 struct guest_walker walker;
708 gpa_t gpa = UNMAPPED_GVA;
711 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
714 gpa = gfn_to_gpa(walker.gfn);
715 gpa |= vaddr & ~PAGE_MASK;
716 } else if (exception)
717 *exception = walker.fault;
722 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
723 struct kvm_mmu_page *sp)
726 pt_element_t pt[256 / sizeof(pt_element_t)];
730 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
731 nonpaging_prefetch_page(vcpu, sp);
735 pte_gpa = gfn_to_gpa(sp->gfn);
737 offset = sp->role.quadrant << PT64_LEVEL_BITS;
738 pte_gpa += offset * sizeof(pt_element_t);
741 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
742 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
743 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
744 for (j = 0; j < ARRAY_SIZE(pt); ++j)
745 if (r || is_present_gpte(pt[j]))
746 sp->spt[i+j] = shadow_trap_nonpresent_pte;
748 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
753 * Using the cached information from sp->gfns is safe because:
754 * - The spte has a reference to the struct page, so the pfn for a given gfn
755 * can't change unless all sptes pointing to it are nuked first.
758 * We should flush all tlbs if spte is dropped even though guest is
759 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
760 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
761 * used by guest then tlbs are not flushed, so guest is allowed to access the
763 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
765 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
767 int i, offset, nr_present;
771 offset = nr_present = 0;
773 /* direct kvm_mmu_page can not be unsync. */
774 BUG_ON(sp->role.direct);
777 offset = sp->role.quadrant << PT64_LEVEL_BITS;
779 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
781 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
787 if (!is_shadow_present_pte(sp->spt[i]))
790 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
792 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
793 sizeof(pt_element_t)))
796 gfn = gpte_to_gfn(gpte);
798 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
799 vcpu->kvm->tlbs_dirty++;
803 if (gfn != sp->gfns[i]) {
804 drop_spte(vcpu->kvm, &sp->spt[i],
805 shadow_trap_nonpresent_pte);
806 vcpu->kvm->tlbs_dirty++;
811 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
812 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
814 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
815 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
816 spte_to_pfn(sp->spt[i]), true, false,
826 #undef PT_BASE_ADDR_MASK
828 #undef PT_LVL_ADDR_MASK
829 #undef PT_LVL_OFFSET_MASK
831 #undef PT_MAX_FULL_LEVELS
833 #undef gpte_to_gfn_lvl