1 /******************************************************************************
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
6 * Copyright (c) 2005 Keir Fraser
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
26 #include <public/xen.h>
27 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
29 #include <linux/kvm_host.h>
30 #include "kvm_cache_regs.h"
31 #define DPRINTF(x...) do {} while (0)
33 #include <linux/module.h>
34 #include <asm/kvm_emulate.h>
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
48 /* Operand sizes: 8-bit operands or specified/overridden size. */
49 #define ByteOp (1<<0) /* 8-bit operands. */
50 /* Destination operand type. */
51 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52 #define DstReg (2<<1) /* Register operand. */
53 #define DstMem (3<<1) /* Memory operand. */
54 #define DstAcc (4<<1) /* Destination Accumulator */
55 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
56 #define DstMem64 (6<<1) /* 64bit memory operand */
57 #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
58 #define DstMask (7<<1)
59 /* Source operand type. */
60 #define SrcNone (0<<4) /* No source operand. */
61 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
62 #define SrcReg (1<<4) /* Register operand. */
63 #define SrcMem (2<<4) /* Memory operand. */
64 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
65 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
66 #define SrcImm (5<<4) /* Immediate operand. */
67 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
68 #define SrcOne (7<<4) /* Implied '1' */
69 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
70 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
71 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
72 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
73 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
74 #define SrcAcc (0xd<<4) /* Source Accumulator */
75 #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
76 #define SrcMask (0xf<<4)
77 /* Generic ModRM decode. */
79 /* Destination is only written; never read. */
82 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
83 #define String (1<<12) /* String instruction (rep capable) */
84 #define Stack (1<<13) /* Stack instruction (push/pop) */
85 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
86 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
88 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
89 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
90 #define Undefined (1<<25) /* No Such Instruction */
91 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
92 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
94 /* Source 2 operand type */
95 #define Src2None (0<<29)
96 #define Src2CL (1<<29)
97 #define Src2ImmByte (2<<29)
98 #define Src2One (3<<29)
99 #define Src2Mask (7<<29)
101 #define X2(x...) x, x
102 #define X3(x...) X2(x), x
103 #define X4(x...) X2(x), X2(x)
104 #define X5(x...) X4(x), x
105 #define X6(x...) X4(x), X2(x)
106 #define X7(x...) X4(x), X3(x)
107 #define X8(x...) X4(x), X4(x)
108 #define X16(x...) X8(x), X8(x)
113 int (*execute)(struct x86_emulate_ctxt *ctxt);
114 struct opcode *group;
115 struct group_dual *gdual;
120 struct opcode mod012[8];
121 struct opcode mod3[8];
124 /* EFLAGS bit definitions. */
125 #define EFLG_ID (1<<21)
126 #define EFLG_VIP (1<<20)
127 #define EFLG_VIF (1<<19)
128 #define EFLG_AC (1<<18)
129 #define EFLG_VM (1<<17)
130 #define EFLG_RF (1<<16)
131 #define EFLG_IOPL (3<<12)
132 #define EFLG_NT (1<<14)
133 #define EFLG_OF (1<<11)
134 #define EFLG_DF (1<<10)
135 #define EFLG_IF (1<<9)
136 #define EFLG_TF (1<<8)
137 #define EFLG_SF (1<<7)
138 #define EFLG_ZF (1<<6)
139 #define EFLG_AF (1<<4)
140 #define EFLG_PF (1<<2)
141 #define EFLG_CF (1<<0)
143 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
144 #define EFLG_RESERVED_ONE_MASK 2
147 * Instruction emulation:
148 * Most instructions are emulated directly via a fragment of inline assembly
149 * code. This allows us to save/restore EFLAGS and thus very easily pick up
150 * any modified flags.
153 #if defined(CONFIG_X86_64)
154 #define _LO32 "k" /* force 32-bit operand */
155 #define _STK "%%rsp" /* stack pointer */
156 #elif defined(__i386__)
157 #define _LO32 "" /* force 32-bit operand */
158 #define _STK "%%esp" /* stack pointer */
162 * These EFLAGS bits are restored from saved value during emulation, and
163 * any changes are written back to the saved value after emulation.
165 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
167 /* Before executing instruction: restore necessary bits in EFLAGS. */
168 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
169 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
170 "movl %"_sav",%"_LO32 _tmp"; " \
173 "movl %"_msk",%"_LO32 _tmp"; " \
174 "andl %"_LO32 _tmp",("_STK"); " \
176 "notl %"_LO32 _tmp"; " \
177 "andl %"_LO32 _tmp",("_STK"); " \
178 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
180 "orl %"_LO32 _tmp",("_STK"); " \
184 /* After executing instruction: write-back necessary bits in EFLAGS. */
185 #define _POST_EFLAGS(_sav, _msk, _tmp) \
186 /* _sav |= EFLAGS & _msk; */ \
189 "andl %"_msk",%"_LO32 _tmp"; " \
190 "orl %"_LO32 _tmp",%"_sav"; "
198 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
200 __asm__ __volatile__ ( \
201 _PRE_EFLAGS("0", "4", "2") \
202 _op _suffix " %"_x"3,%1; " \
203 _POST_EFLAGS("0", "4", "2") \
204 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
206 : _y ((_src).val), "i" (EFLAGS_MASK)); \
210 /* Raw emulation: instruction has two explicit operands. */
211 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
213 unsigned long _tmp; \
215 switch ((_dst).bytes) { \
217 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
220 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
223 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
228 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
230 unsigned long _tmp; \
231 switch ((_dst).bytes) { \
233 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
236 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
237 _wx, _wy, _lx, _ly, _qx, _qy); \
242 /* Source operand is byte-sized and may be restricted to just %cl. */
243 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
244 __emulate_2op(_op, _src, _dst, _eflags, \
245 "b", "c", "b", "c", "b", "c", "b", "c")
247 /* Source operand is byte, word, long or quad sized. */
248 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
249 __emulate_2op(_op, _src, _dst, _eflags, \
250 "b", "q", "w", "r", _LO32, "r", "", "r")
252 /* Source operand is word, long or quad sized. */
253 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
254 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
255 "w", "r", _LO32, "r", "", "r")
257 /* Instruction has three operands and one operand is stored in ECX register */
258 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
260 unsigned long _tmp; \
261 _type _clv = (_cl).val; \
262 _type _srcv = (_src).val; \
263 _type _dstv = (_dst).val; \
265 __asm__ __volatile__ ( \
266 _PRE_EFLAGS("0", "5", "2") \
267 _op _suffix " %4,%1 \n" \
268 _POST_EFLAGS("0", "5", "2") \
269 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
270 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
273 (_cl).val = (unsigned long) _clv; \
274 (_src).val = (unsigned long) _srcv; \
275 (_dst).val = (unsigned long) _dstv; \
278 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
280 switch ((_dst).bytes) { \
282 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
283 "w", unsigned short); \
286 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
287 "l", unsigned int); \
290 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
291 "q", unsigned long)); \
296 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
298 unsigned long _tmp; \
300 __asm__ __volatile__ ( \
301 _PRE_EFLAGS("0", "3", "2") \
302 _op _suffix " %1; " \
303 _POST_EFLAGS("0", "3", "2") \
304 : "=m" (_eflags), "+m" ((_dst).val), \
306 : "i" (EFLAGS_MASK)); \
309 /* Instruction has only one explicit operand (no source operand). */
310 #define emulate_1op(_op, _dst, _eflags) \
312 switch ((_dst).bytes) { \
313 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
314 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
315 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
316 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
320 #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
322 unsigned long _tmp; \
324 __asm__ __volatile__ ( \
325 _PRE_EFLAGS("0", "4", "1") \
326 _op _suffix " %5; " \
327 _POST_EFLAGS("0", "4", "1") \
328 : "=m" (_eflags), "=&r" (_tmp), \
329 "+a" (_rax), "+d" (_rdx) \
330 : "i" (EFLAGS_MASK), "m" ((_src).val), \
331 "a" (_rax), "d" (_rdx)); \
334 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
335 #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
337 switch((_src).bytes) { \
338 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
339 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
340 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
341 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
345 /* Fetch next part of the instruction being emulated. */
346 #define insn_fetch(_type, _size, _eip) \
347 ({ unsigned long _x; \
348 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
349 if (rc != X86EMUL_CONTINUE) \
355 #define insn_fetch_arr(_arr, _size, _eip) \
356 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
357 if (rc != X86EMUL_CONTINUE) \
362 static inline unsigned long ad_mask(struct decode_cache *c)
364 return (1UL << (c->ad_bytes << 3)) - 1;
367 /* Access/update address held in a register, based on addressing mode. */
368 static inline unsigned long
369 address_mask(struct decode_cache *c, unsigned long reg)
371 if (c->ad_bytes == sizeof(unsigned long))
374 return reg & ad_mask(c);
377 static inline unsigned long
378 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
380 return base + address_mask(c, reg);
384 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
386 if (c->ad_bytes == sizeof(unsigned long))
389 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
392 static inline void jmp_rel(struct decode_cache *c, int rel)
394 register_address_increment(c, &c->eip, rel);
397 static void set_seg_override(struct decode_cache *c, int seg)
399 c->has_seg_override = true;
400 c->seg_override = seg;
403 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
404 struct x86_emulate_ops *ops, int seg)
406 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
409 return ops->get_cached_segment_base(seg, ctxt->vcpu);
412 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
413 struct x86_emulate_ops *ops,
414 struct decode_cache *c)
416 if (!c->has_seg_override)
419 return seg_base(ctxt, ops, c->seg_override);
422 static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
423 struct x86_emulate_ops *ops)
425 return seg_base(ctxt, ops, VCPU_SREG_ES);
428 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
429 struct x86_emulate_ops *ops)
431 return seg_base(ctxt, ops, VCPU_SREG_SS);
434 static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
435 u32 error, bool valid)
437 ctxt->exception = vec;
438 ctxt->error_code = error;
439 ctxt->error_code_valid = valid;
440 ctxt->restart = false;
443 static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
445 emulate_exception(ctxt, GP_VECTOR, err, true);
448 static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
452 emulate_exception(ctxt, PF_VECTOR, err, true);
455 static void emulate_ud(struct x86_emulate_ctxt *ctxt)
457 emulate_exception(ctxt, UD_VECTOR, 0, false);
460 static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
462 emulate_exception(ctxt, TS_VECTOR, err, true);
465 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
466 struct x86_emulate_ops *ops,
467 unsigned long eip, u8 *dest)
469 struct fetch_cache *fc = &ctxt->decode.fetch;
473 if (eip == fc->end) {
474 cur_size = fc->end - fc->start;
475 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
476 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
477 size, ctxt->vcpu, NULL);
478 if (rc != X86EMUL_CONTINUE)
482 *dest = fc->data[eip - fc->start];
483 return X86EMUL_CONTINUE;
486 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
487 struct x86_emulate_ops *ops,
488 unsigned long eip, void *dest, unsigned size)
492 /* x86 instructions are limited to 15 bytes. */
493 if (eip + size - ctxt->eip > 15)
494 return X86EMUL_UNHANDLEABLE;
496 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
497 if (rc != X86EMUL_CONTINUE)
500 return X86EMUL_CONTINUE;
504 * Given the 'reg' portion of a ModRM byte, and a register block, return a
505 * pointer into the block that addresses the relevant register.
506 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
508 static void *decode_register(u8 modrm_reg, unsigned long *regs,
513 p = ®s[modrm_reg];
514 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
515 p = (unsigned char *)®s[modrm_reg & 3] + 1;
519 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
520 struct x86_emulate_ops *ops,
522 u16 *size, unsigned long *address, int op_bytes)
529 rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL);
530 if (rc != X86EMUL_CONTINUE)
532 rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL);
536 static int test_cc(unsigned int condition, unsigned int flags)
540 switch ((condition & 15) >> 1) {
542 rc |= (flags & EFLG_OF);
544 case 1: /* b/c/nae */
545 rc |= (flags & EFLG_CF);
548 rc |= (flags & EFLG_ZF);
551 rc |= (flags & (EFLG_CF|EFLG_ZF));
554 rc |= (flags & EFLG_SF);
557 rc |= (flags & EFLG_PF);
560 rc |= (flags & EFLG_ZF);
563 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
567 /* Odd condition identifiers (lsb == 1) have inverted sense. */
568 return (!!rc ^ (condition & 1));
571 static void fetch_register_operand(struct operand *op)
575 op->val = *(u8 *)op->addr.reg;
578 op->val = *(u16 *)op->addr.reg;
581 op->val = *(u32 *)op->addr.reg;
584 op->val = *(u64 *)op->addr.reg;
589 static void decode_register_operand(struct operand *op,
590 struct decode_cache *c,
593 unsigned reg = c->modrm_reg;
594 int highbyte_regs = c->rex_prefix == 0;
597 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
599 if ((c->d & ByteOp) && !inhibit_bytereg) {
600 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
603 op->addr.reg = decode_register(reg, c->regs, 0);
604 op->bytes = c->op_bytes;
606 fetch_register_operand(op);
607 op->orig_val = op->val;
610 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
611 struct x86_emulate_ops *ops,
614 struct decode_cache *c = &ctxt->decode;
616 int index_reg = 0, base_reg = 0, scale;
617 int rc = X86EMUL_CONTINUE;
621 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
622 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
623 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
626 c->modrm = insn_fetch(u8, 1, c->eip);
627 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
628 c->modrm_reg |= (c->modrm & 0x38) >> 3;
629 c->modrm_rm |= (c->modrm & 0x07);
630 c->modrm_seg = VCPU_SREG_DS;
632 if (c->modrm_mod == 3) {
634 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
635 op->addr.reg = decode_register(c->modrm_rm,
636 c->regs, c->d & ByteOp);
637 fetch_register_operand(op);
643 if (c->ad_bytes == 2) {
644 unsigned bx = c->regs[VCPU_REGS_RBX];
645 unsigned bp = c->regs[VCPU_REGS_RBP];
646 unsigned si = c->regs[VCPU_REGS_RSI];
647 unsigned di = c->regs[VCPU_REGS_RDI];
649 /* 16-bit ModR/M decode. */
650 switch (c->modrm_mod) {
652 if (c->modrm_rm == 6)
653 modrm_ea += insn_fetch(u16, 2, c->eip);
656 modrm_ea += insn_fetch(s8, 1, c->eip);
659 modrm_ea += insn_fetch(u16, 2, c->eip);
662 switch (c->modrm_rm) {
682 if (c->modrm_mod != 0)
689 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
690 (c->modrm_rm == 6 && c->modrm_mod != 0))
691 c->modrm_seg = VCPU_SREG_SS;
692 modrm_ea = (u16)modrm_ea;
694 /* 32/64-bit ModR/M decode. */
695 if ((c->modrm_rm & 7) == 4) {
696 sib = insn_fetch(u8, 1, c->eip);
697 index_reg |= (sib >> 3) & 7;
701 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
702 modrm_ea += insn_fetch(s32, 4, c->eip);
704 modrm_ea += c->regs[base_reg];
706 modrm_ea += c->regs[index_reg] << scale;
707 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
708 if (ctxt->mode == X86EMUL_MODE_PROT64)
711 modrm_ea += c->regs[c->modrm_rm];
712 switch (c->modrm_mod) {
714 if (c->modrm_rm == 5)
715 modrm_ea += insn_fetch(s32, 4, c->eip);
718 modrm_ea += insn_fetch(s8, 1, c->eip);
721 modrm_ea += insn_fetch(s32, 4, c->eip);
725 op->addr.mem = modrm_ea;
730 static int decode_abs(struct x86_emulate_ctxt *ctxt,
731 struct x86_emulate_ops *ops,
734 struct decode_cache *c = &ctxt->decode;
735 int rc = X86EMUL_CONTINUE;
738 switch (c->ad_bytes) {
740 op->addr.mem = insn_fetch(u16, 2, c->eip);
743 op->addr.mem = insn_fetch(u32, 4, c->eip);
746 op->addr.mem = insn_fetch(u64, 8, c->eip);
753 static void fetch_bit_operand(struct decode_cache *c)
757 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
758 mask = ~(c->dst.bytes * 8 - 1);
760 if (c->src.bytes == 2)
761 sv = (s16)c->src.val & (s16)mask;
762 else if (c->src.bytes == 4)
763 sv = (s32)c->src.val & (s32)mask;
765 c->dst.addr.mem += (sv >> 3);
768 /* only subword offset */
769 c->src.val &= (c->dst.bytes << 3) - 1;
772 static int read_emulated(struct x86_emulate_ctxt *ctxt,
773 struct x86_emulate_ops *ops,
774 unsigned long addr, void *dest, unsigned size)
777 struct read_cache *mc = &ctxt->decode.mem_read;
781 int n = min(size, 8u);
783 if (mc->pos < mc->end)
786 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
788 if (rc == X86EMUL_PROPAGATE_FAULT)
789 emulate_pf(ctxt, addr, err);
790 if (rc != X86EMUL_CONTINUE)
795 memcpy(dest, mc->data + mc->pos, n);
800 return X86EMUL_CONTINUE;
803 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
804 struct x86_emulate_ops *ops,
805 unsigned int size, unsigned short port,
808 struct read_cache *rc = &ctxt->decode.io_read;
810 if (rc->pos == rc->end) { /* refill pio read ahead */
811 struct decode_cache *c = &ctxt->decode;
812 unsigned int in_page, n;
813 unsigned int count = c->rep_prefix ?
814 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
815 in_page = (ctxt->eflags & EFLG_DF) ?
816 offset_in_page(c->regs[VCPU_REGS_RDI]) :
817 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
818 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
822 rc->pos = rc->end = 0;
823 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
828 memcpy(dest, rc->data + rc->pos, size);
833 static u32 desc_limit_scaled(struct desc_struct *desc)
835 u32 limit = get_desc_limit(desc);
837 return desc->g ? (limit << 12) | 0xfff : limit;
840 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
841 struct x86_emulate_ops *ops,
842 u16 selector, struct desc_ptr *dt)
844 if (selector & 1 << 2) {
845 struct desc_struct desc;
846 memset (dt, 0, sizeof *dt);
847 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
850 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
851 dt->address = get_desc_base(&desc);
853 ops->get_gdt(dt, ctxt->vcpu);
856 /* allowed just for 8 bytes segments */
857 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
858 struct x86_emulate_ops *ops,
859 u16 selector, struct desc_struct *desc)
862 u16 index = selector >> 3;
867 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
869 if (dt.size < index * 8 + 7) {
870 emulate_gp(ctxt, selector & 0xfffc);
871 return X86EMUL_PROPAGATE_FAULT;
873 addr = dt.address + index * 8;
874 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
875 if (ret == X86EMUL_PROPAGATE_FAULT)
876 emulate_pf(ctxt, addr, err);
881 /* allowed just for 8 bytes segments */
882 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
883 struct x86_emulate_ops *ops,
884 u16 selector, struct desc_struct *desc)
887 u16 index = selector >> 3;
892 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
894 if (dt.size < index * 8 + 7) {
895 emulate_gp(ctxt, selector & 0xfffc);
896 return X86EMUL_PROPAGATE_FAULT;
899 addr = dt.address + index * 8;
900 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
901 if (ret == X86EMUL_PROPAGATE_FAULT)
902 emulate_pf(ctxt, addr, err);
907 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
908 struct x86_emulate_ops *ops,
909 u16 selector, int seg)
911 struct desc_struct seg_desc;
913 unsigned err_vec = GP_VECTOR;
915 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
918 memset(&seg_desc, 0, sizeof seg_desc);
920 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
921 || ctxt->mode == X86EMUL_MODE_REAL) {
922 /* set real mode segment descriptor */
923 set_desc_base(&seg_desc, selector << 4);
924 set_desc_limit(&seg_desc, 0xffff);
931 /* NULL selector is not valid for TR, CS and SS */
932 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
936 /* TR should be in GDT only */
937 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
940 if (null_selector) /* for NULL selector skip all following checks */
943 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
944 if (ret != X86EMUL_CONTINUE)
947 err_code = selector & 0xfffc;
950 /* can't load system descriptor into segment selecor */
951 if (seg <= VCPU_SREG_GS && !seg_desc.s)
955 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
961 cpl = ops->cpl(ctxt->vcpu);
966 * segment is not a writable data segment or segment
967 * selector's RPL != CPL or segment selector's RPL != CPL
969 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
973 if (!(seg_desc.type & 8))
976 if (seg_desc.type & 4) {
982 if (rpl > cpl || dpl != cpl)
986 selector = (selector & 0xfffc) | cpl;
989 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
993 if (seg_desc.s || seg_desc.type != 2)
996 default: /* DS, ES, FS, or GS */
998 * segment is not a data or readable code segment or
999 * ((segment is a data or nonconforming code segment)
1000 * and (both RPL and CPL > DPL))
1002 if ((seg_desc.type & 0xa) == 0x8 ||
1003 (((seg_desc.type & 0xc) != 0xc) &&
1004 (rpl > dpl && cpl > dpl)))
1010 /* mark segment as accessed */
1012 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1013 if (ret != X86EMUL_CONTINUE)
1017 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1018 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1019 return X86EMUL_CONTINUE;
1021 emulate_exception(ctxt, err_vec, err_code, true);
1022 return X86EMUL_PROPAGATE_FAULT;
1025 static void write_register_operand(struct operand *op)
1027 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1028 switch (op->bytes) {
1030 *(u8 *)op->addr.reg = (u8)op->val;
1033 *(u16 *)op->addr.reg = (u16)op->val;
1036 *op->addr.reg = (u32)op->val;
1037 break; /* 64b: zero-extend */
1039 *op->addr.reg = op->val;
1044 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1045 struct x86_emulate_ops *ops)
1048 struct decode_cache *c = &ctxt->decode;
1051 switch (c->dst.type) {
1053 write_register_operand(&c->dst);
1057 rc = ops->cmpxchg_emulated(
1065 rc = ops->write_emulated(
1071 if (rc == X86EMUL_PROPAGATE_FAULT)
1072 emulate_pf(ctxt, c->dst.addr.mem, err);
1073 if (rc != X86EMUL_CONTINUE)
1082 return X86EMUL_CONTINUE;
1085 static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1086 struct x86_emulate_ops *ops)
1088 struct decode_cache *c = &ctxt->decode;
1090 c->dst.type = OP_MEM;
1091 c->dst.bytes = c->op_bytes;
1092 c->dst.val = c->src.val;
1093 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1094 c->dst.addr.mem = register_address(c, ss_base(ctxt, ops),
1095 c->regs[VCPU_REGS_RSP]);
1098 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1099 struct x86_emulate_ops *ops,
1100 void *dest, int len)
1102 struct decode_cache *c = &ctxt->decode;
1105 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1106 c->regs[VCPU_REGS_RSP]),
1108 if (rc != X86EMUL_CONTINUE)
1111 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1115 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1116 struct x86_emulate_ops *ops,
1117 void *dest, int len)
1120 unsigned long val, change_mask;
1121 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1122 int cpl = ops->cpl(ctxt->vcpu);
1124 rc = emulate_pop(ctxt, ops, &val, len);
1125 if (rc != X86EMUL_CONTINUE)
1128 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1129 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1131 switch(ctxt->mode) {
1132 case X86EMUL_MODE_PROT64:
1133 case X86EMUL_MODE_PROT32:
1134 case X86EMUL_MODE_PROT16:
1136 change_mask |= EFLG_IOPL;
1138 change_mask |= EFLG_IF;
1140 case X86EMUL_MODE_VM86:
1142 emulate_gp(ctxt, 0);
1143 return X86EMUL_PROPAGATE_FAULT;
1145 change_mask |= EFLG_IF;
1147 default: /* real mode */
1148 change_mask |= (EFLG_IOPL | EFLG_IF);
1152 *(unsigned long *)dest =
1153 (ctxt->eflags & ~change_mask) | (val & change_mask);
1158 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1159 struct x86_emulate_ops *ops, int seg)
1161 struct decode_cache *c = &ctxt->decode;
1163 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
1165 emulate_push(ctxt, ops);
1168 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1169 struct x86_emulate_ops *ops, int seg)
1171 struct decode_cache *c = &ctxt->decode;
1172 unsigned long selector;
1175 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1176 if (rc != X86EMUL_CONTINUE)
1179 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1183 static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1184 struct x86_emulate_ops *ops)
1186 struct decode_cache *c = &ctxt->decode;
1187 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1188 int rc = X86EMUL_CONTINUE;
1189 int reg = VCPU_REGS_RAX;
1191 while (reg <= VCPU_REGS_RDI) {
1192 (reg == VCPU_REGS_RSP) ?
1193 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1195 emulate_push(ctxt, ops);
1197 rc = writeback(ctxt, ops);
1198 if (rc != X86EMUL_CONTINUE)
1204 /* Disable writeback. */
1205 c->dst.type = OP_NONE;
1210 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1211 struct x86_emulate_ops *ops)
1213 struct decode_cache *c = &ctxt->decode;
1214 int rc = X86EMUL_CONTINUE;
1215 int reg = VCPU_REGS_RDI;
1217 while (reg >= VCPU_REGS_RAX) {
1218 if (reg == VCPU_REGS_RSP) {
1219 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1224 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1225 if (rc != X86EMUL_CONTINUE)
1232 int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1233 struct x86_emulate_ops *ops, int irq)
1235 struct decode_cache *c = &ctxt->decode;
1243 /* TODO: Add limit checks */
1244 c->src.val = ctxt->eflags;
1245 emulate_push(ctxt, ops);
1246 rc = writeback(ctxt, ops);
1247 if (rc != X86EMUL_CONTINUE)
1250 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1252 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1253 emulate_push(ctxt, ops);
1254 rc = writeback(ctxt, ops);
1255 if (rc != X86EMUL_CONTINUE)
1258 c->src.val = c->eip;
1259 emulate_push(ctxt, ops);
1260 rc = writeback(ctxt, ops);
1261 if (rc != X86EMUL_CONTINUE)
1264 c->dst.type = OP_NONE;
1266 ops->get_idt(&dt, ctxt->vcpu);
1268 eip_addr = dt.address + (irq << 2);
1269 cs_addr = dt.address + (irq << 2) + 2;
1271 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err);
1272 if (rc != X86EMUL_CONTINUE)
1275 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err);
1276 if (rc != X86EMUL_CONTINUE)
1279 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1280 if (rc != X86EMUL_CONTINUE)
1288 static int emulate_int(struct x86_emulate_ctxt *ctxt,
1289 struct x86_emulate_ops *ops, int irq)
1291 switch(ctxt->mode) {
1292 case X86EMUL_MODE_REAL:
1293 return emulate_int_real(ctxt, ops, irq);
1294 case X86EMUL_MODE_VM86:
1295 case X86EMUL_MODE_PROT16:
1296 case X86EMUL_MODE_PROT32:
1297 case X86EMUL_MODE_PROT64:
1299 /* Protected mode interrupts unimplemented yet */
1300 return X86EMUL_UNHANDLEABLE;
1304 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1305 struct x86_emulate_ops *ops)
1307 struct decode_cache *c = &ctxt->decode;
1308 int rc = X86EMUL_CONTINUE;
1309 unsigned long temp_eip = 0;
1310 unsigned long temp_eflags = 0;
1311 unsigned long cs = 0;
1312 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1313 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1314 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1315 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1317 /* TODO: Add stack limit check */
1319 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1321 if (rc != X86EMUL_CONTINUE)
1324 if (temp_eip & ~0xffff) {
1325 emulate_gp(ctxt, 0);
1326 return X86EMUL_PROPAGATE_FAULT;
1329 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1331 if (rc != X86EMUL_CONTINUE)
1334 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1336 if (rc != X86EMUL_CONTINUE)
1339 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1341 if (rc != X86EMUL_CONTINUE)
1347 if (c->op_bytes == 4)
1348 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1349 else if (c->op_bytes == 2) {
1350 ctxt->eflags &= ~0xffff;
1351 ctxt->eflags |= temp_eflags;
1354 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1355 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1360 static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1361 struct x86_emulate_ops* ops)
1363 switch(ctxt->mode) {
1364 case X86EMUL_MODE_REAL:
1365 return emulate_iret_real(ctxt, ops);
1366 case X86EMUL_MODE_VM86:
1367 case X86EMUL_MODE_PROT16:
1368 case X86EMUL_MODE_PROT32:
1369 case X86EMUL_MODE_PROT64:
1371 /* iret from protected mode unimplemented yet */
1372 return X86EMUL_UNHANDLEABLE;
1376 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1377 struct x86_emulate_ops *ops)
1379 struct decode_cache *c = &ctxt->decode;
1381 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1384 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1386 struct decode_cache *c = &ctxt->decode;
1387 switch (c->modrm_reg) {
1389 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1392 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1395 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1398 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1400 case 4: /* sal/shl */
1401 case 6: /* sal/shl */
1402 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1405 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1408 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1413 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1414 struct x86_emulate_ops *ops)
1416 struct decode_cache *c = &ctxt->decode;
1417 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1418 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1420 switch (c->modrm_reg) {
1421 case 0 ... 1: /* test */
1422 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1425 c->dst.val = ~c->dst.val;
1428 emulate_1op("neg", c->dst, ctxt->eflags);
1431 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1434 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1437 emulate_1op_rax_rdx("div", c->src, *rax, *rdx, ctxt->eflags);
1440 emulate_1op_rax_rdx("idiv", c->src, *rax, *rdx, ctxt->eflags);
1443 return X86EMUL_UNHANDLEABLE;
1445 return X86EMUL_CONTINUE;
1448 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1449 struct x86_emulate_ops *ops)
1451 struct decode_cache *c = &ctxt->decode;
1453 switch (c->modrm_reg) {
1455 emulate_1op("inc", c->dst, ctxt->eflags);
1458 emulate_1op("dec", c->dst, ctxt->eflags);
1460 case 2: /* call near abs */ {
1463 c->eip = c->src.val;
1464 c->src.val = old_eip;
1465 emulate_push(ctxt, ops);
1468 case 4: /* jmp abs */
1469 c->eip = c->src.val;
1472 emulate_push(ctxt, ops);
1475 return X86EMUL_CONTINUE;
1478 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1479 struct x86_emulate_ops *ops)
1481 struct decode_cache *c = &ctxt->decode;
1482 u64 old = c->dst.orig_val64;
1484 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1485 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1486 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1487 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1488 ctxt->eflags &= ~EFLG_ZF;
1490 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1491 (u32) c->regs[VCPU_REGS_RBX];
1493 ctxt->eflags |= EFLG_ZF;
1495 return X86EMUL_CONTINUE;
1498 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1499 struct x86_emulate_ops *ops)
1501 struct decode_cache *c = &ctxt->decode;
1505 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1506 if (rc != X86EMUL_CONTINUE)
1508 if (c->op_bytes == 4)
1509 c->eip = (u32)c->eip;
1510 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1511 if (rc != X86EMUL_CONTINUE)
1513 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1518 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1519 struct x86_emulate_ops *ops, struct desc_struct *cs,
1520 struct desc_struct *ss)
1522 memset(cs, 0, sizeof(struct desc_struct));
1523 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1524 memset(ss, 0, sizeof(struct desc_struct));
1526 cs->l = 0; /* will be adjusted later */
1527 set_desc_base(cs, 0); /* flat segment */
1528 cs->g = 1; /* 4kb granularity */
1529 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1530 cs->type = 0x0b; /* Read, Execute, Accessed */
1532 cs->dpl = 0; /* will be adjusted later */
1536 set_desc_base(ss, 0); /* flat segment */
1537 set_desc_limit(ss, 0xfffff); /* 4GB limit */
1538 ss->g = 1; /* 4kb granularity */
1540 ss->type = 0x03; /* Read/Write, Accessed */
1541 ss->d = 1; /* 32bit stack segment */
1547 emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1549 struct decode_cache *c = &ctxt->decode;
1550 struct desc_struct cs, ss;
1554 /* syscall is not available in real mode */
1555 if (ctxt->mode == X86EMUL_MODE_REAL ||
1556 ctxt->mode == X86EMUL_MODE_VM86) {
1558 return X86EMUL_PROPAGATE_FAULT;
1561 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1563 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1565 cs_sel = (u16)(msr_data & 0xfffc);
1566 ss_sel = (u16)(msr_data + 8);
1568 if (is_long_mode(ctxt->vcpu)) {
1572 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1573 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1574 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1575 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1577 c->regs[VCPU_REGS_RCX] = c->eip;
1578 if (is_long_mode(ctxt->vcpu)) {
1579 #ifdef CONFIG_X86_64
1580 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1582 ops->get_msr(ctxt->vcpu,
1583 ctxt->mode == X86EMUL_MODE_PROT64 ?
1584 MSR_LSTAR : MSR_CSTAR, &msr_data);
1587 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1588 ctxt->eflags &= ~(msr_data | EFLG_RF);
1592 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1593 c->eip = (u32)msr_data;
1595 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1598 return X86EMUL_CONTINUE;
1602 emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1604 struct decode_cache *c = &ctxt->decode;
1605 struct desc_struct cs, ss;
1609 /* inject #GP if in real mode */
1610 if (ctxt->mode == X86EMUL_MODE_REAL) {
1611 emulate_gp(ctxt, 0);
1612 return X86EMUL_PROPAGATE_FAULT;
1615 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1616 * Therefore, we inject an #UD.
1618 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1620 return X86EMUL_PROPAGATE_FAULT;
1623 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1625 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1626 switch (ctxt->mode) {
1627 case X86EMUL_MODE_PROT32:
1628 if ((msr_data & 0xfffc) == 0x0) {
1629 emulate_gp(ctxt, 0);
1630 return X86EMUL_PROPAGATE_FAULT;
1633 case X86EMUL_MODE_PROT64:
1634 if (msr_data == 0x0) {
1635 emulate_gp(ctxt, 0);
1636 return X86EMUL_PROPAGATE_FAULT;
1641 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1642 cs_sel = (u16)msr_data;
1643 cs_sel &= ~SELECTOR_RPL_MASK;
1644 ss_sel = cs_sel + 8;
1645 ss_sel &= ~SELECTOR_RPL_MASK;
1646 if (ctxt->mode == X86EMUL_MODE_PROT64
1647 || is_long_mode(ctxt->vcpu)) {
1652 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1653 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1654 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1655 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1657 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1660 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1661 c->regs[VCPU_REGS_RSP] = msr_data;
1663 return X86EMUL_CONTINUE;
1667 emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1669 struct decode_cache *c = &ctxt->decode;
1670 struct desc_struct cs, ss;
1675 /* inject #GP if in real mode or Virtual 8086 mode */
1676 if (ctxt->mode == X86EMUL_MODE_REAL ||
1677 ctxt->mode == X86EMUL_MODE_VM86) {
1678 emulate_gp(ctxt, 0);
1679 return X86EMUL_PROPAGATE_FAULT;
1682 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1684 if ((c->rex_prefix & 0x8) != 0x0)
1685 usermode = X86EMUL_MODE_PROT64;
1687 usermode = X86EMUL_MODE_PROT32;
1691 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1693 case X86EMUL_MODE_PROT32:
1694 cs_sel = (u16)(msr_data + 16);
1695 if ((msr_data & 0xfffc) == 0x0) {
1696 emulate_gp(ctxt, 0);
1697 return X86EMUL_PROPAGATE_FAULT;
1699 ss_sel = (u16)(msr_data + 24);
1701 case X86EMUL_MODE_PROT64:
1702 cs_sel = (u16)(msr_data + 32);
1703 if (msr_data == 0x0) {
1704 emulate_gp(ctxt, 0);
1705 return X86EMUL_PROPAGATE_FAULT;
1707 ss_sel = cs_sel + 8;
1712 cs_sel |= SELECTOR_RPL_MASK;
1713 ss_sel |= SELECTOR_RPL_MASK;
1715 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1716 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1717 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1718 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1720 c->eip = c->regs[VCPU_REGS_RDX];
1721 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
1723 return X86EMUL_CONTINUE;
1726 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1727 struct x86_emulate_ops *ops)
1730 if (ctxt->mode == X86EMUL_MODE_REAL)
1732 if (ctxt->mode == X86EMUL_MODE_VM86)
1734 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1735 return ops->cpl(ctxt->vcpu) > iopl;
1738 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1739 struct x86_emulate_ops *ops,
1742 struct desc_struct tr_seg;
1745 u8 perm, bit_idx = port & 0x7;
1746 unsigned mask = (1 << len) - 1;
1748 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1751 if (desc_limit_scaled(&tr_seg) < 103)
1753 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1755 if (r != X86EMUL_CONTINUE)
1757 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
1759 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1760 &perm, 1, ctxt->vcpu, NULL);
1761 if (r != X86EMUL_CONTINUE)
1763 if ((perm >> bit_idx) & mask)
1768 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1769 struct x86_emulate_ops *ops,
1775 if (emulator_bad_iopl(ctxt, ops))
1776 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1779 ctxt->perm_ok = true;
1784 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1785 struct x86_emulate_ops *ops,
1786 struct tss_segment_16 *tss)
1788 struct decode_cache *c = &ctxt->decode;
1791 tss->flag = ctxt->eflags;
1792 tss->ax = c->regs[VCPU_REGS_RAX];
1793 tss->cx = c->regs[VCPU_REGS_RCX];
1794 tss->dx = c->regs[VCPU_REGS_RDX];
1795 tss->bx = c->regs[VCPU_REGS_RBX];
1796 tss->sp = c->regs[VCPU_REGS_RSP];
1797 tss->bp = c->regs[VCPU_REGS_RBP];
1798 tss->si = c->regs[VCPU_REGS_RSI];
1799 tss->di = c->regs[VCPU_REGS_RDI];
1801 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1802 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1803 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1804 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1805 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1808 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1809 struct x86_emulate_ops *ops,
1810 struct tss_segment_16 *tss)
1812 struct decode_cache *c = &ctxt->decode;
1816 ctxt->eflags = tss->flag | 2;
1817 c->regs[VCPU_REGS_RAX] = tss->ax;
1818 c->regs[VCPU_REGS_RCX] = tss->cx;
1819 c->regs[VCPU_REGS_RDX] = tss->dx;
1820 c->regs[VCPU_REGS_RBX] = tss->bx;
1821 c->regs[VCPU_REGS_RSP] = tss->sp;
1822 c->regs[VCPU_REGS_RBP] = tss->bp;
1823 c->regs[VCPU_REGS_RSI] = tss->si;
1824 c->regs[VCPU_REGS_RDI] = tss->di;
1827 * SDM says that segment selectors are loaded before segment
1830 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1831 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1832 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1833 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1834 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1837 * Now load segment descriptors. If fault happenes at this stage
1838 * it is handled in a context of new task
1840 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1841 if (ret != X86EMUL_CONTINUE)
1843 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1844 if (ret != X86EMUL_CONTINUE)
1846 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1847 if (ret != X86EMUL_CONTINUE)
1849 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1850 if (ret != X86EMUL_CONTINUE)
1852 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1853 if (ret != X86EMUL_CONTINUE)
1856 return X86EMUL_CONTINUE;
1859 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1860 struct x86_emulate_ops *ops,
1861 u16 tss_selector, u16 old_tss_sel,
1862 ulong old_tss_base, struct desc_struct *new_desc)
1864 struct tss_segment_16 tss_seg;
1866 u32 err, new_tss_base = get_desc_base(new_desc);
1868 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1870 if (ret == X86EMUL_PROPAGATE_FAULT) {
1871 /* FIXME: need to provide precise fault address */
1872 emulate_pf(ctxt, old_tss_base, err);
1876 save_state_to_tss16(ctxt, ops, &tss_seg);
1878 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1880 if (ret == X86EMUL_PROPAGATE_FAULT) {
1881 /* FIXME: need to provide precise fault address */
1882 emulate_pf(ctxt, old_tss_base, err);
1886 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1888 if (ret == X86EMUL_PROPAGATE_FAULT) {
1889 /* FIXME: need to provide precise fault address */
1890 emulate_pf(ctxt, new_tss_base, err);
1894 if (old_tss_sel != 0xffff) {
1895 tss_seg.prev_task_link = old_tss_sel;
1897 ret = ops->write_std(new_tss_base,
1898 &tss_seg.prev_task_link,
1899 sizeof tss_seg.prev_task_link,
1901 if (ret == X86EMUL_PROPAGATE_FAULT) {
1902 /* FIXME: need to provide precise fault address */
1903 emulate_pf(ctxt, new_tss_base, err);
1908 return load_state_from_tss16(ctxt, ops, &tss_seg);
1911 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1912 struct x86_emulate_ops *ops,
1913 struct tss_segment_32 *tss)
1915 struct decode_cache *c = &ctxt->decode;
1917 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1919 tss->eflags = ctxt->eflags;
1920 tss->eax = c->regs[VCPU_REGS_RAX];
1921 tss->ecx = c->regs[VCPU_REGS_RCX];
1922 tss->edx = c->regs[VCPU_REGS_RDX];
1923 tss->ebx = c->regs[VCPU_REGS_RBX];
1924 tss->esp = c->regs[VCPU_REGS_RSP];
1925 tss->ebp = c->regs[VCPU_REGS_RBP];
1926 tss->esi = c->regs[VCPU_REGS_RSI];
1927 tss->edi = c->regs[VCPU_REGS_RDI];
1929 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1930 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1931 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1932 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1933 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1934 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1935 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1938 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1939 struct x86_emulate_ops *ops,
1940 struct tss_segment_32 *tss)
1942 struct decode_cache *c = &ctxt->decode;
1945 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
1946 emulate_gp(ctxt, 0);
1947 return X86EMUL_PROPAGATE_FAULT;
1950 ctxt->eflags = tss->eflags | 2;
1951 c->regs[VCPU_REGS_RAX] = tss->eax;
1952 c->regs[VCPU_REGS_RCX] = tss->ecx;
1953 c->regs[VCPU_REGS_RDX] = tss->edx;
1954 c->regs[VCPU_REGS_RBX] = tss->ebx;
1955 c->regs[VCPU_REGS_RSP] = tss->esp;
1956 c->regs[VCPU_REGS_RBP] = tss->ebp;
1957 c->regs[VCPU_REGS_RSI] = tss->esi;
1958 c->regs[VCPU_REGS_RDI] = tss->edi;
1961 * SDM says that segment selectors are loaded before segment
1964 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1965 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1966 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1967 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1968 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1969 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1970 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1973 * Now load segment descriptors. If fault happenes at this stage
1974 * it is handled in a context of new task
1976 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1977 if (ret != X86EMUL_CONTINUE)
1979 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1980 if (ret != X86EMUL_CONTINUE)
1982 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1983 if (ret != X86EMUL_CONTINUE)
1985 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1986 if (ret != X86EMUL_CONTINUE)
1988 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1989 if (ret != X86EMUL_CONTINUE)
1991 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
1992 if (ret != X86EMUL_CONTINUE)
1994 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
1995 if (ret != X86EMUL_CONTINUE)
1998 return X86EMUL_CONTINUE;
2001 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2002 struct x86_emulate_ops *ops,
2003 u16 tss_selector, u16 old_tss_sel,
2004 ulong old_tss_base, struct desc_struct *new_desc)
2006 struct tss_segment_32 tss_seg;
2008 u32 err, new_tss_base = get_desc_base(new_desc);
2010 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2012 if (ret == X86EMUL_PROPAGATE_FAULT) {
2013 /* FIXME: need to provide precise fault address */
2014 emulate_pf(ctxt, old_tss_base, err);
2018 save_state_to_tss32(ctxt, ops, &tss_seg);
2020 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2022 if (ret == X86EMUL_PROPAGATE_FAULT) {
2023 /* FIXME: need to provide precise fault address */
2024 emulate_pf(ctxt, old_tss_base, err);
2028 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2030 if (ret == X86EMUL_PROPAGATE_FAULT) {
2031 /* FIXME: need to provide precise fault address */
2032 emulate_pf(ctxt, new_tss_base, err);
2036 if (old_tss_sel != 0xffff) {
2037 tss_seg.prev_task_link = old_tss_sel;
2039 ret = ops->write_std(new_tss_base,
2040 &tss_seg.prev_task_link,
2041 sizeof tss_seg.prev_task_link,
2043 if (ret == X86EMUL_PROPAGATE_FAULT) {
2044 /* FIXME: need to provide precise fault address */
2045 emulate_pf(ctxt, new_tss_base, err);
2050 return load_state_from_tss32(ctxt, ops, &tss_seg);
2053 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2054 struct x86_emulate_ops *ops,
2055 u16 tss_selector, int reason,
2056 bool has_error_code, u32 error_code)
2058 struct desc_struct curr_tss_desc, next_tss_desc;
2060 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2061 ulong old_tss_base =
2062 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
2065 /* FIXME: old_tss_base == ~0 ? */
2067 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2068 if (ret != X86EMUL_CONTINUE)
2070 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2071 if (ret != X86EMUL_CONTINUE)
2074 /* FIXME: check that next_tss_desc is tss */
2076 if (reason != TASK_SWITCH_IRET) {
2077 if ((tss_selector & 3) > next_tss_desc.dpl ||
2078 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2079 emulate_gp(ctxt, 0);
2080 return X86EMUL_PROPAGATE_FAULT;
2084 desc_limit = desc_limit_scaled(&next_tss_desc);
2085 if (!next_tss_desc.p ||
2086 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2087 desc_limit < 0x2b)) {
2088 emulate_ts(ctxt, tss_selector & 0xfffc);
2089 return X86EMUL_PROPAGATE_FAULT;
2092 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2093 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2094 write_segment_descriptor(ctxt, ops, old_tss_sel,
2098 if (reason == TASK_SWITCH_IRET)
2099 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2101 /* set back link to prev task only if NT bit is set in eflags
2102 note that old_tss_sel is not used afetr this point */
2103 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2104 old_tss_sel = 0xffff;
2106 if (next_tss_desc.type & 8)
2107 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2108 old_tss_base, &next_tss_desc);
2110 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2111 old_tss_base, &next_tss_desc);
2112 if (ret != X86EMUL_CONTINUE)
2115 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2116 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2118 if (reason != TASK_SWITCH_IRET) {
2119 next_tss_desc.type |= (1 << 1); /* set busy flag */
2120 write_segment_descriptor(ctxt, ops, tss_selector,
2124 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2125 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2126 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2128 if (has_error_code) {
2129 struct decode_cache *c = &ctxt->decode;
2131 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2133 c->src.val = (unsigned long) error_code;
2134 emulate_push(ctxt, ops);
2140 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2141 u16 tss_selector, int reason,
2142 bool has_error_code, u32 error_code)
2144 struct x86_emulate_ops *ops = ctxt->ops;
2145 struct decode_cache *c = &ctxt->decode;
2149 c->dst.type = OP_NONE;
2151 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2152 has_error_code, error_code);
2154 if (rc == X86EMUL_CONTINUE) {
2155 rc = writeback(ctxt, ops);
2156 if (rc == X86EMUL_CONTINUE)
2160 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2163 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
2164 int reg, struct operand *op)
2166 struct decode_cache *c = &ctxt->decode;
2167 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2169 register_address_increment(c, &c->regs[reg], df * op->bytes);
2170 op->addr.mem = register_address(c, base, c->regs[reg]);
2173 static int em_push(struct x86_emulate_ctxt *ctxt)
2175 emulate_push(ctxt, ctxt->ops);
2176 return X86EMUL_CONTINUE;
2179 static int em_das(struct x86_emulate_ctxt *ctxt)
2181 struct decode_cache *c = &ctxt->decode;
2183 bool af, cf, old_cf;
2185 cf = ctxt->eflags & X86_EFLAGS_CF;
2191 af = ctxt->eflags & X86_EFLAGS_AF;
2192 if ((al & 0x0f) > 9 || af) {
2194 cf = old_cf | (al >= 250);
2199 if (old_al > 0x99 || old_cf) {
2205 /* Set PF, ZF, SF */
2206 c->src.type = OP_IMM;
2209 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2210 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2212 ctxt->eflags |= X86_EFLAGS_CF;
2214 ctxt->eflags |= X86_EFLAGS_AF;
2215 return X86EMUL_CONTINUE;
2218 static int em_call_far(struct x86_emulate_ctxt *ctxt)
2220 struct decode_cache *c = &ctxt->decode;
2225 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2228 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2229 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2230 return X86EMUL_CONTINUE;
2233 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2235 c->src.val = old_cs;
2236 emulate_push(ctxt, ctxt->ops);
2237 rc = writeback(ctxt, ctxt->ops);
2238 if (rc != X86EMUL_CONTINUE)
2241 c->src.val = old_eip;
2242 emulate_push(ctxt, ctxt->ops);
2243 rc = writeback(ctxt, ctxt->ops);
2244 if (rc != X86EMUL_CONTINUE)
2247 c->dst.type = OP_NONE;
2249 return X86EMUL_CONTINUE;
2252 #define D(_y) { .flags = (_y) }
2254 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2255 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2256 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2258 static struct opcode group1[] = {
2262 static struct opcode group1A[] = {
2263 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2266 static struct opcode group3[] = {
2267 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2268 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2269 X4(D(SrcMem | ModRM)),
2272 static struct opcode group4[] = {
2273 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2277 static struct opcode group5[] = {
2278 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2279 D(SrcMem | ModRM | Stack),
2280 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
2281 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2282 D(SrcMem | ModRM | Stack), N,
2285 static struct group_dual group7 = { {
2286 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2287 D(SrcNone | ModRM | DstMem | Mov), N,
2288 D(SrcMem16 | ModRM | Mov | Priv),
2289 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
2291 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2292 D(SrcNone | ModRM | DstMem | Mov), N,
2293 D(SrcMem16 | ModRM | Mov | Priv), N,
2296 static struct opcode group8[] = {
2298 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2299 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2302 static struct group_dual group9 = { {
2303 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2305 N, N, N, N, N, N, N, N,
2308 static struct opcode opcode_table[256] = {
2310 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2311 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2312 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2313 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2315 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2316 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2317 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2318 D(ImplicitOps | Stack | No64), N,
2320 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2321 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2322 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2323 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2325 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2326 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2327 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2328 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2330 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2331 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2332 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2334 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2335 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2336 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm),
2337 N, I(ByteOp | DstAcc | No64, em_das),
2339 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2340 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2341 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2343 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2344 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2345 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2350 X8(I(SrcReg | Stack, em_push)),
2352 X8(D(DstReg | Stack)),
2354 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2355 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2358 I(SrcImm | Mov | Stack, em_push), N,
2359 I(SrcImmByte | Mov | Stack, em_push), N,
2360 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
2361 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
2365 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2366 G(DstMem | SrcImm | ModRM | Group, group1),
2367 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2368 G(DstMem | SrcImmByte | ModRM | Group, group1),
2369 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2370 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2372 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
2373 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
2374 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
2375 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2377 X8(D(SrcAcc | DstReg)),
2379 D(DstAcc | SrcNone), N, D(SrcImmFAddr | No64), N,
2380 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2382 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
2383 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
2384 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
2385 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
2387 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm),
2388 D(ByteOp | SrcAcc | DstDI | Mov | String), D(SrcAcc | DstDI | Mov | String),
2389 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
2390 D(ByteOp | SrcAcc | DstDI | String), D(SrcAcc | DstDI | String),
2392 X8(D(ByteOp | DstReg | SrcImm | Mov)),
2394 X8(D(DstReg | SrcImm | Mov)),
2396 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
2397 N, D(ImplicitOps | Stack), N, N,
2398 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
2400 N, N, N, D(ImplicitOps | Stack),
2401 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2403 D(ByteOp | DstMem | SrcOne | ModRM), D(DstMem | SrcOne | ModRM),
2404 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
2407 N, N, N, N, N, N, N, N,
2409 X3(D(SrcImmByte)), N,
2410 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2411 D(ByteOp | SrcAcc | DstImmUByte), D(SrcAcc | DstImmUByte),
2413 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2414 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2415 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2416 D(ByteOp | SrcAcc | ImplicitOps), D(SrcAcc | ImplicitOps),
2419 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2421 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
2422 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2425 static struct opcode twobyte_table[256] = {
2427 N, GD(0, &group7), N, N,
2428 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2429 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2430 N, D(ImplicitOps | ModRM), N, N,
2432 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2434 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2435 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
2437 N, N, N, N, N, N, N, N,
2439 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
2440 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2441 N, N, N, N, N, N, N, N,
2443 X16(D(DstReg | SrcMem | ModRM | Mov)),
2445 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2447 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2449 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2453 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
2455 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2456 N, D(DstMem | SrcReg | ModRM | BitOp),
2457 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2458 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2460 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2461 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2462 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2463 D(DstMem | SrcReg | Src2CL | ModRM),
2466 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2467 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2468 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2469 D(DstReg | SrcMem16 | ModRM | Mov),
2472 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2473 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2474 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
2476 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2477 N, D(DstMem | SrcReg | ModRM | Mov),
2478 N, N, N, GD(0, &group9),
2479 N, N, N, N, N, N, N, N,
2481 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2483 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2485 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2495 x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2497 struct x86_emulate_ops *ops = ctxt->ops;
2498 struct decode_cache *c = &ctxt->decode;
2499 int rc = X86EMUL_CONTINUE;
2500 int mode = ctxt->mode;
2501 int def_op_bytes, def_ad_bytes, dual, goffset;
2502 struct opcode opcode, *g_mod012, *g_mod3;
2503 struct operand memop = { .type = OP_NONE };
2505 /* we cannot decode insn before we complete previous rep insn */
2506 WARN_ON(ctxt->restart);
2509 c->fetch.start = c->fetch.end = c->eip;
2510 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2513 case X86EMUL_MODE_REAL:
2514 case X86EMUL_MODE_VM86:
2515 case X86EMUL_MODE_PROT16:
2516 def_op_bytes = def_ad_bytes = 2;
2518 case X86EMUL_MODE_PROT32:
2519 def_op_bytes = def_ad_bytes = 4;
2521 #ifdef CONFIG_X86_64
2522 case X86EMUL_MODE_PROT64:
2531 c->op_bytes = def_op_bytes;
2532 c->ad_bytes = def_ad_bytes;
2534 /* Legacy prefixes. */
2536 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2537 case 0x66: /* operand-size override */
2538 /* switch between 2/4 bytes */
2539 c->op_bytes = def_op_bytes ^ 6;
2541 case 0x67: /* address-size override */
2542 if (mode == X86EMUL_MODE_PROT64)
2543 /* switch between 4/8 bytes */
2544 c->ad_bytes = def_ad_bytes ^ 12;
2546 /* switch between 2/4 bytes */
2547 c->ad_bytes = def_ad_bytes ^ 6;
2549 case 0x26: /* ES override */
2550 case 0x2e: /* CS override */
2551 case 0x36: /* SS override */
2552 case 0x3e: /* DS override */
2553 set_seg_override(c, (c->b >> 3) & 3);
2555 case 0x64: /* FS override */
2556 case 0x65: /* GS override */
2557 set_seg_override(c, c->b & 7);
2559 case 0x40 ... 0x4f: /* REX */
2560 if (mode != X86EMUL_MODE_PROT64)
2562 c->rex_prefix = c->b;
2564 case 0xf0: /* LOCK */
2567 case 0xf2: /* REPNE/REPNZ */
2568 c->rep_prefix = REPNE_PREFIX;
2570 case 0xf3: /* REP/REPE/REPZ */
2571 c->rep_prefix = REPE_PREFIX;
2577 /* Any legacy prefix after a REX prefix nullifies its effect. */
2585 if (c->rex_prefix & 8)
2586 c->op_bytes = 8; /* REX.W */
2588 /* Opcode byte(s). */
2589 opcode = opcode_table[c->b];
2590 /* Two-byte opcode? */
2593 c->b = insn_fetch(u8, 1, c->eip);
2594 opcode = twobyte_table[c->b];
2596 c->d = opcode.flags;
2599 dual = c->d & GroupDual;
2600 c->modrm = insn_fetch(u8, 1, c->eip);
2603 if (c->d & GroupDual) {
2604 g_mod012 = opcode.u.gdual->mod012;
2605 g_mod3 = opcode.u.gdual->mod3;
2607 g_mod012 = g_mod3 = opcode.u.group;
2609 c->d &= ~(Group | GroupDual);
2611 goffset = (c->modrm >> 3) & 7;
2613 if ((c->modrm >> 6) == 3)
2614 opcode = g_mod3[goffset];
2616 opcode = g_mod012[goffset];
2617 c->d |= opcode.flags;
2620 c->execute = opcode.u.execute;
2623 if (c->d == 0 || (c->d & Undefined)) {
2624 DPRINTF("Cannot emulate %02x\n", c->b);
2628 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2631 if (c->d & Op3264) {
2632 if (mode == X86EMUL_MODE_PROT64)
2638 /* ModRM and SIB bytes. */
2640 rc = decode_modrm(ctxt, ops, &memop);
2641 if (!c->has_seg_override)
2642 set_seg_override(c, c->modrm_seg);
2643 } else if (c->d & MemAbs)
2644 rc = decode_abs(ctxt, ops, &memop);
2645 if (rc != X86EMUL_CONTINUE)
2648 if (!c->has_seg_override)
2649 set_seg_override(c, VCPU_SREG_DS);
2651 if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d))
2652 memop.addr.mem += seg_override_base(ctxt, ops, c);
2654 if (memop.type == OP_MEM && c->ad_bytes != 8)
2655 memop.addr.mem = (u32)memop.addr.mem;
2657 if (memop.type == OP_MEM && c->rip_relative)
2658 memop.addr.mem += c->eip;
2661 * Decode and fetch the source operand: register, memory
2664 switch (c->d & SrcMask) {
2668 decode_register_operand(&c->src, c, 0);
2677 memop.bytes = (c->d & ByteOp) ? 1 :
2687 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2688 if (c->src.bytes == 8)
2691 c->src.type = OP_IMM;
2692 c->src.addr.mem = c->eip;
2693 /* NB. Immediates are sign-extended as necessary. */
2694 switch (c->src.bytes) {
2696 c->src.val = insn_fetch(s8, 1, c->eip);
2699 c->src.val = insn_fetch(s16, 2, c->eip);
2702 c->src.val = insn_fetch(s32, 4, c->eip);
2705 if ((c->d & SrcMask) == SrcImmU
2706 || (c->d & SrcMask) == SrcImmU16) {
2707 switch (c->src.bytes) {
2712 c->src.val &= 0xffff;
2715 c->src.val &= 0xffffffff;
2722 c->src.type = OP_IMM;
2723 c->src.addr.mem = c->eip;
2725 if ((c->d & SrcMask) == SrcImmByte)
2726 c->src.val = insn_fetch(s8, 1, c->eip);
2728 c->src.val = insn_fetch(u8, 1, c->eip);
2731 c->src.type = OP_REG;
2732 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2733 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
2734 fetch_register_operand(&c->src);
2741 c->src.type = OP_MEM;
2742 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2744 register_address(c, seg_override_base(ctxt, ops, c),
2745 c->regs[VCPU_REGS_RSI]);
2749 c->src.type = OP_IMM;
2750 c->src.addr.mem = c->eip;
2751 c->src.bytes = c->op_bytes + 2;
2752 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2755 memop.bytes = c->op_bytes + 2;
2761 * Decode and fetch the second source operand: register, memory
2764 switch (c->d & Src2Mask) {
2769 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2772 c->src2.type = OP_IMM;
2773 c->src2.addr.mem = c->eip;
2775 c->src2.val = insn_fetch(u8, 1, c->eip);
2783 /* Decode and fetch the destination operand: register or memory. */
2784 switch (c->d & DstMask) {
2786 decode_register_operand(&c->dst, c,
2787 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2790 c->dst.type = OP_IMM;
2791 c->dst.addr.mem = c->eip;
2793 c->dst.val = insn_fetch(u8, 1, c->eip);
2798 if ((c->d & DstMask) == DstMem64)
2801 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2803 fetch_bit_operand(c);
2804 c->dst.orig_val = c->dst.val;
2807 c->dst.type = OP_REG;
2808 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2809 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
2810 fetch_register_operand(&c->dst);
2811 c->dst.orig_val = c->dst.val;
2814 c->dst.type = OP_MEM;
2815 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2817 register_address(c, es_base(ctxt, ops),
2818 c->regs[VCPU_REGS_RDI]);
2822 /* Special instructions do their own operand decoding. */
2824 c->dst.type = OP_NONE; /* Disable writeback. */
2829 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2833 x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
2835 struct x86_emulate_ops *ops = ctxt->ops;
2837 struct decode_cache *c = &ctxt->decode;
2838 int rc = X86EMUL_CONTINUE;
2839 int saved_dst_type = c->dst.type;
2840 int irq; /* Used for int 3, int, and into */
2842 ctxt->decode.mem_read.pos = 0;
2844 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2849 /* LOCK prefix is allowed only with some instructions */
2850 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
2855 /* Privileged instruction can be executed only in CPL=0 */
2856 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
2857 emulate_gp(ctxt, 0);
2861 if (c->rep_prefix && (c->d & String)) {
2862 ctxt->restart = true;
2863 /* All REP prefixes have the same first termination condition */
2864 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
2865 ctxt->restart = false;
2871 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
2872 rc = read_emulated(ctxt, ops, c->src.addr.mem,
2873 c->src.valptr, c->src.bytes);
2874 if (rc != X86EMUL_CONTINUE)
2876 c->src.orig_val64 = c->src.val64;
2879 if (c->src2.type == OP_MEM) {
2880 rc = read_emulated(ctxt, ops, c->src2.addr.mem,
2881 &c->src2.val, c->src2.bytes);
2882 if (rc != X86EMUL_CONTINUE)
2886 if ((c->d & DstMask) == ImplicitOps)
2890 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2891 /* optimisation - avoid slow emulated read if Mov */
2892 rc = read_emulated(ctxt, ops, c->dst.addr.mem,
2893 &c->dst.val, c->dst.bytes);
2894 if (rc != X86EMUL_CONTINUE)
2897 c->dst.orig_val = c->dst.val;
2902 rc = c->execute(ctxt);
2903 if (rc != X86EMUL_CONTINUE)
2914 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2916 case 0x06: /* push es */
2917 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
2919 case 0x07: /* pop es */
2920 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
2921 if (rc != X86EMUL_CONTINUE)
2926 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2928 case 0x0e: /* push cs */
2929 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
2933 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2935 case 0x16: /* push ss */
2936 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
2938 case 0x17: /* pop ss */
2939 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
2940 if (rc != X86EMUL_CONTINUE)
2945 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2947 case 0x1e: /* push ds */
2948 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
2950 case 0x1f: /* pop ds */
2951 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
2952 if (rc != X86EMUL_CONTINUE)
2957 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2961 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2965 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2969 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2971 case 0x40 ... 0x47: /* inc r16/r32 */
2972 emulate_1op("inc", c->dst, ctxt->eflags);
2974 case 0x48 ... 0x4f: /* dec r16/r32 */
2975 emulate_1op("dec", c->dst, ctxt->eflags);
2977 case 0x58 ... 0x5f: /* pop reg */
2979 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
2980 if (rc != X86EMUL_CONTINUE)
2983 case 0x60: /* pusha */
2984 rc = emulate_pusha(ctxt, ops);
2985 if (rc != X86EMUL_CONTINUE)
2988 case 0x61: /* popa */
2989 rc = emulate_popa(ctxt, ops);
2990 if (rc != X86EMUL_CONTINUE)
2993 case 0x63: /* movsxd */
2994 if (ctxt->mode != X86EMUL_MODE_PROT64)
2995 goto cannot_emulate;
2996 c->dst.val = (s32) c->src.val;
2998 case 0x6c: /* insb */
2999 case 0x6d: /* insw/insd */
3000 c->src.val = c->regs[VCPU_REGS_RDX];
3002 case 0x6e: /* outsb */
3003 case 0x6f: /* outsw/outsd */
3004 c->dst.val = c->regs[VCPU_REGS_RDX];
3007 case 0x70 ... 0x7f: /* jcc (short) */
3008 if (test_cc(c->b, ctxt->eflags))
3009 jmp_rel(c, c->src.val);
3011 case 0x80 ... 0x83: /* Grp1 */
3012 switch (c->modrm_reg) {
3033 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
3035 case 0x86 ... 0x87: /* xchg */
3037 /* Write back the register source. */
3038 c->src.val = c->dst.val;
3039 write_register_operand(&c->src);
3041 * Write back the memory destination with implicit LOCK
3044 c->dst.val = c->src.orig_val;
3047 case 0x88 ... 0x8b: /* mov */
3049 case 0x8c: /* mov r/m, sreg */
3050 if (c->modrm_reg > VCPU_SREG_GS) {
3054 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
3056 case 0x8d: /* lea r16/r32, m */
3057 c->dst.val = c->src.addr.mem;
3059 case 0x8e: { /* mov seg, r/m16 */
3064 if (c->modrm_reg == VCPU_SREG_CS ||
3065 c->modrm_reg > VCPU_SREG_GS) {
3070 if (c->modrm_reg == VCPU_SREG_SS)
3071 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3073 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3075 c->dst.type = OP_NONE; /* Disable writeback. */
3078 case 0x8f: /* pop (sole member of Grp1a) */
3079 rc = emulate_grp1a(ctxt, ops);
3080 if (rc != X86EMUL_CONTINUE)
3083 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3084 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3087 case 0x98: /* cbw/cwde/cdqe */
3088 switch (c->op_bytes) {
3089 case 2: c->dst.val = (s8)c->dst.val; break;
3090 case 4: c->dst.val = (s16)c->dst.val; break;
3091 case 8: c->dst.val = (s32)c->dst.val; break;
3094 case 0x9c: /* pushf */
3095 c->src.val = (unsigned long) ctxt->eflags;
3096 emulate_push(ctxt, ops);
3098 case 0x9d: /* popf */
3099 c->dst.type = OP_REG;
3100 c->dst.addr.reg = &ctxt->eflags;
3101 c->dst.bytes = c->op_bytes;
3102 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
3103 if (rc != X86EMUL_CONTINUE)
3106 case 0xa0 ... 0xa3: /* mov */
3107 case 0xa4 ... 0xa5: /* movs */
3109 case 0xa6 ... 0xa7: /* cmps */
3110 c->dst.type = OP_NONE; /* Disable writeback. */
3111 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem);
3113 case 0xa8 ... 0xa9: /* test ax, imm */
3115 case 0xaa ... 0xab: /* stos */
3116 case 0xac ... 0xad: /* lods */
3118 case 0xae ... 0xaf: /* scas */
3120 case 0xb0 ... 0xbf: /* mov r, imm */
3125 case 0xc3: /* ret */
3126 c->dst.type = OP_REG;
3127 c->dst.addr.reg = &c->eip;
3128 c->dst.bytes = c->op_bytes;
3129 goto pop_instruction;
3130 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
3132 c->dst.val = c->src.val;
3134 case 0xcb: /* ret far */
3135 rc = emulate_ret_far(ctxt, ops);
3136 if (rc != X86EMUL_CONTINUE)
3139 case 0xcc: /* int3 */
3142 case 0xcd: /* int n */
3145 rc = emulate_int(ctxt, ops, irq);
3146 if (rc != X86EMUL_CONTINUE)
3149 case 0xce: /* into */
3150 if (ctxt->eflags & EFLG_OF) {
3155 case 0xcf: /* iret */
3156 rc = emulate_iret(ctxt, ops);
3158 if (rc != X86EMUL_CONTINUE)
3161 case 0xd0 ... 0xd1: /* Grp2 */
3164 case 0xd2 ... 0xd3: /* Grp2 */
3165 c->src.val = c->regs[VCPU_REGS_RCX];
3168 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3169 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3170 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3171 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3172 jmp_rel(c, c->src.val);
3174 case 0xe4: /* inb */
3177 case 0xe6: /* outb */
3178 case 0xe7: /* out */
3180 case 0xe8: /* call (near) */ {
3181 long int rel = c->src.val;
3182 c->src.val = (unsigned long) c->eip;
3184 emulate_push(ctxt, ops);
3187 case 0xe9: /* jmp rel */
3189 case 0xea: { /* jmp far */
3192 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3194 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3198 memcpy(&c->eip, c->src.valptr, c->op_bytes);
3202 jmp: /* jmp rel short */
3203 jmp_rel(c, c->src.val);
3204 c->dst.type = OP_NONE; /* Disable writeback. */
3206 case 0xec: /* in al,dx */
3207 case 0xed: /* in (e/r)ax,dx */
3208 c->src.val = c->regs[VCPU_REGS_RDX];
3210 c->dst.bytes = min(c->dst.bytes, 4u);
3211 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
3212 emulate_gp(ctxt, 0);
3215 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3217 goto done; /* IO is needed */
3219 case 0xee: /* out dx,al */
3220 case 0xef: /* out dx,(e/r)ax */
3221 c->dst.val = c->regs[VCPU_REGS_RDX];
3223 c->src.bytes = min(c->src.bytes, 4u);
3224 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3226 emulate_gp(ctxt, 0);
3229 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3230 &c->src.val, 1, ctxt->vcpu);
3231 c->dst.type = OP_NONE; /* Disable writeback. */
3233 case 0xf4: /* hlt */
3234 ctxt->vcpu->arch.halt_request = 1;
3236 case 0xf5: /* cmc */
3237 /* complement carry flag from eflags reg */
3238 ctxt->eflags ^= EFLG_CF;
3240 case 0xf6 ... 0xf7: /* Grp3 */
3241 if (emulate_grp3(ctxt, ops) != X86EMUL_CONTINUE)
3242 goto cannot_emulate;
3244 case 0xf8: /* clc */
3245 ctxt->eflags &= ~EFLG_CF;
3247 case 0xf9: /* stc */
3248 ctxt->eflags |= EFLG_CF;
3250 case 0xfa: /* cli */
3251 if (emulator_bad_iopl(ctxt, ops)) {
3252 emulate_gp(ctxt, 0);
3255 ctxt->eflags &= ~X86_EFLAGS_IF;
3257 case 0xfb: /* sti */
3258 if (emulator_bad_iopl(ctxt, ops)) {
3259 emulate_gp(ctxt, 0);
3262 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3263 ctxt->eflags |= X86_EFLAGS_IF;
3266 case 0xfc: /* cld */
3267 ctxt->eflags &= ~EFLG_DF;
3269 case 0xfd: /* std */
3270 ctxt->eflags |= EFLG_DF;
3272 case 0xfe: /* Grp4 */
3274 rc = emulate_grp45(ctxt, ops);
3275 if (rc != X86EMUL_CONTINUE)
3278 case 0xff: /* Grp5 */
3279 if (c->modrm_reg == 5)
3283 goto cannot_emulate;
3287 rc = writeback(ctxt, ops);
3288 if (rc != X86EMUL_CONTINUE)
3292 * restore dst type in case the decoding will be reused
3293 * (happens for string instruction )
3295 c->dst.type = saved_dst_type;
3297 if ((c->d & SrcMask) == SrcSI)
3298 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3299 VCPU_REGS_RSI, &c->src);
3301 if ((c->d & DstMask) == DstDI)
3302 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3305 if (c->rep_prefix && (c->d & String)) {
3306 struct read_cache *rc = &ctxt->decode.io_read;
3307 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3308 /* The second termination condition only applies for REPE
3309 * and REPNE. Test if the repeat string operation prefix is
3310 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3311 * corresponding termination condition according to:
3312 * - if REPE/REPZ and ZF = 0 then done
3313 * - if REPNE/REPNZ and ZF = 1 then done
3315 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3316 (c->b == 0xae) || (c->b == 0xaf))
3317 && (((c->rep_prefix == REPE_PREFIX) &&
3318 ((ctxt->eflags & EFLG_ZF) == 0))
3319 || ((c->rep_prefix == REPNE_PREFIX) &&
3320 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3321 ctxt->restart = false;
3323 * Re-enter guest when pio read ahead buffer is empty or,
3324 * if it is not used, after each 1024 iteration.
3326 else if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3327 (rc->end != 0 && rc->end == rc->pos)) {
3328 ctxt->restart = false;
3333 * reset read cache here in case string instruction is restared
3336 ctxt->decode.mem_read.end = 0;
3341 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
3345 case 0x01: /* lgdt, lidt, lmsw */
3346 switch (c->modrm_reg) {
3348 unsigned long address;
3350 case 0: /* vmcall */
3351 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3352 goto cannot_emulate;
3354 rc = kvm_fix_hypercall(ctxt->vcpu);
3355 if (rc != X86EMUL_CONTINUE)
3358 /* Let the processor re-execute the fixed hypercall */
3360 /* Disable writeback. */
3361 c->dst.type = OP_NONE;
3364 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3365 &size, &address, c->op_bytes);
3366 if (rc != X86EMUL_CONTINUE)
3368 realmode_lgdt(ctxt->vcpu, size, address);
3369 /* Disable writeback. */
3370 c->dst.type = OP_NONE;
3372 case 3: /* lidt/vmmcall */
3373 if (c->modrm_mod == 3) {
3374 switch (c->modrm_rm) {
3376 rc = kvm_fix_hypercall(ctxt->vcpu);
3377 if (rc != X86EMUL_CONTINUE)
3381 goto cannot_emulate;
3384 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3387 if (rc != X86EMUL_CONTINUE)
3389 realmode_lidt(ctxt->vcpu, size, address);
3391 /* Disable writeback. */
3392 c->dst.type = OP_NONE;
3396 c->dst.val = ops->get_cr(0, ctxt->vcpu);
3399 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
3400 (c->src.val & 0x0f), ctxt->vcpu);
3401 c->dst.type = OP_NONE;
3403 case 5: /* not defined */
3407 emulate_invlpg(ctxt->vcpu, c->src.addr.mem);
3408 /* Disable writeback. */
3409 c->dst.type = OP_NONE;
3412 goto cannot_emulate;
3415 case 0x05: /* syscall */
3416 rc = emulate_syscall(ctxt, ops);
3417 if (rc != X86EMUL_CONTINUE)
3423 emulate_clts(ctxt->vcpu);
3425 case 0x09: /* wbinvd */
3426 kvm_emulate_wbinvd(ctxt->vcpu);
3428 case 0x08: /* invd */
3429 case 0x0d: /* GrpP (prefetch) */
3430 case 0x18: /* Grp16 (prefetch/nop) */
3432 case 0x20: /* mov cr, reg */
3433 switch (c->modrm_reg) {
3440 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
3442 case 0x21: /* mov from dr to reg */
3443 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3444 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3448 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
3450 case 0x22: /* mov reg, cr */
3451 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
3452 emulate_gp(ctxt, 0);
3455 c->dst.type = OP_NONE;
3457 case 0x23: /* mov from reg to dr */
3458 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3459 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3464 if (ops->set_dr(c->modrm_reg, c->src.val &
3465 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3466 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3467 /* #UD condition is already handled by the code above */
3468 emulate_gp(ctxt, 0);
3472 c->dst.type = OP_NONE; /* no writeback */
3476 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3477 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3478 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
3479 emulate_gp(ctxt, 0);
3482 rc = X86EMUL_CONTINUE;
3486 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
3487 emulate_gp(ctxt, 0);
3490 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3491 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3493 rc = X86EMUL_CONTINUE;
3495 case 0x34: /* sysenter */
3496 rc = emulate_sysenter(ctxt, ops);
3497 if (rc != X86EMUL_CONTINUE)
3502 case 0x35: /* sysexit */
3503 rc = emulate_sysexit(ctxt, ops);
3504 if (rc != X86EMUL_CONTINUE)
3509 case 0x40 ... 0x4f: /* cmov */
3510 c->dst.val = c->dst.orig_val = c->src.val;
3511 if (!test_cc(c->b, ctxt->eflags))
3512 c->dst.type = OP_NONE; /* no writeback */
3514 case 0x80 ... 0x8f: /* jnz rel, etc*/
3515 if (test_cc(c->b, ctxt->eflags))
3516 jmp_rel(c, c->src.val);
3518 case 0x90 ... 0x9f: /* setcc r/m8 */
3519 c->dst.val = test_cc(c->b, ctxt->eflags);
3521 case 0xa0: /* push fs */
3522 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
3524 case 0xa1: /* pop fs */
3525 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
3526 if (rc != X86EMUL_CONTINUE)
3531 c->dst.type = OP_NONE;
3532 /* only subword offset */
3533 c->src.val &= (c->dst.bytes << 3) - 1;
3534 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
3536 case 0xa4: /* shld imm8, r, r/m */
3537 case 0xa5: /* shld cl, r, r/m */
3538 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3540 case 0xa8: /* push gs */
3541 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
3543 case 0xa9: /* pop gs */
3544 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
3545 if (rc != X86EMUL_CONTINUE)
3550 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
3552 case 0xac: /* shrd imm8, r, r/m */
3553 case 0xad: /* shrd cl, r, r/m */
3554 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3556 case 0xae: /* clflush */
3558 case 0xb0 ... 0xb1: /* cmpxchg */
3560 * Save real source value, then compare EAX against
3563 c->src.orig_val = c->src.val;
3564 c->src.val = c->regs[VCPU_REGS_RAX];
3565 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3566 if (ctxt->eflags & EFLG_ZF) {
3567 /* Success: write back to memory. */
3568 c->dst.val = c->src.orig_val;
3570 /* Failure: write the value we saw to EAX. */
3571 c->dst.type = OP_REG;
3572 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
3577 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
3579 case 0xb6 ... 0xb7: /* movzx */
3580 c->dst.bytes = c->op_bytes;
3581 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3584 case 0xba: /* Grp8 */
3585 switch (c->modrm_reg & 3) {
3598 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
3600 case 0xbc: { /* bsf */
3602 __asm__ ("bsf %2, %0; setz %1"
3603 : "=r"(c->dst.val), "=q"(zf)
3605 ctxt->eflags &= ~X86_EFLAGS_ZF;
3607 ctxt->eflags |= X86_EFLAGS_ZF;
3608 c->dst.type = OP_NONE; /* Disable writeback. */
3612 case 0xbd: { /* bsr */
3614 __asm__ ("bsr %2, %0; setz %1"
3615 : "=r"(c->dst.val), "=q"(zf)
3617 ctxt->eflags &= ~X86_EFLAGS_ZF;
3619 ctxt->eflags |= X86_EFLAGS_ZF;
3620 c->dst.type = OP_NONE; /* Disable writeback. */
3624 case 0xbe ... 0xbf: /* movsx */
3625 c->dst.bytes = c->op_bytes;
3626 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3629 case 0xc0 ... 0xc1: /* xadd */
3630 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3631 /* Write back the register source. */
3632 c->src.val = c->dst.orig_val;
3633 write_register_operand(&c->src);
3635 case 0xc3: /* movnti */
3636 c->dst.bytes = c->op_bytes;
3637 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3640 case 0xc7: /* Grp9 (cmpxchg8b) */
3641 rc = emulate_grp9(ctxt, ops);
3642 if (rc != X86EMUL_CONTINUE)
3646 goto cannot_emulate;
3651 DPRINTF("Cannot emulate %02x\n", c->b);