1 #include <linux/kernel.h>
2 #include <linux/sched.h>
3 #include <linux/init.h>
4 #include <linux/module.h>
5 #include <linux/timer.h>
6 #include <linux/acpi_pmtmr.h>
7 #include <linux/cpufreq.h>
9 #include <linux/delay.h>
10 #include <linux/clocksource.h>
11 #include <linux/percpu.h>
12 #include <linux/timex.h>
15 #include <asm/timer.h>
16 #include <asm/vgtod.h>
18 #include <asm/delay.h>
19 #include <asm/hypervisor.h>
21 #include <asm/x86_init.h>
23 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
24 EXPORT_SYMBOL(cpu_khz);
26 unsigned int __read_mostly tsc_khz;
27 EXPORT_SYMBOL(tsc_khz);
30 * TSC can be unstable due to cpufreq or due to unsynced TSCs
32 static int __read_mostly tsc_unstable;
34 /* native_sched_clock() is called before tsc_init(), so
35 we must start with the TSC soft disabled to prevent
36 erroneous rdtsc usage on !cpu_has_tsc processors */
37 static int __read_mostly tsc_disabled = -1;
39 static int tsc_clocksource_reliable;
41 * Scheduler clock - returns current time in nanosec units.
43 u64 native_sched_clock(void)
48 * Fall back to jiffies if there's no TSC available:
49 * ( But note that we still use it if the TSC is marked
50 * unstable. We do this because unlike Time Of Day,
51 * the scheduler clock tolerates small errors and it's
52 * very important for it to be as fast as the platform
55 if (unlikely(tsc_disabled)) {
56 /* No locking but a rare wrong value is not a big deal: */
57 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
60 /* read the Time Stamp Counter: */
63 /* return the value in ns */
64 return __cycles_2_ns(this_offset);
67 /* We need to define a real function for sched_clock, to override the
68 weak default version */
69 #ifdef CONFIG_PARAVIRT
70 unsigned long long sched_clock(void)
72 return paravirt_sched_clock();
76 sched_clock(void) __attribute__((alias("native_sched_clock")));
79 int check_tsc_unstable(void)
83 EXPORT_SYMBOL_GPL(check_tsc_unstable);
86 int __init notsc_setup(char *str)
88 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
89 "cannot disable TSC completely.\n");
95 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
98 int __init notsc_setup(char *str)
100 setup_clear_cpu_cap(X86_FEATURE_TSC);
105 __setup("notsc", notsc_setup);
107 static int no_sched_irq_time;
109 static int __init tsc_setup(char *str)
111 if (!strcmp(str, "reliable"))
112 tsc_clocksource_reliable = 1;
113 if (!strncmp(str, "noirqtime", 9))
114 no_sched_irq_time = 1;
118 __setup("tsc=", tsc_setup);
120 #define MAX_RETRIES 5
121 #define SMI_TRESHOLD 50000
124 * Read TSC and the reference counters. Take care of SMI disturbance
126 static u64 tsc_read_refs(u64 *p, int hpet)
131 for (i = 0; i < MAX_RETRIES; i++) {
134 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
136 *p = acpi_pm_read_early();
138 if ((t2 - t1) < SMI_TRESHOLD)
145 * Calculate the TSC frequency from HPET reference
147 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
152 hpet2 += 0x100000000ULL;
154 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
155 do_div(tmp, 1000000);
156 do_div(deltatsc, tmp);
158 return (unsigned long) deltatsc;
162 * Calculate the TSC frequency from PMTimer reference
164 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
172 pm2 += (u64)ACPI_PM_OVRRUN;
174 tmp = pm2 * 1000000000LL;
175 do_div(tmp, PMTMR_TICKS_PER_SEC);
176 do_div(deltatsc, tmp);
178 return (unsigned long) deltatsc;
182 #define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS))
183 #define CAL_PIT_LOOPS 1000
186 #define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS))
187 #define CAL2_PIT_LOOPS 5000
191 * Try to calibrate the TSC against the Programmable
192 * Interrupt Timer and return the frequency of the TSC
195 * Return ULONG_MAX on failure to calibrate.
197 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
199 u64 tsc, t1, t2, delta;
200 unsigned long tscmin, tscmax;
203 /* Set the Gate high, disable speaker */
204 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
207 * Setup CTC channel 2* for mode 0, (interrupt on terminal
208 * count mode), binary count. Set the latch register to 50ms
209 * (LSB then MSB) to begin countdown.
212 outb(latch & 0xff, 0x42);
213 outb(latch >> 8, 0x42);
215 tsc = t1 = t2 = get_cycles();
220 while ((inb(0x61) & 0x20) == 0) {
224 if ((unsigned long) delta < tscmin)
225 tscmin = (unsigned int) delta;
226 if ((unsigned long) delta > tscmax)
227 tscmax = (unsigned int) delta;
234 * If we were not able to read the PIT more than loopmin
235 * times, then we have been hit by a massive SMI
237 * If the maximum is 10 times larger than the minimum,
238 * then we got hit by an SMI as well.
240 if (pitcnt < loopmin || tscmax > 10 * tscmin)
243 /* Calculate the PIT value */
250 * This reads the current MSB of the PIT counter, and
251 * checks if we are running on sufficiently fast and
252 * non-virtualized hardware.
254 * Our expectations are:
256 * - the PIT is running at roughly 1.19MHz
258 * - each IO is going to take about 1us on real hardware,
259 * but we allow it to be much faster (by a factor of 10) or
260 * _slightly_ slower (ie we allow up to a 2us read+counter
261 * update - anything else implies a unacceptably slow CPU
262 * or PIT for the fast calibration to work.
264 * - with 256 PIT ticks to read the value, we have 214us to
265 * see the same MSB (and overhead like doing a single TSC
266 * read per MSB value etc).
268 * - We're doing 2 reads per loop (LSB, MSB), and we expect
269 * them each to take about a microsecond on real hardware.
270 * So we expect a count value of around 100. But we'll be
271 * generous, and accept anything over 50.
273 * - if the PIT is stuck, and we see *many* more reads, we
274 * return early (and the next caller of pit_expect_msb()
275 * then consider it a failure when they don't see the
276 * next expected value).
278 * These expectations mean that we know that we have seen the
279 * transition from one expected value to another with a fairly
280 * high accuracy, and we didn't miss any events. We can thus
281 * use the TSC value at the transitions to calculate a pretty
282 * good value for the TSC frequencty.
284 static inline int pit_verify_msb(unsigned char val)
288 return inb(0x42) == val;
291 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
296 for (count = 0; count < 50000; count++) {
297 if (!pit_verify_msb(val))
301 *deltap = get_cycles() - tsc;
305 * We require _some_ success, but the quality control
306 * will be based on the error terms on the TSC values.
312 * How many MSB values do we want to see? We aim for
313 * a maximum error rate of 500ppm (in practice the
314 * real error is much smaller), but refuse to spend
315 * more than 25ms on it.
317 #define MAX_QUICK_PIT_MS 25
318 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
320 static unsigned long quick_pit_calibrate(void)
324 unsigned long d1, d2;
326 /* Set the Gate high, disable speaker */
327 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
330 * Counter 2, mode 0 (one-shot), binary count
332 * NOTE! Mode 2 decrements by two (and then the
333 * output is flipped each time, giving the same
334 * final output frequency as a decrement-by-one),
335 * so mode 0 is much better when looking at the
340 /* Start at 0xffff */
345 * The PIT starts counting at the next edge, so we
346 * need to delay for a microsecond. The easiest way
347 * to do that is to just read back the 16-bit counter
352 if (pit_expect_msb(0xff, &tsc, &d1)) {
353 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
354 if (!pit_expect_msb(0xff-i, &delta, &d2))
358 * Iterate until the error is less than 500 ppm
361 if (d1+d2 >= delta >> 11)
365 * Check the PIT one more time to verify that
366 * all TSC reads were stable wrt the PIT.
368 * This also guarantees serialization of the
369 * last cycle read ('d2') in pit_expect_msb.
371 if (!pit_verify_msb(0xfe - i))
376 printk("Fast TSC calibration failed\n");
381 * Ok, if we get here, then we've seen the
382 * MSB of the PIT decrement 'i' times, and the
383 * error has shrunk to less than 500 ppm.
385 * As a result, we can depend on there not being
386 * any odd delays anywhere, and the TSC reads are
387 * reliable (within the error). We also adjust the
388 * delta to the middle of the error bars, just
389 * because it looks nicer.
391 * kHz = ticks / time-in-seconds / 1000;
392 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
393 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
395 delta += (long)(d2 - d1)/2;
396 delta *= PIT_TICK_RATE;
397 do_div(delta, i*256*1000);
398 printk("Fast TSC calibration using PIT\n");
403 * native_calibrate_tsc - calibrate the tsc on boot
405 unsigned long native_calibrate_tsc(void)
407 u64 tsc1, tsc2, delta, ref1, ref2;
408 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
409 unsigned long flags, latch, ms, fast_calibrate;
410 int hpet = is_hpet_enabled(), i, loopmin;
412 local_irq_save(flags);
413 fast_calibrate = quick_pit_calibrate();
414 local_irq_restore(flags);
416 return fast_calibrate;
419 * Run 5 calibration loops to get the lowest frequency value
420 * (the best estimate). We use two different calibration modes
423 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
424 * load a timeout of 50ms. We read the time right after we
425 * started the timer and wait until the PIT count down reaches
426 * zero. In each wait loop iteration we read the TSC and check
427 * the delta to the previous read. We keep track of the min
428 * and max values of that delta. The delta is mostly defined
429 * by the IO time of the PIT access, so we can detect when a
430 * SMI/SMM disturbance happend between the two reads. If the
431 * maximum time is significantly larger than the minimum time,
432 * then we discard the result and have another try.
434 * 2) Reference counter. If available we use the HPET or the
435 * PMTIMER as a reference to check the sanity of that value.
436 * We use separate TSC readouts and check inside of the
437 * reference read for a SMI/SMM disturbance. We dicard
438 * disturbed values here as well. We do that around the PIT
439 * calibration delay loop as we have to wait for a certain
440 * amount of time anyway.
443 /* Preset PIT loop values */
446 loopmin = CAL_PIT_LOOPS;
448 for (i = 0; i < 3; i++) {
449 unsigned long tsc_pit_khz;
452 * Read the start value and the reference count of
453 * hpet/pmtimer when available. Then do the PIT
454 * calibration, which will take at least 50ms, and
455 * read the end value.
457 local_irq_save(flags);
458 tsc1 = tsc_read_refs(&ref1, hpet);
459 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
460 tsc2 = tsc_read_refs(&ref2, hpet);
461 local_irq_restore(flags);
463 /* Pick the lowest PIT TSC calibration so far */
464 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
466 /* hpet or pmtimer available ? */
470 /* Check, whether the sampling was disturbed by an SMI */
471 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
474 tsc2 = (tsc2 - tsc1) * 1000000LL;
476 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
478 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
480 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
482 /* Check the reference deviation */
483 delta = ((u64) tsc_pit_min) * 100;
484 do_div(delta, tsc_ref_min);
487 * If both calibration results are inside a 10% window
488 * then we can be sure, that the calibration
489 * succeeded. We break out of the loop right away. We
490 * use the reference value, as it is more precise.
492 if (delta >= 90 && delta <= 110) {
494 "TSC: PIT calibration matches %s. %d loops\n",
495 hpet ? "HPET" : "PMTIMER", i + 1);
500 * Check whether PIT failed more than once. This
501 * happens in virtualized environments. We need to
502 * give the virtual PC a slightly longer timeframe for
503 * the HPET/PMTIMER to make the result precise.
505 if (i == 1 && tsc_pit_min == ULONG_MAX) {
508 loopmin = CAL2_PIT_LOOPS;
513 * Now check the results.
515 if (tsc_pit_min == ULONG_MAX) {
516 /* PIT gave no useful value */
517 printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
519 /* We don't have an alternative source, disable TSC */
520 if (!hpet && !ref1 && !ref2) {
521 printk("TSC: No reference (HPET/PMTIMER) available\n");
525 /* The alternative source failed as well, disable TSC */
526 if (tsc_ref_min == ULONG_MAX) {
527 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
532 /* Use the alternative source */
533 printk(KERN_INFO "TSC: using %s reference calibration\n",
534 hpet ? "HPET" : "PMTIMER");
539 /* We don't have an alternative source, use the PIT calibration value */
540 if (!hpet && !ref1 && !ref2) {
541 printk(KERN_INFO "TSC: Using PIT calibration value\n");
545 /* The alternative source failed, use the PIT calibration value */
546 if (tsc_ref_min == ULONG_MAX) {
547 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
548 "Using PIT calibration\n");
553 * The calibration values differ too much. In doubt, we use
554 * the PIT value as we know that there are PMTIMERs around
555 * running at double speed. At least we let the user know:
557 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
558 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
559 printk(KERN_INFO "TSC: Using PIT calibration value\n");
563 int recalibrate_cpu_khz(void)
566 unsigned long cpu_khz_old = cpu_khz;
569 tsc_khz = x86_platform.calibrate_tsc();
571 cpu_data(0).loops_per_jiffy =
572 cpufreq_scale(cpu_data(0).loops_per_jiffy,
573 cpu_khz_old, cpu_khz);
582 EXPORT_SYMBOL(recalibrate_cpu_khz);
585 /* Accelerators for sched_clock()
586 * convert from cycles(64bits) => nanoseconds (64bits)
588 * ns = cycles / (freq / ns_per_sec)
589 * ns = cycles * (ns_per_sec / freq)
590 * ns = cycles * (10^9 / (cpu_khz * 10^3))
591 * ns = cycles * (10^6 / cpu_khz)
593 * Then we use scaling math (suggested by george@mvista.com) to get:
594 * ns = cycles * (10^6 * SC / cpu_khz) / SC
595 * ns = cycles * cyc2ns_scale / SC
597 * And since SC is a constant power of two, we can convert the div
600 * We can use khz divisor instead of mhz to keep a better precision, since
601 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
602 * (mathieu.desnoyers@polymtl.ca)
604 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
607 DEFINE_PER_CPU(unsigned long, cyc2ns);
608 DEFINE_PER_CPU(unsigned long long, cyc2ns_offset);
610 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
612 unsigned long long tsc_now, ns_now, *offset;
613 unsigned long flags, *scale;
615 local_irq_save(flags);
616 sched_clock_idle_sleep_event();
618 scale = &per_cpu(cyc2ns, cpu);
619 offset = &per_cpu(cyc2ns_offset, cpu);
622 ns_now = __cycles_2_ns(tsc_now);
625 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
626 *offset = ns_now - (tsc_now * *scale >> CYC2NS_SCALE_FACTOR);
629 sched_clock_idle_wakeup_event(0);
630 local_irq_restore(flags);
633 static unsigned long long cyc2ns_suspend;
635 void save_sched_clock_state(void)
637 if (!sched_clock_stable)
640 cyc2ns_suspend = sched_clock();
644 * Even on processors with invariant TSC, TSC gets reset in some the
645 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
646 * arbitrary value (still sync'd across cpu's) during resume from such sleep
647 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
648 * that sched_clock() continues from the point where it was left off during
651 void restore_sched_clock_state(void)
653 unsigned long long offset;
657 if (!sched_clock_stable)
660 local_irq_save(flags);
662 __this_cpu_write(cyc2ns_offset, 0);
663 offset = cyc2ns_suspend - sched_clock();
665 for_each_possible_cpu(cpu)
666 per_cpu(cyc2ns_offset, cpu) = offset;
668 local_irq_restore(flags);
671 #ifdef CONFIG_CPU_FREQ
673 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
676 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
677 * not that important because current Opteron setups do not support
678 * scaling on SMP anyroads.
680 * Should fix up last_tsc too. Currently gettimeofday in the
681 * first tick after the change will be slightly wrong.
684 static unsigned int ref_freq;
685 static unsigned long loops_per_jiffy_ref;
686 static unsigned long tsc_khz_ref;
688 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
691 struct cpufreq_freqs *freq = data;
694 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
697 lpj = &boot_cpu_data.loops_per_jiffy;
699 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
700 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
704 ref_freq = freq->old;
705 loops_per_jiffy_ref = *lpj;
706 tsc_khz_ref = tsc_khz;
708 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
709 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
710 (val == CPUFREQ_RESUMECHANGE)) {
711 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
713 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
714 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
715 mark_tsc_unstable("cpufreq changes");
718 set_cyc2ns_scale(tsc_khz, freq->cpu);
723 static struct notifier_block time_cpufreq_notifier_block = {
724 .notifier_call = time_cpufreq_notifier
727 static int __init cpufreq_tsc(void)
731 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
733 cpufreq_register_notifier(&time_cpufreq_notifier_block,
734 CPUFREQ_TRANSITION_NOTIFIER);
738 core_initcall(cpufreq_tsc);
740 #endif /* CONFIG_CPU_FREQ */
742 /* clocksource code */
744 static struct clocksource clocksource_tsc;
747 * We compare the TSC to the cycle_last value in the clocksource
748 * structure to avoid a nasty time-warp. This can be observed in a
749 * very small window right after one CPU updated cycle_last under
750 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
751 * is smaller than the cycle_last reference value due to a TSC which
752 * is slighty behind. This delta is nowhere else observable, but in
753 * that case it results in a forward time jump in the range of hours
754 * due to the unsigned delta calculation of the time keeping core
755 * code, which is necessary to support wrapping clocksources like pm
758 static cycle_t read_tsc(struct clocksource *cs)
760 cycle_t ret = (cycle_t)get_cycles();
762 return ret >= clocksource_tsc.cycle_last ?
763 ret : clocksource_tsc.cycle_last;
767 static cycle_t __vsyscall_fn vread_tsc(void)
772 * Surround the RDTSC by barriers, to make sure it's not
773 * speculated to outside the seqlock critical section and
774 * does not cause time warps:
777 ret = (cycle_t)vget_cycles();
780 return ret >= __vsyscall_gtod_data.clock.cycle_last ?
781 ret : __vsyscall_gtod_data.clock.cycle_last;
785 static void resume_tsc(struct clocksource *cs)
787 clocksource_tsc.cycle_last = 0;
790 static struct clocksource clocksource_tsc = {
794 .resume = resume_tsc,
795 .mask = CLOCKSOURCE_MASK(64),
796 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
797 CLOCK_SOURCE_MUST_VERIFY,
803 void mark_tsc_unstable(char *reason)
807 sched_clock_stable = 0;
808 disable_sched_clock_irqtime();
809 printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
810 /* Change only the rating, when not registered */
811 if (clocksource_tsc.mult)
812 clocksource_mark_unstable(&clocksource_tsc);
814 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
815 clocksource_tsc.rating = 0;
820 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
822 static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
824 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
830 /* List of systems that have known TSC problems */
831 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
833 .callback = dmi_mark_tsc_unstable,
834 .ident = "IBM Thinkpad 380XD",
836 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
837 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
843 static void __init check_system_tsc_reliable(void)
845 #ifdef CONFIG_MGEODE_LX
846 /* RTSC counts during suspend */
847 #define RTSC_SUSP 0x100
848 unsigned long res_low, res_high;
850 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
851 /* Geode_LX - the OLPC CPU has a very reliable TSC */
852 if (res_low & RTSC_SUSP)
853 tsc_clocksource_reliable = 1;
855 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
856 tsc_clocksource_reliable = 1;
860 * Make an educated guess if the TSC is trustworthy and synchronized
863 __cpuinit int unsynchronized_tsc(void)
865 if (!cpu_has_tsc || tsc_unstable)
869 if (apic_is_clustered_box())
873 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
876 if (tsc_clocksource_reliable)
879 * Intel systems are normally all synchronized.
880 * Exceptions must mark TSC as unstable:
882 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
883 /* assume multi socket systems are not synchronized: */
884 if (num_possible_cpus() > 1)
892 static void tsc_refine_calibration_work(struct work_struct *work);
893 static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
895 * tsc_refine_calibration_work - Further refine tsc freq calibration
898 * This functions uses delayed work over a period of a
899 * second to further refine the TSC freq value. Since this is
900 * timer based, instead of loop based, we don't block the boot
901 * process while this longer calibration is done.
903 * If there are any calibration anomolies (too many SMIs, etc),
904 * or the refined calibration is off by 1% of the fast early
905 * calibration, we throw out the new calibration and use the
908 static void tsc_refine_calibration_work(struct work_struct *work)
910 static u64 tsc_start = -1, ref_start;
912 u64 tsc_stop, ref_stop, delta;
915 /* Don't bother refining TSC on unstable systems */
916 if (check_tsc_unstable())
920 * Since the work is started early in boot, we may be
921 * delayed the first time we expire. So set the workqueue
922 * again once we know timers are working.
924 if (tsc_start == -1) {
926 * Only set hpet once, to avoid mixing hardware
927 * if the hpet becomes enabled later.
929 hpet = is_hpet_enabled();
930 schedule_delayed_work(&tsc_irqwork, HZ);
931 tsc_start = tsc_read_refs(&ref_start, hpet);
935 tsc_stop = tsc_read_refs(&ref_stop, hpet);
937 /* hpet or pmtimer available ? */
938 if (ref_start == ref_stop)
941 /* Check, whether the sampling was disturbed by an SMI */
942 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
945 delta = tsc_stop - tsc_start;
948 freq = calc_hpet_ref(delta, ref_start, ref_stop);
950 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
952 /* Make sure we're within 1% */
953 if (abs(tsc_khz - freq) > tsc_khz/100)
957 printk(KERN_INFO "Refined TSC clocksource calibration: "
958 "%lu.%03lu MHz.\n", (unsigned long)tsc_khz / 1000,
959 (unsigned long)tsc_khz % 1000);
962 clocksource_register_khz(&clocksource_tsc, tsc_khz);
966 static int __init init_tsc_clocksource(void)
968 if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
971 if (tsc_clocksource_reliable)
972 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
973 /* lower the rating if we already know its unstable: */
974 if (check_tsc_unstable()) {
975 clocksource_tsc.rating = 0;
976 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
978 schedule_delayed_work(&tsc_irqwork, 0);
982 * We use device_initcall here, to ensure we run after the hpet
983 * is fully initialized, which may occur at fs_initcall time.
985 device_initcall(init_tsc_clocksource);
987 void __init tsc_init(void)
992 x86_init.timers.tsc_pre_init();
997 tsc_khz = x86_platform.calibrate_tsc();
1001 mark_tsc_unstable("could not calculate TSC khz");
1005 printk("Detected %lu.%03lu MHz processor.\n",
1006 (unsigned long)cpu_khz / 1000,
1007 (unsigned long)cpu_khz % 1000);
1010 * Secondary CPUs do not run through tsc_init(), so set up
1011 * all the scale factors for all CPUs, assuming the same
1012 * speed as the bootup CPU. (cpufreq notifiers will fix this
1013 * up if their speed diverges)
1015 for_each_possible_cpu(cpu)
1016 set_cyc2ns_scale(cpu_khz, cpu);
1018 if (tsc_disabled > 0)
1021 /* now allow native_sched_clock() to use rdtsc */
1024 if (!no_sched_irq_time)
1025 enable_sched_clock_irqtime();
1027 lpj = ((u64)tsc_khz * 1000);
1032 /* Check and install the TSC clocksource */
1033 dmi_check_system(bad_tsc_dmi_table);
1035 if (unsynchronized_tsc())
1036 mark_tsc_unstable("TSCs unsynchronized");
1038 check_system_tsc_reliable();