2 * SGI UltraViolet TLB flush routines.
4 * (c) 2008 Cliff Wickman <cpw@sgi.com>, SGI.
6 * This code is released under the GNU General Public License version 2 or
9 #include <linux/mc146818rtc.h>
10 #include <linux/proc_fs.h>
11 #include <linux/kernel.h>
13 #include <asm/mmu_context.h>
15 #include <asm/genapic.h>
16 #include <asm/uv/uv_hub.h>
17 #include <asm/uv/uv_mmrs.h>
18 #include <asm/uv/uv_bau.h>
21 #include <mach_apic.h>
23 static struct bau_control **uv_bau_table_bases __read_mostly;
24 static int uv_bau_retry_limit __read_mostly;
25 static int uv_nshift __read_mostly; /* position of pnode (which is nasid>>1) */
26 static unsigned long uv_mmask __read_mostly;
28 static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
29 static DEFINE_PER_CPU(struct bau_control, bau_control);
32 * Free a software acknowledge hardware resource by clearing its Pending
33 * bit. This will return a reply to the sender.
34 * If the message has timed out, a reply has already been sent by the
35 * hardware but the resource has not been released. In that case our
36 * clear of the Timeout bit (as well) will free the resource. No reply will
37 * be sent (the hardware will only do one reply per message).
39 static void uv_reply_to_message(int resource,
40 struct bau_payload_queue_entry *msg,
41 struct bau_msg_status *msp)
45 dw = (1 << (resource + UV_SW_ACK_NPENDING)) | (1 << resource);
47 msg->sw_ack_vector = 0;
49 msp->seen_by.bits = 0;
50 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw);
54 * Do all the things a cpu should do for a TLB shootdown message.
55 * Other cpu's may come here at the same time for this message.
57 static void uv_bau_process_message(struct bau_payload_queue_entry *msg,
58 int msg_slot, int sw_ack_slot)
61 unsigned long this_cpu_mask;
62 struct bau_msg_status *msp;
64 msp = __get_cpu_var(bau_control).msg_statuses + msg_slot;
65 cpu = uv_blade_processor_id();
67 uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id()));
68 this_cpu_mask = 1UL << cpu;
69 if (msp->seen_by.bits & this_cpu_mask)
71 atomic_or_long(&msp->seen_by.bits, this_cpu_mask);
73 if (msg->replied_to == 1)
76 if (msg->address == TLB_FLUSH_ALL) {
78 __get_cpu_var(ptcstats).alltlb++;
80 __flush_tlb_one(msg->address);
81 __get_cpu_var(ptcstats).onetlb++;
84 __get_cpu_var(ptcstats).requestee++;
86 atomic_inc_short(&msg->acknowledge_count);
87 if (msg->number_of_cpus == msg->acknowledge_count)
88 uv_reply_to_message(sw_ack_slot, msg, msp);
92 * Examine the payload queue on one distribution node to see
93 * which messages have not been seen, and which cpu(s) have not seen them.
95 * Returns the number of cpu's that have not responded.
97 static int uv_examine_destination(struct bau_control *bau_tablesp, int sender)
102 struct bau_payload_queue_entry *msg;
103 struct bau_msg_status *msp;
105 for (msg = bau_tablesp->va_queue_first, i = 0; i < DEST_Q_SIZE;
107 if ((msg->sending_cpu == sender) && (!msg->replied_to)) {
108 msp = bau_tablesp->msg_statuses + i;
110 "blade %d: address:%#lx %d of %d, not cpu(s): ",
111 i, msg->address, msg->acknowledge_count,
112 msg->number_of_cpus);
113 for (j = 0; j < msg->number_of_cpus; j++) {
114 if (!((long)1 << j & msp-> seen_by.bits)) {
126 * Examine the payload queue on all the distribution nodes to see
127 * which messages have not been seen, and which cpu(s) have not seen them.
129 * Returns the number of cpu's that have not responded.
131 static int uv_examine_destinations(struct bau_target_nodemask *distribution)
137 sender = smp_processor_id();
138 for (i = 0; i < (sizeof(struct bau_target_nodemask) * BITSPERBYTE);
140 if (!bau_node_isset(i, distribution))
142 count += uv_examine_destination(uv_bau_table_bases[i], sender);
148 * wait for completion of a broadcast message
150 * return COMPLETE, RETRY or GIVEUP
152 static int uv_wait_completion(struct bau_desc *bau_desc,
153 unsigned long mmr_offset, int right_shift)
156 long destination_timeouts = 0;
157 long source_timeouts = 0;
158 unsigned long descriptor_status;
160 while ((descriptor_status = (((unsigned long)
161 uv_read_local_mmr(mmr_offset) >>
162 right_shift) & UV_ACT_STATUS_MASK)) !=
164 if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) {
166 if (source_timeouts > SOURCE_TIMEOUT_LIMIT)
168 __get_cpu_var(ptcstats).s_retry++;
172 * spin here looking for progress at the destinations
174 if (descriptor_status == DESC_STATUS_DESTINATION_TIMEOUT) {
175 destination_timeouts++;
176 if (destination_timeouts > DESTINATION_TIMEOUT_LIMIT) {
178 * returns number of cpus not responding
180 if (uv_examine_destinations
181 (&bau_desc->distribution) == 0) {
182 __get_cpu_var(ptcstats).d_retry++;
186 if (exams >= uv_bau_retry_limit) {
188 "uv_flush_tlb_others");
189 printk("giving up on cpu %d\n",
194 * delays can hang the simulator
197 destination_timeouts = 0;
201 return FLUSH_COMPLETE;
205 * uv_flush_send_and_wait
207 * Send a broadcast and wait for a broadcast message to complete.
209 * The cpumaskp mask contains the cpus the broadcast was sent to.
211 * Returns 1 if all remote flushing was done. The mask is zeroed.
212 * Returns 0 if some remote flushing remains to be done. The mask is left
215 int uv_flush_send_and_wait(int cpu, int this_blade, struct bau_desc *bau_desc,
218 int completion_status = 0;
224 unsigned long mmr_offset;
228 if (cpu < UV_CPUS_PER_ACT_STATUS) {
229 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
230 right_shift = cpu * UV_ACT_STATUS_SIZE;
232 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
234 ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE);
236 time1 = get_cycles();
239 index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) |
241 uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
242 completion_status = uv_wait_completion(bau_desc, mmr_offset,
244 } while (completion_status == FLUSH_RETRY);
245 time2 = get_cycles();
246 __get_cpu_var(ptcstats).sflush += (time2 - time1);
248 __get_cpu_var(ptcstats).retriesok++;
250 if (completion_status == FLUSH_GIVEUP) {
252 * Cause the caller to do an IPI-style TLB shootdown on
253 * the cpu's, all of which are still in the mask.
255 __get_cpu_var(ptcstats).ptc_i++;
260 * Success, so clear the remote cpu's from the mask so we don't
261 * use the IPI method of shootdown on them.
263 for_each_cpu_mask(bit, *cpumaskp) {
264 blade = uv_cpu_to_blade_id(bit);
265 if (blade == this_blade)
267 cpu_clear(bit, *cpumaskp);
269 if (!cpus_empty(*cpumaskp))
275 * uv_flush_tlb_others - globally purge translation cache of a virtual
276 * address or all TLB's
277 * @cpumaskp: mask of all cpu's in which the address is to be removed
278 * @mm: mm_struct containing virtual address range
279 * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
281 * This is the entry point for initiating any UV global TLB shootdown.
283 * Purges the translation caches of all specified processors of the given
284 * virtual address, or purges all TLB's on specified processors.
286 * The caller has derived the cpumaskp from the mm_struct and has subtracted
287 * the local cpu from the mask. This function is called only if there
288 * are bits set in the mask. (e.g. flush_tlb_page())
290 * The cpumaskp is converted into a nodemask of the nodes containing
293 * Returns 1 if all remote flushing was done.
294 * Returns 0 if some remote flushing remains to be done.
296 int uv_flush_tlb_others(cpumask_t *cpumaskp, struct mm_struct *mm,
305 struct bau_desc *bau_desc;
307 cpu = uv_blade_processor_id();
308 this_blade = uv_numa_blade_id();
309 bau_desc = __get_cpu_var(bau_control).descriptor_base;
310 bau_desc += UV_ITEMS_PER_DESCRIPTOR * cpu;
312 bau_nodes_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
315 for_each_cpu_mask(bit, *cpumaskp) {
316 blade = uv_cpu_to_blade_id(bit);
317 BUG_ON(blade > (UV_DISTRIBUTION_SIZE - 1));
318 if (blade == this_blade) {
322 bau_node_set(blade, &bau_desc->distribution);
327 * no off_node flushing; return status for local node
334 __get_cpu_var(ptcstats).requestor++;
335 __get_cpu_var(ptcstats).ntargeted += i;
337 bau_desc->payload.address = va;
338 bau_desc->payload.sending_cpu = smp_processor_id();
340 return uv_flush_send_and_wait(cpu, this_blade, bau_desc, cpumaskp);
344 * The BAU message interrupt comes here. (registered by set_intr_gate)
347 * We received a broadcast assist message.
349 * Interrupts may have been disabled; this interrupt could represent
350 * the receipt of several messages.
352 * All cores/threads on this node get this interrupt.
353 * The last one to see it does the s/w ack.
354 * (the resource will not be freed until noninterruptable cpus see this
355 * interrupt; hardware will timeout the s/w ack and reply ERROR)
357 void uv_bau_message_interrupt(struct pt_regs *regs)
359 struct bau_payload_queue_entry *pqp;
360 struct bau_payload_queue_entry *msg;
361 struct bau_payload_queue_entry *va_queue_first;
362 struct bau_payload_queue_entry *va_queue_last;
363 struct pt_regs *old_regs = set_irq_regs(regs);
364 cycles_t time1, time2;
369 unsigned long local_pnode;
375 time1 = get_cycles();
377 local_pnode = uv_blade_to_pnode(uv_numa_blade_id());
379 pqp = va_queue_first = __get_cpu_var(bau_control).va_queue_first;
380 va_queue_last = __get_cpu_var(bau_control).va_queue_last;
381 msg = __get_cpu_var(bau_control).bau_msg_head;
382 while (msg->sw_ack_vector) {
384 fw = msg->sw_ack_vector;
385 msg_slot = msg - pqp;
386 sw_ack_slot = ffs(fw) - 1;
388 uv_bau_process_message(msg, msg_slot, sw_ack_slot);
391 if (msg > va_queue_last)
392 msg = va_queue_first;
393 __get_cpu_var(bau_control).bau_msg_head = msg;
396 __get_cpu_var(ptcstats).nomsg++;
398 __get_cpu_var(ptcstats).multmsg++;
400 time2 = get_cycles();
401 __get_cpu_var(ptcstats).dflush += (time2 - time1);
404 set_irq_regs(old_regs);
407 static void uv_enable_timeouts(void)
414 unsigned long apicid;
417 for_each_online_node(i) {
418 blade = uv_node_to_blade_id(i);
419 if (blade == last_blade)
422 apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
423 pnode = uv_blade_to_pnode(blade);
424 cur_cpu += uv_blade_nr_possible_cpus(i);
428 static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset)
430 if (*offset < num_possible_cpus())
435 static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
438 if (*offset < num_possible_cpus())
443 static void uv_ptc_seq_stop(struct seq_file *file, void *data)
448 * Display the statistics thru /proc
449 * data points to the cpu number
451 static int uv_ptc_seq_show(struct seq_file *file, void *data)
453 struct ptc_stats *stat;
456 cpu = *(loff_t *)data;
460 "# cpu requestor requestee one all sretry dretry ptc_i ");
462 "sw_ack sflush dflush sok dnomsg dmult starget\n");
464 if (cpu < num_possible_cpus() && cpu_online(cpu)) {
465 stat = &per_cpu(ptcstats, cpu);
466 seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld ",
467 cpu, stat->requestor,
468 stat->requestee, stat->onetlb, stat->alltlb,
469 stat->s_retry, stat->d_retry, stat->ptc_i);
470 seq_printf(file, "%lx %ld %ld %ld %ld %ld %ld\n",
471 uv_read_global_mmr64(uv_blade_to_pnode
472 (uv_cpu_to_blade_id(cpu)),
473 UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
474 stat->sflush, stat->dflush,
475 stat->retriesok, stat->nomsg,
476 stat->multmsg, stat->ntargeted);
483 * 0: display meaning of the statistics
486 static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
487 size_t count, loff_t *data)
492 if (copy_from_user(optstr, user, count))
494 optstr[count - 1] = '\0';
495 if (strict_strtoul(optstr, 10, &newmode) < 0) {
496 printk(KERN_DEBUG "%s is invalid\n", optstr);
501 printk(KERN_DEBUG "# cpu: cpu number\n");
503 "requestor: times this cpu was the flush requestor\n");
505 "requestee: times this cpu was requested to flush its TLBs\n");
507 "one: times requested to flush a single address\n");
509 "all: times requested to flush all TLB's\n");
511 "sretry: number of retries of source-side timeouts\n");
513 "dretry: number of retries of destination-side timeouts\n");
515 "ptc_i: times UV fell through to IPI-style flushes\n");
517 "sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n");
519 "sflush_us: cycles spent in uv_flush_tlb_others()\n");
521 "dflush_us: cycles spent in handling flush requests\n");
522 printk(KERN_DEBUG "sok: successes on retry\n");
523 printk(KERN_DEBUG "dnomsg: interrupts with no message\n");
525 "dmult: interrupts with multiple messages\n");
526 printk(KERN_DEBUG "starget: nodes targeted\n");
528 uv_bau_retry_limit = newmode;
529 printk(KERN_DEBUG "timeout retry limit:%d\n",
536 static const struct seq_operations uv_ptc_seq_ops = {
537 .start = uv_ptc_seq_start,
538 .next = uv_ptc_seq_next,
539 .stop = uv_ptc_seq_stop,
540 .show = uv_ptc_seq_show
543 static int uv_ptc_proc_open(struct inode *inode, struct file *file)
545 return seq_open(file, &uv_ptc_seq_ops);
548 static const struct file_operations proc_uv_ptc_operations = {
549 .open = uv_ptc_proc_open,
551 .write = uv_ptc_proc_write,
553 .release = seq_release,
556 static int __init uv_ptc_init(void)
558 struct proc_dir_entry *proc_uv_ptc;
563 if (!proc_mkdir("sgi_uv", NULL))
566 proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL);
568 printk(KERN_ERR "unable to create %s proc entry\n",
570 remove_proc_entry("sgi_uv", NULL);
573 proc_uv_ptc->proc_fops = &proc_uv_ptc_operations;
578 * begin the initialization of the per-blade control structures
580 static struct bau_control * __init uv_table_bases_init(int blade, int node)
584 struct bau_msg_status *msp;
585 struct bau_control *bau_tabp;
588 kmalloc_node(sizeof(struct bau_control), GFP_KERNEL, node);
590 bau_tabp->msg_statuses =
591 kmalloc_node(sizeof(struct bau_msg_status) *
592 DEST_Q_SIZE, GFP_KERNEL, node);
593 BUG_ON(!bau_tabp->msg_statuses);
594 for (i = 0, msp = bau_tabp->msg_statuses; i < DEST_Q_SIZE; i++, msp++)
595 bau_cpubits_clear(&msp->seen_by, (int)
596 uv_blade_nr_possible_cpus(blade));
598 kmalloc_node(sizeof(int) * DEST_NUM_RESOURCES, GFP_KERNEL, node);
599 BUG_ON(!bau_tabp->watching);
600 for (i = 0, ip = bau_tabp->watching; i < DEST_Q_SIZE; i++, ip++) {
603 uv_bau_table_bases[blade] = bau_tabp;
608 * finish the initialization of the per-blade control structures
610 static void __init uv_table_bases_finish(int blade, int node, int cur_cpu,
611 struct bau_control *bau_tablesp,
612 struct bau_desc *adp)
615 struct bau_control *bcp;
617 for (i = cur_cpu; i < (cur_cpu + uv_blade_nr_possible_cpus(blade));
619 bcp = (struct bau_control *)&per_cpu(bau_control, i);
620 bcp->bau_msg_head = bau_tablesp->va_queue_first;
621 bcp->va_queue_first = bau_tablesp->va_queue_first;
622 bcp->va_queue_last = bau_tablesp->va_queue_last;
623 bcp->watching = bau_tablesp->watching;
624 bcp->msg_statuses = bau_tablesp->msg_statuses;
625 bcp->descriptor_base = adp;
630 * initialize the sending side's sending buffers
632 static struct bau_desc * __init
633 uv_activation_descriptor_init(int node, int pnode)
639 unsigned long mmr_image;
640 struct bau_desc *adp;
641 struct bau_desc *ad2;
643 adp = (struct bau_desc *)
644 kmalloc_node(16384, GFP_KERNEL, node);
646 pa = __pa((unsigned long)adp);
649 mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE);
651 uv_write_global_mmr64(pnode, (unsigned long)
652 UVH_LB_BAU_SB_DESCRIPTOR_BASE,
653 (n << UV_DESC_BASE_PNODE_SHIFT | m));
654 for (i = 0, ad2 = adp; i < UV_ACTIVATION_DESCRIPTOR_SIZE; i++, ad2++) {
655 memset(ad2, 0, sizeof(struct bau_desc));
656 ad2->header.sw_ack_flag = 1;
657 ad2->header.base_dest_nodeid =
658 uv_blade_to_pnode(uv_cpu_to_blade_id(0));
659 ad2->header.command = UV_NET_ENDPOINT_INTD;
660 ad2->header.int_both = 1;
662 * all others need to be set to zero:
663 * fairness chaining multilevel count replied_to
670 * initialize the destination side's receiving buffers
672 static struct bau_payload_queue_entry * __init uv_payload_queue_init(int node,
673 int pnode, struct bau_control *bau_tablesp)
676 struct bau_payload_queue_entry *pqp;
678 pqp = (struct bau_payload_queue_entry *) kmalloc_node(
679 (DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry),
682 cp = (char *)pqp + 31;
683 pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5);
684 bau_tablesp->va_queue_first = pqp;
685 uv_write_global_mmr64(pnode,
686 UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST,
687 ((unsigned long)pnode <<
688 UV_PAYLOADQ_PNODE_SHIFT) |
689 uv_physnodeaddr(pqp));
690 uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL,
691 uv_physnodeaddr(pqp));
692 bau_tablesp->va_queue_last = pqp + (DEST_Q_SIZE - 1);
693 uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST,
695 uv_physnodeaddr(bau_tablesp->va_queue_last));
696 memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE);
701 * Initialization of each UV blade's structures
703 static int __init uv_init_blade(int blade, int node, int cur_cpu)
707 unsigned long apicid;
708 struct bau_desc *adp;
709 struct bau_payload_queue_entry *pqp;
710 struct bau_control *bau_tablesp;
712 bau_tablesp = uv_table_bases_init(blade, node);
713 pnode = uv_blade_to_pnode(blade);
714 adp = uv_activation_descriptor_init(node, pnode);
715 pqp = uv_payload_queue_init(node, pnode, bau_tablesp);
716 uv_table_bases_finish(blade, node, cur_cpu, bau_tablesp, adp);
718 * the below initialization can't be in firmware because the
719 * messaging IRQ will be determined by the OS
721 apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
722 pa = uv_read_global_mmr64(pnode, UVH_BAU_DATA_CONFIG);
723 if ((pa & 0xff) != UV_BAU_MESSAGE) {
724 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
725 ((apicid << 32) | UV_BAU_MESSAGE));
731 * Initialization of BAU-related structures
733 static int __init uv_bau_init(void)
744 uv_bau_retry_limit = 1;
745 uv_nshift = uv_hub_info->n_val;
746 uv_mmask = (1UL << uv_hub_info->n_val) - 1;
749 for_each_online_node(node) {
750 blade = uv_node_to_blade_id(node);
751 if (blade == last_blade)
756 uv_bau_table_bases = (struct bau_control **)
757 kmalloc(nblades * sizeof(struct bau_control *), GFP_KERNEL);
758 BUG_ON(!uv_bau_table_bases);
760 for_each_online_node(node) {
761 blade = uv_node_to_blade_id(node);
762 if (blade == last_blade)
765 uv_init_blade(blade, node, cur_cpu);
766 cur_cpu += uv_blade_nr_possible_cpus(blade);
768 set_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1);
769 uv_enable_timeouts();
772 __initcall(uv_bau_init);
773 __initcall(uv_ptc_init);