2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
53 #include <linux/cpuidle.h>
60 #include <asm/realmode.h>
63 #include <asm/pgtable.h>
64 #include <asm/tlbflush.h>
66 #include <asm/mwait.h>
68 #include <asm/io_apic.h>
69 #include <asm/setup.h>
70 #include <asm/uv/uv.h>
71 #include <linux/mc146818rtc.h>
73 #include <asm/smpboot_hooks.h>
74 #include <asm/i8259.h>
76 #include <asm/realmode.h>
78 /* State of each CPU */
79 DEFINE_PER_CPU(int, cpu_state) = { 0 };
81 #ifdef CONFIG_HOTPLUG_CPU
83 * We need this for trampoline_base protection from concurrent accesses when
84 * off- and onlining cores wildly.
86 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
88 void cpu_hotplug_driver_lock(void)
90 mutex_lock(&x86_cpu_hotplug_driver_mutex);
93 void cpu_hotplug_driver_unlock(void)
95 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
98 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
99 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
102 /* Number of siblings per CPU package */
103 int smp_num_siblings = 1;
104 EXPORT_SYMBOL(smp_num_siblings);
106 /* Last level cache ID of each logical CPU */
107 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
109 /* representing HT siblings of each logical CPU */
110 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
111 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
113 /* representing HT and core siblings of each logical CPU */
114 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
115 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
117 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
119 /* Per CPU bogomips and other parameters */
120 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
121 EXPORT_PER_CPU_SYMBOL(cpu_info);
123 atomic_t init_deasserted;
126 * Report back to the Boot Processor.
129 static void __cpuinit smp_callin(void)
132 unsigned long timeout;
135 * If waken up by an INIT in an 82489DX configuration
136 * we may get here before an INIT-deassert IPI reaches
137 * our local APIC. We have to wait for the IPI or we'll
138 * lock up on an APIC access.
140 if (apic->wait_for_init_deassert)
141 apic->wait_for_init_deassert(&init_deasserted);
144 * (This works even if the APIC is not enabled.)
146 phys_id = read_apic_id();
147 cpuid = smp_processor_id();
148 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
149 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
152 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
155 * STARTUP IPIs are fragile beasts as they might sometimes
156 * trigger some glue motherboard logic. Complete APIC bus
157 * silence for 1 second, this overestimates the time the
158 * boot CPU is spending to send the up to 2 STARTUP IPIs
159 * by a factor of two. This should be enough.
163 * Waiting 2s total for startup (udelay is not yet working)
165 timeout = jiffies + 2*HZ;
166 while (time_before(jiffies, timeout)) {
168 * Has the boot CPU finished it's STARTUP sequence?
170 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
175 if (!time_before(jiffies, timeout)) {
176 panic("%s: CPU%d started up but did not get a callout!\n",
181 * the boot CPU has finished the init stage and is spinning
182 * on callin_map until we finish. We are free to set up this
183 * CPU, first the APIC. (this is probably redundant on most
187 pr_debug("CALLIN, before setup_local_APIC().\n");
188 if (apic->smp_callin_clear_local_apic)
189 apic->smp_callin_clear_local_apic();
191 end_local_APIC_setup();
194 * Need to setup vector mappings before we enable interrupts.
196 setup_vector_irq(smp_processor_id());
199 * Save our processor parameters. Note: this information
200 * is needed for clock calibration.
202 smp_store_cpu_info(cpuid);
206 * Update loops_per_jiffy in cpu_data. Previous call to
207 * smp_store_cpu_info() stored a value that is close but not as
208 * accurate as the value just calculated.
211 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
212 pr_debug("Stack at about %p\n", &cpuid);
215 * This must be done before setting cpu_online_mask
216 * or calling notify_cpu_starting.
218 set_cpu_sibling_map(raw_smp_processor_id());
221 notify_cpu_starting(cpuid);
224 * Allow the master to continue.
226 cpumask_set_cpu(cpuid, cpu_callin_mask);
230 * Activate a secondary processor.
232 notrace static void __cpuinit start_secondary(void *unused)
235 * Don't put *anything* before cpu_init(), SMP booting is too
236 * fragile that we want to limit the things done here to the
237 * most necessary things.
240 x86_cpuinit.early_percpu_clock_init();
245 /* switch away from the initial page table */
246 load_cr3(swapper_pg_dir);
250 /* otherwise gcc will move up smp_processor_id before the cpu_init */
253 * Check TSC synchronization with the BP:
255 check_tsc_sync_target();
258 * We need to hold call_lock, so there is no inconsistency
259 * between the time smp_call_function() determines number of
260 * IPI recipients, and the time when the determination is made
261 * for which cpus receive the IPI. Holding this
262 * lock helps us to not include this cpu in a currently in progress
263 * smp_call_function().
265 * We need to hold vector_lock so there the set of online cpus
266 * does not change while we are assigning vectors to cpus. Holding
267 * this lock ensures we don't half assign or remove an irq from a cpu.
271 set_cpu_online(smp_processor_id(), true);
272 unlock_vector_lock();
274 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
275 x86_platform.nmi_init();
277 /* enable local interrupts */
280 /* to prevent fake stack check failure in clock setup */
281 boot_init_stack_canary();
283 x86_cpuinit.setup_percpu_clockev();
290 * The bootstrap kernel entry code has set these up. Save them for
294 void __cpuinit smp_store_cpu_info(int id)
296 struct cpuinfo_x86 *c = &cpu_data(id);
301 identify_secondary_cpu(c);
304 static bool __cpuinit
305 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
307 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
309 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
310 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
311 "[node: %d != %d]. Ignoring dependency.\n",
312 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
315 #define link_mask(_m, c1, c2) \
317 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
318 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
321 static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
323 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
324 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
326 if (c->phys_proc_id == o->phys_proc_id &&
327 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
328 c->compute_unit_id == o->compute_unit_id)
329 return topology_sane(c, o, "smt");
331 } else if (c->phys_proc_id == o->phys_proc_id &&
332 c->cpu_core_id == o->cpu_core_id) {
333 return topology_sane(c, o, "smt");
339 static bool __cpuinit match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
341 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
343 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
344 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
345 return topology_sane(c, o, "llc");
350 static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
352 if (c->phys_proc_id == o->phys_proc_id)
353 return topology_sane(c, o, "mc");
358 void __cpuinit set_cpu_sibling_map(int cpu)
360 bool has_mc = boot_cpu_data.x86_max_cores > 1;
361 bool has_smt = smp_num_siblings > 1;
362 struct cpuinfo_x86 *c = &cpu_data(cpu);
363 struct cpuinfo_x86 *o;
366 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
368 if (!has_smt && !has_mc) {
369 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
370 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
371 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
376 for_each_cpu(i, cpu_sibling_setup_mask) {
379 if ((i == cpu) || (has_smt && match_smt(c, o)))
380 link_mask(sibling, cpu, i);
382 if ((i == cpu) || (has_mc && match_llc(c, o)))
383 link_mask(llc_shared, cpu, i);
385 if ((i == cpu) || (has_mc && match_mc(c, o))) {
386 link_mask(core, cpu, i);
389 * Does this new cpu bringup a new core?
391 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
393 * for each core in package, increment
394 * the booted_cores for this new cpu
396 if (cpumask_first(cpu_sibling_mask(i)) == i)
399 * increment the core count for all
400 * the other cpus in this package
403 cpu_data(i).booted_cores++;
404 } else if (i != cpu && !c->booted_cores)
405 c->booted_cores = cpu_data(i).booted_cores;
410 /* maps the cpu to the sched domain representing multi-core */
411 const struct cpumask *cpu_coregroup_mask(int cpu)
413 struct cpuinfo_x86 *c = &cpu_data(cpu);
415 * For perf, we return last level cache shared map.
416 * And for power savings, we return cpu_core_map
418 if (!(cpu_has(c, X86_FEATURE_AMD_DCM)))
419 return cpu_core_mask(cpu);
421 return cpu_llc_shared_mask(cpu);
424 static void impress_friends(void)
427 unsigned long bogosum = 0;
429 * Allow the user to impress friends.
431 pr_debug("Before bogomips.\n");
432 for_each_possible_cpu(cpu)
433 if (cpumask_test_cpu(cpu, cpu_callout_mask))
434 bogosum += cpu_data(cpu).loops_per_jiffy;
436 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
439 (bogosum/(5000/HZ))%100);
441 pr_debug("Before bogocount - setting activated=1.\n");
444 void __inquire_remote_apic(int apicid)
446 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
447 const char * const names[] = { "ID", "VERSION", "SPIV" };
451 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
453 for (i = 0; i < ARRAY_SIZE(regs); i++) {
454 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
459 status = safe_apic_wait_icr_idle();
462 "a previous APIC delivery may have failed\n");
464 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
469 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
470 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
473 case APIC_ICR_RR_VALID:
474 status = apic_read(APIC_RRR);
475 printk(KERN_CONT "%08x\n", status);
478 printk(KERN_CONT "failed\n");
484 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
485 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
486 * won't ... remember to clear down the APIC, etc later.
489 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
491 unsigned long send_status, accept_status = 0;
495 /* Boot on the stack */
496 /* Kick the second */
497 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
499 pr_debug("Waiting for send to finish...\n");
500 send_status = safe_apic_wait_icr_idle();
503 * Give the other CPU some time to accept the IPI.
506 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
507 maxlvt = lapic_get_maxlvt();
508 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
509 apic_write(APIC_ESR, 0);
510 accept_status = (apic_read(APIC_ESR) & 0xEF);
512 pr_debug("NMI sent.\n");
515 printk(KERN_ERR "APIC never delivered???\n");
517 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
519 return (send_status | accept_status);
523 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
525 unsigned long send_status, accept_status = 0;
526 int maxlvt, num_starts, j;
528 maxlvt = lapic_get_maxlvt();
531 * Be paranoid about clearing APIC errors.
533 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
534 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
535 apic_write(APIC_ESR, 0);
539 pr_debug("Asserting INIT.\n");
542 * Turn INIT on target chip
547 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
550 pr_debug("Waiting for send to finish...\n");
551 send_status = safe_apic_wait_icr_idle();
555 pr_debug("Deasserting INIT.\n");
559 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
561 pr_debug("Waiting for send to finish...\n");
562 send_status = safe_apic_wait_icr_idle();
565 atomic_set(&init_deasserted, 1);
568 * Should we send STARTUP IPIs ?
570 * Determine this based on the APIC version.
571 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
573 if (APIC_INTEGRATED(apic_version[phys_apicid]))
579 * Paravirt / VMI wants a startup IPI hook here to set up the
580 * target processor state.
582 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
586 * Run STARTUP IPI loop.
588 pr_debug("#startup loops: %d.\n", num_starts);
590 for (j = 1; j <= num_starts; j++) {
591 pr_debug("Sending STARTUP #%d.\n", j);
592 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
593 apic_write(APIC_ESR, 0);
595 pr_debug("After apic_write.\n");
602 /* Boot on the stack */
603 /* Kick the second */
604 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
608 * Give the other CPU some time to accept the IPI.
612 pr_debug("Startup point 1.\n");
614 pr_debug("Waiting for send to finish...\n");
615 send_status = safe_apic_wait_icr_idle();
618 * Give the other CPU some time to accept the IPI.
621 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
622 apic_write(APIC_ESR, 0);
623 accept_status = (apic_read(APIC_ESR) & 0xEF);
624 if (send_status || accept_status)
627 pr_debug("After Startup.\n");
630 printk(KERN_ERR "APIC never delivered???\n");
632 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
634 return (send_status | accept_status);
637 /* reduce the number of lines printed when booting a large cpu count system */
638 static void __cpuinit announce_cpu(int cpu, int apicid)
640 static int current_node = -1;
641 int node = early_cpu_to_node(cpu);
643 if (system_state == SYSTEM_BOOTING) {
644 if (node != current_node) {
645 if (current_node > (-1))
648 pr_info("Booting Node %3d, Processors ", node);
650 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
653 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
658 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
659 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
660 * Returns zero if CPU booted OK, else error code from
661 * ->wakeup_secondary_cpu.
663 static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
665 volatile u32 *trampoline_status =
666 (volatile u32 *) __va(real_mode_header->trampoline_status);
667 /* start_ip had better be page-aligned! */
668 unsigned long start_ip = real_mode_header->trampoline_start;
670 unsigned long boot_error = 0;
673 alternatives_smp_switch(1);
675 idle->thread.sp = (unsigned long) (((struct pt_regs *)
676 (THREAD_SIZE + task_stack_page(idle))) - 1);
677 per_cpu(current_task, cpu) = idle;
680 /* Stack for startup_32 can be just as for start_secondary onwards */
683 clear_tsk_thread_flag(idle, TIF_FORK);
684 initial_gs = per_cpu_offset(cpu);
685 per_cpu(kernel_stack, cpu) =
686 (unsigned long)task_stack_page(idle) -
687 KERNEL_STACK_OFFSET + THREAD_SIZE;
689 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
690 initial_code = (unsigned long)start_secondary;
691 stack_start = idle->thread.sp;
693 /* So we see what's up */
694 announce_cpu(cpu, apicid);
697 * This grunge runs the startup process for
698 * the targeted processor.
701 atomic_set(&init_deasserted, 0);
703 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
705 pr_debug("Setting warm reset code and vector.\n");
707 smpboot_setup_warm_reset_vector(start_ip);
709 * Be paranoid about clearing APIC errors.
711 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
712 apic_write(APIC_ESR, 0);
718 * Kick the secondary CPU. Use the method in the APIC driver
719 * if it's defined - or use an INIT boot APIC message otherwise:
721 if (apic->wakeup_secondary_cpu)
722 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
724 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
728 * allow APs to start initializing.
730 pr_debug("Before Callout %d.\n", cpu);
731 cpumask_set_cpu(cpu, cpu_callout_mask);
732 pr_debug("After Callout %d.\n", cpu);
735 * Wait 5s total for a response
737 for (timeout = 0; timeout < 50000; timeout++) {
738 if (cpumask_test_cpu(cpu, cpu_callin_mask))
739 break; /* It has booted */
742 * Allow other tasks to run while we wait for the
743 * AP to come online. This also gives a chance
744 * for the MTRR work(triggered by the AP coming online)
745 * to be completed in the stop machine context.
750 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
751 print_cpu_msr(&cpu_data(cpu));
752 pr_debug("CPU%d: has booted.\n", cpu);
755 if (*trampoline_status == 0xA5A5A5A5)
756 /* trampoline started but...? */
757 pr_err("CPU%d: Stuck ??\n", cpu);
759 /* trampoline code not run */
760 pr_err("CPU%d: Not responding.\n", cpu);
761 if (apic->inquire_remote_apic)
762 apic->inquire_remote_apic(apicid);
767 /* Try to put things back the way they were before ... */
768 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
770 /* was set by do_boot_cpu() */
771 cpumask_clear_cpu(cpu, cpu_callout_mask);
773 /* was set by cpu_init() */
774 cpumask_clear_cpu(cpu, cpu_initialized_mask);
776 set_cpu_present(cpu, false);
777 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
780 /* mark "stuck" area as not stuck */
781 *trampoline_status = 0;
783 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
785 * Cleanup possible dangling ends...
787 smpboot_restore_warm_reset_vector();
792 int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle)
794 int apicid = apic->cpu_present_to_apicid(cpu);
798 WARN_ON(irqs_disabled());
800 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
802 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
803 !physid_isset(apicid, phys_cpu_present_map) ||
804 !apic->apic_id_valid(apicid)) {
805 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
810 * Already booted CPU?
812 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
813 pr_debug("do_boot_cpu %d Already started\n", cpu);
818 * Save current MTRR state in case it was changed since early boot
819 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
823 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
825 err = do_boot_cpu(apicid, cpu, tidle);
827 pr_debug("do_boot_cpu failed %d\n", err);
832 * Check TSC synchronization with the AP (keep irqs disabled
835 local_irq_save(flags);
836 check_tsc_sync_source(cpu);
837 local_irq_restore(flags);
839 while (!cpu_online(cpu)) {
841 touch_nmi_watchdog();
848 * arch_disable_smp_support() - disables SMP support for x86 at runtime
850 void arch_disable_smp_support(void)
852 disable_ioapic_support();
856 * Fall back to non SMP mode after errors.
858 * RED-PEN audit/test this more. I bet there is more state messed up here.
860 static __init void disable_smp(void)
862 init_cpu_present(cpumask_of(0));
863 init_cpu_possible(cpumask_of(0));
864 smpboot_clear_io_apic_irqs();
866 if (smp_found_config)
867 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
869 physid_set_mask_of_physid(0, &phys_cpu_present_map);
870 cpumask_set_cpu(0, cpu_sibling_mask(0));
871 cpumask_set_cpu(0, cpu_core_mask(0));
875 * Various sanity checks.
877 static int __init smp_sanity_check(unsigned max_cpus)
881 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
882 if (def_to_bigsmp && nr_cpu_ids > 8) {
887 "More than 8 CPUs detected - skipping them.\n"
888 "Use CONFIG_X86_BIGSMP.\n");
891 for_each_present_cpu(cpu) {
893 set_cpu_present(cpu, false);
898 for_each_possible_cpu(cpu) {
900 set_cpu_possible(cpu, false);
908 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
910 "weird, boot CPU (#%d) not listed by the BIOS.\n",
911 hard_smp_processor_id());
913 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
917 * If we couldn't find an SMP configuration at boot time,
918 * get out of here now!
920 if (!smp_found_config && !acpi_lapic) {
922 printk(KERN_NOTICE "SMP motherboard not detected.\n");
924 if (APIC_init_uniprocessor())
925 printk(KERN_NOTICE "Local APIC not detected."
926 " Using dummy APIC emulation.\n");
931 * Should not be necessary because the MP table should list the boot
932 * CPU too, but we do it for the sake of robustness anyway.
934 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
936 "weird, boot CPU (#%d) not listed by the BIOS.\n",
937 boot_cpu_physical_apicid);
938 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
943 * If we couldn't find a local APIC, then get out of here now!
945 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
948 pr_err("BIOS bug, local APIC #%d not detected!...\n",
949 boot_cpu_physical_apicid);
950 pr_err("... forcing use of dummy APIC emulation."
951 "(tell your hw vendor)\n");
953 smpboot_clear_io_apic();
954 disable_ioapic_support();
961 * If SMP should be disabled, then really disable it!
964 printk(KERN_INFO "SMP mode deactivated.\n");
965 smpboot_clear_io_apic();
969 bsp_end_local_APIC_setup();
976 static void __init smp_cpu_index_default(void)
979 struct cpuinfo_x86 *c;
981 for_each_possible_cpu(i) {
983 /* mark all to hotplug */
984 c->cpu_index = nr_cpu_ids;
989 * Prepare for SMP bootup. The MP table or ACPI has been read
990 * earlier. Just do some sanity checking here and enable APIC mode.
992 void __init native_smp_prepare_cpus(unsigned int max_cpus)
997 smp_cpu_index_default();
1000 * Setup boot CPU information
1002 smp_store_cpu_info(0); /* Final full version of the data */
1003 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1006 current_thread_info()->cpu = 0; /* needed? */
1007 for_each_possible_cpu(i) {
1008 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1009 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1010 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1012 set_cpu_sibling_map(0);
1015 if (smp_sanity_check(max_cpus) < 0) {
1016 printk(KERN_INFO "SMP disabled\n");
1021 default_setup_apic_routing();
1024 if (read_apic_id() != boot_cpu_physical_apicid) {
1025 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1026 read_apic_id(), boot_cpu_physical_apicid);
1027 /* Or can we switch back to PIC here? */
1034 * Switch from PIC to APIC mode.
1039 * Enable IO APIC before setting up error vector
1041 if (!skip_ioapic_setup && nr_ioapics)
1044 bsp_end_local_APIC_setup();
1046 if (apic->setup_portio_remap)
1047 apic->setup_portio_remap();
1049 smpboot_setup_io_apic();
1051 * Set up local APIC timer on boot CPU.
1054 printk(KERN_INFO "CPU%d: ", 0);
1055 print_cpu_info(&cpu_data(0));
1056 x86_init.timers.setup_percpu_clockev();
1061 set_mtrr_aps_delayed_init();
1066 void arch_disable_nonboot_cpus_begin(void)
1069 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1070 * In the suspend path, we will be back in the SMP mode shortly anyways.
1072 skip_smp_alternatives = true;
1075 void arch_disable_nonboot_cpus_end(void)
1077 skip_smp_alternatives = false;
1080 void arch_enable_nonboot_cpus_begin(void)
1082 set_mtrr_aps_delayed_init();
1085 void arch_enable_nonboot_cpus_end(void)
1091 * Early setup to make printk work.
1093 void __init native_smp_prepare_boot_cpu(void)
1095 int me = smp_processor_id();
1096 switch_to_new_gdt(me);
1097 /* already set me in cpu_online_mask in boot_cpu_init() */
1098 cpumask_set_cpu(me, cpu_callout_mask);
1099 per_cpu(cpu_state, me) = CPU_ONLINE;
1102 void __init native_smp_cpus_done(unsigned int max_cpus)
1104 pr_debug("Boot done.\n");
1108 #ifdef CONFIG_X86_IO_APIC
1109 setup_ioapic_dest();
1114 static int __initdata setup_possible_cpus = -1;
1115 static int __init _setup_possible_cpus(char *str)
1117 get_option(&str, &setup_possible_cpus);
1120 early_param("possible_cpus", _setup_possible_cpus);
1124 * cpu_possible_mask should be static, it cannot change as cpu's
1125 * are onlined, or offlined. The reason is per-cpu data-structures
1126 * are allocated by some modules at init time, and dont expect to
1127 * do this dynamically on cpu arrival/departure.
1128 * cpu_present_mask on the other hand can change dynamically.
1129 * In case when cpu_hotplug is not compiled, then we resort to current
1130 * behaviour, which is cpu_possible == cpu_present.
1133 * Three ways to find out the number of additional hotplug CPUs:
1134 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1135 * - The user can overwrite it with possible_cpus=NUM
1136 * - Otherwise don't reserve additional CPUs.
1137 * We do this because additional CPUs waste a lot of memory.
1140 __init void prefill_possible_map(void)
1144 /* no processor from mptable or madt */
1145 if (!num_processors)
1148 i = setup_max_cpus ?: 1;
1149 if (setup_possible_cpus == -1) {
1150 possible = num_processors;
1151 #ifdef CONFIG_HOTPLUG_CPU
1153 possible += disabled_cpus;
1159 possible = setup_possible_cpus;
1161 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1163 /* nr_cpu_ids could be reduced via nr_cpus= */
1164 if (possible > nr_cpu_ids) {
1166 "%d Processors exceeds NR_CPUS limit of %d\n",
1167 possible, nr_cpu_ids);
1168 possible = nr_cpu_ids;
1171 #ifdef CONFIG_HOTPLUG_CPU
1172 if (!setup_max_cpus)
1176 "%d Processors exceeds max_cpus limit of %u\n",
1177 possible, setup_max_cpus);
1181 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1182 possible, max_t(int, possible - num_processors, 0));
1184 for (i = 0; i < possible; i++)
1185 set_cpu_possible(i, true);
1186 for (; i < NR_CPUS; i++)
1187 set_cpu_possible(i, false);
1189 nr_cpu_ids = possible;
1192 #ifdef CONFIG_HOTPLUG_CPU
1194 static void remove_siblinginfo(int cpu)
1197 struct cpuinfo_x86 *c = &cpu_data(cpu);
1199 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1200 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1202 * last thread sibling in this cpu core going down
1204 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1205 cpu_data(sibling).booted_cores--;
1208 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1209 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1210 cpumask_clear(cpu_sibling_mask(cpu));
1211 cpumask_clear(cpu_core_mask(cpu));
1212 c->phys_proc_id = 0;
1214 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1217 static void __ref remove_cpu_from_maps(int cpu)
1219 set_cpu_online(cpu, false);
1220 cpumask_clear_cpu(cpu, cpu_callout_mask);
1221 cpumask_clear_cpu(cpu, cpu_callin_mask);
1222 /* was set by cpu_init() */
1223 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1224 numa_remove_cpu(cpu);
1227 void cpu_disable_common(void)
1229 int cpu = smp_processor_id();
1231 remove_siblinginfo(cpu);
1233 /* It's now safe to remove this processor from the online map */
1235 remove_cpu_from_maps(cpu);
1236 unlock_vector_lock();
1240 int native_cpu_disable(void)
1242 int cpu = smp_processor_id();
1245 * Perhaps use cpufreq to drop frequency, but that could go
1246 * into generic code.
1248 * We won't take down the boot processor on i386 due to some
1249 * interrupts only being able to be serviced by the BSP.
1250 * Especially so if we're not using an IOAPIC -zwane
1257 cpu_disable_common();
1261 void native_cpu_die(unsigned int cpu)
1263 /* We don't do anything here: idle task is faking death itself. */
1266 for (i = 0; i < 10; i++) {
1267 /* They ack this in play_dead by setting CPU_DEAD */
1268 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1269 if (system_state == SYSTEM_RUNNING)
1270 pr_info("CPU %u is now offline\n", cpu);
1272 if (1 == num_online_cpus())
1273 alternatives_smp_switch(0);
1278 pr_err("CPU %u didn't die...\n", cpu);
1281 void play_dead_common(void)
1284 reset_lazy_tlbstate();
1285 amd_e400_remove_cpu(raw_smp_processor_id());
1289 __this_cpu_write(cpu_state, CPU_DEAD);
1292 * With physical CPU hotplug, we should halt the cpu
1294 local_irq_disable();
1298 * We need to flush the caches before going to sleep, lest we have
1299 * dirty data in our caches when we come back up.
1301 static inline void mwait_play_dead(void)
1303 unsigned int eax, ebx, ecx, edx;
1304 unsigned int highest_cstate = 0;
1305 unsigned int highest_subcstate = 0;
1308 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1310 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1312 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1314 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1317 eax = CPUID_MWAIT_LEAF;
1319 native_cpuid(&eax, &ebx, &ecx, &edx);
1322 * eax will be 0 if EDX enumeration is not valid.
1323 * Initialized below to cstate, sub_cstate value when EDX is valid.
1325 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1328 edx >>= MWAIT_SUBSTATE_SIZE;
1329 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1330 if (edx & MWAIT_SUBSTATE_MASK) {
1332 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1335 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1336 (highest_subcstate - 1);
1340 * This should be a memory location in a cache line which is
1341 * unlikely to be touched by other processors. The actual
1342 * content is immaterial as it is not actually modified in any way.
1344 mwait_ptr = ¤t_thread_info()->flags;
1350 * The CLFLUSH is a workaround for erratum AAI65 for
1351 * the Xeon 7400 series. It's not clear it is actually
1352 * needed, but it should be harmless in either case.
1353 * The WBINVD is insufficient due to the spurious-wakeup
1354 * case where we return around the loop.
1357 __monitor(mwait_ptr, 0, 0);
1363 static inline void hlt_play_dead(void)
1365 if (__this_cpu_read(cpu_info.x86) >= 4)
1373 void native_play_dead(void)
1376 tboot_shutdown(TB_SHUTDOWN_WFS);
1378 mwait_play_dead(); /* Only returns on failure */
1379 if (cpuidle_play_dead())
1383 #else /* ... !CONFIG_HOTPLUG_CPU */
1384 int native_cpu_disable(void)
1389 void native_cpu_die(unsigned int cpu)
1391 /* We said "no" in __cpu_disable */
1395 void native_play_dead(void)