1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <linux/user-return-notifier.h>
13 #include <linux/dmi.h>
14 #include <linux/utsname.h>
15 #include <trace/events/power.h>
16 #include <linux/hw_breakpoint.h>
17 #include <asm/system.h>
19 #include <asm/syscalls.h>
21 #include <asm/uaccess.h>
24 #include <asm/debugreg.h>
26 unsigned long idle_halt;
27 EXPORT_SYMBOL(idle_halt);
28 unsigned long idle_nomwait;
29 EXPORT_SYMBOL(idle_nomwait);
31 struct kmem_cache *task_xstate_cachep;
33 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
36 if (src->thread.xstate) {
37 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
39 if (!dst->thread.xstate)
41 WARN_ON((unsigned long)dst->thread.xstate & 15);
42 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
47 void free_thread_xstate(struct task_struct *tsk)
49 if (tsk->thread.xstate) {
50 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
51 tsk->thread.xstate = NULL;
54 WARN(tsk->thread.ds_ctx, "leaking DS context\n");
57 void free_thread_info(struct thread_info *ti)
59 free_thread_xstate(ti->task);
60 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
63 void arch_task_cache_init(void)
66 kmem_cache_create("task_xstate", xstate_size,
67 __alignof__(union thread_xstate),
68 SLAB_PANIC | SLAB_NOTRACK, NULL);
72 * Free current thread data structures etc..
74 void exit_thread(void)
76 struct task_struct *me = current;
77 struct thread_struct *t = &me->thread;
78 unsigned long *bp = t->io_bitmap_ptr;
81 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
83 t->io_bitmap_ptr = NULL;
84 clear_thread_flag(TIF_IO_BITMAP);
86 * Careful, clear this in the TSS too:
88 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
95 void show_regs_common(void)
97 const char *board, *product;
99 board = dmi_get_system_info(DMI_BOARD_NAME);
102 product = dmi_get_system_info(DMI_PRODUCT_NAME);
107 printk(KERN_INFO "Pid: %d, comm: %.20s %s %s %.*s %s/%s\n",
108 current->pid, current->comm, print_tainted(),
109 init_utsname()->release,
110 (int)strcspn(init_utsname()->version, " "),
111 init_utsname()->version, board, product);
114 void flush_thread(void)
116 struct task_struct *tsk = current;
119 if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
120 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
121 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
122 clear_tsk_thread_flag(tsk, TIF_IA32);
124 set_tsk_thread_flag(tsk, TIF_IA32);
125 current_thread_info()->status |= TS_COMPAT;
130 flush_ptrace_hw_breakpoint(tsk);
131 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
133 * Forget coprocessor state..
135 tsk->fpu_counter = 0;
140 static void hard_disable_TSC(void)
142 write_cr4(read_cr4() | X86_CR4_TSD);
145 void disable_TSC(void)
148 if (!test_and_set_thread_flag(TIF_NOTSC))
150 * Must flip the CPU state synchronously with
151 * TIF_NOTSC in the current running context.
157 static void hard_enable_TSC(void)
159 write_cr4(read_cr4() & ~X86_CR4_TSD);
162 static void enable_TSC(void)
165 if (test_and_clear_thread_flag(TIF_NOTSC))
167 * Must flip the CPU state synchronously with
168 * TIF_NOTSC in the current running context.
174 int get_tsc_mode(unsigned long adr)
178 if (test_thread_flag(TIF_NOTSC))
179 val = PR_TSC_SIGSEGV;
183 return put_user(val, (unsigned int __user *)adr);
186 int set_tsc_mode(unsigned int val)
188 if (val == PR_TSC_SIGSEGV)
190 else if (val == PR_TSC_ENABLE)
198 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
199 struct tss_struct *tss)
201 struct thread_struct *prev, *next;
203 prev = &prev_p->thread;
204 next = &next_p->thread;
206 if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
207 test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
208 ds_switch_to(prev_p, next_p);
209 else if (next->debugctlmsr != prev->debugctlmsr)
210 update_debugctlmsr(next->debugctlmsr);
212 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
213 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
214 /* prev and next are different */
215 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
221 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
223 * Copy the relevant range of the IO bitmap.
224 * Normally this is 128 bytes or less:
226 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
227 max(prev->io_bitmap_max, next->io_bitmap_max));
228 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
230 * Clear any possible leftover bits:
232 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
234 propagate_user_return_notify(prev_p, next_p);
237 int sys_fork(struct pt_regs *regs)
239 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
243 * This is trivial, and on the face of it looks like it
244 * could equally well be done in user mode.
246 * Not so, for quite unobvious reasons - register pressure.
247 * In user mode vfork() cannot have a stack frame, and if
248 * done by calling the "clone()" system call directly, you
249 * do not have enough call-clobbered registers to hold all
250 * the information you need.
252 int sys_vfork(struct pt_regs *regs)
254 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
260 * Idle related variables and functions
262 unsigned long boot_option_idle_override = 0;
263 EXPORT_SYMBOL(boot_option_idle_override);
266 * Powermanagement idle function, if any..
268 void (*pm_idle)(void);
269 EXPORT_SYMBOL(pm_idle);
273 * This halt magic was a workaround for ancient floppy DMA
274 * wreckage. It should be safe to remove.
276 static int hlt_counter;
277 void disable_hlt(void)
281 EXPORT_SYMBOL(disable_hlt);
283 void enable_hlt(void)
287 EXPORT_SYMBOL(enable_hlt);
289 static inline int hlt_use_halt(void)
291 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
294 static inline int hlt_use_halt(void)
301 * We use this if we don't have any better
304 void default_idle(void)
306 if (hlt_use_halt()) {
307 trace_power_start(POWER_CSTATE, 1);
308 current_thread_info()->status &= ~TS_POLLING;
310 * TS_POLLING-cleared state must be visible before we
316 safe_halt(); /* enables interrupts racelessly */
319 current_thread_info()->status |= TS_POLLING;
322 /* loop is done by the caller */
326 #ifdef CONFIG_APM_MODULE
327 EXPORT_SYMBOL(default_idle);
330 void stop_this_cpu(void *dummy)
336 set_cpu_online(smp_processor_id(), false);
337 disable_local_APIC();
340 if (hlt_works(smp_processor_id()))
345 static void do_nothing(void *unused)
350 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
351 * pm_idle and update to new pm_idle value. Required while changing pm_idle
352 * handler on SMP systems.
354 * Caller must have changed pm_idle to the new value before the call. Old
355 * pm_idle value will not be used by any CPU after the return of this function.
357 void cpu_idle_wait(void)
360 /* kick all the CPUs so that they exit out of pm_idle */
361 smp_call_function(do_nothing, NULL, 1);
363 EXPORT_SYMBOL_GPL(cpu_idle_wait);
366 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
367 * which can obviate IPI to trigger checking of need_resched.
368 * We execute MONITOR against need_resched and enter optimized wait state
369 * through MWAIT. Whenever someone changes need_resched, we would be woken
370 * up from MWAIT (without an IPI).
372 * New with Core Duo processors, MWAIT can take some hints based on CPU
375 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
377 trace_power_start(POWER_CSTATE, (ax>>4)+1);
378 if (!need_resched()) {
379 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
380 clflush((void *)¤t_thread_info()->flags);
382 __monitor((void *)¤t_thread_info()->flags, 0, 0);
389 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
390 static void mwait_idle(void)
392 if (!need_resched()) {
393 trace_power_start(POWER_CSTATE, 1);
394 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
395 clflush((void *)¤t_thread_info()->flags);
397 __monitor((void *)¤t_thread_info()->flags, 0, 0);
408 * On SMP it's slightly faster (but much more power-consuming!)
409 * to poll the ->work.need_resched flag instead of waiting for the
410 * cross-CPU IPI to arrive. Use this option with caution.
412 static void poll_idle(void)
414 trace_power_start(POWER_CSTATE, 0);
416 while (!need_resched())
422 * mwait selection logic:
424 * It depends on the CPU. For AMD CPUs that support MWAIT this is
425 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
426 * then depend on a clock divisor and current Pstate of the core. If
427 * all cores of a processor are in halt state (C1) the processor can
428 * enter the C1E (C1 enhanced) state. If mwait is used this will never
431 * idle=mwait overrides this decision and forces the usage of mwait.
433 static int __cpuinitdata force_mwait;
435 #define MWAIT_INFO 0x05
436 #define MWAIT_ECX_EXTENDED_INFO 0x01
437 #define MWAIT_EDX_C1 0xf0
439 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
441 u32 eax, ebx, ecx, edx;
446 if (c->cpuid_level < MWAIT_INFO)
449 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
450 /* Check, whether EDX has extended info about MWAIT */
451 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
455 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
458 return (edx & MWAIT_EDX_C1);
462 * Check for AMD CPUs, which have potentially C1E support
464 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
466 if (c->x86_vendor != X86_VENDOR_AMD)
472 /* Family 0x0f models < rev F do not have C1E */
473 if (c->x86 == 0x0f && c->x86_model < 0x40)
479 static cpumask_var_t c1e_mask;
480 static int c1e_detected;
482 void c1e_remove_cpu(int cpu)
484 if (c1e_mask != NULL)
485 cpumask_clear_cpu(cpu, c1e_mask);
489 * C1E aware idle routine. We check for C1E active in the interrupt
490 * pending message MSR. If we detect C1E, then we handle it the same
491 * way as C3 power states (local apic timer and TSC stop)
493 static void c1e_idle(void)
501 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
502 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
504 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
505 mark_tsc_unstable("TSC halt in AMD C1E");
506 printk(KERN_INFO "System has AMD C1E enabled\n");
507 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
512 int cpu = smp_processor_id();
514 if (!cpumask_test_cpu(cpu, c1e_mask)) {
515 cpumask_set_cpu(cpu, c1e_mask);
517 * Force broadcast so ACPI can not interfere.
519 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
521 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
524 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
529 * The switch back from broadcast mode needs to be
530 * called with interrupts disabled.
533 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
539 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
542 if (pm_idle == poll_idle && smp_num_siblings > 1) {
543 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
544 " performance may degrade.\n");
550 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
552 * One CPU supports mwait => All CPUs supports mwait
554 printk(KERN_INFO "using mwait in idle threads.\n");
555 pm_idle = mwait_idle;
556 } else if (check_c1e_idle(c)) {
557 printk(KERN_INFO "using C1E aware idle routine\n");
560 pm_idle = default_idle;
563 void __init init_c1e_mask(void)
565 /* If we're using c1e_idle, we need to allocate c1e_mask. */
566 if (pm_idle == c1e_idle)
567 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
570 static int __init idle_setup(char *str)
575 if (!strcmp(str, "poll")) {
576 printk("using polling idle threads.\n");
578 } else if (!strcmp(str, "mwait"))
580 else if (!strcmp(str, "halt")) {
582 * When the boot option of idle=halt is added, halt is
583 * forced to be used for CPU idle. In such case CPU C2/C3
584 * won't be used again.
585 * To continue to load the CPU idle driver, don't touch
586 * the boot_option_idle_override.
588 pm_idle = default_idle;
591 } else if (!strcmp(str, "nomwait")) {
593 * If the boot option of "idle=nomwait" is added,
594 * it means that mwait will be disabled for CPU C2/C3
595 * states. In such case it won't touch the variable
596 * of boot_option_idle_override.
603 boot_option_idle_override = 1;
606 early_param("idle", idle_setup);
608 unsigned long arch_align_stack(unsigned long sp)
610 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
611 sp -= get_random_int() % 8192;
615 unsigned long arch_randomize_brk(struct mm_struct *mm)
617 unsigned long range_end = mm->brk + 0x02000000;
618 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;