arch/x86/kernel/process.c

   1 #include <linux/errno.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mm.h>
   4 #include <linux/smp.h>
   5 #include <linux/prctl.h>
   6 #include <linux/slab.h>
   7 #include <linux/sched.h>
   8 #include <linux/module.h>
   9 #include <linux/pm.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/random.h>
  12 #include <linux/user-return-notifier.h>
  13 #include <linux/dmi.h>
  14 #include <linux/utsname.h>
  15 #include <trace/events/power.h>
  16 #include <linux/hw_breakpoint.h>
  17 #include <asm/system.h>
  18 #include <asm/apic.h>
  19 #include <asm/syscalls.h>
  20 #include <asm/idle.h>
  21 #include <asm/uaccess.h>
  22 #include <asm/i387.h>
  23 #include <asm/ds.h>
  24 #include <asm/debugreg.h>
  25
  26 unsigned long idle_halt;
  27 EXPORT_SYMBOL(idle_halt);
  28 unsigned long idle_nomwait;
  29 EXPORT_SYMBOL(idle_nomwait);
  30
  31 struct kmem_cache *task_xstate_cachep;
  32
  33 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  34 {
  35         *dst = *src;
  36         if (src->thread.xstate) {
  37                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
  38                                                       GFP_KERNEL);
  39                 if (!dst->thread.xstate)
  40                         return -ENOMEM;
  41                 WARN_ON((unsigned long)dst->thread.xstate & 15);
  42                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
  43         }
  44         return 0;
  45 }
  46
  47 void free_thread_xstate(struct task_struct *tsk)
  48 {
  49         if (tsk->thread.xstate) {
  50                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
  51                 tsk->thread.xstate = NULL;
  52         }
  53
  54         WARN(tsk->thread.ds_ctx, "leaking DS context\n");
  55 }
  56
  57 void free_thread_info(struct thread_info *ti)
  58 {
  59         free_thread_xstate(ti->task);
  60         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  61 }
  62
  63 void arch_task_cache_init(void)
  64 {
  65         task_xstate_cachep =
  66                 kmem_cache_create("task_xstate", xstate_size,
  67                                   __alignof__(union thread_xstate),
  68                                   SLAB_PANIC | SLAB_NOTRACK, NULL);
  69 }
  70
  71 /*
  72  * Free current thread data structures etc..
  73  */
  74 void exit_thread(void)
  75 {
  76         struct task_struct *me = current;
  77         struct thread_struct *t = &me->thread;
  78         unsigned long *bp = t->io_bitmap_ptr;
  79
  80         if (bp) {
  81                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
  82
  83                 t->io_bitmap_ptr = NULL;
  84                 clear_thread_flag(TIF_IO_BITMAP);
  85                 /*
  86                  * Careful, clear this in the TSS too:
  87                  */
  88                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
  89                 t->io_bitmap_max = 0;
  90                 put_cpu();
  91                 kfree(bp);
  92         }
  93 }
  94
  95 void show_regs_common(void)
  96 {
  97         const char *board, *product;
  98
  99         board = dmi_get_system_info(DMI_BOARD_NAME);
 100         if (!board)
 101                 board = "";
 102         product = dmi_get_system_info(DMI_PRODUCT_NAME);
 103         if (!product)
 104                 product = "";
 105
 106         printk("\n");
 107         printk(KERN_INFO "Pid: %d, comm: %.20s %s %s %.*s %s/%s\n",
 108                 current->pid, current->comm, print_tainted(),
 109                 init_utsname()->release,
 110                 (int)strcspn(init_utsname()->version, " "),
 111                 init_utsname()->version, board, product);
 112 }
 113
 114 void flush_thread(void)
 115 {
 116         struct task_struct *tsk = current;
 117
 118 #ifdef CONFIG_X86_64
 119         if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
 120                 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
 121                 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
 122                         clear_tsk_thread_flag(tsk, TIF_IA32);
 123                 } else {
 124                         set_tsk_thread_flag(tsk, TIF_IA32);
 125                         current_thread_info()->status |= TS_COMPAT;
 126                 }
 127         }
 128 #endif
 129
 130         flush_ptrace_hw_breakpoint(tsk);
 131         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 132         /*
 133          * Forget coprocessor state..
 134          */
 135         tsk->fpu_counter = 0;
 136         clear_fpu(tsk);
 137         clear_used_math();
 138 }
 139
 140 static void hard_disable_TSC(void)
 141 {
 142         write_cr4(read_cr4() | X86_CR4_TSD);
 143 }
 144
 145 void disable_TSC(void)
 146 {
 147         preempt_disable();
 148         if (!test_and_set_thread_flag(TIF_NOTSC))
 149                 /*
 150                  * Must flip the CPU state synchronously with
 151                  * TIF_NOTSC in the current running context.
 152                  */
 153                 hard_disable_TSC();
 154         preempt_enable();
 155 }
 156
 157 static void hard_enable_TSC(void)
 158 {
 159         write_cr4(read_cr4() & ~X86_CR4_TSD);
 160 }
 161
 162 static void enable_TSC(void)
 163 {
 164         preempt_disable();
 165         if (test_and_clear_thread_flag(TIF_NOTSC))
 166                 /*
 167                  * Must flip the CPU state synchronously with
 168                  * TIF_NOTSC in the current running context.
 169                  */
 170                 hard_enable_TSC();
 171         preempt_enable();
 172 }
 173
 174 int get_tsc_mode(unsigned long adr)
 175 {
 176         unsigned int val;
 177
 178         if (test_thread_flag(TIF_NOTSC))
 179                 val = PR_TSC_SIGSEGV;
 180         else
 181                 val = PR_TSC_ENABLE;
 182
 183         return put_user(val, (unsigned int __user *)adr);
 184 }
 185
 186 int set_tsc_mode(unsigned int val)
 187 {
 188         if (val == PR_TSC_SIGSEGV)
 189                 disable_TSC();
 190         else if (val == PR_TSC_ENABLE)
 191                 enable_TSC();
 192         else
 193                 return -EINVAL;
 194
 195         return 0;
 196 }
 197
 198 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 199                       struct tss_struct *tss)
 200 {
 201         struct thread_struct *prev, *next;
 202
 203         prev = &prev_p->thread;
 204         next = &next_p->thread;
 205
 206         if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
 207             test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
 208                 ds_switch_to(prev_p, next_p);
 209         else if (next->debugctlmsr != prev->debugctlmsr)
 210                 update_debugctlmsr(next->debugctlmsr);
 211
 212         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 213             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 214                 /* prev and next are different */
 215                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 216                         hard_disable_TSC();
 217                 else
 218                         hard_enable_TSC();
 219         }
 220
 221         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 222                 /*
 223                  * Copy the relevant range of the IO bitmap.
 224                  * Normally this is 128 bytes or less:
 225                  */
 226                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 227                        max(prev->io_bitmap_max, next->io_bitmap_max));
 228         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 229                 /*
 230                  * Clear any possible leftover bits:
 231                  */
 232                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 233         }
 234         propagate_user_return_notify(prev_p, next_p);
 235 }
 236
 237 int sys_fork(struct pt_regs *regs)
 238 {
 239         return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
 240 }
 241
 242 /*
 243  * This is trivial, and on the face of it looks like it
 244  * could equally well be done in user mode.
 245  *
 246  * Not so, for quite unobvious reasons - register pressure.
 247  * In user mode vfork() cannot have a stack frame, and if
 248  * done by calling the "clone()" system call directly, you
 249  * do not have enough call-clobbered registers to hold all
 250  * the information you need.
 251  */
 252 int sys_vfork(struct pt_regs *regs)
 253 {
 254         return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
 255                        NULL, NULL);
 256 }
 257
 258
 259 /*
 260  * Idle related variables and functions
 261  */
 262 unsigned long boot_option_idle_override = 0;
 263 EXPORT_SYMBOL(boot_option_idle_override);
 264
 265 /*
 266  * Powermanagement idle function, if any..
 267  */
 268 void (*pm_idle)(void);
 269 EXPORT_SYMBOL(pm_idle);
 270
 271 #ifdef CONFIG_X86_32
 272 /*
 273  * This halt magic was a workaround for ancient floppy DMA
 274  * wreckage. It should be safe to remove.
 275  */
 276 static int hlt_counter;
 277 void disable_hlt(void)
 278 {
 279         hlt_counter++;
 280 }
 281 EXPORT_SYMBOL(disable_hlt);
 282
 283 void enable_hlt(void)
 284 {
 285         hlt_counter--;
 286 }
 287 EXPORT_SYMBOL(enable_hlt);
 288
 289 static inline int hlt_use_halt(void)
 290 {
 291         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
 292 }
 293 #else
 294 static inline int hlt_use_halt(void)
 295 {
 296         return 1;
 297 }
 298 #endif
 299
 300 /*
 301  * We use this if we don't have any better
 302  * idle routine..
 303  */
 304 void default_idle(void)
 305 {
 306         if (hlt_use_halt()) {
 307                 trace_power_start(POWER_CSTATE, 1);
 308                 current_thread_info()->status &= ~TS_POLLING;
 309                 /*
 310                  * TS_POLLING-cleared state must be visible before we
 311                  * test NEED_RESCHED:
 312                  */
 313                 smp_mb();
 314
 315                 if (!need_resched())
 316                         safe_halt();    /* enables interrupts racelessly */
 317                 else
 318                         local_irq_enable();
 319                 current_thread_info()->status |= TS_POLLING;
 320         } else {
 321                 local_irq_enable();
 322                 /* loop is done by the caller */
 323                 cpu_relax();
 324         }
 325 }
 326 #ifdef CONFIG_APM_MODULE
 327 EXPORT_SYMBOL(default_idle);
 328 #endif
 329
 330 void stop_this_cpu(void *dummy)
 331 {
 332         local_irq_disable();
 333         /*
 334          * Remove this CPU:
 335          */
 336         set_cpu_online(smp_processor_id(), false);
 337         disable_local_APIC();
 338
 339         for (;;) {
 340                 if (hlt_works(smp_processor_id()))
 341                         halt();
 342         }
 343 }
 344
 345 static void do_nothing(void *unused)
 346 {
 347 }
 348
 349 /*
 350  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 351  * pm_idle and update to new pm_idle value. Required while changing pm_idle
 352  * handler on SMP systems.
 353  *
 354  * Caller must have changed pm_idle to the new value before the call. Old
 355  * pm_idle value will not be used by any CPU after the return of this function.
 356  */
 357 void cpu_idle_wait(void)
 358 {
 359         smp_mb();
 360         /* kick all the CPUs so that they exit out of pm_idle */
 361         smp_call_function(do_nothing, NULL, 1);
 362 }
 363 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 364
 365 /*
 366  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 367  * which can obviate IPI to trigger checking of need_resched.
 368  * We execute MONITOR against need_resched and enter optimized wait state
 369  * through MWAIT. Whenever someone changes need_resched, we would be woken
 370  * up from MWAIT (without an IPI).
 371  *
 372  * New with Core Duo processors, MWAIT can take some hints based on CPU
 373  * capability.
 374  */
 375 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 376 {
 377         trace_power_start(POWER_CSTATE, (ax>>4)+1);
 378         if (!need_resched()) {
 379                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 380                         clflush((void *)&current_thread_info()->flags);
 381
 382                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 383                 smp_mb();
 384                 if (!need_resched())
 385                         __mwait(ax, cx);
 386         }
 387 }
 388
 389 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 390 static void mwait_idle(void)
 391 {
 392         if (!need_resched()) {
 393                 trace_power_start(POWER_CSTATE, 1);
 394                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 395                         clflush((void *)&current_thread_info()->flags);
 396
 397                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 398                 smp_mb();
 399                 if (!need_resched())
 400                         __sti_mwait(0, 0);
 401                 else
 402                         local_irq_enable();
 403         } else
 404                 local_irq_enable();
 405 }
 406
 407 /*
 408  * On SMP it's slightly faster (but much more power-consuming!)
 409  * to poll the ->work.need_resched flag instead of waiting for the
 410  * cross-CPU IPI to arrive. Use this option with caution.
 411  */
 412 static void poll_idle(void)
 413 {
 414         trace_power_start(POWER_CSTATE, 0);
 415         local_irq_enable();
 416         while (!need_resched())
 417                 cpu_relax();
 418         trace_power_end(0);
 419 }
 420
 421 /*
 422  * mwait selection logic:
 423  *
 424  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 425  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 426  * then depend on a clock divisor and current Pstate of the core. If
 427  * all cores of a processor are in halt state (C1) the processor can
 428  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 429  * happen.
 430  *
 431  * idle=mwait overrides this decision and forces the usage of mwait.
 432  */
 433 static int __cpuinitdata force_mwait;
 434
 435 #define MWAIT_INFO                      0x05
 436 #define MWAIT_ECX_EXTENDED_INFO         0x01
 437 #define MWAIT_EDX_C1                    0xf0
 438
 439 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 440 {
 441         u32 eax, ebx, ecx, edx;
 442
 443         if (force_mwait)
 444                 return 1;
 445
 446         if (c->cpuid_level < MWAIT_INFO)
 447                 return 0;
 448
 449         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 450         /* Check, whether EDX has extended info about MWAIT */
 451         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 452                 return 1;
 453
 454         /*
 455          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 456          * C1  supports MWAIT
 457          */
 458         return (edx & MWAIT_EDX_C1);
 459 }
 460
 461 /*
 462  * Check for AMD CPUs, which have potentially C1E support
 463  */
 464 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 465 {
 466         if (c->x86_vendor != X86_VENDOR_AMD)
 467                 return 0;
 468
 469         if (c->x86 < 0x0F)
 470                 return 0;
 471
 472         /* Family 0x0f models < rev F do not have C1E */
 473         if (c->x86 == 0x0f && c->x86_model < 0x40)
 474                 return 0;
 475
 476         return 1;
 477 }
 478
 479 static cpumask_var_t c1e_mask;
 480 static int c1e_detected;
 481
 482 void c1e_remove_cpu(int cpu)
 483 {
 484         if (c1e_mask != NULL)
 485                 cpumask_clear_cpu(cpu, c1e_mask);
 486 }
 487
 488 /*
 489  * C1E aware idle routine. We check for C1E active in the interrupt
 490  * pending message MSR. If we detect C1E, then we handle it the same
 491  * way as C3 power states (local apic timer and TSC stop)
 492  */
 493 static void c1e_idle(void)
 494 {
 495         if (need_resched())
 496                 return;
 497
 498         if (!c1e_detected) {
 499                 u32 lo, hi;
 500
 501                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 502                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 503                         c1e_detected = 1;
 504                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 505                                 mark_tsc_unstable("TSC halt in AMD C1E");
 506                         printk(KERN_INFO "System has AMD C1E enabled\n");
 507                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
 508                 }
 509         }
 510
 511         if (c1e_detected) {
 512                 int cpu = smp_processor_id();
 513
 514                 if (!cpumask_test_cpu(cpu, c1e_mask)) {
 515                         cpumask_set_cpu(cpu, c1e_mask);
 516                         /*
 517                          * Force broadcast so ACPI can not interfere.
 518                          */
 519                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 520                                            &cpu);
 521                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
 522                                cpu);
 523                 }
 524                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 525
 526                 default_idle();
 527
 528                 /*
 529                  * The switch back from broadcast mode needs to be
 530                  * called with interrupts disabled.
 531                  */
 532                  local_irq_disable();
 533                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 534                  local_irq_enable();
 535         } else
 536                 default_idle();
 537 }
 538
 539 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 540 {
 541 #ifdef CONFIG_SMP
 542         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 543                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
 544                         " performance may degrade.\n");
 545         }
 546 #endif
 547         if (pm_idle)
 548                 return;
 549
 550         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 551                 /*
 552                  * One CPU supports mwait => All CPUs supports mwait
 553                  */
 554                 printk(KERN_INFO "using mwait in idle threads.\n");
 555                 pm_idle = mwait_idle;
 556         } else if (check_c1e_idle(c)) {
 557                 printk(KERN_INFO "using C1E aware idle routine\n");
 558                 pm_idle = c1e_idle;
 559         } else
 560                 pm_idle = default_idle;
 561 }
 562
 563 void __init init_c1e_mask(void)
 564 {
 565         /* If we're using c1e_idle, we need to allocate c1e_mask. */
 566         if (pm_idle == c1e_idle)
 567                 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
 568 }
 569
 570 static int __init idle_setup(char *str)
 571 {
 572         if (!str)
 573                 return -EINVAL;
 574
 575         if (!strcmp(str, "poll")) {
 576                 printk("using polling idle threads.\n");
 577                 pm_idle = poll_idle;
 578         } else if (!strcmp(str, "mwait"))
 579                 force_mwait = 1;
 580         else if (!strcmp(str, "halt")) {
 581                 /*
 582                  * When the boot option of idle=halt is added, halt is
 583                  * forced to be used for CPU idle. In such case CPU C2/C3
 584                  * won't be used again.
 585                  * To continue to load the CPU idle driver, don't touch
 586                  * the boot_option_idle_override.
 587                  */
 588                 pm_idle = default_idle;
 589                 idle_halt = 1;
 590                 return 0;
 591         } else if (!strcmp(str, "nomwait")) {
 592                 /*
 593                  * If the boot option of "idle=nomwait" is added,
 594                  * it means that mwait will be disabled for CPU C2/C3
 595                  * states. In such case it won't touch the variable
 596                  * of boot_option_idle_override.
 597                  */
 598                 idle_nomwait = 1;
 599                 return 0;
 600         } else
 601                 return -1;
 602
 603         boot_option_idle_override = 1;
 604         return 0;
 605 }
 606 early_param("idle", idle_setup);
 607
 608 unsigned long arch_align_stack(unsigned long sp)
 609 {
 610         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 611                 sp -= get_random_int() % 8192;
 612         return sp & ~0xf;
 613 }
 614
 615 unsigned long arch_randomize_brk(struct mm_struct *mm)
 616 {
 617         unsigned long range_end = mm->brk + 0x02000000;
 618         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 619 }
 620