arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/crash_dump.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <linux/scatterlist.h>
  39 #include <linux/iommu-helper.h>
  40
  41 #include <asm/iommu.h>
  42 #include <asm/calgary.h>
  43 #include <asm/tce.h>
  44 #include <asm/pci-direct.h>
  45 #include <asm/system.h>
  46 #include <asm/dma.h>
  47 #include <asm/rio.h>
  48 #include <asm/bios_ebda.h>
  49
  50 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  51 int use_calgary __read_mostly = 1;
  52 #else
  53 int use_calgary __read_mostly = 0;
  54 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  55
  56 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  57 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  58
  59 /* register offsets inside the host bridge space */
  60 #define CALGARY_CONFIG_REG      0x0108
  61 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  62 #define PHB_PLSSR_OFFSET        0x0120
  63 #define PHB_CONFIG_RW_OFFSET    0x0160
  64 #define PHB_IOBASE_BAR_LOW      0x0170
  65 #define PHB_IOBASE_BAR_HIGH     0x0180
  66 #define PHB_MEM_1_LOW           0x0190
  67 #define PHB_MEM_1_HIGH          0x01A0
  68 #define PHB_IO_ADDR_SIZE        0x01B0
  69 #define PHB_MEM_1_SIZE          0x01C0
  70 #define PHB_MEM_ST_OFFSET       0x01D0
  71 #define PHB_AER_OFFSET          0x0200
  72 #define PHB_CONFIG_0_HIGH       0x0220
  73 #define PHB_CONFIG_0_LOW        0x0230
  74 #define PHB_CONFIG_0_END        0x0240
  75 #define PHB_MEM_2_LOW           0x02B0
  76 #define PHB_MEM_2_HIGH          0x02C0
  77 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  78 #define PHB_MEM_2_SIZE_LOW      0x02E0
  79 #define PHB_DOSHOLE_OFFSET      0x08E0
  80
  81 /* CalIOC2 specific */
  82 #define PHB_SAVIOR_L2           0x0DB0
  83 #define PHB_PAGE_MIG_CTRL       0x0DA8
  84 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  85 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  86
  87 /* PHB_CONFIG_RW */
  88 #define PHB_TCE_ENABLE          0x20000000
  89 #define PHB_SLOT_DISABLE        0x1C000000
  90 #define PHB_DAC_DISABLE         0x01000000
  91 #define PHB_MEM2_ENABLE         0x00400000
  92 #define PHB_MCSR_ENABLE         0x00100000
  93 /* TAR (Table Address Register) */
  94 #define TAR_SW_BITS             0x0000ffffffff800fUL
  95 #define TAR_VALID               0x0000000000000008UL
  96 /* CSR (Channel/DMA Status Register) */
  97 #define CSR_AGENT_MASK          0xffe0ffff
  98 /* CCR (Calgary Configuration Register) */
  99 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
 100 /* PMCR/PMDR (Page Migration Control/Debug Registers */
 101 #define PMR_SOFTSTOP            0x80000000
 102 #define PMR_SOFTSTOPFAULT       0x40000000
 103 #define PMR_HARDSTOP            0x20000000
 104
 105 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 106 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 107 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 108 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 109 #define PHBS_PER_CALGARY        4
 110
 111 /* register offsets in Calgary's internal register space */
 112 static const unsigned long tar_offsets[] = {
 113         0x0580 /* TAR0 */,
 114         0x0588 /* TAR1 */,
 115         0x0590 /* TAR2 */,
 116         0x0598 /* TAR3 */
 117 };
 118
 119 static const unsigned long split_queue_offsets[] = {
 120         0x4870 /* SPLIT QUEUE 0 */,
 121         0x5870 /* SPLIT QUEUE 1 */,
 122         0x6870 /* SPLIT QUEUE 2 */,
 123         0x7870 /* SPLIT QUEUE 3 */
 124 };
 125
 126 static const unsigned long phb_offsets[] = {
 127         0x8000 /* PHB0 */,
 128         0x9000 /* PHB1 */,
 129         0xA000 /* PHB2 */,
 130         0xB000 /* PHB3 */
 131 };
 132
 133 /* PHB debug registers */
 134
 135 static const unsigned long phb_debug_offsets[] = {
 136         0x4000  /* PHB 0 DEBUG */,
 137         0x5000  /* PHB 1 DEBUG */,
 138         0x6000  /* PHB 2 DEBUG */,
 139         0x7000  /* PHB 3 DEBUG */
 140 };
 141
 142 /*
 143  * STUFF register for each debug PHB,
 144  * byte 1 = start bus number, byte 2 = end bus number
 145  */
 146
 147 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 148
 149 #define EMERGENCY_PAGES 32 /* = 128KB */
 150
 151 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 152 static int translate_empty_slots __read_mostly = 0;
 153 static int calgary_detected __read_mostly = 0;
 154
 155 static struct rio_table_hdr     *rio_table_hdr __initdata;
 156 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 157 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 158
 159 struct calgary_bus_info {
 160         void *tce_space;
 161         unsigned char translation_disabled;
 162         signed char phbid;
 163         void __iomem *bbar;
 164 };
 165
 166 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 167 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 168 static void calgary_dump_error_regs(struct iommu_table *tbl);
 169 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 170 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 171 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 172 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 173 static void get_tce_space_from_tar(void);
 174
 175 static struct cal_chipset_ops calgary_chip_ops = {
 176         .handle_quirks = calgary_handle_quirks,
 177         .tce_cache_blast = calgary_tce_cache_blast,
 178         .dump_error_regs = calgary_dump_error_regs
 179 };
 180
 181 static struct cal_chipset_ops calioc2_chip_ops = {
 182         .handle_quirks = calioc2_handle_quirks,
 183         .tce_cache_blast = calioc2_tce_cache_blast,
 184         .dump_error_regs = calioc2_dump_error_regs
 185 };
 186
 187 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 188
 189 /* enable this to stress test the chip's TCE cache */
 190 #ifdef CONFIG_IOMMU_DEBUG
 191 static int debugging = 1;
 192
 193 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 194         int expected, unsigned long start, unsigned long end)
 195 {
 196         unsigned long idx = start;
 197
 198         BUG_ON(start >= end);
 199
 200         while (idx < end) {
 201                 if (!!test_bit(idx, bitmap) != expected)
 202                         return idx;
 203                 ++idx;
 204         }
 205
 206         /* all bits have the expected value */
 207         return ~0UL;
 208 }
 209 #else /* debugging is disabled */
 210 static int debugging;
 211
 212 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 213         int expected, unsigned long start, unsigned long end)
 214 {
 215         return ~0UL;
 216 }
 217
 218 #endif /* CONFIG_IOMMU_DEBUG */
 219
 220 static inline int translation_enabled(struct iommu_table *tbl)
 221 {
 222         /* only PHBs with translation enabled have an IOMMU table */
 223         return (tbl != NULL);
 224 }
 225
 226 static void iommu_range_reserve(struct iommu_table *tbl,
 227         unsigned long start_addr, unsigned int npages)
 228 {
 229         unsigned long index;
 230         unsigned long end;
 231         unsigned long badbit;
 232         unsigned long flags;
 233
 234         index = start_addr >> PAGE_SHIFT;
 235
 236         /* bail out if we're asked to reserve a region we don't cover */
 237         if (index >= tbl->it_size)
 238                 return;
 239
 240         end = index + npages;
 241         if (end > tbl->it_size) /* don't go off the table */
 242                 end = tbl->it_size;
 243
 244         spin_lock_irqsave(&tbl->it_lock, flags);
 245
 246         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 247         if (badbit != ~0UL) {
 248                 if (printk_ratelimit())
 249                         printk(KERN_ERR "Calgary: entry already allocated at "
 250                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 251                                badbit, tbl, start_addr, npages);
 252         }
 253
 254         iommu_area_reserve(tbl->it_map, index, npages);
 255
 256         spin_unlock_irqrestore(&tbl->it_lock, flags);
 257 }
 258
 259 static unsigned long iommu_range_alloc(struct device *dev,
 260                                        struct iommu_table *tbl,
 261                                        unsigned int npages)
 262 {
 263         unsigned long flags;
 264         unsigned long offset;
 265         unsigned long boundary_size;
 266
 267         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 268                               PAGE_SIZE) >> PAGE_SHIFT;
 269
 270         BUG_ON(npages == 0);
 271
 272         spin_lock_irqsave(&tbl->it_lock, flags);
 273
 274         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 275                                   npages, 0, boundary_size, 0);
 276         if (offset == ~0UL) {
 277                 tbl->chip_ops->tce_cache_blast(tbl);
 278
 279                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 280                                           npages, 0, boundary_size, 0);
 281                 if (offset == ~0UL) {
 282                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 283                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 284                         if (panic_on_overflow)
 285                                 panic("Calgary: fix the allocator.\n");
 286                         else
 287                                 return bad_dma_address;
 288                 }
 289         }
 290
 291         tbl->it_hint = offset + npages;
 292         BUG_ON(tbl->it_hint > tbl->it_size);
 293
 294         spin_unlock_irqrestore(&tbl->it_lock, flags);
 295
 296         return offset;
 297 }
 298
 299 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 300                               void *vaddr, unsigned int npages, int direction)
 301 {
 302         unsigned long entry;
 303         dma_addr_t ret = bad_dma_address;
 304
 305         entry = iommu_range_alloc(dev, tbl, npages);
 306
 307         if (unlikely(entry == bad_dma_address))
 308                 goto error;
 309
 310         /* set the return dma address */
 311         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 312
 313         /* put the TCEs in the HW table */
 314         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 315                   direction);
 316
 317         return ret;
 318
 319 error:
 320         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 321                "iommu %p\n", npages, tbl);
 322         return bad_dma_address;
 323 }
 324
 325 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 326         unsigned int npages)
 327 {
 328         unsigned long entry;
 329         unsigned long badbit;
 330         unsigned long badend;
 331         unsigned long flags;
 332
 333         /* were we called with bad_dma_address? */
 334         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 335         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 336                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
 337                        "address 0x%Lx\n", dma_addr);
 338                 return;
 339         }
 340
 341         entry = dma_addr >> PAGE_SHIFT;
 342
 343         BUG_ON(entry + npages > tbl->it_size);
 344
 345         tce_free(tbl, entry, npages);
 346
 347         spin_lock_irqsave(&tbl->it_lock, flags);
 348
 349         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 350         if (badbit != ~0UL) {
 351                 if (printk_ratelimit())
 352                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 353                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 354                                badbit, tbl, dma_addr, entry, npages);
 355         }
 356
 357         iommu_area_free(tbl->it_map, entry, npages);
 358
 359         spin_unlock_irqrestore(&tbl->it_lock, flags);
 360 }
 361
 362 static inline struct iommu_table *find_iommu_table(struct device *dev)
 363 {
 364         struct pci_dev *pdev;
 365         struct pci_bus *pbus;
 366         struct iommu_table *tbl;
 367
 368         pdev = to_pci_dev(dev);
 369
 370         pbus = pdev->bus;
 371
 372         /* is the device behind a bridge? Look for the root bus */
 373         while (pbus->parent)
 374                 pbus = pbus->parent;
 375
 376         tbl = pci_iommu(pbus);
 377
 378         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 379
 380         return tbl;
 381 }
 382
 383 static void calgary_unmap_sg(struct device *dev,
 384         struct scatterlist *sglist, int nelems, int direction)
 385 {
 386         struct iommu_table *tbl = find_iommu_table(dev);
 387         struct scatterlist *s;
 388         int i;
 389
 390         if (!translation_enabled(tbl))
 391                 return;
 392
 393         for_each_sg(sglist, s, nelems, i) {
 394                 unsigned int npages;
 395                 dma_addr_t dma = s->dma_address;
 396                 unsigned int dmalen = s->dma_length;
 397
 398                 if (dmalen == 0)
 399                         break;
 400
 401                 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
 402                 iommu_free(tbl, dma, npages);
 403         }
 404 }
 405
 406 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 407         int nelems, int direction)
 408 {
 409         struct iommu_table *tbl = find_iommu_table(dev);
 410         struct scatterlist *s;
 411         unsigned long vaddr;
 412         unsigned int npages;
 413         unsigned long entry;
 414         int i;
 415
 416         for_each_sg(sg, s, nelems, i) {
 417                 BUG_ON(!sg_page(s));
 418
 419                 vaddr = (unsigned long) sg_virt(s);
 420                 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
 421
 422                 entry = iommu_range_alloc(dev, tbl, npages);
 423                 if (entry == bad_dma_address) {
 424                         /* makes sure unmap knows to stop */
 425                         s->dma_length = 0;
 426                         goto error;
 427                 }
 428
 429                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 430
 431                 /* insert into HW table */
 432                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 433                           direction);
 434
 435                 s->dma_length = s->length;
 436         }
 437
 438         return nelems;
 439 error:
 440         calgary_unmap_sg(dev, sg, nelems, direction);
 441         for_each_sg(sg, s, nelems, i) {
 442                 sg->dma_address = bad_dma_address;
 443                 sg->dma_length = 0;
 444         }
 445         return 0;
 446 }
 447
 448 static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
 449                                    unsigned long offset, size_t size,
 450                                    enum dma_data_direction dir,
 451                                    struct dma_attrs *attrs)
 452 {
 453         void *vaddr = page_address(page) + offset;
 454         unsigned long uaddr;
 455         unsigned int npages;
 456         struct iommu_table *tbl = find_iommu_table(dev);
 457
 458         uaddr = (unsigned long)vaddr;
 459         npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
 460
 461         return iommu_alloc(dev, tbl, vaddr, npages, dir);
 462 }
 463
 464 static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr,
 465                                      size_t size, int direction)
 466 {
 467         return calgary_map_page(dev, pfn_to_page(paddr >> PAGE_SHIFT),
 468                                 paddr & ~PAGE_MASK, size,
 469                                 direction, NULL);
 470 }
 471
 472 static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
 473                                size_t size, enum dma_data_direction dir,
 474                                struct dma_attrs *attrs)
 475 {
 476         struct iommu_table *tbl = find_iommu_table(dev);
 477         unsigned int npages;
 478
 479         npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
 480         iommu_free(tbl, dma_addr, npages);
 481 }
 482
 483 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 484                                  size_t size, int direction)
 485 {
 486         calgary_unmap_page(dev, dma_handle, size, direction, NULL);
 487 }
 488
 489 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 490         dma_addr_t *dma_handle, gfp_t flag)
 491 {
 492         void *ret = NULL;
 493         dma_addr_t mapping;
 494         unsigned int npages, order;
 495         struct iommu_table *tbl = find_iommu_table(dev);
 496
 497         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 498         npages = size >> PAGE_SHIFT;
 499         order = get_order(size);
 500
 501         flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
 502
 503         /* alloc enough pages (and possibly more) */
 504         ret = (void *)__get_free_pages(flag, order);
 505         if (!ret)
 506                 goto error;
 507         memset(ret, 0, size);
 508
 509         /* set up tces to cover the allocated range */
 510         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 511         if (mapping == bad_dma_address)
 512                 goto free;
 513         *dma_handle = mapping;
 514         return ret;
 515 free:
 516         free_pages((unsigned long)ret, get_order(size));
 517         ret = NULL;
 518 error:
 519         return ret;
 520 }
 521
 522 static void calgary_free_coherent(struct device *dev, size_t size,
 523                                   void *vaddr, dma_addr_t dma_handle)
 524 {
 525         unsigned int npages;
 526         struct iommu_table *tbl = find_iommu_table(dev);
 527
 528         size = PAGE_ALIGN(size);
 529         npages = size >> PAGE_SHIFT;
 530
 531         iommu_free(tbl, dma_handle, npages);
 532         free_pages((unsigned long)vaddr, get_order(size));
 533 }
 534
 535 static struct dma_mapping_ops calgary_dma_ops = {
 536         .alloc_coherent = calgary_alloc_coherent,
 537         .free_coherent = calgary_free_coherent,
 538         .map_single = calgary_map_single,
 539         .unmap_single = calgary_unmap_single,
 540         .map_sg = calgary_map_sg,
 541         .unmap_sg = calgary_unmap_sg,
 542         .map_page = calgary_map_page,
 543         .unmap_page = calgary_unmap_page,
 544 };
 545
 546 static inline void __iomem * busno_to_bbar(unsigned char num)
 547 {
 548         return bus_info[num].bbar;
 549 }
 550
 551 static inline int busno_to_phbid(unsigned char num)
 552 {
 553         return bus_info[num].phbid;
 554 }
 555
 556 static inline unsigned long split_queue_offset(unsigned char num)
 557 {
 558         size_t idx = busno_to_phbid(num);
 559
 560         return split_queue_offsets[idx];
 561 }
 562
 563 static inline unsigned long tar_offset(unsigned char num)
 564 {
 565         size_t idx = busno_to_phbid(num);
 566
 567         return tar_offsets[idx];
 568 }
 569
 570 static inline unsigned long phb_offset(unsigned char num)
 571 {
 572         size_t idx = busno_to_phbid(num);
 573
 574         return phb_offsets[idx];
 575 }
 576
 577 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 578 {
 579         unsigned long target = ((unsigned long)bar) | offset;
 580         return (void __iomem*)target;
 581 }
 582
 583 static inline int is_calioc2(unsigned short device)
 584 {
 585         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 586 }
 587
 588 static inline int is_calgary(unsigned short device)
 589 {
 590         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 591 }
 592
 593 static inline int is_cal_pci_dev(unsigned short device)
 594 {
 595         return (is_calgary(device) || is_calioc2(device));
 596 }
 597
 598 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 599 {
 600         u64 val;
 601         u32 aer;
 602         int i = 0;
 603         void __iomem *bbar = tbl->bbar;
 604         void __iomem *target;
 605
 606         /* disable arbitration on the bus */
 607         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 608         aer = readl(target);
 609         writel(0, target);
 610
 611         /* read plssr to ensure it got there */
 612         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 613         val = readl(target);
 614
 615         /* poll split queues until all DMA activity is done */
 616         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 617         do {
 618                 val = readq(target);
 619                 i++;
 620         } while ((val & 0xff) != 0xff && i < 100);
 621         if (i == 100)
 622                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 623                        "continuing anyway\n");
 624
 625         /* invalidate TCE cache */
 626         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 627         writeq(tbl->tar_val, target);
 628
 629         /* enable arbitration */
 630         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 631         writel(aer, target);
 632         (void)readl(target); /* flush */
 633 }
 634
 635 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 636 {
 637         void __iomem *bbar = tbl->bbar;
 638         void __iomem *target;
 639         u64 val64;
 640         u32 val;
 641         int i = 0;
 642         int count = 1;
 643         unsigned char bus = tbl->it_busno;
 644
 645 begin:
 646         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 647                "sequence - count %d\n", bus, count);
 648
 649         /* 1. using the Page Migration Control reg set SoftStop */
 650         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 651         val = be32_to_cpu(readl(target));
 652         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 653         val |= PMR_SOFTSTOP;
 654         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 655         writel(cpu_to_be32(val), target);
 656
 657         /* 2. poll split queues until all DMA activity is done */
 658         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 659         target = calgary_reg(bbar, split_queue_offset(bus));
 660         do {
 661                 val64 = readq(target);
 662                 i++;
 663         } while ((val64 & 0xff) != 0xff && i < 100);
 664         if (i == 100)
 665                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 666                        "continuing anyway\n");
 667
 668         /* 3. poll Page Migration DEBUG for SoftStopFault */
 669         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 670         val = be32_to_cpu(readl(target));
 671         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 672
 673         /* 4. if SoftStopFault - goto (1) */
 674         if (val & PMR_SOFTSTOPFAULT) {
 675                 if (++count < 100)
 676                         goto begin;
 677                 else {
 678                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 679                                "aborting TCE cache flush sequence!\n");
 680                         return; /* pray for the best */
 681                 }
 682         }
 683
 684         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 685         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 686         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 687         val = be32_to_cpu(readl(target));
 688         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 689         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 690         val = be32_to_cpu(readl(target));
 691         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 692
 693         /* 6. invalidate TCE cache */
 694         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 695         target = calgary_reg(bbar, tar_offset(bus));
 696         writeq(tbl->tar_val, target);
 697
 698         /* 7. Re-read PMCR */
 699         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 700         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 701         val = be32_to_cpu(readl(target));
 702         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 703
 704         /* 8. Remove HardStop */
 705         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 706         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 707         val = 0;
 708         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 709         writel(cpu_to_be32(val), target);
 710         val = be32_to_cpu(readl(target));
 711         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 712 }
 713
 714 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 715         u64 limit)
 716 {
 717         unsigned int numpages;
 718
 719         limit = limit | 0xfffff;
 720         limit++;
 721
 722         numpages = ((limit - start) >> PAGE_SHIFT);
 723         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 724 }
 725
 726 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 727 {
 728         void __iomem *target;
 729         u64 low, high, sizelow;
 730         u64 start, limit;
 731         struct iommu_table *tbl = pci_iommu(dev->bus);
 732         unsigned char busnum = dev->bus->number;
 733         void __iomem *bbar = tbl->bbar;
 734
 735         /* peripheral MEM_1 region */
 736         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 737         low = be32_to_cpu(readl(target));
 738         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 739         high = be32_to_cpu(readl(target));
 740         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 741         sizelow = be32_to_cpu(readl(target));
 742
 743         start = (high << 32) | low;
 744         limit = sizelow;
 745
 746         calgary_reserve_mem_region(dev, start, limit);
 747 }
 748
 749 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 750 {
 751         void __iomem *target;
 752         u32 val32;
 753         u64 low, high, sizelow, sizehigh;
 754         u64 start, limit;
 755         struct iommu_table *tbl = pci_iommu(dev->bus);
 756         unsigned char busnum = dev->bus->number;
 757         void __iomem *bbar = tbl->bbar;
 758
 759         /* is it enabled? */
 760         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 761         val32 = be32_to_cpu(readl(target));
 762         if (!(val32 & PHB_MEM2_ENABLE))
 763                 return;
 764
 765         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 766         low = be32_to_cpu(readl(target));
 767         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 768         high = be32_to_cpu(readl(target));
 769         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 770         sizelow = be32_to_cpu(readl(target));
 771         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 772         sizehigh = be32_to_cpu(readl(target));
 773
 774         start = (high << 32) | low;
 775         limit = (sizehigh << 32) | sizelow;
 776
 777         calgary_reserve_mem_region(dev, start, limit);
 778 }
 779
 780 /*
 781  * some regions of the IO address space do not get translated, so we
 782  * must not give devices IO addresses in those regions. The regions
 783  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 784  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 785  * later.
 786  */
 787 static void __init calgary_reserve_regions(struct pci_dev *dev)
 788 {
 789         unsigned int npages;
 790         u64 start;
 791         struct iommu_table *tbl = pci_iommu(dev->bus);
 792
 793         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 794         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 795
 796         /* avoid the BIOS/VGA first 640KB-1MB region */
 797         /* for CalIOC2 - avoid the entire first MB */
 798         if (is_calgary(dev->device)) {
 799                 start = (640 * 1024);
 800                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 801         } else { /* calioc2 */
 802                 start = 0;
 803                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 804         }
 805         iommu_range_reserve(tbl, start, npages);
 806
 807         /* reserve the two PCI peripheral memory regions in IO space */
 808         calgary_reserve_peripheral_mem_1(dev);
 809         calgary_reserve_peripheral_mem_2(dev);
 810 }
 811
 812 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 813 {
 814         u64 val64;
 815         u64 table_phys;
 816         void __iomem *target;
 817         int ret;
 818         struct iommu_table *tbl;
 819
 820         /* build TCE tables for each PHB */
 821         ret = build_tce_table(dev, bbar);
 822         if (ret)
 823                 return ret;
 824
 825         tbl = pci_iommu(dev->bus);
 826         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 827
 828         if (is_kdump_kernel())
 829                 calgary_init_bitmap_from_tce_table(tbl);
 830         else
 831                 tce_free(tbl, 0, tbl->it_size);
 832
 833         if (is_calgary(dev->device))
 834                 tbl->chip_ops = &calgary_chip_ops;
 835         else if (is_calioc2(dev->device))
 836                 tbl->chip_ops = &calioc2_chip_ops;
 837         else
 838                 BUG();
 839
 840         calgary_reserve_regions(dev);
 841
 842         /* set TARs for each PHB */
 843         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 844         val64 = be64_to_cpu(readq(target));
 845
 846         /* zero out all TAR bits under sw control */
 847         val64 &= ~TAR_SW_BITS;
 848         table_phys = (u64)__pa(tbl->it_base);
 849
 850         val64 |= table_phys;
 851
 852         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 853         val64 |= (u64) specified_table_size;
 854
 855         tbl->tar_val = cpu_to_be64(val64);
 856
 857         writeq(tbl->tar_val, target);
 858         readq(target); /* flush */
 859
 860         return 0;
 861 }
 862
 863 static void __init calgary_free_bus(struct pci_dev *dev)
 864 {
 865         u64 val64;
 866         struct iommu_table *tbl = pci_iommu(dev->bus);
 867         void __iomem *target;
 868         unsigned int bitmapsz;
 869
 870         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 871         val64 = be64_to_cpu(readq(target));
 872         val64 &= ~TAR_SW_BITS;
 873         writeq(cpu_to_be64(val64), target);
 874         readq(target); /* flush */
 875
 876         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 877         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 878         tbl->it_map = NULL;
 879
 880         kfree(tbl);
 881
 882         set_pci_iommu(dev->bus, NULL);
 883
 884         /* Can't free bootmem allocated memory after system is up :-( */
 885         bus_info[dev->bus->number].tce_space = NULL;
 886 }
 887
 888 static void calgary_dump_error_regs(struct iommu_table *tbl)
 889 {
 890         void __iomem *bbar = tbl->bbar;
 891         void __iomem *target;
 892         u32 csr, plssr;
 893
 894         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 895         csr = be32_to_cpu(readl(target));
 896
 897         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 898         plssr = be32_to_cpu(readl(target));
 899
 900         /* If no error, the agent ID in the CSR is not valid */
 901         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 902                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 903 }
 904
 905 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 906 {
 907         void __iomem *bbar = tbl->bbar;
 908         u32 csr, csmr, plssr, mck, rcstat;
 909         void __iomem *target;
 910         unsigned long phboff = phb_offset(tbl->it_busno);
 911         unsigned long erroff;
 912         u32 errregs[7];
 913         int i;
 914
 915         /* dump CSR */
 916         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 917         csr = be32_to_cpu(readl(target));
 918         /* dump PLSSR */
 919         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 920         plssr = be32_to_cpu(readl(target));
 921         /* dump CSMR */
 922         target = calgary_reg(bbar, phboff | 0x290);
 923         csmr = be32_to_cpu(readl(target));
 924         /* dump mck */
 925         target = calgary_reg(bbar, phboff | 0x800);
 926         mck = be32_to_cpu(readl(target));
 927
 928         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 929                tbl->it_busno);
 930
 931         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 932                csr, plssr, csmr, mck);
 933
 934         /* dump rest of error regs */
 935         printk(KERN_EMERG "Calgary: ");
 936         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 937                 /* err regs are at 0x810 - 0x870 */
 938                 erroff = (0x810 + (i * 0x10));
 939                 target = calgary_reg(bbar, phboff | erroff);
 940                 errregs[i] = be32_to_cpu(readl(target));
 941                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 942         }
 943         printk("\n");
 944
 945         /* root complex status */
 946         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 947         rcstat = be32_to_cpu(readl(target));
 948         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 949                PHB_ROOT_COMPLEX_STATUS);
 950 }
 951
 952 static void calgary_watchdog(unsigned long data)
 953 {
 954         struct pci_dev *dev = (struct pci_dev *)data;
 955         struct iommu_table *tbl = pci_iommu(dev->bus);
 956         void __iomem *bbar = tbl->bbar;
 957         u32 val32;
 958         void __iomem *target;
 959
 960         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 961         val32 = be32_to_cpu(readl(target));
 962
 963         /* If no error, the agent ID in the CSR is not valid */
 964         if (val32 & CSR_AGENT_MASK) {
 965                 tbl->chip_ops->dump_error_regs(tbl);
 966
 967                 /* reset error */
 968                 writel(0, target);
 969
 970                 /* Disable bus that caused the error */
 971                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 972                                      PHB_CONFIG_RW_OFFSET);
 973                 val32 = be32_to_cpu(readl(target));
 974                 val32 |= PHB_SLOT_DISABLE;
 975                 writel(cpu_to_be32(val32), target);
 976                 readl(target); /* flush */
 977         } else {
 978                 /* Reset the timer */
 979                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 980         }
 981 }
 982
 983 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 984         unsigned char busnum, unsigned long timeout)
 985 {
 986         u64 val64;
 987         void __iomem *target;
 988         unsigned int phb_shift = ~0; /* silence gcc */
 989         u64 mask;
 990
 991         switch (busno_to_phbid(busnum)) {
 992         case 0: phb_shift = (63 - 19);
 993                 break;
 994         case 1: phb_shift = (63 - 23);
 995                 break;
 996         case 2: phb_shift = (63 - 27);
 997                 break;
 998         case 3: phb_shift = (63 - 35);
 999                 break;
1000         default:
1001                 BUG_ON(busno_to_phbid(busnum));
1002         }
1003
1004         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
1005         val64 = be64_to_cpu(readq(target));
1006
1007         /* zero out this PHB's timer bits */
1008         mask = ~(0xFUL << phb_shift);
1009         val64 &= mask;
1010         val64 |= (timeout << phb_shift);
1011         writeq(cpu_to_be64(val64), target);
1012         readq(target); /* flush */
1013 }
1014
1015 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1016 {
1017         unsigned char busnum = dev->bus->number;
1018         void __iomem *bbar = tbl->bbar;
1019         void __iomem *target;
1020         u32 val;
1021
1022         /*
1023          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1024          */
1025         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1026         val = cpu_to_be32(readl(target));
1027         val |= 0x00800000;
1028         writel(cpu_to_be32(val), target);
1029 }
1030
1031 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1032 {
1033         unsigned char busnum = dev->bus->number;
1034
1035         /*
1036          * Give split completion a longer timeout on bus 1 for aic94xx
1037          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1038          */
1039         if (is_calgary(dev->device) && (busnum == 1))
1040                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1041                                                      CCR_2SEC_TIMEOUT);
1042 }
1043
1044 static void __init calgary_enable_translation(struct pci_dev *dev)
1045 {
1046         u32 val32;
1047         unsigned char busnum;
1048         void __iomem *target;
1049         void __iomem *bbar;
1050         struct iommu_table *tbl;
1051
1052         busnum = dev->bus->number;
1053         tbl = pci_iommu(dev->bus);
1054         bbar = tbl->bbar;
1055
1056         /* enable TCE in PHB Config Register */
1057         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1058         val32 = be32_to_cpu(readl(target));
1059         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1060
1061         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1062                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1063                "Calgary" : "CalIOC2", busnum);
1064         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1065                "bus.\n");
1066
1067         writel(cpu_to_be32(val32), target);
1068         readl(target); /* flush */
1069
1070         init_timer(&tbl->watchdog_timer);
1071         tbl->watchdog_timer.function = &calgary_watchdog;
1072         tbl->watchdog_timer.data = (unsigned long)dev;
1073         mod_timer(&tbl->watchdog_timer, jiffies);
1074 }
1075
1076 static void __init calgary_disable_translation(struct pci_dev *dev)
1077 {
1078         u32 val32;
1079         unsigned char busnum;
1080         void __iomem *target;
1081         void __iomem *bbar;
1082         struct iommu_table *tbl;
1083
1084         busnum = dev->bus->number;
1085         tbl = pci_iommu(dev->bus);
1086         bbar = tbl->bbar;
1087
1088         /* disable TCE in PHB Config Register */
1089         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1090         val32 = be32_to_cpu(readl(target));
1091         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1092
1093         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1094         writel(cpu_to_be32(val32), target);
1095         readl(target); /* flush */
1096
1097         del_timer_sync(&tbl->watchdog_timer);
1098 }
1099
1100 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1101 {
1102         pci_dev_get(dev);
1103         set_pci_iommu(dev->bus, NULL);
1104
1105         /* is the device behind a bridge? */
1106         if (dev->bus->parent)
1107                 dev->bus->parent->self = dev;
1108         else
1109                 dev->bus->self = dev;
1110 }
1111
1112 static int __init calgary_init_one(struct pci_dev *dev)
1113 {
1114         void __iomem *bbar;
1115         struct iommu_table *tbl;
1116         int ret;
1117
1118         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1119
1120         bbar = busno_to_bbar(dev->bus->number);
1121         ret = calgary_setup_tar(dev, bbar);
1122         if (ret)
1123                 goto done;
1124
1125         pci_dev_get(dev);
1126
1127         if (dev->bus->parent) {
1128                 if (dev->bus->parent->self)
1129                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1130                                "bus->parent->self!\n", dev);
1131                 dev->bus->parent->self = dev;
1132         } else
1133                 dev->bus->self = dev;
1134
1135         tbl = pci_iommu(dev->bus);
1136         tbl->chip_ops->handle_quirks(tbl, dev);
1137
1138         calgary_enable_translation(dev);
1139
1140         return 0;
1141
1142 done:
1143         return ret;
1144 }
1145
1146 static int __init calgary_locate_bbars(void)
1147 {
1148         int ret;
1149         int rioidx, phb, bus;
1150         void __iomem *bbar;
1151         void __iomem *target;
1152         unsigned long offset;
1153         u8 start_bus, end_bus;
1154         u32 val;
1155
1156         ret = -ENODATA;
1157         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1158                 struct rio_detail *rio = rio_devs[rioidx];
1159
1160                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1161                         continue;
1162
1163                 /* map entire 1MB of Calgary config space */
1164                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1165                 if (!bbar)
1166                         goto error;
1167
1168                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1169                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1170                         target = calgary_reg(bbar, offset);
1171
1172                         val = be32_to_cpu(readl(target));
1173
1174                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1175                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1176
1177                         if (end_bus) {
1178                                 for (bus = start_bus; bus <= end_bus; bus++) {
1179                                         bus_info[bus].bbar = bbar;
1180                                         bus_info[bus].phbid = phb;
1181                                 }
1182                         } else {
1183                                 bus_info[start_bus].bbar = bbar;
1184                                 bus_info[start_bus].phbid = phb;
1185                         }
1186                 }
1187         }
1188
1189         return 0;
1190
1191 error:
1192         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1193         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1194                 if (bus_info[bus].bbar)
1195                         iounmap(bus_info[bus].bbar);
1196
1197         return ret;
1198 }
1199
1200 static int __init calgary_init(void)
1201 {
1202         int ret;
1203         struct pci_dev *dev = NULL;
1204         struct calgary_bus_info *info;
1205
1206         ret = calgary_locate_bbars();
1207         if (ret)
1208                 return ret;
1209
1210         /* Purely for kdump kernel case */
1211         if (is_kdump_kernel())
1212                 get_tce_space_from_tar();
1213
1214         do {
1215                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1216                 if (!dev)
1217                         break;
1218                 if (!is_cal_pci_dev(dev->device))
1219                         continue;
1220
1221                 info = &bus_info[dev->bus->number];
1222                 if (info->translation_disabled) {
1223                         calgary_init_one_nontraslated(dev);
1224                         continue;
1225                 }
1226
1227                 if (!info->tce_space && !translate_empty_slots)
1228                         continue;
1229
1230                 ret = calgary_init_one(dev);
1231                 if (ret)
1232                         goto error;
1233         } while (1);
1234
1235         dev = NULL;
1236         for_each_pci_dev(dev) {
1237                 struct iommu_table *tbl;
1238
1239                 tbl = find_iommu_table(&dev->dev);
1240
1241                 if (translation_enabled(tbl))
1242                         dev->dev.archdata.dma_ops = &calgary_dma_ops;
1243         }
1244
1245         return ret;
1246
1247 error:
1248         do {
1249                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1250                 if (!dev)
1251                         break;
1252                 if (!is_cal_pci_dev(dev->device))
1253                         continue;
1254
1255                 info = &bus_info[dev->bus->number];
1256                 if (info->translation_disabled) {
1257                         pci_dev_put(dev);
1258                         continue;
1259                 }
1260                 if (!info->tce_space && !translate_empty_slots)
1261                         continue;
1262
1263                 calgary_disable_translation(dev);
1264                 calgary_free_bus(dev);
1265                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1266                 dev->dev.archdata.dma_ops = NULL;
1267         } while (1);
1268
1269         return ret;
1270 }
1271
1272 static inline int __init determine_tce_table_size(u64 ram)
1273 {
1274         int ret;
1275
1276         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1277                 return specified_table_size;
1278
1279         /*
1280          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1281          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1282          * larger table size has twice as many entries, so shift the
1283          * max ram address by 13 to divide by 8K and then look at the
1284          * order of the result to choose between 0-7.
1285          */
1286         ret = get_order(ram >> 13);
1287         if (ret > TCE_TABLE_SIZE_8M)
1288                 ret = TCE_TABLE_SIZE_8M;
1289
1290         return ret;
1291 }
1292
1293 static int __init build_detail_arrays(void)
1294 {
1295         unsigned long ptr;
1296         unsigned numnodes, i;
1297         int scal_detail_size, rio_detail_size;
1298
1299         numnodes = rio_table_hdr->num_scal_dev;
1300         if (numnodes > MAX_NUMNODES){
1301                 printk(KERN_WARNING
1302                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1303                         "but system has %d nodes.\n",
1304                         MAX_NUMNODES, numnodes);
1305                 return -ENODEV;
1306         }
1307
1308         switch (rio_table_hdr->version){
1309         case 2:
1310                 scal_detail_size = 11;
1311                 rio_detail_size = 13;
1312                 break;
1313         case 3:
1314                 scal_detail_size = 12;
1315                 rio_detail_size = 15;
1316                 break;
1317         default:
1318                 printk(KERN_WARNING
1319                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1320                        rio_table_hdr->version);
1321                 return -EPROTO;
1322         }
1323
1324         ptr = ((unsigned long)rio_table_hdr) + 3;
1325         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1326                 scal_devs[i] = (struct scal_detail *)ptr;
1327
1328         for (i = 0; i < rio_table_hdr->num_rio_dev;
1329                     i++, ptr += rio_detail_size)
1330                 rio_devs[i] = (struct rio_detail *)ptr;
1331
1332         return 0;
1333 }
1334
1335 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1336 {
1337         int dev;
1338         u32 val;
1339
1340         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1341                 /*
1342                  * FIXME: properly scan for devices accross the
1343                  * PCI-to-PCI bridge on every CalIOC2 port.
1344                  */
1345                 return 1;
1346         }
1347
1348         for (dev = 1; dev < 8; dev++) {
1349                 val = read_pci_config(bus, dev, 0, 0);
1350                 if (val != 0xffffffff)
1351                         break;
1352         }
1353         return (val != 0xffffffff);
1354 }
1355
1356 /*
1357  * calgary_init_bitmap_from_tce_table():
1358  * Funtion for kdump case. In the second/kdump kernel initialize
1359  * the bitmap based on the tce table entries obtained from first kernel
1360  */
1361 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1362 {
1363         u64 *tp;
1364         unsigned int index;
1365         tp = ((u64 *)tbl->it_base);
1366         for (index = 0 ; index < tbl->it_size; index++) {
1367                 if (*tp != 0x0)
1368                         set_bit(index, tbl->it_map);
1369                 tp++;
1370         }
1371 }
1372
1373 /*
1374  * get_tce_space_from_tar():
1375  * Function for kdump case. Get the tce tables from first kernel
1376  * by reading the contents of the base adress register of calgary iommu
1377  */
1378 static void __init get_tce_space_from_tar(void)
1379 {
1380         int bus;
1381         void __iomem *target;
1382         unsigned long tce_space;
1383
1384         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1385                 struct calgary_bus_info *info = &bus_info[bus];
1386                 unsigned short pci_device;
1387                 u32 val;
1388
1389                 val = read_pci_config(bus, 0, 0, 0);
1390                 pci_device = (val & 0xFFFF0000) >> 16;
1391
1392                 if (!is_cal_pci_dev(pci_device))
1393                         continue;
1394                 if (info->translation_disabled)
1395                         continue;
1396
1397                 if (calgary_bus_has_devices(bus, pci_device) ||
1398                                                 translate_empty_slots) {
1399                         target = calgary_reg(bus_info[bus].bbar,
1400                                                 tar_offset(bus));
1401                         tce_space = be64_to_cpu(readq(target));
1402                         tce_space = tce_space & TAR_SW_BITS;
1403
1404                         tce_space = tce_space & (~specified_table_size);
1405                         info->tce_space = (u64 *)__va(tce_space);
1406                 }
1407         }
1408         return;
1409 }
1410
1411 void __init detect_calgary(void)
1412 {
1413         int bus;
1414         void *tbl;
1415         int calgary_found = 0;
1416         unsigned long ptr;
1417         unsigned int offset, prev_offset;
1418         int ret;
1419
1420         /*
1421          * if the user specified iommu=off or iommu=soft or we found
1422          * another HW IOMMU already, bail out.
1423          */
1424         if (swiotlb || no_iommu || iommu_detected)
1425                 return;
1426
1427         if (!use_calgary)
1428                 return;
1429
1430         if (!early_pci_allowed())
1431                 return;
1432
1433         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1434
1435         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1436
1437         rio_table_hdr = NULL;
1438         prev_offset = 0;
1439         offset = 0x180;
1440         /*
1441          * The next offset is stored in the 1st word.
1442          * Only parse up until the offset increases:
1443          */
1444         while (offset > prev_offset) {
1445                 /* The block id is stored in the 2nd word */
1446                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1447                         /* set the pointer past the offset & block id */
1448                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1449                         break;
1450                 }
1451                 prev_offset = offset;
1452                 offset = *((unsigned short *)(ptr + offset));
1453         }
1454         if (!rio_table_hdr) {
1455                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1456                        "in EBDA - bailing!\n");
1457                 return;
1458         }
1459
1460         ret = build_detail_arrays();
1461         if (ret) {
1462                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1463                 return;
1464         }
1465
1466         specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1467                                         saved_max_pfn : max_pfn) * PAGE_SIZE);
1468
1469         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1470                 struct calgary_bus_info *info = &bus_info[bus];
1471                 unsigned short pci_device;
1472                 u32 val;
1473
1474                 val = read_pci_config(bus, 0, 0, 0);
1475                 pci_device = (val & 0xFFFF0000) >> 16;
1476
1477                 if (!is_cal_pci_dev(pci_device))
1478                         continue;
1479
1480                 if (info->translation_disabled)
1481                         continue;
1482
1483                 if (calgary_bus_has_devices(bus, pci_device) ||
1484                     translate_empty_slots) {
1485                         /*
1486                          * If it is kdump kernel, find and use tce tables
1487                          * from first kernel, else allocate tce tables here
1488                          */
1489                         if (!is_kdump_kernel()) {
1490                                 tbl = alloc_tce_table();
1491                                 if (!tbl)
1492                                         goto cleanup;
1493                                 info->tce_space = tbl;
1494                         }
1495                         calgary_found = 1;
1496                 }
1497         }
1498
1499         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1500                calgary_found ? "found" : "not found");
1501
1502         if (calgary_found) {
1503                 iommu_detected = 1;
1504                 calgary_detected = 1;
1505                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1506                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1507                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1508                        debugging ? "enabled" : "disabled");
1509
1510                 /* swiotlb for devices that aren't behind the Calgary. */
1511                 if (max_pfn > MAX_DMA32_PFN)
1512                         swiotlb = 1;
1513         }
1514         return;
1515
1516 cleanup:
1517         for (--bus; bus >= 0; --bus) {
1518                 struct calgary_bus_info *info = &bus_info[bus];
1519
1520                 if (info->tce_space)
1521                         free_tce_table(info->tce_space);
1522         }
1523 }
1524
1525 int __init calgary_iommu_init(void)
1526 {
1527         int ret;
1528
1529         if (no_iommu || (swiotlb && !calgary_detected))
1530                 return -ENODEV;
1531
1532         if (!calgary_detected)
1533                 return -ENODEV;
1534
1535         /* ok, we're trying to use Calgary - let's roll */
1536         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1537
1538         ret = calgary_init();
1539         if (ret) {
1540                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1541                        "falling back to no_iommu\n", ret);
1542                 return ret;
1543         }
1544
1545         force_iommu = 1;
1546         bad_dma_address = 0x0;
1547         /* dma_ops is set to swiotlb or nommu */
1548         if (!dma_ops)
1549                 dma_ops = &nommu_dma_ops;
1550
1551         return 0;
1552 }
1553
1554 static int __init calgary_parse_options(char *p)
1555 {
1556         unsigned int bridge;
1557         size_t len;
1558         char* endp;
1559
1560         while (*p) {
1561                 if (!strncmp(p, "64k", 3))
1562                         specified_table_size = TCE_TABLE_SIZE_64K;
1563                 else if (!strncmp(p, "128k", 4))
1564                         specified_table_size = TCE_TABLE_SIZE_128K;
1565                 else if (!strncmp(p, "256k", 4))
1566                         specified_table_size = TCE_TABLE_SIZE_256K;
1567                 else if (!strncmp(p, "512k", 4))
1568                         specified_table_size = TCE_TABLE_SIZE_512K;
1569                 else if (!strncmp(p, "1M", 2))
1570                         specified_table_size = TCE_TABLE_SIZE_1M;
1571                 else if (!strncmp(p, "2M", 2))
1572                         specified_table_size = TCE_TABLE_SIZE_2M;
1573                 else if (!strncmp(p, "4M", 2))
1574                         specified_table_size = TCE_TABLE_SIZE_4M;
1575                 else if (!strncmp(p, "8M", 2))
1576                         specified_table_size = TCE_TABLE_SIZE_8M;
1577
1578                 len = strlen("translate_empty_slots");
1579                 if (!strncmp(p, "translate_empty_slots", len))
1580                         translate_empty_slots = 1;
1581
1582                 len = strlen("disable");
1583                 if (!strncmp(p, "disable", len)) {
1584                         p += len;
1585                         if (*p == '=')
1586                                 ++p;
1587                         if (*p == '\0')
1588                                 break;
1589                         bridge = simple_strtoul(p, &endp, 0);
1590                         if (p == endp)
1591                                 break;
1592
1593                         if (bridge < MAX_PHB_BUS_NUM) {
1594                                 printk(KERN_INFO "Calgary: disabling "
1595                                        "translation for PHB %#x\n", bridge);
1596                                 bus_info[bridge].translation_disabled = 1;
1597                         }
1598                 }
1599
1600                 p = strpbrk(p, ",");
1601                 if (!p)
1602                         break;
1603
1604                 p++; /* skip ',' */
1605         }
1606         return 1;
1607 }
1608 __setup("calgary=", calgary_parse_options);
1609
1610 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1611 {
1612         struct iommu_table *tbl;
1613         unsigned int npages;
1614         int i;
1615
1616         tbl = pci_iommu(dev->bus);
1617
1618         for (i = 0; i < 4; i++) {
1619                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1620
1621                 /* Don't give out TCEs that map MEM resources */
1622                 if (!(r->flags & IORESOURCE_MEM))
1623                         continue;
1624
1625                 /* 0-based? we reserve the whole 1st MB anyway */
1626                 if (!r->start)
1627                         continue;
1628
1629                 /* cover the whole region */
1630                 npages = (r->end - r->start) >> PAGE_SHIFT;
1631                 npages++;
1632
1633                 iommu_range_reserve(tbl, r->start, npages);
1634         }
1635 }
1636
1637 static int __init calgary_fixup_tce_spaces(void)
1638 {
1639         struct pci_dev *dev = NULL;
1640         struct calgary_bus_info *info;
1641
1642         if (no_iommu || swiotlb || !calgary_detected)
1643                 return -ENODEV;
1644
1645         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1646
1647         do {
1648                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1649                 if (!dev)
1650                         break;
1651                 if (!is_cal_pci_dev(dev->device))
1652                         continue;
1653
1654                 info = &bus_info[dev->bus->number];
1655                 if (info->translation_disabled)
1656                         continue;
1657
1658                 if (!info->tce_space)
1659                         continue;
1660
1661                 calgary_fixup_one_tce_space(dev);
1662
1663         } while (1);
1664
1665         return 0;
1666 }
1667
1668 /*
1669  * We need to be call after pcibios_assign_resources (fs_initcall level)
1670  * and before device_initcall.
1671  */
1672 rootfs_initcall(calgary_fixup_tce_spaces);