arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/crash_dump.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <linux/scatterlist.h>
  39 #include <linux/iommu-helper.h>
  40
  41 #include <asm/iommu.h>
  42 #include <asm/calgary.h>
  43 #include <asm/tce.h>
  44 #include <asm/pci-direct.h>
  45 #include <asm/system.h>
  46 #include <asm/dma.h>
  47 #include <asm/rio.h>
  48 #include <asm/bios_ebda.h>
  49
  50 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  51 int use_calgary __read_mostly = 1;
  52 #else
  53 int use_calgary __read_mostly = 0;
  54 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  55
  56 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  57 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  58
  59 /* register offsets inside the host bridge space */
  60 #define CALGARY_CONFIG_REG      0x0108
  61 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  62 #define PHB_PLSSR_OFFSET        0x0120
  63 #define PHB_CONFIG_RW_OFFSET    0x0160
  64 #define PHB_IOBASE_BAR_LOW      0x0170
  65 #define PHB_IOBASE_BAR_HIGH     0x0180
  66 #define PHB_MEM_1_LOW           0x0190
  67 #define PHB_MEM_1_HIGH          0x01A0
  68 #define PHB_IO_ADDR_SIZE        0x01B0
  69 #define PHB_MEM_1_SIZE          0x01C0
  70 #define PHB_MEM_ST_OFFSET       0x01D0
  71 #define PHB_AER_OFFSET          0x0200
  72 #define PHB_CONFIG_0_HIGH       0x0220
  73 #define PHB_CONFIG_0_LOW        0x0230
  74 #define PHB_CONFIG_0_END        0x0240
  75 #define PHB_MEM_2_LOW           0x02B0
  76 #define PHB_MEM_2_HIGH          0x02C0
  77 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  78 #define PHB_MEM_2_SIZE_LOW      0x02E0
  79 #define PHB_DOSHOLE_OFFSET      0x08E0
  80
  81 /* CalIOC2 specific */
  82 #define PHB_SAVIOR_L2           0x0DB0
  83 #define PHB_PAGE_MIG_CTRL       0x0DA8
  84 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  85 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  86
  87 /* PHB_CONFIG_RW */
  88 #define PHB_TCE_ENABLE          0x20000000
  89 #define PHB_SLOT_DISABLE        0x1C000000
  90 #define PHB_DAC_DISABLE         0x01000000
  91 #define PHB_MEM2_ENABLE         0x00400000
  92 #define PHB_MCSR_ENABLE         0x00100000
  93 /* TAR (Table Address Register) */
  94 #define TAR_SW_BITS             0x0000ffffffff800fUL
  95 #define TAR_VALID               0x0000000000000008UL
  96 /* CSR (Channel/DMA Status Register) */
  97 #define CSR_AGENT_MASK          0xffe0ffff
  98 /* CCR (Calgary Configuration Register) */
  99 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
 100 /* PMCR/PMDR (Page Migration Control/Debug Registers */
 101 #define PMR_SOFTSTOP            0x80000000
 102 #define PMR_SOFTSTOPFAULT       0x40000000
 103 #define PMR_HARDSTOP            0x20000000
 104
 105 /*
 106  * The maximum PHB bus number.
 107  * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
 108  * x3950M2: 4 chassis, 48 PHBs per chassis        = 192
 109  * x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
 110  * x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
 111  */
 112 #define MAX_PHB_BUS_NUM         256
 113
 114 #define PHBS_PER_CALGARY          4
 115
 116 /* register offsets in Calgary's internal register space */
 117 static const unsigned long tar_offsets[] = {
 118         0x0580 /* TAR0 */,
 119         0x0588 /* TAR1 */,
 120         0x0590 /* TAR2 */,
 121         0x0598 /* TAR3 */
 122 };
 123
 124 static const unsigned long split_queue_offsets[] = {
 125         0x4870 /* SPLIT QUEUE 0 */,
 126         0x5870 /* SPLIT QUEUE 1 */,
 127         0x6870 /* SPLIT QUEUE 2 */,
 128         0x7870 /* SPLIT QUEUE 3 */
 129 };
 130
 131 static const unsigned long phb_offsets[] = {
 132         0x8000 /* PHB0 */,
 133         0x9000 /* PHB1 */,
 134         0xA000 /* PHB2 */,
 135         0xB000 /* PHB3 */
 136 };
 137
 138 /* PHB debug registers */
 139
 140 static const unsigned long phb_debug_offsets[] = {
 141         0x4000  /* PHB 0 DEBUG */,
 142         0x5000  /* PHB 1 DEBUG */,
 143         0x6000  /* PHB 2 DEBUG */,
 144         0x7000  /* PHB 3 DEBUG */
 145 };
 146
 147 /*
 148  * STUFF register for each debug PHB,
 149  * byte 1 = start bus number, byte 2 = end bus number
 150  */
 151
 152 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 153
 154 #define EMERGENCY_PAGES 32 /* = 128KB */
 155
 156 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 157 static int translate_empty_slots __read_mostly = 0;
 158 static int calgary_detected __read_mostly = 0;
 159
 160 static struct rio_table_hdr     *rio_table_hdr __initdata;
 161 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 162 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 163
 164 struct calgary_bus_info {
 165         void *tce_space;
 166         unsigned char translation_disabled;
 167         signed char phbid;
 168         void __iomem *bbar;
 169 };
 170
 171 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 172 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 173 static void calgary_dump_error_regs(struct iommu_table *tbl);
 174 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 175 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 176 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 177 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 178 static void get_tce_space_from_tar(void);
 179
 180 static struct cal_chipset_ops calgary_chip_ops = {
 181         .handle_quirks = calgary_handle_quirks,
 182         .tce_cache_blast = calgary_tce_cache_blast,
 183         .dump_error_regs = calgary_dump_error_regs
 184 };
 185
 186 static struct cal_chipset_ops calioc2_chip_ops = {
 187         .handle_quirks = calioc2_handle_quirks,
 188         .tce_cache_blast = calioc2_tce_cache_blast,
 189         .dump_error_regs = calioc2_dump_error_regs
 190 };
 191
 192 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 193
 194 /* enable this to stress test the chip's TCE cache */
 195 #ifdef CONFIG_IOMMU_DEBUG
 196 static int debugging = 1;
 197
 198 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 199         int expected, unsigned long start, unsigned long end)
 200 {
 201         unsigned long idx = start;
 202
 203         BUG_ON(start >= end);
 204
 205         while (idx < end) {
 206                 if (!!test_bit(idx, bitmap) != expected)
 207                         return idx;
 208                 ++idx;
 209         }
 210
 211         /* all bits have the expected value */
 212         return ~0UL;
 213 }
 214 #else /* debugging is disabled */
 215 static int debugging;
 216
 217 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 218         int expected, unsigned long start, unsigned long end)
 219 {
 220         return ~0UL;
 221 }
 222
 223 #endif /* CONFIG_IOMMU_DEBUG */
 224
 225 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 226 {
 227         unsigned int npages;
 228
 229         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 230         npages >>= PAGE_SHIFT;
 231
 232         return npages;
 233 }
 234
 235 static inline int translation_enabled(struct iommu_table *tbl)
 236 {
 237         /* only PHBs with translation enabled have an IOMMU table */
 238         return (tbl != NULL);
 239 }
 240
 241 static void iommu_range_reserve(struct iommu_table *tbl,
 242         unsigned long start_addr, unsigned int npages)
 243 {
 244         unsigned long index;
 245         unsigned long end;
 246         unsigned long badbit;
 247         unsigned long flags;
 248
 249         index = start_addr >> PAGE_SHIFT;
 250
 251         /* bail out if we're asked to reserve a region we don't cover */
 252         if (index >= tbl->it_size)
 253                 return;
 254
 255         end = index + npages;
 256         if (end > tbl->it_size) /* don't go off the table */
 257                 end = tbl->it_size;
 258
 259         spin_lock_irqsave(&tbl->it_lock, flags);
 260
 261         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 262         if (badbit != ~0UL) {
 263                 if (printk_ratelimit())
 264                         printk(KERN_ERR "Calgary: entry already allocated at "
 265                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 266                                badbit, tbl, start_addr, npages);
 267         }
 268
 269         set_bit_string(tbl->it_map, index, npages);
 270
 271         spin_unlock_irqrestore(&tbl->it_lock, flags);
 272 }
 273
 274 static unsigned long iommu_range_alloc(struct device *dev,
 275                                        struct iommu_table *tbl,
 276                                        unsigned int npages)
 277 {
 278         unsigned long flags;
 279         unsigned long offset;
 280         unsigned long boundary_size;
 281
 282         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 283                               PAGE_SIZE) >> PAGE_SHIFT;
 284
 285         BUG_ON(npages == 0);
 286
 287         spin_lock_irqsave(&tbl->it_lock, flags);
 288
 289         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 290                                   npages, 0, boundary_size, 0);
 291         if (offset == ~0UL) {
 292                 tbl->chip_ops->tce_cache_blast(tbl);
 293
 294                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 295                                           npages, 0, boundary_size, 0);
 296                 if (offset == ~0UL) {
 297                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 298                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 299                         if (panic_on_overflow)
 300                                 panic("Calgary: fix the allocator.\n");
 301                         else
 302                                 return bad_dma_address;
 303                 }
 304         }
 305
 306         tbl->it_hint = offset + npages;
 307         BUG_ON(tbl->it_hint > tbl->it_size);
 308
 309         spin_unlock_irqrestore(&tbl->it_lock, flags);
 310
 311         return offset;
 312 }
 313
 314 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 315                               void *vaddr, unsigned int npages, int direction)
 316 {
 317         unsigned long entry;
 318         dma_addr_t ret = bad_dma_address;
 319
 320         entry = iommu_range_alloc(dev, tbl, npages);
 321
 322         if (unlikely(entry == bad_dma_address))
 323                 goto error;
 324
 325         /* set the return dma address */
 326         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 327
 328         /* put the TCEs in the HW table */
 329         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 330                   direction);
 331
 332         return ret;
 333
 334 error:
 335         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 336                "iommu %p\n", npages, tbl);
 337         return bad_dma_address;
 338 }
 339
 340 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 341         unsigned int npages)
 342 {
 343         unsigned long entry;
 344         unsigned long badbit;
 345         unsigned long badend;
 346         unsigned long flags;
 347
 348         /* were we called with bad_dma_address? */
 349         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 350         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 351                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
 352                        "address 0x%Lx\n", dma_addr);
 353                 return;
 354         }
 355
 356         entry = dma_addr >> PAGE_SHIFT;
 357
 358         BUG_ON(entry + npages > tbl->it_size);
 359
 360         tce_free(tbl, entry, npages);
 361
 362         spin_lock_irqsave(&tbl->it_lock, flags);
 363
 364         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 365         if (badbit != ~0UL) {
 366                 if (printk_ratelimit())
 367                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 368                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 369                                badbit, tbl, dma_addr, entry, npages);
 370         }
 371
 372         iommu_area_free(tbl->it_map, entry, npages);
 373
 374         spin_unlock_irqrestore(&tbl->it_lock, flags);
 375 }
 376
 377 static inline struct iommu_table *find_iommu_table(struct device *dev)
 378 {
 379         struct pci_dev *pdev;
 380         struct pci_bus *pbus;
 381         struct iommu_table *tbl;
 382
 383         pdev = to_pci_dev(dev);
 384
 385         /* search up the device tree for an iommu */
 386         pbus = pdev->bus;
 387         do {
 388                 tbl = pci_iommu(pbus);
 389                 if (tbl && tbl->it_busno == pbus->number)
 390                         break;
 391                 tbl = NULL;
 392                 pbus = pbus->parent;
 393         } while (pbus);
 394
 395         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 396
 397         return tbl;
 398 }
 399
 400 static void calgary_unmap_sg(struct device *dev,
 401         struct scatterlist *sglist, int nelems, int direction)
 402 {
 403         struct iommu_table *tbl = find_iommu_table(dev);
 404         struct scatterlist *s;
 405         int i;
 406
 407         if (!translation_enabled(tbl))
 408                 return;
 409
 410         for_each_sg(sglist, s, nelems, i) {
 411                 unsigned int npages;
 412                 dma_addr_t dma = s->dma_address;
 413                 unsigned int dmalen = s->dma_length;
 414
 415                 if (dmalen == 0)
 416                         break;
 417
 418                 npages = num_dma_pages(dma, dmalen);
 419                 iommu_free(tbl, dma, npages);
 420         }
 421 }
 422
 423 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 424         int nelems, int direction)
 425 {
 426         struct iommu_table *tbl = find_iommu_table(dev);
 427         struct scatterlist *s;
 428         unsigned long vaddr;
 429         unsigned int npages;
 430         unsigned long entry;
 431         int i;
 432
 433         for_each_sg(sg, s, nelems, i) {
 434                 BUG_ON(!sg_page(s));
 435
 436                 vaddr = (unsigned long) sg_virt(s);
 437                 npages = num_dma_pages(vaddr, s->length);
 438
 439                 entry = iommu_range_alloc(dev, tbl, npages);
 440                 if (entry == bad_dma_address) {
 441                         /* makes sure unmap knows to stop */
 442                         s->dma_length = 0;
 443                         goto error;
 444                 }
 445
 446                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 447
 448                 /* insert into HW table */
 449                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 450                           direction);
 451
 452                 s->dma_length = s->length;
 453         }
 454
 455         return nelems;
 456 error:
 457         calgary_unmap_sg(dev, sg, nelems, direction);
 458         for_each_sg(sg, s, nelems, i) {
 459                 sg->dma_address = bad_dma_address;
 460                 sg->dma_length = 0;
 461         }
 462         return 0;
 463 }
 464
 465 static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr,
 466         size_t size, int direction)
 467 {
 468         void *vaddr = phys_to_virt(paddr);
 469         unsigned long uaddr;
 470         unsigned int npages;
 471         struct iommu_table *tbl = find_iommu_table(dev);
 472
 473         uaddr = (unsigned long)vaddr;
 474         npages = num_dma_pages(uaddr, size);
 475
 476         return iommu_alloc(dev, tbl, vaddr, npages, direction);
 477 }
 478
 479 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 480         size_t size, int direction)
 481 {
 482         struct iommu_table *tbl = find_iommu_table(dev);
 483         unsigned int npages;
 484
 485         npages = num_dma_pages(dma_handle, size);
 486         iommu_free(tbl, dma_handle, npages);
 487 }
 488
 489 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 490         dma_addr_t *dma_handle, gfp_t flag)
 491 {
 492         void *ret = NULL;
 493         dma_addr_t mapping;
 494         unsigned int npages, order;
 495         struct iommu_table *tbl = find_iommu_table(dev);
 496
 497         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 498         npages = size >> PAGE_SHIFT;
 499         order = get_order(size);
 500
 501         /* alloc enough pages (and possibly more) */
 502         ret = (void *)__get_free_pages(flag, order);
 503         if (!ret)
 504                 goto error;
 505         memset(ret, 0, size);
 506
 507         /* set up tces to cover the allocated range */
 508         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 509         if (mapping == bad_dma_address)
 510                 goto free;
 511         *dma_handle = mapping;
 512         return ret;
 513 free:
 514         free_pages((unsigned long)ret, get_order(size));
 515         ret = NULL;
 516 error:
 517         return ret;
 518 }
 519
 520 static struct dma_mapping_ops calgary_dma_ops = {
 521         .alloc_coherent = calgary_alloc_coherent,
 522         .map_single = calgary_map_single,
 523         .unmap_single = calgary_unmap_single,
 524         .map_sg = calgary_map_sg,
 525         .unmap_sg = calgary_unmap_sg,
 526 };
 527
 528 static inline void __iomem * busno_to_bbar(unsigned char num)
 529 {
 530         return bus_info[num].bbar;
 531 }
 532
 533 static inline int busno_to_phbid(unsigned char num)
 534 {
 535         return bus_info[num].phbid;
 536 }
 537
 538 static inline unsigned long split_queue_offset(unsigned char num)
 539 {
 540         size_t idx = busno_to_phbid(num);
 541
 542         return split_queue_offsets[idx];
 543 }
 544
 545 static inline unsigned long tar_offset(unsigned char num)
 546 {
 547         size_t idx = busno_to_phbid(num);
 548
 549         return tar_offsets[idx];
 550 }
 551
 552 static inline unsigned long phb_offset(unsigned char num)
 553 {
 554         size_t idx = busno_to_phbid(num);
 555
 556         return phb_offsets[idx];
 557 }
 558
 559 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 560 {
 561         unsigned long target = ((unsigned long)bar) | offset;
 562         return (void __iomem*)target;
 563 }
 564
 565 static inline int is_calioc2(unsigned short device)
 566 {
 567         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 568 }
 569
 570 static inline int is_calgary(unsigned short device)
 571 {
 572         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 573 }
 574
 575 static inline int is_cal_pci_dev(unsigned short device)
 576 {
 577         return (is_calgary(device) || is_calioc2(device));
 578 }
 579
 580 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 581 {
 582         u64 val;
 583         u32 aer;
 584         int i = 0;
 585         void __iomem *bbar = tbl->bbar;
 586         void __iomem *target;
 587
 588         /* disable arbitration on the bus */
 589         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 590         aer = readl(target);
 591         writel(0, target);
 592
 593         /* read plssr to ensure it got there */
 594         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 595         val = readl(target);
 596
 597         /* poll split queues until all DMA activity is done */
 598         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 599         do {
 600                 val = readq(target);
 601                 i++;
 602         } while ((val & 0xff) != 0xff && i < 100);
 603         if (i == 100)
 604                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 605                        "continuing anyway\n");
 606
 607         /* invalidate TCE cache */
 608         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 609         writeq(tbl->tar_val, target);
 610
 611         /* enable arbitration */
 612         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 613         writel(aer, target);
 614         (void)readl(target); /* flush */
 615 }
 616
 617 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 618 {
 619         void __iomem *bbar = tbl->bbar;
 620         void __iomem *target;
 621         u64 val64;
 622         u32 val;
 623         int i = 0;
 624         int count = 1;
 625         unsigned char bus = tbl->it_busno;
 626
 627 begin:
 628         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 629                "sequence - count %d\n", bus, count);
 630
 631         /* 1. using the Page Migration Control reg set SoftStop */
 632         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 633         val = be32_to_cpu(readl(target));
 634         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 635         val |= PMR_SOFTSTOP;
 636         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 637         writel(cpu_to_be32(val), target);
 638
 639         /* 2. poll split queues until all DMA activity is done */
 640         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 641         target = calgary_reg(bbar, split_queue_offset(bus));
 642         do {
 643                 val64 = readq(target);
 644                 i++;
 645         } while ((val64 & 0xff) != 0xff && i < 100);
 646         if (i == 100)
 647                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 648                        "continuing anyway\n");
 649
 650         /* 3. poll Page Migration DEBUG for SoftStopFault */
 651         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 652         val = be32_to_cpu(readl(target));
 653         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 654
 655         /* 4. if SoftStopFault - goto (1) */
 656         if (val & PMR_SOFTSTOPFAULT) {
 657                 if (++count < 100)
 658                         goto begin;
 659                 else {
 660                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 661                                "aborting TCE cache flush sequence!\n");
 662                         return; /* pray for the best */
 663                 }
 664         }
 665
 666         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 667         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 668         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 669         val = be32_to_cpu(readl(target));
 670         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 671         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 672         val = be32_to_cpu(readl(target));
 673         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 674
 675         /* 6. invalidate TCE cache */
 676         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 677         target = calgary_reg(bbar, tar_offset(bus));
 678         writeq(tbl->tar_val, target);
 679
 680         /* 7. Re-read PMCR */
 681         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 682         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 683         val = be32_to_cpu(readl(target));
 684         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 685
 686         /* 8. Remove HardStop */
 687         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 688         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 689         val = 0;
 690         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 691         writel(cpu_to_be32(val), target);
 692         val = be32_to_cpu(readl(target));
 693         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 694 }
 695
 696 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 697         u64 limit)
 698 {
 699         unsigned int numpages;
 700
 701         limit = limit | 0xfffff;
 702         limit++;
 703
 704         numpages = ((limit - start) >> PAGE_SHIFT);
 705         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 706 }
 707
 708 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 709 {
 710         void __iomem *target;
 711         u64 low, high, sizelow;
 712         u64 start, limit;
 713         struct iommu_table *tbl = pci_iommu(dev->bus);
 714         unsigned char busnum = dev->bus->number;
 715         void __iomem *bbar = tbl->bbar;
 716
 717         /* peripheral MEM_1 region */
 718         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 719         low = be32_to_cpu(readl(target));
 720         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 721         high = be32_to_cpu(readl(target));
 722         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 723         sizelow = be32_to_cpu(readl(target));
 724
 725         start = (high << 32) | low;
 726         limit = sizelow;
 727
 728         calgary_reserve_mem_region(dev, start, limit);
 729 }
 730
 731 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 732 {
 733         void __iomem *target;
 734         u32 val32;
 735         u64 low, high, sizelow, sizehigh;
 736         u64 start, limit;
 737         struct iommu_table *tbl = pci_iommu(dev->bus);
 738         unsigned char busnum = dev->bus->number;
 739         void __iomem *bbar = tbl->bbar;
 740
 741         /* is it enabled? */
 742         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 743         val32 = be32_to_cpu(readl(target));
 744         if (!(val32 & PHB_MEM2_ENABLE))
 745                 return;
 746
 747         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 748         low = be32_to_cpu(readl(target));
 749         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 750         high = be32_to_cpu(readl(target));
 751         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 752         sizelow = be32_to_cpu(readl(target));
 753         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 754         sizehigh = be32_to_cpu(readl(target));
 755
 756         start = (high << 32) | low;
 757         limit = (sizehigh << 32) | sizelow;
 758
 759         calgary_reserve_mem_region(dev, start, limit);
 760 }
 761
 762 /*
 763  * some regions of the IO address space do not get translated, so we
 764  * must not give devices IO addresses in those regions. The regions
 765  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 766  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 767  * later.
 768  */
 769 static void __init calgary_reserve_regions(struct pci_dev *dev)
 770 {
 771         unsigned int npages;
 772         u64 start;
 773         struct iommu_table *tbl = pci_iommu(dev->bus);
 774
 775         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 776         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 777
 778         /* avoid the BIOS/VGA first 640KB-1MB region */
 779         /* for CalIOC2 - avoid the entire first MB */
 780         if (is_calgary(dev->device)) {
 781                 start = (640 * 1024);
 782                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 783         } else { /* calioc2 */
 784                 start = 0;
 785                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 786         }
 787         iommu_range_reserve(tbl, start, npages);
 788
 789         /* reserve the two PCI peripheral memory regions in IO space */
 790         calgary_reserve_peripheral_mem_1(dev);
 791         calgary_reserve_peripheral_mem_2(dev);
 792 }
 793
 794 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 795 {
 796         u64 val64;
 797         u64 table_phys;
 798         void __iomem *target;
 799         int ret;
 800         struct iommu_table *tbl;
 801
 802         /* build TCE tables for each PHB */
 803         ret = build_tce_table(dev, bbar);
 804         if (ret)
 805                 return ret;
 806
 807         tbl = pci_iommu(dev->bus);
 808         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 809
 810         if (is_kdump_kernel())
 811                 calgary_init_bitmap_from_tce_table(tbl);
 812         else
 813                 tce_free(tbl, 0, tbl->it_size);
 814
 815         if (is_calgary(dev->device))
 816                 tbl->chip_ops = &calgary_chip_ops;
 817         else if (is_calioc2(dev->device))
 818                 tbl->chip_ops = &calioc2_chip_ops;
 819         else
 820                 BUG();
 821
 822         calgary_reserve_regions(dev);
 823
 824         /* set TARs for each PHB */
 825         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 826         val64 = be64_to_cpu(readq(target));
 827
 828         /* zero out all TAR bits under sw control */
 829         val64 &= ~TAR_SW_BITS;
 830         table_phys = (u64)__pa(tbl->it_base);
 831
 832         val64 |= table_phys;
 833
 834         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 835         val64 |= (u64) specified_table_size;
 836
 837         tbl->tar_val = cpu_to_be64(val64);
 838
 839         writeq(tbl->tar_val, target);
 840         readq(target); /* flush */
 841
 842         return 0;
 843 }
 844
 845 static void __init calgary_free_bus(struct pci_dev *dev)
 846 {
 847         u64 val64;
 848         struct iommu_table *tbl = pci_iommu(dev->bus);
 849         void __iomem *target;
 850         unsigned int bitmapsz;
 851
 852         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 853         val64 = be64_to_cpu(readq(target));
 854         val64 &= ~TAR_SW_BITS;
 855         writeq(cpu_to_be64(val64), target);
 856         readq(target); /* flush */
 857
 858         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 859         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 860         tbl->it_map = NULL;
 861
 862         kfree(tbl);
 863
 864         set_pci_iommu(dev->bus, NULL);
 865
 866         /* Can't free bootmem allocated memory after system is up :-( */
 867         bus_info[dev->bus->number].tce_space = NULL;
 868 }
 869
 870 static void calgary_dump_error_regs(struct iommu_table *tbl)
 871 {
 872         void __iomem *bbar = tbl->bbar;
 873         void __iomem *target;
 874         u32 csr, plssr;
 875
 876         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 877         csr = be32_to_cpu(readl(target));
 878
 879         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 880         plssr = be32_to_cpu(readl(target));
 881
 882         /* If no error, the agent ID in the CSR is not valid */
 883         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 884                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 885 }
 886
 887 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 888 {
 889         void __iomem *bbar = tbl->bbar;
 890         u32 csr, csmr, plssr, mck, rcstat;
 891         void __iomem *target;
 892         unsigned long phboff = phb_offset(tbl->it_busno);
 893         unsigned long erroff;
 894         u32 errregs[7];
 895         int i;
 896
 897         /* dump CSR */
 898         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 899         csr = be32_to_cpu(readl(target));
 900         /* dump PLSSR */
 901         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 902         plssr = be32_to_cpu(readl(target));
 903         /* dump CSMR */
 904         target = calgary_reg(bbar, phboff | 0x290);
 905         csmr = be32_to_cpu(readl(target));
 906         /* dump mck */
 907         target = calgary_reg(bbar, phboff | 0x800);
 908         mck = be32_to_cpu(readl(target));
 909
 910         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 911                tbl->it_busno);
 912
 913         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 914                csr, plssr, csmr, mck);
 915
 916         /* dump rest of error regs */
 917         printk(KERN_EMERG "Calgary: ");
 918         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 919                 /* err regs are at 0x810 - 0x870 */
 920                 erroff = (0x810 + (i * 0x10));
 921                 target = calgary_reg(bbar, phboff | erroff);
 922                 errregs[i] = be32_to_cpu(readl(target));
 923                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 924         }
 925         printk("\n");
 926
 927         /* root complex status */
 928         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 929         rcstat = be32_to_cpu(readl(target));
 930         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 931                PHB_ROOT_COMPLEX_STATUS);
 932 }
 933
 934 static void calgary_watchdog(unsigned long data)
 935 {
 936         struct pci_dev *dev = (struct pci_dev *)data;
 937         struct iommu_table *tbl = pci_iommu(dev->bus);
 938         void __iomem *bbar = tbl->bbar;
 939         u32 val32;
 940         void __iomem *target;
 941
 942         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 943         val32 = be32_to_cpu(readl(target));
 944
 945         /* If no error, the agent ID in the CSR is not valid */
 946         if (val32 & CSR_AGENT_MASK) {
 947                 tbl->chip_ops->dump_error_regs(tbl);
 948
 949                 /* reset error */
 950                 writel(0, target);
 951
 952                 /* Disable bus that caused the error */
 953                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 954                                      PHB_CONFIG_RW_OFFSET);
 955                 val32 = be32_to_cpu(readl(target));
 956                 val32 |= PHB_SLOT_DISABLE;
 957                 writel(cpu_to_be32(val32), target);
 958                 readl(target); /* flush */
 959         } else {
 960                 /* Reset the timer */
 961                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 962         }
 963 }
 964
 965 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 966         unsigned char busnum, unsigned long timeout)
 967 {
 968         u64 val64;
 969         void __iomem *target;
 970         unsigned int phb_shift = ~0; /* silence gcc */
 971         u64 mask;
 972
 973         switch (busno_to_phbid(busnum)) {
 974         case 0: phb_shift = (63 - 19);
 975                 break;
 976         case 1: phb_shift = (63 - 23);
 977                 break;
 978         case 2: phb_shift = (63 - 27);
 979                 break;
 980         case 3: phb_shift = (63 - 35);
 981                 break;
 982         default:
 983                 BUG_ON(busno_to_phbid(busnum));
 984         }
 985
 986         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 987         val64 = be64_to_cpu(readq(target));
 988
 989         /* zero out this PHB's timer bits */
 990         mask = ~(0xFUL << phb_shift);
 991         val64 &= mask;
 992         val64 |= (timeout << phb_shift);
 993         writeq(cpu_to_be64(val64), target);
 994         readq(target); /* flush */
 995 }
 996
 997 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 998 {
 999         unsigned char busnum = dev->bus->number;
1000         void __iomem *bbar = tbl->bbar;
1001         void __iomem *target;
1002         u32 val;
1003
1004         /*
1005          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1006          */
1007         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1008         val = cpu_to_be32(readl(target));
1009         val |= 0x00800000;
1010         writel(cpu_to_be32(val), target);
1011 }
1012
1013 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1014 {
1015         unsigned char busnum = dev->bus->number;
1016
1017         /*
1018          * Give split completion a longer timeout on bus 1 for aic94xx
1019          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1020          */
1021         if (is_calgary(dev->device) && (busnum == 1))
1022                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1023                                                      CCR_2SEC_TIMEOUT);
1024 }
1025
1026 static void __init calgary_enable_translation(struct pci_dev *dev)
1027 {
1028         u32 val32;
1029         unsigned char busnum;
1030         void __iomem *target;
1031         void __iomem *bbar;
1032         struct iommu_table *tbl;
1033
1034         busnum = dev->bus->number;
1035         tbl = pci_iommu(dev->bus);
1036         bbar = tbl->bbar;
1037
1038         /* enable TCE in PHB Config Register */
1039         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1040         val32 = be32_to_cpu(readl(target));
1041         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1042
1043         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1044                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1045                "Calgary" : "CalIOC2", busnum);
1046         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1047                "bus.\n");
1048
1049         writel(cpu_to_be32(val32), target);
1050         readl(target); /* flush */
1051
1052         init_timer(&tbl->watchdog_timer);
1053         tbl->watchdog_timer.function = &calgary_watchdog;
1054         tbl->watchdog_timer.data = (unsigned long)dev;
1055         mod_timer(&tbl->watchdog_timer, jiffies);
1056 }
1057
1058 static void __init calgary_disable_translation(struct pci_dev *dev)
1059 {
1060         u32 val32;
1061         unsigned char busnum;
1062         void __iomem *target;
1063         void __iomem *bbar;
1064         struct iommu_table *tbl;
1065
1066         busnum = dev->bus->number;
1067         tbl = pci_iommu(dev->bus);
1068         bbar = tbl->bbar;
1069
1070         /* disable TCE in PHB Config Register */
1071         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1072         val32 = be32_to_cpu(readl(target));
1073         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1074
1075         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1076         writel(cpu_to_be32(val32), target);
1077         readl(target); /* flush */
1078
1079         del_timer_sync(&tbl->watchdog_timer);
1080 }
1081
1082 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1083 {
1084         pci_dev_get(dev);
1085         set_pci_iommu(dev->bus, NULL);
1086
1087         /* is the device behind a bridge? */
1088         if (dev->bus->parent)
1089                 dev->bus->parent->self = dev;
1090         else
1091                 dev->bus->self = dev;
1092 }
1093
1094 static int __init calgary_init_one(struct pci_dev *dev)
1095 {
1096         void __iomem *bbar;
1097         struct iommu_table *tbl;
1098         int ret;
1099
1100         bbar = busno_to_bbar(dev->bus->number);
1101         ret = calgary_setup_tar(dev, bbar);
1102         if (ret)
1103                 goto done;
1104
1105         pci_dev_get(dev);
1106
1107         if (dev->bus->parent) {
1108                 if (dev->bus->parent->self)
1109                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1110                                "bus->parent->self!\n", dev);
1111                 dev->bus->parent->self = dev;
1112         } else
1113                 dev->bus->self = dev;
1114
1115         tbl = pci_iommu(dev->bus);
1116         tbl->chip_ops->handle_quirks(tbl, dev);
1117
1118         calgary_enable_translation(dev);
1119
1120         return 0;
1121
1122 done:
1123         return ret;
1124 }
1125
1126 static int __init calgary_locate_bbars(void)
1127 {
1128         int ret;
1129         int rioidx, phb, bus;
1130         void __iomem *bbar;
1131         void __iomem *target;
1132         unsigned long offset;
1133         u8 start_bus, end_bus;
1134         u32 val;
1135
1136         ret = -ENODATA;
1137         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1138                 struct rio_detail *rio = rio_devs[rioidx];
1139
1140                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1141                         continue;
1142
1143                 /* map entire 1MB of Calgary config space */
1144                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1145                 if (!bbar)
1146                         goto error;
1147
1148                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1149                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1150                         target = calgary_reg(bbar, offset);
1151
1152                         val = be32_to_cpu(readl(target));
1153
1154                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1155                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1156
1157                         if (end_bus) {
1158                                 for (bus = start_bus; bus <= end_bus; bus++) {
1159                                         bus_info[bus].bbar = bbar;
1160                                         bus_info[bus].phbid = phb;
1161                                 }
1162                         } else {
1163                                 bus_info[start_bus].bbar = bbar;
1164                                 bus_info[start_bus].phbid = phb;
1165                         }
1166                 }
1167         }
1168
1169         return 0;
1170
1171 error:
1172         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1173         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1174                 if (bus_info[bus].bbar)
1175                         iounmap(bus_info[bus].bbar);
1176
1177         return ret;
1178 }
1179
1180 static int __init calgary_init(void)
1181 {
1182         int ret;
1183         struct pci_dev *dev = NULL;
1184         struct calgary_bus_info *info;
1185
1186         ret = calgary_locate_bbars();
1187         if (ret)
1188                 return ret;
1189
1190         /* Purely for kdump kernel case */
1191         if (is_kdump_kernel())
1192                 get_tce_space_from_tar();
1193
1194         do {
1195                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1196                 if (!dev)
1197                         break;
1198                 if (!is_cal_pci_dev(dev->device))
1199                         continue;
1200
1201                 info = &bus_info[dev->bus->number];
1202                 if (info->translation_disabled) {
1203                         calgary_init_one_nontraslated(dev);
1204                         continue;
1205                 }
1206
1207                 if (!info->tce_space && !translate_empty_slots)
1208                         continue;
1209
1210                 ret = calgary_init_one(dev);
1211                 if (ret)
1212                         goto error;
1213         } while (1);
1214
1215         dev = NULL;
1216         for_each_pci_dev(dev) {
1217                 struct iommu_table *tbl;
1218
1219                 tbl = find_iommu_table(&dev->dev);
1220
1221                 if (translation_enabled(tbl))
1222                         dev->dev.archdata.dma_ops = &calgary_dma_ops;
1223         }
1224
1225         return ret;
1226
1227 error:
1228         do {
1229                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1230                 if (!dev)
1231                         break;
1232                 if (!is_cal_pci_dev(dev->device))
1233                         continue;
1234
1235                 info = &bus_info[dev->bus->number];
1236                 if (info->translation_disabled) {
1237                         pci_dev_put(dev);
1238                         continue;
1239                 }
1240                 if (!info->tce_space && !translate_empty_slots)
1241                         continue;
1242
1243                 calgary_disable_translation(dev);
1244                 calgary_free_bus(dev);
1245                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1246                 dev->dev.archdata.dma_ops = NULL;
1247         } while (1);
1248
1249         return ret;
1250 }
1251
1252 static inline int __init determine_tce_table_size(u64 ram)
1253 {
1254         int ret;
1255
1256         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1257                 return specified_table_size;
1258
1259         /*
1260          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1261          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1262          * larger table size has twice as many entries, so shift the
1263          * max ram address by 13 to divide by 8K and then look at the
1264          * order of the result to choose between 0-7.
1265          */
1266         ret = get_order(ram >> 13);
1267         if (ret > TCE_TABLE_SIZE_8M)
1268                 ret = TCE_TABLE_SIZE_8M;
1269
1270         return ret;
1271 }
1272
1273 static int __init build_detail_arrays(void)
1274 {
1275         unsigned long ptr;
1276         unsigned numnodes, i;
1277         int scal_detail_size, rio_detail_size;
1278
1279         numnodes = rio_table_hdr->num_scal_dev;
1280         if (numnodes > MAX_NUMNODES){
1281                 printk(KERN_WARNING
1282                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1283                         "but system has %d nodes.\n",
1284                         MAX_NUMNODES, numnodes);
1285                 return -ENODEV;
1286         }
1287
1288         switch (rio_table_hdr->version){
1289         case 2:
1290                 scal_detail_size = 11;
1291                 rio_detail_size = 13;
1292                 break;
1293         case 3:
1294                 scal_detail_size = 12;
1295                 rio_detail_size = 15;
1296                 break;
1297         default:
1298                 printk(KERN_WARNING
1299                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1300                        rio_table_hdr->version);
1301                 return -EPROTO;
1302         }
1303
1304         ptr = ((unsigned long)rio_table_hdr) + 3;
1305         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1306                 scal_devs[i] = (struct scal_detail *)ptr;
1307
1308         for (i = 0; i < rio_table_hdr->num_rio_dev;
1309                     i++, ptr += rio_detail_size)
1310                 rio_devs[i] = (struct rio_detail *)ptr;
1311
1312         return 0;
1313 }
1314
1315 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1316 {
1317         int dev;
1318         u32 val;
1319
1320         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1321                 /*
1322                  * FIXME: properly scan for devices accross the
1323                  * PCI-to-PCI bridge on every CalIOC2 port.
1324                  */
1325                 return 1;
1326         }
1327
1328         for (dev = 1; dev < 8; dev++) {
1329                 val = read_pci_config(bus, dev, 0, 0);
1330                 if (val != 0xffffffff)
1331                         break;
1332         }
1333         return (val != 0xffffffff);
1334 }
1335
1336 /*
1337  * calgary_init_bitmap_from_tce_table():
1338  * Funtion for kdump case. In the second/kdump kernel initialize
1339  * the bitmap based on the tce table entries obtained from first kernel
1340  */
1341 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1342 {
1343         u64 *tp;
1344         unsigned int index;
1345         tp = ((u64 *)tbl->it_base);
1346         for (index = 0 ; index < tbl->it_size; index++) {
1347                 if (*tp != 0x0)
1348                         set_bit(index, tbl->it_map);
1349                 tp++;
1350         }
1351 }
1352
1353 /*
1354  * get_tce_space_from_tar():
1355  * Function for kdump case. Get the tce tables from first kernel
1356  * by reading the contents of the base adress register of calgary iommu
1357  */
1358 static void __init get_tce_space_from_tar(void)
1359 {
1360         int bus;
1361         void __iomem *target;
1362         unsigned long tce_space;
1363
1364         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1365                 struct calgary_bus_info *info = &bus_info[bus];
1366                 unsigned short pci_device;
1367                 u32 val;
1368
1369                 val = read_pci_config(bus, 0, 0, 0);
1370                 pci_device = (val & 0xFFFF0000) >> 16;
1371
1372                 if (!is_cal_pci_dev(pci_device))
1373                         continue;
1374                 if (info->translation_disabled)
1375                         continue;
1376
1377                 if (calgary_bus_has_devices(bus, pci_device) ||
1378                                                 translate_empty_slots) {
1379                         target = calgary_reg(bus_info[bus].bbar,
1380                                                 tar_offset(bus));
1381                         tce_space = be64_to_cpu(readq(target));
1382                         tce_space = tce_space & TAR_SW_BITS;
1383
1384                         tce_space = tce_space & (~specified_table_size);
1385                         info->tce_space = (u64 *)__va(tce_space);
1386                 }
1387         }
1388         return;
1389 }
1390
1391 void __init detect_calgary(void)
1392 {
1393         int bus;
1394         void *tbl;
1395         int calgary_found = 0;
1396         unsigned long ptr;
1397         unsigned int offset, prev_offset;
1398         int ret;
1399
1400         /*
1401          * if the user specified iommu=off or iommu=soft or we found
1402          * another HW IOMMU already, bail out.
1403          */
1404         if (swiotlb || no_iommu || iommu_detected)
1405                 return;
1406
1407         if (!use_calgary)
1408                 return;
1409
1410         if (!early_pci_allowed())
1411                 return;
1412
1413         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1414
1415         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1416
1417         rio_table_hdr = NULL;
1418         prev_offset = 0;
1419         offset = 0x180;
1420         /*
1421          * The next offset is stored in the 1st word.
1422          * Only parse up until the offset increases:
1423          */
1424         while (offset > prev_offset) {
1425                 /* The block id is stored in the 2nd word */
1426                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1427                         /* set the pointer past the offset & block id */
1428                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1429                         break;
1430                 }
1431                 prev_offset = offset;
1432                 offset = *((unsigned short *)(ptr + offset));
1433         }
1434         if (!rio_table_hdr) {
1435                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1436                        "in EBDA - bailing!\n");
1437                 return;
1438         }
1439
1440         ret = build_detail_arrays();
1441         if (ret) {
1442                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1443                 return;
1444         }
1445
1446         specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1447                                         saved_max_pfn : max_pfn) * PAGE_SIZE);
1448
1449         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1450                 struct calgary_bus_info *info = &bus_info[bus];
1451                 unsigned short pci_device;
1452                 u32 val;
1453
1454                 val = read_pci_config(bus, 0, 0, 0);
1455                 pci_device = (val & 0xFFFF0000) >> 16;
1456
1457                 if (!is_cal_pci_dev(pci_device))
1458                         continue;
1459
1460                 if (info->translation_disabled)
1461                         continue;
1462
1463                 if (calgary_bus_has_devices(bus, pci_device) ||
1464                     translate_empty_slots) {
1465                         /*
1466                          * If it is kdump kernel, find and use tce tables
1467                          * from first kernel, else allocate tce tables here
1468                          */
1469                         if (!is_kdump_kernel()) {
1470                                 tbl = alloc_tce_table();
1471                                 if (!tbl)
1472                                         goto cleanup;
1473                                 info->tce_space = tbl;
1474                         }
1475                         calgary_found = 1;
1476                 }
1477         }
1478
1479         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1480                calgary_found ? "found" : "not found");
1481
1482         if (calgary_found) {
1483                 iommu_detected = 1;
1484                 calgary_detected = 1;
1485                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1486                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1487                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1488                        debugging ? "enabled" : "disabled");
1489
1490                 /* swiotlb for devices that aren't behind the Calgary. */
1491                 if (max_pfn > MAX_DMA32_PFN)
1492                         swiotlb = 1;
1493         }
1494         return;
1495
1496 cleanup:
1497         for (--bus; bus >= 0; --bus) {
1498                 struct calgary_bus_info *info = &bus_info[bus];
1499
1500                 if (info->tce_space)
1501                         free_tce_table(info->tce_space);
1502         }
1503 }
1504
1505 int __init calgary_iommu_init(void)
1506 {
1507         int ret;
1508
1509         if (no_iommu || (swiotlb && !calgary_detected))
1510                 return -ENODEV;
1511
1512         if (!calgary_detected)
1513                 return -ENODEV;
1514
1515         /* ok, we're trying to use Calgary - let's roll */
1516         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1517
1518         ret = calgary_init();
1519         if (ret) {
1520                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1521                        "falling back to no_iommu\n", ret);
1522                 return ret;
1523         }
1524
1525         force_iommu = 1;
1526         bad_dma_address = 0x0;
1527         /* dma_ops is set to swiotlb or nommu */
1528         if (!dma_ops)
1529                 dma_ops = &nommu_dma_ops;
1530
1531         return 0;
1532 }
1533
1534 static int __init calgary_parse_options(char *p)
1535 {
1536         unsigned int bridge;
1537         size_t len;
1538         char* endp;
1539
1540         while (*p) {
1541                 if (!strncmp(p, "64k", 3))
1542                         specified_table_size = TCE_TABLE_SIZE_64K;
1543                 else if (!strncmp(p, "128k", 4))
1544                         specified_table_size = TCE_TABLE_SIZE_128K;
1545                 else if (!strncmp(p, "256k", 4))
1546                         specified_table_size = TCE_TABLE_SIZE_256K;
1547                 else if (!strncmp(p, "512k", 4))
1548                         specified_table_size = TCE_TABLE_SIZE_512K;
1549                 else if (!strncmp(p, "1M", 2))
1550                         specified_table_size = TCE_TABLE_SIZE_1M;
1551                 else if (!strncmp(p, "2M", 2))
1552                         specified_table_size = TCE_TABLE_SIZE_2M;
1553                 else if (!strncmp(p, "4M", 2))
1554                         specified_table_size = TCE_TABLE_SIZE_4M;
1555                 else if (!strncmp(p, "8M", 2))
1556                         specified_table_size = TCE_TABLE_SIZE_8M;
1557
1558                 len = strlen("translate_empty_slots");
1559                 if (!strncmp(p, "translate_empty_slots", len))
1560                         translate_empty_slots = 1;
1561
1562                 len = strlen("disable");
1563                 if (!strncmp(p, "disable", len)) {
1564                         p += len;
1565                         if (*p == '=')
1566                                 ++p;
1567                         if (*p == '\0')
1568                                 break;
1569                         bridge = simple_strtol(p, &endp, 0);
1570                         if (p == endp)
1571                                 break;
1572
1573                         if (bridge < MAX_PHB_BUS_NUM) {
1574                                 printk(KERN_INFO "Calgary: disabling "
1575                                        "translation for PHB %#x\n", bridge);
1576                                 bus_info[bridge].translation_disabled = 1;
1577                         }
1578                 }
1579
1580                 p = strpbrk(p, ",");
1581                 if (!p)
1582                         break;
1583
1584                 p++; /* skip ',' */
1585         }
1586         return 1;
1587 }
1588 __setup("calgary=", calgary_parse_options);
1589
1590 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1591 {
1592         struct iommu_table *tbl;
1593         unsigned int npages;
1594         int i;
1595
1596         tbl = pci_iommu(dev->bus);
1597
1598         for (i = 0; i < 4; i++) {
1599                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1600
1601                 /* Don't give out TCEs that map MEM resources */
1602                 if (!(r->flags & IORESOURCE_MEM))
1603                         continue;
1604
1605                 /* 0-based? we reserve the whole 1st MB anyway */
1606                 if (!r->start)
1607                         continue;
1608
1609                 /* cover the whole region */
1610                 npages = (r->end - r->start) >> PAGE_SHIFT;
1611                 npages++;
1612
1613                 iommu_range_reserve(tbl, r->start, npages);
1614         }
1615 }
1616
1617 static int __init calgary_fixup_tce_spaces(void)
1618 {
1619         struct pci_dev *dev = NULL;
1620         struct calgary_bus_info *info;
1621
1622         if (no_iommu || swiotlb || !calgary_detected)
1623                 return -ENODEV;
1624
1625         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1626
1627         do {
1628                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1629                 if (!dev)
1630                         break;
1631                 if (!is_cal_pci_dev(dev->device))
1632                         continue;
1633
1634                 info = &bus_info[dev->bus->number];
1635                 if (info->translation_disabled)
1636                         continue;
1637
1638                 if (!info->tce_space)
1639                         continue;
1640
1641                 calgary_fixup_one_tce_space(dev);
1642
1643         } while (1);
1644
1645         return 0;
1646 }
1647
1648 /*
1649  * We need to be call after pcibios_assign_resources (fs_initcall level)
1650  * and before device_initcall.
1651  */
1652 rootfs_initcall(calgary_fixup_tce_spaces);