1 #include <linux/cpumask.h>
2 #include <linux/interrupt.h>
3 #include <linux/init.h>
6 #include <linux/delay.h>
7 #include <linux/spinlock.h>
8 #include <linux/kernel_stat.h>
9 #include <linux/mc146818rtc.h>
10 #include <linux/cache.h>
11 #include <linux/interrupt.h>
12 #include <linux/cpu.h>
13 #include <linux/module.h>
17 #include <asm/tlbflush.h>
18 #include <asm/mmu_context.h>
20 #include <asm/proto.h>
23 #include <mach_apic.h>
25 * the following functions deal with sending IPIs between CPUs.
27 * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
30 static inline int __prepare_ICR(unsigned int shortcut, int vector)
32 unsigned int icr = shortcut | APIC_DEST_LOGICAL;
36 icr |= APIC_DM_FIXED | vector;
45 static inline int __prepare_ICR2(unsigned int mask)
47 return SET_APIC_DEST_FIELD(mask);
50 void __send_IPI_shortcut(unsigned int shortcut, int vector)
53 * Subtle. In the case of the 'never do double writes' workaround
54 * we have to lock out interrupts to be safe. As we don't care
55 * of the value read we use an atomic rmw access to avoid costly
56 * cli/sti. Otherwise we use an even cheaper single atomic write
67 * No need to touch the target chip field
69 cfg = __prepare_ICR(shortcut, vector);
72 * Send the IPI. The write to APIC_ICR fires this off.
74 apic_write_around(APIC_ICR, cfg);
77 void send_IPI_self(int vector)
79 __send_IPI_shortcut(APIC_DEST_SELF, vector);
83 * This is used to send an IPI with no shorthand notation (the destination is
84 * specified in bits 56 to 63 of the ICR).
86 static inline void __send_IPI_dest_field(unsigned long mask, int vector)
93 if (unlikely(vector == NMI_VECTOR))
94 safe_apic_wait_icr_idle();
99 * prepare target chip field
101 cfg = __prepare_ICR2(mask);
102 apic_write_around(APIC_ICR2, cfg);
107 cfg = __prepare_ICR(0, vector);
110 * Send the IPI. The write to APIC_ICR fires this off.
112 apic_write_around(APIC_ICR, cfg);
116 * This is only used on smaller machines.
118 void send_IPI_mask_bitmask(cpumask_t cpumask, int vector)
120 unsigned long mask = cpus_addr(cpumask)[0];
123 local_irq_save(flags);
124 WARN_ON(mask & ~cpus_addr(cpu_online_map)[0]);
125 __send_IPI_dest_field(mask, vector);
126 local_irq_restore(flags);
129 void send_IPI_mask_sequence(cpumask_t mask, int vector)
132 unsigned int query_cpu;
135 * Hack. The clustered APIC addressing mode doesn't allow us to send
136 * to an arbitrary mask, so I do a unicasts to each CPU instead. This
137 * should be modified to do 1 message per cluster ID - mbligh
140 local_irq_save(flags);
141 for_each_possible_cpu(query_cpu) {
142 if (cpu_isset(query_cpu, mask)) {
143 __send_IPI_dest_field(cpu_to_logical_apicid(query_cpu),
147 local_irq_restore(flags);
150 /* must come after the send_IPI functions above for inlining */
151 #include <mach_ipi.h>
152 static int convert_apicid_to_cpu(int apic_id)
156 for_each_possible_cpu(i) {
157 if (per_cpu(x86_cpu_to_apicid, i) == apic_id)
163 int safe_smp_processor_id(void)
167 if (!boot_cpu_has(X86_FEATURE_APIC))
170 apicid = hard_smp_processor_id();
171 if (apicid == BAD_APICID)
174 cpuid = convert_apicid_to_cpu(apicid);
176 return cpuid >= 0 ? cpuid : 0;