arch/x86/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/pci.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39 #ifdef CONFIG_ACPI
  40 #include <acpi/acpi_bus.h>
  41 #endif
  42 #include <linux/bootmem.h>
  43 #include <linux/dmar.h>
  44 #include <linux/hpet.h>
  45
  46 #include <asm/idle.h>
  47 #include <asm/io.h>
  48 #include <asm/smp.h>
  49 #include <asm/cpu.h>
  50 #include <asm/desc.h>
  51 #include <asm/proto.h>
  52 #include <asm/acpi.h>
  53 #include <asm/dma.h>
  54 #include <asm/timer.h>
  55 #include <asm/i8259.h>
  56 #include <asm/nmi.h>
  57 #include <asm/msidef.h>
  58 #include <asm/hypertransport.h>
  59 #include <asm/setup.h>
  60 #include <asm/irq_remapping.h>
  61 #include <asm/hpet.h>
  62 #include <asm/uv/uv_hub.h>
  63 #include <asm/uv/uv_irq.h>
  64
  65 #include <asm/genapic.h>
  66
  67 #define __apicdebuginit(type) static type __init
  68
  69 /*
  70  *      Is the SiS APIC rmw bug present ?
  71  *      -1 = don't know, 0 = no, 1 = yes
  72  */
  73 int sis_apic_bug = -1;
  74
  75 static DEFINE_SPINLOCK(ioapic_lock);
  76 static DEFINE_SPINLOCK(vector_lock);
  77
  78 /*
  79  * # of IRQ routing registers
  80  */
  81 int nr_ioapic_registers[MAX_IO_APICS];
  82
  83 /* I/O APIC entries */
  84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
  85 int nr_ioapics;
  86
  87 /* MP IRQ source entries */
  88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
  89
  90 /* # of MP IRQ source entries */
  91 int mp_irq_entries;
  92
  93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  94 int mp_bus_id_to_type[MAX_MP_BUSSES];
  95 #endif
  96
  97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  98
  99 int skip_ioapic_setup;
 100
 101 static int __init parse_noapic(char *str)
 102 {
 103         /* disable IO-APIC */
 104         disable_ioapic_setup();
 105         return 0;
 106 }
 107 early_param("noapic", parse_noapic);
 108
 109 struct irq_pin_list;
 110
 111 /*
 112  * This is performance-critical, we want to do it O(1)
 113  *
 114  * the indexing order of this array favors 1:1 mappings
 115  * between pins and IRQs.
 116  */
 117
 118 struct irq_pin_list {
 119         int apic, pin;
 120         struct irq_pin_list *next;
 121 };
 122
 123 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
 124 {
 125         struct irq_pin_list *pin;
 126         int node;
 127
 128         node = cpu_to_node(cpu);
 129
 130         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
 131
 132         return pin;
 133 }
 134
 135 struct irq_cfg {
 136         struct irq_pin_list *irq_2_pin;
 137         cpumask_var_t domain;
 138         cpumask_var_t old_domain;
 139         unsigned move_cleanup_count;
 140         u8 vector;
 141         u8 move_in_progress : 1;
 142 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 143         u8 move_desc_pending : 1;
 144 #endif
 145 };
 146
 147 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
 148 #ifdef CONFIG_SPARSE_IRQ
 149 static struct irq_cfg irq_cfgx[] = {
 150 #else
 151 static struct irq_cfg irq_cfgx[NR_IRQS] = {
 152 #endif
 153         [0]  = { .vector = IRQ0_VECTOR,  },
 154         [1]  = { .vector = IRQ1_VECTOR,  },
 155         [2]  = { .vector = IRQ2_VECTOR,  },
 156         [3]  = { .vector = IRQ3_VECTOR,  },
 157         [4]  = { .vector = IRQ4_VECTOR,  },
 158         [5]  = { .vector = IRQ5_VECTOR,  },
 159         [6]  = { .vector = IRQ6_VECTOR,  },
 160         [7]  = { .vector = IRQ7_VECTOR,  },
 161         [8]  = { .vector = IRQ8_VECTOR,  },
 162         [9]  = { .vector = IRQ9_VECTOR,  },
 163         [10] = { .vector = IRQ10_VECTOR, },
 164         [11] = { .vector = IRQ11_VECTOR, },
 165         [12] = { .vector = IRQ12_VECTOR, },
 166         [13] = { .vector = IRQ13_VECTOR, },
 167         [14] = { .vector = IRQ14_VECTOR, },
 168         [15] = { .vector = IRQ15_VECTOR, },
 169 };
 170
 171 int __init arch_early_irq_init(void)
 172 {
 173         struct irq_cfg *cfg;
 174         struct irq_desc *desc;
 175         int count;
 176         int i;
 177
 178         cfg = irq_cfgx;
 179         count = ARRAY_SIZE(irq_cfgx);
 180
 181         for (i = 0; i < count; i++) {
 182                 desc = irq_to_desc(i);
 183                 desc->chip_data = &cfg[i];
 184                 alloc_bootmem_cpumask_var(&cfg[i].domain);
 185                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
 186                 if (i < NR_IRQS_LEGACY)
 187                         cpumask_setall(cfg[i].domain);
 188         }
 189
 190         return 0;
 191 }
 192
 193 #ifdef CONFIG_SPARSE_IRQ
 194 static struct irq_cfg *irq_cfg(unsigned int irq)
 195 {
 196         struct irq_cfg *cfg = NULL;
 197         struct irq_desc *desc;
 198
 199         desc = irq_to_desc(irq);
 200         if (desc)
 201                 cfg = desc->chip_data;
 202
 203         return cfg;
 204 }
 205
 206 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
 207 {
 208         struct irq_cfg *cfg;
 209         int node;
 210
 211         node = cpu_to_node(cpu);
 212
 213         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
 214         if (cfg) {
 215                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
 216                         kfree(cfg);
 217                         cfg = NULL;
 218                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
 219                                                           GFP_ATOMIC, node)) {
 220                         free_cpumask_var(cfg->domain);
 221                         kfree(cfg);
 222                         cfg = NULL;
 223                 } else {
 224                         cpumask_clear(cfg->domain);
 225                         cpumask_clear(cfg->old_domain);
 226                 }
 227         }
 228
 229         return cfg;
 230 }
 231
 232 int arch_init_chip_data(struct irq_desc *desc, int cpu)
 233 {
 234         struct irq_cfg *cfg;
 235
 236         cfg = desc->chip_data;
 237         if (!cfg) {
 238                 desc->chip_data = get_one_free_irq_cfg(cpu);
 239                 if (!desc->chip_data) {
 240                         printk(KERN_ERR "can not alloc irq_cfg\n");
 241                         BUG_ON(1);
 242                 }
 243         }
 244
 245         return 0;
 246 }
 247
 248 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 249
 250 static void
 251 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
 252 {
 253         struct irq_pin_list *old_entry, *head, *tail, *entry;
 254
 255         cfg->irq_2_pin = NULL;
 256         old_entry = old_cfg->irq_2_pin;
 257         if (!old_entry)
 258                 return;
 259
 260         entry = get_one_free_irq_2_pin(cpu);
 261         if (!entry)
 262                 return;
 263
 264         entry->apic     = old_entry->apic;
 265         entry->pin      = old_entry->pin;
 266         head            = entry;
 267         tail            = entry;
 268         old_entry       = old_entry->next;
 269         while (old_entry) {
 270                 entry = get_one_free_irq_2_pin(cpu);
 271                 if (!entry) {
 272                         entry = head;
 273                         while (entry) {
 274                                 head = entry->next;
 275                                 kfree(entry);
 276                                 entry = head;
 277                         }
 278                         /* still use the old one */
 279                         return;
 280                 }
 281                 entry->apic     = old_entry->apic;
 282                 entry->pin      = old_entry->pin;
 283                 tail->next      = entry;
 284                 tail            = entry;
 285                 old_entry       = old_entry->next;
 286         }
 287
 288         tail->next = NULL;
 289         cfg->irq_2_pin = head;
 290 }
 291
 292 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
 293 {
 294         struct irq_pin_list *entry, *next;
 295
 296         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
 297                 return;
 298
 299         entry = old_cfg->irq_2_pin;
 300
 301         while (entry) {
 302                 next = entry->next;
 303                 kfree(entry);
 304                 entry = next;
 305         }
 306         old_cfg->irq_2_pin = NULL;
 307 }
 308
 309 void arch_init_copy_chip_data(struct irq_desc *old_desc,
 310                                  struct irq_desc *desc, int cpu)
 311 {
 312         struct irq_cfg *cfg;
 313         struct irq_cfg *old_cfg;
 314
 315         cfg = get_one_free_irq_cfg(cpu);
 316
 317         if (!cfg)
 318                 return;
 319
 320         desc->chip_data = cfg;
 321
 322         old_cfg = old_desc->chip_data;
 323
 324         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
 325
 326         init_copy_irq_2_pin(old_cfg, cfg, cpu);
 327 }
 328
 329 static void free_irq_cfg(struct irq_cfg *old_cfg)
 330 {
 331         kfree(old_cfg);
 332 }
 333
 334 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
 335 {
 336         struct irq_cfg *old_cfg, *cfg;
 337
 338         old_cfg = old_desc->chip_data;
 339         cfg = desc->chip_data;
 340
 341         if (old_cfg == cfg)
 342                 return;
 343
 344         if (old_cfg) {
 345                 free_irq_2_pin(old_cfg, cfg);
 346                 free_irq_cfg(old_cfg);
 347                 old_desc->chip_data = NULL;
 348         }
 349 }
 350
 351 static void
 352 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 353 {
 354         struct irq_cfg *cfg = desc->chip_data;
 355
 356         if (!cfg->move_in_progress) {
 357                 /* it means that domain is not changed */
 358                 if (!cpumask_intersects(desc->affinity, mask))
 359                         cfg->move_desc_pending = 1;
 360         }
 361 }
 362 #endif
 363
 364 #else
 365 static struct irq_cfg *irq_cfg(unsigned int irq)
 366 {
 367         return irq < nr_irqs ? irq_cfgx + irq : NULL;
 368 }
 369
 370 #endif
 371
 372 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
 373 static inline void
 374 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 375 {
 376 }
 377 #endif
 378
 379 struct io_apic {
 380         unsigned int index;
 381         unsigned int unused[3];
 382         unsigned int data;
 383 };
 384
 385 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 386 {
 387         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 388                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
 389 }
 390
 391 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 392 {
 393         struct io_apic __iomem *io_apic = io_apic_base(apic);
 394         writel(reg, &io_apic->index);
 395         return readl(&io_apic->data);
 396 }
 397
 398 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 399 {
 400         struct io_apic __iomem *io_apic = io_apic_base(apic);
 401         writel(reg, &io_apic->index);
 402         writel(value, &io_apic->data);
 403 }
 404
 405 /*
 406  * Re-write a value: to be used for read-modify-write
 407  * cycles where the read already set up the index register.
 408  *
 409  * Older SiS APIC requires we rewrite the index register
 410  */
 411 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 412 {
 413         struct io_apic __iomem *io_apic = io_apic_base(apic);
 414
 415         if (sis_apic_bug)
 416                 writel(reg, &io_apic->index);
 417         writel(value, &io_apic->data);
 418 }
 419
 420 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
 421 {
 422         struct irq_pin_list *entry;
 423         unsigned long flags;
 424
 425         spin_lock_irqsave(&ioapic_lock, flags);
 426         entry = cfg->irq_2_pin;
 427         for (;;) {
 428                 unsigned int reg;
 429                 int pin;
 430
 431                 if (!entry)
 432                         break;
 433                 pin = entry->pin;
 434                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 435                 /* Is the remote IRR bit set? */
 436                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
 437                         spin_unlock_irqrestore(&ioapic_lock, flags);
 438                         return true;
 439                 }
 440                 if (!entry->next)
 441                         break;
 442                 entry = entry->next;
 443         }
 444         spin_unlock_irqrestore(&ioapic_lock, flags);
 445
 446         return false;
 447 }
 448
 449 union entry_union {
 450         struct { u32 w1, w2; };
 451         struct IO_APIC_route_entry entry;
 452 };
 453
 454 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 455 {
 456         union entry_union eu;
 457         unsigned long flags;
 458         spin_lock_irqsave(&ioapic_lock, flags);
 459         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 460         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 461         spin_unlock_irqrestore(&ioapic_lock, flags);
 462         return eu.entry;
 463 }
 464
 465 /*
 466  * When we write a new IO APIC routing entry, we need to write the high
 467  * word first! If the mask bit in the low word is clear, we will enable
 468  * the interrupt, and we need to make sure the entry is fully populated
 469  * before that happens.
 470  */
 471 static void
 472 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 473 {
 474         union entry_union eu;
 475         eu.entry = e;
 476         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 477         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 478 }
 479
 480 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 481 {
 482         unsigned long flags;
 483         spin_lock_irqsave(&ioapic_lock, flags);
 484         __ioapic_write_entry(apic, pin, e);
 485         spin_unlock_irqrestore(&ioapic_lock, flags);
 486 }
 487
 488 /*
 489  * When we mask an IO APIC routing entry, we need to write the low
 490  * word first, in order to set the mask bit before we change the
 491  * high bits!
 492  */
 493 static void ioapic_mask_entry(int apic, int pin)
 494 {
 495         unsigned long flags;
 496         union entry_union eu = { .entry.mask = 1 };
 497
 498         spin_lock_irqsave(&ioapic_lock, flags);
 499         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 500         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 501         spin_unlock_irqrestore(&ioapic_lock, flags);
 502 }
 503
 504 #ifdef CONFIG_SMP
 505 static void send_cleanup_vector(struct irq_cfg *cfg)
 506 {
 507         cpumask_var_t cleanup_mask;
 508
 509         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
 510                 unsigned int i;
 511                 cfg->move_cleanup_count = 0;
 512                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 513                         cfg->move_cleanup_count++;
 514                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 515                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
 516         } else {
 517                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
 518                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
 519                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
 520                 free_cpumask_var(cleanup_mask);
 521         }
 522         cfg->move_in_progress = 0;
 523 }
 524
 525 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
 526 {
 527         int apic, pin;
 528         struct irq_pin_list *entry;
 529         u8 vector = cfg->vector;
 530
 531         entry = cfg->irq_2_pin;
 532         for (;;) {
 533                 unsigned int reg;
 534
 535                 if (!entry)
 536                         break;
 537
 538                 apic = entry->apic;
 539                 pin = entry->pin;
 540 #ifdef CONFIG_INTR_REMAP
 541                 /*
 542                  * With interrupt-remapping, destination information comes
 543                  * from interrupt-remapping table entry.
 544                  */
 545                 if (!irq_remapped(irq))
 546                         io_apic_write(apic, 0x11 + pin*2, dest);
 547 #else
 548                 io_apic_write(apic, 0x11 + pin*2, dest);
 549 #endif
 550                 reg = io_apic_read(apic, 0x10 + pin*2);
 551                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
 552                 reg |= vector;
 553                 io_apic_modify(apic, 0x10 + pin*2, reg);
 554                 if (!entry->next)
 555                         break;
 556                 entry = entry->next;
 557         }
 558 }
 559
 560 static int
 561 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
 562
 563 /*
 564  * Either sets desc->affinity to a valid value, and returns
 565  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
 566  * leaves desc->affinity untouched.
 567  */
 568 static unsigned int
 569 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
 570 {
 571         struct irq_cfg *cfg;
 572         unsigned int irq;
 573
 574         if (!cpumask_intersects(mask, cpu_online_mask))
 575                 return BAD_APICID;
 576
 577         irq = desc->irq;
 578         cfg = desc->chip_data;
 579         if (assign_irq_vector(irq, cfg, mask))
 580                 return BAD_APICID;
 581
 582         cpumask_and(desc->affinity, cfg->domain, mask);
 583         set_extra_move_desc(desc, mask);
 584
 585         return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
 586 }
 587
 588 static void
 589 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
 590 {
 591         struct irq_cfg *cfg;
 592         unsigned long flags;
 593         unsigned int dest;
 594         unsigned int irq;
 595
 596         irq = desc->irq;
 597         cfg = desc->chip_data;
 598
 599         spin_lock_irqsave(&ioapic_lock, flags);
 600         dest = set_desc_affinity(desc, mask);
 601         if (dest != BAD_APICID) {
 602                 /* Only the high 8 bits are valid. */
 603                 dest = SET_APIC_LOGICAL_ID(dest);
 604                 __target_IO_APIC_irq(irq, dest, cfg);
 605         }
 606         spin_unlock_irqrestore(&ioapic_lock, flags);
 607 }
 608
 609 static void
 610 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
 611 {
 612         struct irq_desc *desc;
 613
 614         desc = irq_to_desc(irq);
 615
 616         set_ioapic_affinity_irq_desc(desc, mask);
 617 }
 618 #endif /* CONFIG_SMP */
 619
 620 /*
 621  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 622  * shared ISA-space IRQs, so we have to support them. We are super
 623  * fast in the common case, and fast for shared ISA-space IRQs.
 624  */
 625 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
 626 {
 627         struct irq_pin_list *entry;
 628
 629         entry = cfg->irq_2_pin;
 630         if (!entry) {
 631                 entry = get_one_free_irq_2_pin(cpu);
 632                 if (!entry) {
 633                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
 634                                         apic, pin);
 635                         return;
 636                 }
 637                 cfg->irq_2_pin = entry;
 638                 entry->apic = apic;
 639                 entry->pin = pin;
 640                 return;
 641         }
 642
 643         while (entry->next) {
 644                 /* not again, please */
 645                 if (entry->apic == apic && entry->pin == pin)
 646                         return;
 647
 648                 entry = entry->next;
 649         }
 650
 651         entry->next = get_one_free_irq_2_pin(cpu);
 652         entry = entry->next;
 653         entry->apic = apic;
 654         entry->pin = pin;
 655 }
 656
 657 /*
 658  * Reroute an IRQ to a different pin.
 659  */
 660 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
 661                                       int oldapic, int oldpin,
 662                                       int newapic, int newpin)
 663 {
 664         struct irq_pin_list *entry = cfg->irq_2_pin;
 665         int replaced = 0;
 666
 667         while (entry) {
 668                 if (entry->apic == oldapic && entry->pin == oldpin) {
 669                         entry->apic = newapic;
 670                         entry->pin = newpin;
 671                         replaced = 1;
 672                         /* every one is different, right? */
 673                         break;
 674                 }
 675                 entry = entry->next;
 676         }
 677
 678         /* why? call replace before add? */
 679         if (!replaced)
 680                 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
 681 }
 682
 683 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
 684                                 int mask_and, int mask_or,
 685                                 void (*final)(struct irq_pin_list *entry))
 686 {
 687         int pin;
 688         struct irq_pin_list *entry;
 689
 690         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
 691                 unsigned int reg;
 692                 pin = entry->pin;
 693                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
 694                 reg &= mask_and;
 695                 reg |= mask_or;
 696                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
 697                 if (final)
 698                         final(entry);
 699         }
 700 }
 701
 702 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
 703 {
 704         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
 705 }
 706
 707 #ifdef CONFIG_X86_64
 708 static void io_apic_sync(struct irq_pin_list *entry)
 709 {
 710         /*
 711          * Synchronize the IO-APIC and the CPU by doing
 712          * a dummy read from the IO-APIC
 713          */
 714         struct io_apic __iomem *io_apic;
 715         io_apic = io_apic_base(entry->apic);
 716         readl(&io_apic->data);
 717 }
 718
 719 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 720 {
 721         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
 722 }
 723 #else /* CONFIG_X86_32 */
 724 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 725 {
 726         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
 727 }
 728
 729 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
 730 {
 731         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
 732                         IO_APIC_REDIR_MASKED, NULL);
 733 }
 734
 735 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
 736 {
 737         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
 738                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
 739 }
 740 #endif /* CONFIG_X86_32 */
 741
 742 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
 743 {
 744         struct irq_cfg *cfg = desc->chip_data;
 745         unsigned long flags;
 746
 747         BUG_ON(!cfg);
 748
 749         spin_lock_irqsave(&ioapic_lock, flags);
 750         __mask_IO_APIC_irq(cfg);
 751         spin_unlock_irqrestore(&ioapic_lock, flags);
 752 }
 753
 754 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
 755 {
 756         struct irq_cfg *cfg = desc->chip_data;
 757         unsigned long flags;
 758
 759         spin_lock_irqsave(&ioapic_lock, flags);
 760         __unmask_IO_APIC_irq(cfg);
 761         spin_unlock_irqrestore(&ioapic_lock, flags);
 762 }
 763
 764 static void mask_IO_APIC_irq(unsigned int irq)
 765 {
 766         struct irq_desc *desc = irq_to_desc(irq);
 767
 768         mask_IO_APIC_irq_desc(desc);
 769 }
 770 static void unmask_IO_APIC_irq(unsigned int irq)
 771 {
 772         struct irq_desc *desc = irq_to_desc(irq);
 773
 774         unmask_IO_APIC_irq_desc(desc);
 775 }
 776
 777 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 778 {
 779         struct IO_APIC_route_entry entry;
 780
 781         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 782         entry = ioapic_read_entry(apic, pin);
 783         if (entry.delivery_mode == dest_SMI)
 784                 return;
 785         /*
 786          * Disable it in the IO-APIC irq-routing table:
 787          */
 788         ioapic_mask_entry(apic, pin);
 789 }
 790
 791 static void clear_IO_APIC (void)
 792 {
 793         int apic, pin;
 794
 795         for (apic = 0; apic < nr_ioapics; apic++)
 796                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 797                         clear_IO_APIC_pin(apic, pin);
 798 }
 799
 800 #ifdef CONFIG_X86_32
 801 /*
 802  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 803  * specific CPU-side IRQs.
 804  */
 805
 806 #define MAX_PIRQS 8
 807 static int pirq_entries [MAX_PIRQS];
 808 static int pirqs_enabled;
 809
 810 static int __init ioapic_pirq_setup(char *str)
 811 {
 812         int i, max;
 813         int ints[MAX_PIRQS+1];
 814
 815         get_options(str, ARRAY_SIZE(ints), ints);
 816
 817         for (i = 0; i < MAX_PIRQS; i++)
 818                 pirq_entries[i] = -1;
 819
 820         pirqs_enabled = 1;
 821         apic_printk(APIC_VERBOSE, KERN_INFO
 822                         "PIRQ redirection, working around broken MP-BIOS.\n");
 823         max = MAX_PIRQS;
 824         if (ints[0] < MAX_PIRQS)
 825                 max = ints[0];
 826
 827         for (i = 0; i < max; i++) {
 828                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 829                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 830                 /*
 831                  * PIRQs are mapped upside down, usually.
 832                  */
 833                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 834         }
 835         return 1;
 836 }
 837
 838 __setup("pirq=", ioapic_pirq_setup);
 839 #endif /* CONFIG_X86_32 */
 840
 841 #ifdef CONFIG_INTR_REMAP
 842 /* I/O APIC RTE contents at the OS boot up */
 843 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
 844
 845 /*
 846  * Saves and masks all the unmasked IO-APIC RTE's
 847  */
 848 int save_mask_IO_APIC_setup(void)
 849 {
 850         union IO_APIC_reg_01 reg_01;
 851         unsigned long flags;
 852         int apic, pin;
 853
 854         /*
 855          * The number of IO-APIC IRQ registers (== #pins):
 856          */
 857         for (apic = 0; apic < nr_ioapics; apic++) {
 858                 spin_lock_irqsave(&ioapic_lock, flags);
 859                 reg_01.raw = io_apic_read(apic, 1);
 860                 spin_unlock_irqrestore(&ioapic_lock, flags);
 861                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
 862         }
 863
 864         for (apic = 0; apic < nr_ioapics; apic++) {
 865                 early_ioapic_entries[apic] =
 866                         kzalloc(sizeof(struct IO_APIC_route_entry) *
 867                                 nr_ioapic_registers[apic], GFP_KERNEL);
 868                 if (!early_ioapic_entries[apic])
 869                         goto nomem;
 870         }
 871
 872         for (apic = 0; apic < nr_ioapics; apic++)
 873                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 874                         struct IO_APIC_route_entry entry;
 875
 876                         entry = early_ioapic_entries[apic][pin] =
 877                                 ioapic_read_entry(apic, pin);
 878                         if (!entry.mask) {
 879                                 entry.mask = 1;
 880                                 ioapic_write_entry(apic, pin, entry);
 881                         }
 882                 }
 883
 884         return 0;
 885
 886 nomem:
 887         while (apic >= 0)
 888                 kfree(early_ioapic_entries[apic--]);
 889         memset(early_ioapic_entries, 0,
 890                 ARRAY_SIZE(early_ioapic_entries));
 891
 892         return -ENOMEM;
 893 }
 894
 895 void restore_IO_APIC_setup(void)
 896 {
 897         int apic, pin;
 898
 899         for (apic = 0; apic < nr_ioapics; apic++) {
 900                 if (!early_ioapic_entries[apic])
 901                         break;
 902                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 903                         ioapic_write_entry(apic, pin,
 904                                            early_ioapic_entries[apic][pin]);
 905                 kfree(early_ioapic_entries[apic]);
 906                 early_ioapic_entries[apic] = NULL;
 907         }
 908 }
 909
 910 void reinit_intr_remapped_IO_APIC(int intr_remapping)
 911 {
 912         /*
 913          * for now plain restore of previous settings.
 914          * TBD: In the case of OS enabling interrupt-remapping,
 915          * IO-APIC RTE's need to be setup to point to interrupt-remapping
 916          * table entries. for now, do a plain restore, and wait for
 917          * the setup_IO_APIC_irqs() to do proper initialization.
 918          */
 919         restore_IO_APIC_setup();
 920 }
 921 #endif
 922
 923 /*
 924  * Find the IRQ entry number of a certain pin.
 925  */
 926 static int find_irq_entry(int apic, int pin, int type)
 927 {
 928         int i;
 929
 930         for (i = 0; i < mp_irq_entries; i++)
 931                 if (mp_irqs[i].irqtype == type &&
 932                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
 933                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
 934                     mp_irqs[i].dstirq == pin)
 935                         return i;
 936
 937         return -1;
 938 }
 939
 940 /*
 941  * Find the pin to which IRQ[irq] (ISA) is connected
 942  */
 943 static int __init find_isa_irq_pin(int irq, int type)
 944 {
 945         int i;
 946
 947         for (i = 0; i < mp_irq_entries; i++) {
 948                 int lbus = mp_irqs[i].srcbus;
 949
 950                 if (test_bit(lbus, mp_bus_not_pci) &&
 951                     (mp_irqs[i].irqtype == type) &&
 952                     (mp_irqs[i].srcbusirq == irq))
 953
 954                         return mp_irqs[i].dstirq;
 955         }
 956         return -1;
 957 }
 958
 959 static int __init find_isa_irq_apic(int irq, int type)
 960 {
 961         int i;
 962
 963         for (i = 0; i < mp_irq_entries; i++) {
 964                 int lbus = mp_irqs[i].srcbus;
 965
 966                 if (test_bit(lbus, mp_bus_not_pci) &&
 967                     (mp_irqs[i].irqtype == type) &&
 968                     (mp_irqs[i].srcbusirq == irq))
 969                         break;
 970         }
 971         if (i < mp_irq_entries) {
 972                 int apic;
 973                 for(apic = 0; apic < nr_ioapics; apic++) {
 974                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
 975                                 return apic;
 976                 }
 977         }
 978
 979         return -1;
 980 }
 981
 982 /*
 983  * Find a specific PCI IRQ entry.
 984  * Not an __init, possibly needed by modules
 985  */
 986 static int pin_2_irq(int idx, int apic, int pin);
 987
 988 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 989 {
 990         int apic, i, best_guess = -1;
 991
 992         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 993                 bus, slot, pin);
 994         if (test_bit(bus, mp_bus_not_pci)) {
 995                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 996                 return -1;
 997         }
 998         for (i = 0; i < mp_irq_entries; i++) {
 999                 int lbus = mp_irqs[i].srcbus;
1000
1001                 for (apic = 0; apic < nr_ioapics; apic++)
1002                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1003                             mp_irqs[i].dstapic == MP_APIC_ALL)
1004                                 break;
1005
1006                 if (!test_bit(lbus, mp_bus_not_pci) &&
1007                     !mp_irqs[i].irqtype &&
1008                     (bus == lbus) &&
1009                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1010                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1011
1012                         if (!(apic || IO_APIC_IRQ(irq)))
1013                                 continue;
1014
1015                         if (pin == (mp_irqs[i].srcbusirq & 3))
1016                                 return irq;
1017                         /*
1018                          * Use the first all-but-pin matching entry as a
1019                          * best-guess fuzzy result for broken mptables.
1020                          */
1021                         if (best_guess < 0)
1022                                 best_guess = irq;
1023                 }
1024         }
1025         return best_guess;
1026 }
1027
1028 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1029
1030 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1031 /*
1032  * EISA Edge/Level control register, ELCR
1033  */
1034 static int EISA_ELCR(unsigned int irq)
1035 {
1036         if (irq < NR_IRQS_LEGACY) {
1037                 unsigned int port = 0x4d0 + (irq >> 3);
1038                 return (inb(port) >> (irq & 7)) & 1;
1039         }
1040         apic_printk(APIC_VERBOSE, KERN_INFO
1041                         "Broken MPtable reports ISA irq %d\n", irq);
1042         return 0;
1043 }
1044
1045 #endif
1046
1047 /* ISA interrupts are always polarity zero edge triggered,
1048  * when listed as conforming in the MP table. */
1049
1050 #define default_ISA_trigger(idx)        (0)
1051 #define default_ISA_polarity(idx)       (0)
1052
1053 /* EISA interrupts are always polarity zero and can be edge or level
1054  * trigger depending on the ELCR value.  If an interrupt is listed as
1055  * EISA conforming in the MP table, that means its trigger type must
1056  * be read in from the ELCR */
1057
1058 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
1059 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
1060
1061 /* PCI interrupts are always polarity one level triggered,
1062  * when listed as conforming in the MP table. */
1063
1064 #define default_PCI_trigger(idx)        (1)
1065 #define default_PCI_polarity(idx)       (1)
1066
1067 /* MCA interrupts are always polarity zero level triggered,
1068  * when listed as conforming in the MP table. */
1069
1070 #define default_MCA_trigger(idx)        (1)
1071 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
1072
1073 static int MPBIOS_polarity(int idx)
1074 {
1075         int bus = mp_irqs[idx].srcbus;
1076         int polarity;
1077
1078         /*
1079          * Determine IRQ line polarity (high active or low active):
1080          */
1081         switch (mp_irqs[idx].irqflag & 3)
1082         {
1083                 case 0: /* conforms, ie. bus-type dependent polarity */
1084                         if (test_bit(bus, mp_bus_not_pci))
1085                                 polarity = default_ISA_polarity(idx);
1086                         else
1087                                 polarity = default_PCI_polarity(idx);
1088                         break;
1089                 case 1: /* high active */
1090                 {
1091                         polarity = 0;
1092                         break;
1093                 }
1094                 case 2: /* reserved */
1095                 {
1096                         printk(KERN_WARNING "broken BIOS!!\n");
1097                         polarity = 1;
1098                         break;
1099                 }
1100                 case 3: /* low active */
1101                 {
1102                         polarity = 1;
1103                         break;
1104                 }
1105                 default: /* invalid */
1106                 {
1107                         printk(KERN_WARNING "broken BIOS!!\n");
1108                         polarity = 1;
1109                         break;
1110                 }
1111         }
1112         return polarity;
1113 }
1114
1115 static int MPBIOS_trigger(int idx)
1116 {
1117         int bus = mp_irqs[idx].srcbus;
1118         int trigger;
1119
1120         /*
1121          * Determine IRQ trigger mode (edge or level sensitive):
1122          */
1123         switch ((mp_irqs[idx].irqflag>>2) & 3)
1124         {
1125                 case 0: /* conforms, ie. bus-type dependent */
1126                         if (test_bit(bus, mp_bus_not_pci))
1127                                 trigger = default_ISA_trigger(idx);
1128                         else
1129                                 trigger = default_PCI_trigger(idx);
1130 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1131                         switch (mp_bus_id_to_type[bus]) {
1132                                 case MP_BUS_ISA: /* ISA pin */
1133                                 {
1134                                         /* set before the switch */
1135                                         break;
1136                                 }
1137                                 case MP_BUS_EISA: /* EISA pin */
1138                                 {
1139                                         trigger = default_EISA_trigger(idx);
1140                                         break;
1141                                 }
1142                                 case MP_BUS_PCI: /* PCI pin */
1143                                 {
1144                                         /* set before the switch */
1145                                         break;
1146                                 }
1147                                 case MP_BUS_MCA: /* MCA pin */
1148                                 {
1149                                         trigger = default_MCA_trigger(idx);
1150                                         break;
1151                                 }
1152                                 default:
1153                                 {
1154                                         printk(KERN_WARNING "broken BIOS!!\n");
1155                                         trigger = 1;
1156                                         break;
1157                                 }
1158                         }
1159 #endif
1160                         break;
1161                 case 1: /* edge */
1162                 {
1163                         trigger = 0;
1164                         break;
1165                 }
1166                 case 2: /* reserved */
1167                 {
1168                         printk(KERN_WARNING "broken BIOS!!\n");
1169                         trigger = 1;
1170                         break;
1171                 }
1172                 case 3: /* level */
1173                 {
1174                         trigger = 1;
1175                         break;
1176                 }
1177                 default: /* invalid */
1178                 {
1179                         printk(KERN_WARNING "broken BIOS!!\n");
1180                         trigger = 0;
1181                         break;
1182                 }
1183         }
1184         return trigger;
1185 }
1186
1187 static inline int irq_polarity(int idx)
1188 {
1189         return MPBIOS_polarity(idx);
1190 }
1191
1192 static inline int irq_trigger(int idx)
1193 {
1194         return MPBIOS_trigger(idx);
1195 }
1196
1197 int (*ioapic_renumber_irq)(int ioapic, int irq);
1198 static int pin_2_irq(int idx, int apic, int pin)
1199 {
1200         int irq, i;
1201         int bus = mp_irqs[idx].srcbus;
1202
1203         /*
1204          * Debugging check, we are in big trouble if this message pops up!
1205          */
1206         if (mp_irqs[idx].dstirq != pin)
1207                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1208
1209         if (test_bit(bus, mp_bus_not_pci)) {
1210                 irq = mp_irqs[idx].srcbusirq;
1211         } else {
1212                 /*
1213                  * PCI IRQs are mapped in order
1214                  */
1215                 i = irq = 0;
1216                 while (i < apic)
1217                         irq += nr_ioapic_registers[i++];
1218                 irq += pin;
1219                 /*
1220                  * For MPS mode, so far only needed by ES7000 platform
1221                  */
1222                 if (ioapic_renumber_irq)
1223                         irq = ioapic_renumber_irq(apic, irq);
1224         }
1225
1226 #ifdef CONFIG_X86_32
1227         /*
1228          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1229          */
1230         if ((pin >= 16) && (pin <= 23)) {
1231                 if (pirq_entries[pin-16] != -1) {
1232                         if (!pirq_entries[pin-16]) {
1233                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1234                                                 "disabling PIRQ%d\n", pin-16);
1235                         } else {
1236                                 irq = pirq_entries[pin-16];
1237                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1238                                                 "using PIRQ%d -> IRQ %d\n",
1239                                                 pin-16, irq);
1240                         }
1241                 }
1242         }
1243 #endif
1244
1245         return irq;
1246 }
1247
1248 void lock_vector_lock(void)
1249 {
1250         /* Used to the online set of cpus does not change
1251          * during assign_irq_vector.
1252          */
1253         spin_lock(&vector_lock);
1254 }
1255
1256 void unlock_vector_lock(void)
1257 {
1258         spin_unlock(&vector_lock);
1259 }
1260
1261 static int
1262 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1263 {
1264         /*
1265          * NOTE! The local APIC isn't very good at handling
1266          * multiple interrupts at the same interrupt level.
1267          * As the interrupt level is determined by taking the
1268          * vector number and shifting that right by 4, we
1269          * want to spread these out a bit so that they don't
1270          * all fall in the same interrupt level.
1271          *
1272          * Also, we've got to be careful not to trash gate
1273          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1274          */
1275         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1276         unsigned int old_vector;
1277         int cpu, err;
1278         cpumask_var_t tmp_mask;
1279
1280         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1281                 return -EBUSY;
1282
1283         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1284                 return -ENOMEM;
1285
1286         old_vector = cfg->vector;
1287         if (old_vector) {
1288                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1289                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1290                 if (!cpumask_empty(tmp_mask)) {
1291                         free_cpumask_var(tmp_mask);
1292                         return 0;
1293                 }
1294         }
1295
1296         /* Only try and allocate irqs on cpus that are present */
1297         err = -ENOSPC;
1298         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1299                 int new_cpu;
1300                 int vector, offset;
1301
1302                 apic->vector_allocation_domain(cpu, tmp_mask);
1303
1304                 vector = current_vector;
1305                 offset = current_offset;
1306 next:
1307                 vector += 8;
1308                 if (vector >= first_system_vector) {
1309                         /* If out of vectors on large boxen, must share them. */
1310                         offset = (offset + 1) % 8;
1311                         vector = FIRST_DEVICE_VECTOR + offset;
1312                 }
1313                 if (unlikely(current_vector == vector))
1314                         continue;
1315
1316                 if (test_bit(vector, used_vectors))
1317                         goto next;
1318
1319                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1320                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1321                                 goto next;
1322                 /* Found one! */
1323                 current_vector = vector;
1324                 current_offset = offset;
1325                 if (old_vector) {
1326                         cfg->move_in_progress = 1;
1327                         cpumask_copy(cfg->old_domain, cfg->domain);
1328                 }
1329                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1330                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1331                 cfg->vector = vector;
1332                 cpumask_copy(cfg->domain, tmp_mask);
1333                 err = 0;
1334                 break;
1335         }
1336         free_cpumask_var(tmp_mask);
1337         return err;
1338 }
1339
1340 static int
1341 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1342 {
1343         int err;
1344         unsigned long flags;
1345
1346         spin_lock_irqsave(&vector_lock, flags);
1347         err = __assign_irq_vector(irq, cfg, mask);
1348         spin_unlock_irqrestore(&vector_lock, flags);
1349         return err;
1350 }
1351
1352 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1353 {
1354         int cpu, vector;
1355
1356         BUG_ON(!cfg->vector);
1357
1358         vector = cfg->vector;
1359         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1360                 per_cpu(vector_irq, cpu)[vector] = -1;
1361
1362         cfg->vector = 0;
1363         cpumask_clear(cfg->domain);
1364
1365         if (likely(!cfg->move_in_progress))
1366                 return;
1367         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1368                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1369                                                                 vector++) {
1370                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1371                                 continue;
1372                         per_cpu(vector_irq, cpu)[vector] = -1;
1373                         break;
1374                 }
1375         }
1376         cfg->move_in_progress = 0;
1377 }
1378
1379 void __setup_vector_irq(int cpu)
1380 {
1381         /* Initialize vector_irq on a new cpu */
1382         /* This function must be called with vector_lock held */
1383         int irq, vector;
1384         struct irq_cfg *cfg;
1385         struct irq_desc *desc;
1386
1387         /* Mark the inuse vectors */
1388         for_each_irq_desc(irq, desc) {
1389                 cfg = desc->chip_data;
1390                 if (!cpumask_test_cpu(cpu, cfg->domain))
1391                         continue;
1392                 vector = cfg->vector;
1393                 per_cpu(vector_irq, cpu)[vector] = irq;
1394         }
1395         /* Mark the free vectors */
1396         for (vector = 0; vector < NR_VECTORS; ++vector) {
1397                 irq = per_cpu(vector_irq, cpu)[vector];
1398                 if (irq < 0)
1399                         continue;
1400
1401                 cfg = irq_cfg(irq);
1402                 if (!cpumask_test_cpu(cpu, cfg->domain))
1403                         per_cpu(vector_irq, cpu)[vector] = -1;
1404         }
1405 }
1406
1407 static struct irq_chip ioapic_chip;
1408 #ifdef CONFIG_INTR_REMAP
1409 static struct irq_chip ir_ioapic_chip;
1410 #endif
1411
1412 #define IOAPIC_AUTO     -1
1413 #define IOAPIC_EDGE     0
1414 #define IOAPIC_LEVEL    1
1415
1416 #ifdef CONFIG_X86_32
1417 static inline int IO_APIC_irq_trigger(int irq)
1418 {
1419         int apic, idx, pin;
1420
1421         for (apic = 0; apic < nr_ioapics; apic++) {
1422                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1423                         idx = find_irq_entry(apic, pin, mp_INT);
1424                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1425                                 return irq_trigger(idx);
1426                 }
1427         }
1428         /*
1429          * nonexistent IRQs are edge default
1430          */
1431         return 0;
1432 }
1433 #else
1434 static inline int IO_APIC_irq_trigger(int irq)
1435 {
1436         return 1;
1437 }
1438 #endif
1439
1440 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1441 {
1442
1443         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1444             trigger == IOAPIC_LEVEL)
1445                 desc->status |= IRQ_LEVEL;
1446         else
1447                 desc->status &= ~IRQ_LEVEL;
1448
1449 #ifdef CONFIG_INTR_REMAP
1450         if (irq_remapped(irq)) {
1451                 desc->status |= IRQ_MOVE_PCNTXT;
1452                 if (trigger)
1453                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1454                                                       handle_fasteoi_irq,
1455                                                      "fasteoi");
1456                 else
1457                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1458                                                       handle_edge_irq, "edge");
1459                 return;
1460         }
1461 #endif
1462         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1463             trigger == IOAPIC_LEVEL)
1464                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1465                                               handle_fasteoi_irq,
1466                                               "fasteoi");
1467         else
1468                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1469                                               handle_edge_irq, "edge");
1470 }
1471
1472 static int setup_ioapic_entry(int apic_id, int irq,
1473                               struct IO_APIC_route_entry *entry,
1474                               unsigned int destination, int trigger,
1475                               int polarity, int vector)
1476 {
1477         /*
1478          * add it to the IO-APIC irq-routing table:
1479          */
1480         memset(entry,0,sizeof(*entry));
1481
1482 #ifdef CONFIG_INTR_REMAP
1483         if (intr_remapping_enabled) {
1484                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1485                 struct irte irte;
1486                 struct IR_IO_APIC_route_entry *ir_entry =
1487                         (struct IR_IO_APIC_route_entry *) entry;
1488                 int index;
1489
1490                 if (!iommu)
1491                         panic("No mapping iommu for ioapic %d\n", apic_id);
1492
1493                 index = alloc_irte(iommu, irq, 1);
1494                 if (index < 0)
1495                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1496
1497                 memset(&irte, 0, sizeof(irte));
1498
1499                 irte.present = 1;
1500                 irte.dst_mode = apic->irq_dest_mode;
1501                 irte.trigger_mode = trigger;
1502                 irte.dlvry_mode = apic->irq_delivery_mode;
1503                 irte.vector = vector;
1504                 irte.dest_id = IRTE_DEST(destination);
1505
1506                 modify_irte(irq, &irte);
1507
1508                 ir_entry->index2 = (index >> 15) & 0x1;
1509                 ir_entry->zero = 0;
1510                 ir_entry->format = 1;
1511                 ir_entry->index = (index & 0x7fff);
1512         } else
1513 #endif
1514         {
1515                 entry->delivery_mode = apic->irq_delivery_mode;
1516                 entry->dest_mode = apic->irq_dest_mode;
1517                 entry->dest = destination;
1518         }
1519
1520         entry->mask = 0;                                /* enable IRQ */
1521         entry->trigger = trigger;
1522         entry->polarity = polarity;
1523         entry->vector = vector;
1524
1525         /* Mask level triggered irqs.
1526          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1527          */
1528         if (trigger)
1529                 entry->mask = 1;
1530         return 0;
1531 }
1532
1533 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1534                               int trigger, int polarity)
1535 {
1536         struct irq_cfg *cfg;
1537         struct IO_APIC_route_entry entry;
1538         unsigned int dest;
1539
1540         if (!IO_APIC_IRQ(irq))
1541                 return;
1542
1543         cfg = desc->chip_data;
1544
1545         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1546                 return;
1547
1548         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1549
1550         apic_printk(APIC_VERBOSE,KERN_DEBUG
1551                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1552                     "IRQ %d Mode:%i Active:%i)\n",
1553                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1554                     irq, trigger, polarity);
1555
1556
1557         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1558                                dest, trigger, polarity, cfg->vector)) {
1559                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1560                        mp_ioapics[apic_id].apicid, pin);
1561                 __clear_irq_vector(irq, cfg);
1562                 return;
1563         }
1564
1565         ioapic_register_intr(irq, desc, trigger);
1566         if (irq < NR_IRQS_LEGACY)
1567                 disable_8259A_irq(irq);
1568
1569         ioapic_write_entry(apic_id, pin, entry);
1570 }
1571
1572 static void __init setup_IO_APIC_irqs(void)
1573 {
1574         int apic_id, pin, idx, irq;
1575         int notcon = 0;
1576         struct irq_desc *desc;
1577         struct irq_cfg *cfg;
1578         int cpu = boot_cpu_id;
1579
1580         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1581
1582         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1583                 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1584
1585                         idx = find_irq_entry(apic_id, pin, mp_INT);
1586                         if (idx == -1) {
1587                                 if (!notcon) {
1588                                         notcon = 1;
1589                                         apic_printk(APIC_VERBOSE,
1590                                                 KERN_DEBUG " %d-%d",
1591                                                 mp_ioapics[apic_id].apicid, pin);
1592                                 } else
1593                                         apic_printk(APIC_VERBOSE, " %d-%d",
1594                                                 mp_ioapics[apic_id].apicid, pin);
1595                                 continue;
1596                         }
1597                         if (notcon) {
1598                                 apic_printk(APIC_VERBOSE,
1599                                         " (apicid-pin) not connected\n");
1600                                 notcon = 0;
1601                         }
1602
1603                         irq = pin_2_irq(idx, apic_id, pin);
1604
1605                         /*
1606                          * Skip the timer IRQ if there's a quirk handler
1607                          * installed and if it returns 1:
1608                          */
1609                         if (apic->multi_timer_check &&
1610                                         apic->multi_timer_check(apic_id, irq))
1611                                 continue;
1612
1613                         desc = irq_to_desc_alloc_cpu(irq, cpu);
1614                         if (!desc) {
1615                                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1616                                 continue;
1617                         }
1618                         cfg = desc->chip_data;
1619                         add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1620
1621                         setup_IO_APIC_irq(apic_id, pin, irq, desc,
1622                                         irq_trigger(idx), irq_polarity(idx));
1623                 }
1624         }
1625
1626         if (notcon)
1627                 apic_printk(APIC_VERBOSE,
1628                         " (apicid-pin) not connected\n");
1629 }
1630
1631 /*
1632  * Set up the timer pin, possibly with the 8259A-master behind.
1633  */
1634 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1635                                         int vector)
1636 {
1637         struct IO_APIC_route_entry entry;
1638
1639 #ifdef CONFIG_INTR_REMAP
1640         if (intr_remapping_enabled)
1641                 return;
1642 #endif
1643
1644         memset(&entry, 0, sizeof(entry));
1645
1646         /*
1647          * We use logical delivery to get the timer IRQ
1648          * to the first CPU.
1649          */
1650         entry.dest_mode = apic->irq_dest_mode;
1651         entry.mask = 1;                                 /* mask IRQ now */
1652         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1653         entry.delivery_mode = apic->irq_delivery_mode;
1654         entry.polarity = 0;
1655         entry.trigger = 0;
1656         entry.vector = vector;
1657
1658         /*
1659          * The timer IRQ doesn't have to know that behind the
1660          * scene we may have a 8259A-master in AEOI mode ...
1661          */
1662         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1663
1664         /*
1665          * Add it to the IO-APIC irq-routing table:
1666          */
1667         ioapic_write_entry(apic_id, pin, entry);
1668 }
1669
1670
1671 __apicdebuginit(void) print_IO_APIC(void)
1672 {
1673         int apic, i;
1674         union IO_APIC_reg_00 reg_00;
1675         union IO_APIC_reg_01 reg_01;
1676         union IO_APIC_reg_02 reg_02;
1677         union IO_APIC_reg_03 reg_03;
1678         unsigned long flags;
1679         struct irq_cfg *cfg;
1680         struct irq_desc *desc;
1681         unsigned int irq;
1682
1683         if (apic_verbosity == APIC_QUIET)
1684                 return;
1685
1686         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1687         for (i = 0; i < nr_ioapics; i++)
1688                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1689                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1690
1691         /*
1692          * We are a bit conservative about what we expect.  We have to
1693          * know about every hardware change ASAP.
1694          */
1695         printk(KERN_INFO "testing the IO APIC.......................\n");
1696
1697         for (apic = 0; apic < nr_ioapics; apic++) {
1698
1699         spin_lock_irqsave(&ioapic_lock, flags);
1700         reg_00.raw = io_apic_read(apic, 0);
1701         reg_01.raw = io_apic_read(apic, 1);
1702         if (reg_01.bits.version >= 0x10)
1703                 reg_02.raw = io_apic_read(apic, 2);
1704         if (reg_01.bits.version >= 0x20)
1705                 reg_03.raw = io_apic_read(apic, 3);
1706         spin_unlock_irqrestore(&ioapic_lock, flags);
1707
1708         printk("\n");
1709         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1710         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1711         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1712         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1713         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1714
1715         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1716         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1717
1718         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1719         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1720
1721         /*
1722          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1723          * but the value of reg_02 is read as the previous read register
1724          * value, so ignore it if reg_02 == reg_01.
1725          */
1726         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1727                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1728                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1729         }
1730
1731         /*
1732          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1733          * or reg_03, but the value of reg_0[23] is read as the previous read
1734          * register value, so ignore it if reg_03 == reg_0[12].
1735          */
1736         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1737             reg_03.raw != reg_01.raw) {
1738                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1739                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1740         }
1741
1742         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1743
1744         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1745                           " Stat Dmod Deli Vect:   \n");
1746
1747         for (i = 0; i <= reg_01.bits.entries; i++) {
1748                 struct IO_APIC_route_entry entry;
1749
1750                 entry = ioapic_read_entry(apic, i);
1751
1752                 printk(KERN_DEBUG " %02x %03X ",
1753                         i,
1754                         entry.dest
1755                 );
1756
1757                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1758                         entry.mask,
1759                         entry.trigger,
1760                         entry.irr,
1761                         entry.polarity,
1762                         entry.delivery_status,
1763                         entry.dest_mode,
1764                         entry.delivery_mode,
1765                         entry.vector
1766                 );
1767         }
1768         }
1769         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1770         for_each_irq_desc(irq, desc) {
1771                 struct irq_pin_list *entry;
1772
1773                 cfg = desc->chip_data;
1774                 entry = cfg->irq_2_pin;
1775                 if (!entry)
1776                         continue;
1777                 printk(KERN_DEBUG "IRQ%d ", irq);
1778                 for (;;) {
1779                         printk("-> %d:%d", entry->apic, entry->pin);
1780                         if (!entry->next)
1781                                 break;
1782                         entry = entry->next;
1783                 }
1784                 printk("\n");
1785         }
1786
1787         printk(KERN_INFO ".................................... done.\n");
1788
1789         return;
1790 }
1791
1792 __apicdebuginit(void) print_APIC_bitfield(int base)
1793 {
1794         unsigned int v;
1795         int i, j;
1796
1797         if (apic_verbosity == APIC_QUIET)
1798                 return;
1799
1800         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1801         for (i = 0; i < 8; i++) {
1802                 v = apic_read(base + i*0x10);
1803                 for (j = 0; j < 32; j++) {
1804                         if (v & (1<<j))
1805                                 printk("1");
1806                         else
1807                                 printk("0");
1808                 }
1809                 printk("\n");
1810         }
1811 }
1812
1813 __apicdebuginit(void) print_local_APIC(void *dummy)
1814 {
1815         unsigned int v, ver, maxlvt;
1816         u64 icr;
1817
1818         if (apic_verbosity == APIC_QUIET)
1819                 return;
1820
1821         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1822                 smp_processor_id(), hard_smp_processor_id());
1823         v = apic_read(APIC_ID);
1824         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1825         v = apic_read(APIC_LVR);
1826         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1827         ver = GET_APIC_VERSION(v);
1828         maxlvt = lapic_get_maxlvt();
1829
1830         v = apic_read(APIC_TASKPRI);
1831         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1832
1833         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1834                 if (!APIC_XAPIC(ver)) {
1835                         v = apic_read(APIC_ARBPRI);
1836                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1837                                v & APIC_ARBPRI_MASK);
1838                 }
1839                 v = apic_read(APIC_PROCPRI);
1840                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1841         }
1842
1843         /*
1844          * Remote read supported only in the 82489DX and local APIC for
1845          * Pentium processors.
1846          */
1847         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1848                 v = apic_read(APIC_RRR);
1849                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1850         }
1851
1852         v = apic_read(APIC_LDR);
1853         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1854         if (!x2apic_enabled()) {
1855                 v = apic_read(APIC_DFR);
1856                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1857         }
1858         v = apic_read(APIC_SPIV);
1859         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1860
1861         printk(KERN_DEBUG "... APIC ISR field:\n");
1862         print_APIC_bitfield(APIC_ISR);
1863         printk(KERN_DEBUG "... APIC TMR field:\n");
1864         print_APIC_bitfield(APIC_TMR);
1865         printk(KERN_DEBUG "... APIC IRR field:\n");
1866         print_APIC_bitfield(APIC_IRR);
1867
1868         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1869                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1870                         apic_write(APIC_ESR, 0);
1871
1872                 v = apic_read(APIC_ESR);
1873                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1874         }
1875
1876         icr = apic_icr_read();
1877         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1878         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1879
1880         v = apic_read(APIC_LVTT);
1881         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1882
1883         if (maxlvt > 3) {                       /* PC is LVT#4. */
1884                 v = apic_read(APIC_LVTPC);
1885                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1886         }
1887         v = apic_read(APIC_LVT0);
1888         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1889         v = apic_read(APIC_LVT1);
1890         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1891
1892         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1893                 v = apic_read(APIC_LVTERR);
1894                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1895         }
1896
1897         v = apic_read(APIC_TMICT);
1898         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1899         v = apic_read(APIC_TMCCT);
1900         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1901         v = apic_read(APIC_TDCR);
1902         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1903         printk("\n");
1904 }
1905
1906 __apicdebuginit(void) print_all_local_APICs(void)
1907 {
1908         int cpu;
1909
1910         preempt_disable();
1911         for_each_online_cpu(cpu)
1912                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1913         preempt_enable();
1914 }
1915
1916 __apicdebuginit(void) print_PIC(void)
1917 {
1918         unsigned int v;
1919         unsigned long flags;
1920
1921         if (apic_verbosity == APIC_QUIET)
1922                 return;
1923
1924         printk(KERN_DEBUG "\nprinting PIC contents\n");
1925
1926         spin_lock_irqsave(&i8259A_lock, flags);
1927
1928         v = inb(0xa1) << 8 | inb(0x21);
1929         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1930
1931         v = inb(0xa0) << 8 | inb(0x20);
1932         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1933
1934         outb(0x0b,0xa0);
1935         outb(0x0b,0x20);
1936         v = inb(0xa0) << 8 | inb(0x20);
1937         outb(0x0a,0xa0);
1938         outb(0x0a,0x20);
1939
1940         spin_unlock_irqrestore(&i8259A_lock, flags);
1941
1942         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1943
1944         v = inb(0x4d1) << 8 | inb(0x4d0);
1945         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1946 }
1947
1948 __apicdebuginit(int) print_all_ICs(void)
1949 {
1950         print_PIC();
1951         print_all_local_APICs();
1952         print_IO_APIC();
1953
1954         return 0;
1955 }
1956
1957 fs_initcall(print_all_ICs);
1958
1959
1960 /* Where if anywhere is the i8259 connect in external int mode */
1961 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1962
1963 void __init enable_IO_APIC(void)
1964 {
1965         union IO_APIC_reg_01 reg_01;
1966         int i8259_apic, i8259_pin;
1967         int apic;
1968         unsigned long flags;
1969
1970 #ifdef CONFIG_X86_32
1971         int i;
1972         if (!pirqs_enabled)
1973                 for (i = 0; i < MAX_PIRQS; i++)
1974                         pirq_entries[i] = -1;
1975 #endif
1976
1977         /*
1978          * The number of IO-APIC IRQ registers (== #pins):
1979          */
1980         for (apic = 0; apic < nr_ioapics; apic++) {
1981                 spin_lock_irqsave(&ioapic_lock, flags);
1982                 reg_01.raw = io_apic_read(apic, 1);
1983                 spin_unlock_irqrestore(&ioapic_lock, flags);
1984                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1985         }
1986         for(apic = 0; apic < nr_ioapics; apic++) {
1987                 int pin;
1988                 /* See if any of the pins is in ExtINT mode */
1989                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1990                         struct IO_APIC_route_entry entry;
1991                         entry = ioapic_read_entry(apic, pin);
1992
1993                         /* If the interrupt line is enabled and in ExtInt mode
1994                          * I have found the pin where the i8259 is connected.
1995                          */
1996                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1997                                 ioapic_i8259.apic = apic;
1998                                 ioapic_i8259.pin  = pin;
1999                                 goto found_i8259;
2000                         }
2001                 }
2002         }
2003  found_i8259:
2004         /* Look to see what if the MP table has reported the ExtINT */
2005         /* If we could not find the appropriate pin by looking at the ioapic
2006          * the i8259 probably is not connected the ioapic but give the
2007          * mptable a chance anyway.
2008          */
2009         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
2010         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2011         /* Trust the MP table if nothing is setup in the hardware */
2012         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2013                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2014                 ioapic_i8259.pin  = i8259_pin;
2015                 ioapic_i8259.apic = i8259_apic;
2016         }
2017         /* Complain if the MP table and the hardware disagree */
2018         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2019                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2020         {
2021                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2022         }
2023
2024         /*
2025          * Do not trust the IO-APIC being empty at bootup
2026          */
2027         clear_IO_APIC();
2028 }
2029
2030 /*
2031  * Not an __init, needed by the reboot code
2032  */
2033 void disable_IO_APIC(void)
2034 {
2035         /*
2036          * Clear the IO-APIC before rebooting:
2037          */
2038         clear_IO_APIC();
2039
2040         /*
2041          * If the i8259 is routed through an IOAPIC
2042          * Put that IOAPIC in virtual wire mode
2043          * so legacy interrupts can be delivered.
2044          */
2045         if (ioapic_i8259.pin != -1) {
2046                 struct IO_APIC_route_entry entry;
2047
2048                 memset(&entry, 0, sizeof(entry));
2049                 entry.mask            = 0; /* Enabled */
2050                 entry.trigger         = 0; /* Edge */
2051                 entry.irr             = 0;
2052                 entry.polarity        = 0; /* High */
2053                 entry.delivery_status = 0;
2054                 entry.dest_mode       = 0; /* Physical */
2055                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
2056                 entry.vector          = 0;
2057                 entry.dest            = read_apic_id();
2058
2059                 /*
2060                  * Add it to the IO-APIC irq-routing table:
2061                  */
2062                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2063         }
2064
2065         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2066 }
2067
2068 #ifdef CONFIG_X86_32
2069 /*
2070  * function to set the IO-APIC physical IDs based on the
2071  * values stored in the MPC table.
2072  *
2073  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2074  */
2075
2076 static void __init setup_ioapic_ids_from_mpc(void)
2077 {
2078         union IO_APIC_reg_00 reg_00;
2079         physid_mask_t phys_id_present_map;
2080         int apic_id;
2081         int i;
2082         unsigned char old_id;
2083         unsigned long flags;
2084
2085         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2086                 return;
2087
2088         /*
2089          * Don't check I/O APIC IDs for xAPIC systems.  They have
2090          * no meaning without the serial APIC bus.
2091          */
2092         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2093                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2094                 return;
2095         /*
2096          * This is broken; anything with a real cpu count has to
2097          * circumvent this idiocy regardless.
2098          */
2099         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2100
2101         /*
2102          * Set the IOAPIC ID to the value stored in the MPC table.
2103          */
2104         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2105
2106                 /* Read the register 0 value */
2107                 spin_lock_irqsave(&ioapic_lock, flags);
2108                 reg_00.raw = io_apic_read(apic_id, 0);
2109                 spin_unlock_irqrestore(&ioapic_lock, flags);
2110
2111                 old_id = mp_ioapics[apic_id].apicid;
2112
2113                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2114                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2115                                 apic_id, mp_ioapics[apic_id].apicid);
2116                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2117                                 reg_00.bits.ID);
2118                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2119                 }
2120
2121                 /*
2122                  * Sanity check, is the ID really free? Every APIC in a
2123                  * system must have a unique ID or we get lots of nice
2124                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2125                  */
2126                 if (apic->check_apicid_used(phys_id_present_map,
2127                                         mp_ioapics[apic_id].apicid)) {
2128                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2129                                 apic_id, mp_ioapics[apic_id].apicid);
2130                         for (i = 0; i < get_physical_broadcast(); i++)
2131                                 if (!physid_isset(i, phys_id_present_map))
2132                                         break;
2133                         if (i >= get_physical_broadcast())
2134                                 panic("Max APIC ID exceeded!\n");
2135                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2136                                 i);
2137                         physid_set(i, phys_id_present_map);
2138                         mp_ioapics[apic_id].apicid = i;
2139                 } else {
2140                         physid_mask_t tmp;
2141                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2142                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2143                                         "phys_id_present_map\n",
2144                                         mp_ioapics[apic_id].apicid);
2145                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2146                 }
2147
2148
2149                 /*
2150                  * We need to adjust the IRQ routing table
2151                  * if the ID changed.
2152                  */
2153                 if (old_id != mp_ioapics[apic_id].apicid)
2154                         for (i = 0; i < mp_irq_entries; i++)
2155                                 if (mp_irqs[i].dstapic == old_id)
2156                                         mp_irqs[i].dstapic
2157                                                 = mp_ioapics[apic_id].apicid;
2158
2159                 /*
2160                  * Read the right value from the MPC table and
2161                  * write it into the ID register.
2162                  */
2163                 apic_printk(APIC_VERBOSE, KERN_INFO
2164                         "...changing IO-APIC physical APIC ID to %d ...",
2165                         mp_ioapics[apic_id].apicid);
2166
2167                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2168                 spin_lock_irqsave(&ioapic_lock, flags);
2169                 io_apic_write(apic_id, 0, reg_00.raw);
2170                 spin_unlock_irqrestore(&ioapic_lock, flags);
2171
2172                 /*
2173                  * Sanity check
2174                  */
2175                 spin_lock_irqsave(&ioapic_lock, flags);
2176                 reg_00.raw = io_apic_read(apic_id, 0);
2177                 spin_unlock_irqrestore(&ioapic_lock, flags);
2178                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2179                         printk("could not set ID!\n");
2180                 else
2181                         apic_printk(APIC_VERBOSE, " ok.\n");
2182         }
2183 }
2184 #endif
2185
2186 int no_timer_check __initdata;
2187
2188 static int __init notimercheck(char *s)
2189 {
2190         no_timer_check = 1;
2191         return 1;
2192 }
2193 __setup("no_timer_check", notimercheck);
2194
2195 /*
2196  * There is a nasty bug in some older SMP boards, their mptable lies
2197  * about the timer IRQ. We do the following to work around the situation:
2198  *
2199  *      - timer IRQ defaults to IO-APIC IRQ
2200  *      - if this function detects that timer IRQs are defunct, then we fall
2201  *        back to ISA timer IRQs
2202  */
2203 static int __init timer_irq_works(void)
2204 {
2205         unsigned long t1 = jiffies;
2206         unsigned long flags;
2207
2208         if (no_timer_check)
2209                 return 1;
2210
2211         local_save_flags(flags);
2212         local_irq_enable();
2213         /* Let ten ticks pass... */
2214         mdelay((10 * 1000) / HZ);
2215         local_irq_restore(flags);
2216
2217         /*
2218          * Expect a few ticks at least, to be sure some possible
2219          * glue logic does not lock up after one or two first
2220          * ticks in a non-ExtINT mode.  Also the local APIC
2221          * might have cached one ExtINT interrupt.  Finally, at
2222          * least one tick may be lost due to delays.
2223          */
2224
2225         /* jiffies wrap? */
2226         if (time_after(jiffies, t1 + 4))
2227                 return 1;
2228         return 0;
2229 }
2230
2231 /*
2232  * In the SMP+IOAPIC case it might happen that there are an unspecified
2233  * number of pending IRQ events unhandled. These cases are very rare,
2234  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2235  * better to do it this way as thus we do not have to be aware of
2236  * 'pending' interrupts in the IRQ path, except at this point.
2237  */
2238 /*
2239  * Edge triggered needs to resend any interrupt
2240  * that was delayed but this is now handled in the device
2241  * independent code.
2242  */
2243
2244 /*
2245  * Starting up a edge-triggered IO-APIC interrupt is
2246  * nasty - we need to make sure that we get the edge.
2247  * If it is already asserted for some reason, we need
2248  * return 1 to indicate that is was pending.
2249  *
2250  * This is not complete - we should be able to fake
2251  * an edge even if it isn't on the 8259A...
2252  */
2253
2254 static unsigned int startup_ioapic_irq(unsigned int irq)
2255 {
2256         int was_pending = 0;
2257         unsigned long flags;
2258         struct irq_cfg *cfg;
2259
2260         spin_lock_irqsave(&ioapic_lock, flags);
2261         if (irq < NR_IRQS_LEGACY) {
2262                 disable_8259A_irq(irq);
2263                 if (i8259A_irq_pending(irq))
2264                         was_pending = 1;
2265         }
2266         cfg = irq_cfg(irq);
2267         __unmask_IO_APIC_irq(cfg);
2268         spin_unlock_irqrestore(&ioapic_lock, flags);
2269
2270         return was_pending;
2271 }
2272
2273 #ifdef CONFIG_X86_64
2274 static int ioapic_retrigger_irq(unsigned int irq)
2275 {
2276
2277         struct irq_cfg *cfg = irq_cfg(irq);
2278         unsigned long flags;
2279
2280         spin_lock_irqsave(&vector_lock, flags);
2281         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2282         spin_unlock_irqrestore(&vector_lock, flags);
2283
2284         return 1;
2285 }
2286 #else
2287 static int ioapic_retrigger_irq(unsigned int irq)
2288 {
2289         apic->send_IPI_self(irq_cfg(irq)->vector);
2290
2291         return 1;
2292 }
2293 #endif
2294
2295 /*
2296  * Level and edge triggered IO-APIC interrupts need different handling,
2297  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2298  * handled with the level-triggered descriptor, but that one has slightly
2299  * more overhead. Level-triggered interrupts cannot be handled with the
2300  * edge-triggered handler, without risking IRQ storms and other ugly
2301  * races.
2302  */
2303
2304 #ifdef CONFIG_SMP
2305
2306 #ifdef CONFIG_INTR_REMAP
2307 static void ir_irq_migration(struct work_struct *work);
2308
2309 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2310
2311 /*
2312  * Migrate the IO-APIC irq in the presence of intr-remapping.
2313  *
2314  * For edge triggered, irq migration is a simple atomic update(of vector
2315  * and cpu destination) of IRTE and flush the hardware cache.
2316  *
2317  * For level triggered, we need to modify the io-apic RTE aswell with the update
2318  * vector information, along with modifying IRTE with vector and destination.
2319  * So irq migration for level triggered is little  bit more complex compared to
2320  * edge triggered migration. But the good news is, we use the same algorithm
2321  * for level triggered migration as we have today, only difference being,
2322  * we now initiate the irq migration from process context instead of the
2323  * interrupt context.
2324  *
2325  * In future, when we do a directed EOI (combined with cpu EOI broadcast
2326  * suppression) to the IO-APIC, level triggered irq migration will also be
2327  * as simple as edge triggered migration and we can do the irq migration
2328  * with a simple atomic update to IO-APIC RTE.
2329  */
2330 static void
2331 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2332 {
2333         struct irq_cfg *cfg;
2334         struct irte irte;
2335         int modify_ioapic_rte;
2336         unsigned int dest;
2337         unsigned long flags;
2338         unsigned int irq;
2339
2340         if (!cpumask_intersects(mask, cpu_online_mask))
2341                 return;
2342
2343         irq = desc->irq;
2344         if (get_irte(irq, &irte))
2345                 return;
2346
2347         cfg = desc->chip_data;
2348         if (assign_irq_vector(irq, cfg, mask))
2349                 return;
2350
2351         set_extra_move_desc(desc, mask);
2352
2353         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2354
2355         modify_ioapic_rte = desc->status & IRQ_LEVEL;
2356         if (modify_ioapic_rte) {
2357                 spin_lock_irqsave(&ioapic_lock, flags);
2358                 __target_IO_APIC_irq(irq, dest, cfg);
2359                 spin_unlock_irqrestore(&ioapic_lock, flags);
2360         }
2361
2362         irte.vector = cfg->vector;
2363         irte.dest_id = IRTE_DEST(dest);
2364
2365         /*
2366          * Modified the IRTE and flushes the Interrupt entry cache.
2367          */
2368         modify_irte(irq, &irte);
2369
2370         if (cfg->move_in_progress)
2371                 send_cleanup_vector(cfg);
2372
2373         cpumask_copy(desc->affinity, mask);
2374 }
2375
2376 static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2377 {
2378         int ret = -1;
2379         struct irq_cfg *cfg = desc->chip_data;
2380
2381         mask_IO_APIC_irq_desc(desc);
2382
2383         if (io_apic_level_ack_pending(cfg)) {
2384                 /*
2385                  * Interrupt in progress. Migrating irq now will change the
2386                  * vector information in the IO-APIC RTE and that will confuse
2387                  * the EOI broadcast performed by cpu.
2388                  * So, delay the irq migration to the next instance.
2389                  */
2390                 schedule_delayed_work(&ir_migration_work, 1);
2391                 goto unmask;
2392         }
2393
2394         /* everthing is clear. we have right of way */
2395         migrate_ioapic_irq_desc(desc, desc->pending_mask);
2396
2397         ret = 0;
2398         desc->status &= ~IRQ_MOVE_PENDING;
2399         cpumask_clear(desc->pending_mask);
2400
2401 unmask:
2402         unmask_IO_APIC_irq_desc(desc);
2403
2404         return ret;
2405 }
2406
2407 static void ir_irq_migration(struct work_struct *work)
2408 {
2409         unsigned int irq;
2410         struct irq_desc *desc;
2411
2412         for_each_irq_desc(irq, desc) {
2413                 if (desc->status & IRQ_MOVE_PENDING) {
2414                         unsigned long flags;
2415
2416                         spin_lock_irqsave(&desc->lock, flags);
2417                         if (!desc->chip->set_affinity ||
2418                             !(desc->status & IRQ_MOVE_PENDING)) {
2419                                 desc->status &= ~IRQ_MOVE_PENDING;
2420                                 spin_unlock_irqrestore(&desc->lock, flags);
2421                                 continue;
2422                         }
2423
2424                         desc->chip->set_affinity(irq, desc->pending_mask);
2425                         spin_unlock_irqrestore(&desc->lock, flags);
2426                 }
2427         }
2428 }
2429
2430 /*
2431  * Migrates the IRQ destination in the process context.
2432  */
2433 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2434                                             const struct cpumask *mask)
2435 {
2436         if (desc->status & IRQ_LEVEL) {
2437                 desc->status |= IRQ_MOVE_PENDING;
2438                 cpumask_copy(desc->pending_mask, mask);
2439                 migrate_irq_remapped_level_desc(desc);
2440                 return;
2441         }
2442
2443         migrate_ioapic_irq_desc(desc, mask);
2444 }
2445 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2446                                        const struct cpumask *mask)
2447 {
2448         struct irq_desc *desc = irq_to_desc(irq);
2449
2450         set_ir_ioapic_affinity_irq_desc(desc, mask);
2451 }
2452 #endif
2453
2454 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2455 {
2456         unsigned vector, me;
2457
2458         ack_APIC_irq();
2459         exit_idle();
2460         irq_enter();
2461
2462         me = smp_processor_id();
2463         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2464                 unsigned int irq;
2465                 struct irq_desc *desc;
2466                 struct irq_cfg *cfg;
2467                 irq = __get_cpu_var(vector_irq)[vector];
2468
2469                 if (irq == -1)
2470                         continue;
2471
2472                 desc = irq_to_desc(irq);
2473                 if (!desc)
2474                         continue;
2475
2476                 cfg = irq_cfg(irq);
2477                 spin_lock(&desc->lock);
2478                 if (!cfg->move_cleanup_count)
2479                         goto unlock;
2480
2481                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2482                         goto unlock;
2483
2484                 __get_cpu_var(vector_irq)[vector] = -1;
2485                 cfg->move_cleanup_count--;
2486 unlock:
2487                 spin_unlock(&desc->lock);
2488         }
2489
2490         irq_exit();
2491 }
2492
2493 static void irq_complete_move(struct irq_desc **descp)
2494 {
2495         struct irq_desc *desc = *descp;
2496         struct irq_cfg *cfg = desc->chip_data;
2497         unsigned vector, me;
2498
2499         if (likely(!cfg->move_in_progress)) {
2500 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2501                 if (likely(!cfg->move_desc_pending))
2502                         return;
2503
2504                 /* domain has not changed, but affinity did */
2505                 me = smp_processor_id();
2506                 if (cpumask_test_cpu(me, desc->affinity)) {
2507                         *descp = desc = move_irq_desc(desc, me);
2508                         /* get the new one */
2509                         cfg = desc->chip_data;
2510                         cfg->move_desc_pending = 0;
2511                 }
2512 #endif
2513                 return;
2514         }
2515
2516         vector = ~get_irq_regs()->orig_ax;
2517         me = smp_processor_id();
2518 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2519                 *descp = desc = move_irq_desc(desc, me);
2520                 /* get the new one */
2521                 cfg = desc->chip_data;
2522 #endif
2523
2524         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2525                 send_cleanup_vector(cfg);
2526 }
2527 #else
2528 static inline void irq_complete_move(struct irq_desc **descp) {}
2529 #endif
2530
2531 #ifdef CONFIG_INTR_REMAP
2532 static void ack_x2apic_level(unsigned int irq)
2533 {
2534         ack_x2APIC_irq();
2535 }
2536
2537 static void ack_x2apic_edge(unsigned int irq)
2538 {
2539         ack_x2APIC_irq();
2540 }
2541
2542 #endif
2543
2544 static void ack_apic_edge(unsigned int irq)
2545 {
2546         struct irq_desc *desc = irq_to_desc(irq);
2547
2548         irq_complete_move(&desc);
2549         move_native_irq(irq);
2550         ack_APIC_irq();
2551 }
2552
2553 atomic_t irq_mis_count;
2554
2555 static void ack_apic_level(unsigned int irq)
2556 {
2557         struct irq_desc *desc = irq_to_desc(irq);
2558
2559 #ifdef CONFIG_X86_32
2560         unsigned long v;
2561         int i;
2562 #endif
2563         struct irq_cfg *cfg;
2564         int do_unmask_irq = 0;
2565
2566         irq_complete_move(&desc);
2567 #ifdef CONFIG_GENERIC_PENDING_IRQ
2568         /* If we are moving the irq we need to mask it */
2569         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2570                 do_unmask_irq = 1;
2571                 mask_IO_APIC_irq_desc(desc);
2572         }
2573 #endif
2574
2575 #ifdef CONFIG_X86_32
2576         /*
2577         * It appears there is an erratum which affects at least version 0x11
2578         * of I/O APIC (that's the 82093AA and cores integrated into various
2579         * chipsets).  Under certain conditions a level-triggered interrupt is
2580         * erroneously delivered as edge-triggered one but the respective IRR
2581         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2582         * message but it will never arrive and further interrupts are blocked
2583         * from the source.  The exact reason is so far unknown, but the
2584         * phenomenon was observed when two consecutive interrupt requests
2585         * from a given source get delivered to the same CPU and the source is
2586         * temporarily disabled in between.
2587         *
2588         * A workaround is to simulate an EOI message manually.  We achieve it
2589         * by setting the trigger mode to edge and then to level when the edge
2590         * trigger mode gets detected in the TMR of a local APIC for a
2591         * level-triggered interrupt.  We mask the source for the time of the
2592         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2593         * The idea is from Manfred Spraul.  --macro
2594         */
2595         cfg = desc->chip_data;
2596         i = cfg->vector;
2597
2598         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2599 #endif
2600
2601         /*
2602          * We must acknowledge the irq before we move it or the acknowledge will
2603          * not propagate properly.
2604          */
2605         ack_APIC_irq();
2606
2607         /* Now we can move and renable the irq */
2608         if (unlikely(do_unmask_irq)) {
2609                 /* Only migrate the irq if the ack has been received.
2610                  *
2611                  * On rare occasions the broadcast level triggered ack gets
2612                  * delayed going to ioapics, and if we reprogram the
2613                  * vector while Remote IRR is still set the irq will never
2614                  * fire again.
2615                  *
2616                  * To prevent this scenario we read the Remote IRR bit
2617                  * of the ioapic.  This has two effects.
2618                  * - On any sane system the read of the ioapic will
2619                  *   flush writes (and acks) going to the ioapic from
2620                  *   this cpu.
2621                  * - We get to see if the ACK has actually been delivered.
2622                  *
2623                  * Based on failed experiments of reprogramming the
2624                  * ioapic entry from outside of irq context starting
2625                  * with masking the ioapic entry and then polling until
2626                  * Remote IRR was clear before reprogramming the
2627                  * ioapic I don't trust the Remote IRR bit to be
2628                  * completey accurate.
2629                  *
2630                  * However there appears to be no other way to plug
2631                  * this race, so if the Remote IRR bit is not
2632                  * accurate and is causing problems then it is a hardware bug
2633                  * and you can go talk to the chipset vendor about it.
2634                  */
2635                 cfg = desc->chip_data;
2636                 if (!io_apic_level_ack_pending(cfg))
2637                         move_masked_irq(irq);
2638                 unmask_IO_APIC_irq_desc(desc);
2639         }
2640
2641 #ifdef CONFIG_X86_32
2642         if (!(v & (1 << (i & 0x1f)))) {
2643                 atomic_inc(&irq_mis_count);
2644                 spin_lock(&ioapic_lock);
2645                 __mask_and_edge_IO_APIC_irq(cfg);
2646                 __unmask_and_level_IO_APIC_irq(cfg);
2647                 spin_unlock(&ioapic_lock);
2648         }
2649 #endif
2650 }
2651
2652 static struct irq_chip ioapic_chip __read_mostly = {
2653         .name           = "IO-APIC",
2654         .startup        = startup_ioapic_irq,
2655         .mask           = mask_IO_APIC_irq,
2656         .unmask         = unmask_IO_APIC_irq,
2657         .ack            = ack_apic_edge,
2658         .eoi            = ack_apic_level,
2659 #ifdef CONFIG_SMP
2660         .set_affinity   = set_ioapic_affinity_irq,
2661 #endif
2662         .retrigger      = ioapic_retrigger_irq,
2663 };
2664
2665 #ifdef CONFIG_INTR_REMAP
2666 static struct irq_chip ir_ioapic_chip __read_mostly = {
2667         .name           = "IR-IO-APIC",
2668         .startup        = startup_ioapic_irq,
2669         .mask           = mask_IO_APIC_irq,
2670         .unmask         = unmask_IO_APIC_irq,
2671         .ack            = ack_x2apic_edge,
2672         .eoi            = ack_x2apic_level,
2673 #ifdef CONFIG_SMP
2674         .set_affinity   = set_ir_ioapic_affinity_irq,
2675 #endif
2676         .retrigger      = ioapic_retrigger_irq,
2677 };
2678 #endif
2679
2680 static inline void init_IO_APIC_traps(void)
2681 {
2682         int irq;
2683         struct irq_desc *desc;
2684         struct irq_cfg *cfg;
2685
2686         /*
2687          * NOTE! The local APIC isn't very good at handling
2688          * multiple interrupts at the same interrupt level.
2689          * As the interrupt level is determined by taking the
2690          * vector number and shifting that right by 4, we
2691          * want to spread these out a bit so that they don't
2692          * all fall in the same interrupt level.
2693          *
2694          * Also, we've got to be careful not to trash gate
2695          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2696          */
2697         for_each_irq_desc(irq, desc) {
2698                 cfg = desc->chip_data;
2699                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2700                         /*
2701                          * Hmm.. We don't have an entry for this,
2702                          * so default to an old-fashioned 8259
2703                          * interrupt if we can..
2704                          */
2705                         if (irq < NR_IRQS_LEGACY)
2706                                 make_8259A_irq(irq);
2707                         else
2708                                 /* Strange. Oh, well.. */
2709                                 desc->chip = &no_irq_chip;
2710                 }
2711         }
2712 }
2713
2714 /*
2715  * The local APIC irq-chip implementation:
2716  */
2717
2718 static void mask_lapic_irq(unsigned int irq)
2719 {
2720         unsigned long v;
2721
2722         v = apic_read(APIC_LVT0);
2723         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2724 }
2725
2726 static void unmask_lapic_irq(unsigned int irq)
2727 {
2728         unsigned long v;
2729
2730         v = apic_read(APIC_LVT0);
2731         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2732 }
2733
2734 static void ack_lapic_irq(unsigned int irq)
2735 {
2736         ack_APIC_irq();
2737 }
2738
2739 static struct irq_chip lapic_chip __read_mostly = {
2740         .name           = "local-APIC",
2741         .mask           = mask_lapic_irq,
2742         .unmask         = unmask_lapic_irq,
2743         .ack            = ack_lapic_irq,
2744 };
2745
2746 static void lapic_register_intr(int irq, struct irq_desc *desc)
2747 {
2748         desc->status &= ~IRQ_LEVEL;
2749         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2750                                       "edge");
2751 }
2752
2753 static void __init setup_nmi(void)
2754 {
2755         /*
2756          * Dirty trick to enable the NMI watchdog ...
2757          * We put the 8259A master into AEOI mode and
2758          * unmask on all local APICs LVT0 as NMI.
2759          *
2760          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2761          * is from Maciej W. Rozycki - so we do not have to EOI from
2762          * the NMI handler or the timer interrupt.
2763          */
2764         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2765
2766         enable_NMI_through_LVT0();
2767
2768         apic_printk(APIC_VERBOSE, " done.\n");
2769 }
2770
2771 /*
2772  * This looks a bit hackish but it's about the only one way of sending
2773  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2774  * not support the ExtINT mode, unfortunately.  We need to send these
2775  * cycles as some i82489DX-based boards have glue logic that keeps the
2776  * 8259A interrupt line asserted until INTA.  --macro
2777  */
2778 static inline void __init unlock_ExtINT_logic(void)
2779 {
2780         int apic, pin, i;
2781         struct IO_APIC_route_entry entry0, entry1;
2782         unsigned char save_control, save_freq_select;
2783
2784         pin  = find_isa_irq_pin(8, mp_INT);
2785         if (pin == -1) {
2786                 WARN_ON_ONCE(1);
2787                 return;
2788         }
2789         apic = find_isa_irq_apic(8, mp_INT);
2790         if (apic == -1) {
2791                 WARN_ON_ONCE(1);
2792                 return;
2793         }
2794
2795         entry0 = ioapic_read_entry(apic, pin);
2796         clear_IO_APIC_pin(apic, pin);
2797
2798         memset(&entry1, 0, sizeof(entry1));
2799
2800         entry1.dest_mode = 0;                   /* physical delivery */
2801         entry1.mask = 0;                        /* unmask IRQ now */
2802         entry1.dest = hard_smp_processor_id();
2803         entry1.delivery_mode = dest_ExtINT;
2804         entry1.polarity = entry0.polarity;
2805         entry1.trigger = 0;
2806         entry1.vector = 0;
2807
2808         ioapic_write_entry(apic, pin, entry1);
2809
2810         save_control = CMOS_READ(RTC_CONTROL);
2811         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2812         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2813                    RTC_FREQ_SELECT);
2814         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2815
2816         i = 100;
2817         while (i-- > 0) {
2818                 mdelay(10);
2819                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2820                         i -= 10;
2821         }
2822
2823         CMOS_WRITE(save_control, RTC_CONTROL);
2824         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2825         clear_IO_APIC_pin(apic, pin);
2826
2827         ioapic_write_entry(apic, pin, entry0);
2828 }
2829
2830 static int disable_timer_pin_1 __initdata;
2831 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2832 static int __init disable_timer_pin_setup(char *arg)
2833 {
2834         disable_timer_pin_1 = 1;
2835         return 0;
2836 }
2837 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2838
2839 int timer_through_8259 __initdata;
2840
2841 /*
2842  * This code may look a bit paranoid, but it's supposed to cooperate with
2843  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2844  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2845  * fanatically on his truly buggy board.
2846  *
2847  * FIXME: really need to revamp this for all platforms.
2848  */
2849 static inline void __init check_timer(void)
2850 {
2851         struct irq_desc *desc = irq_to_desc(0);
2852         struct irq_cfg *cfg = desc->chip_data;
2853         int cpu = boot_cpu_id;
2854         int apic1, pin1, apic2, pin2;
2855         unsigned long flags;
2856         unsigned int ver;
2857         int no_pin1 = 0;
2858
2859         local_irq_save(flags);
2860
2861         ver = apic_read(APIC_LVR);
2862         ver = GET_APIC_VERSION(ver);
2863
2864         /*
2865          * get/set the timer IRQ vector:
2866          */
2867         disable_8259A_irq(0);
2868         assign_irq_vector(0, cfg, apic->target_cpus());
2869
2870         /*
2871          * As IRQ0 is to be enabled in the 8259A, the virtual
2872          * wire has to be disabled in the local APIC.  Also
2873          * timer interrupts need to be acknowledged manually in
2874          * the 8259A for the i82489DX when using the NMI
2875          * watchdog as that APIC treats NMIs as level-triggered.
2876          * The AEOI mode will finish them in the 8259A
2877          * automatically.
2878          */
2879         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2880         init_8259A(1);
2881 #ifdef CONFIG_X86_32
2882         timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2883 #endif
2884
2885         pin1  = find_isa_irq_pin(0, mp_INT);
2886         apic1 = find_isa_irq_apic(0, mp_INT);
2887         pin2  = ioapic_i8259.pin;
2888         apic2 = ioapic_i8259.apic;
2889
2890         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2891                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2892                     cfg->vector, apic1, pin1, apic2, pin2);
2893
2894         /*
2895          * Some BIOS writers are clueless and report the ExtINTA
2896          * I/O APIC input from the cascaded 8259A as the timer
2897          * interrupt input.  So just in case, if only one pin
2898          * was found above, try it both directly and through the
2899          * 8259A.
2900          */
2901         if (pin1 == -1) {
2902 #ifdef CONFIG_INTR_REMAP
2903                 if (intr_remapping_enabled)
2904                         panic("BIOS bug: timer not connected to IO-APIC");
2905 #endif
2906                 pin1 = pin2;
2907                 apic1 = apic2;
2908                 no_pin1 = 1;
2909         } else if (pin2 == -1) {
2910                 pin2 = pin1;
2911                 apic2 = apic1;
2912         }
2913
2914         if (pin1 != -1) {
2915                 /*
2916                  * Ok, does IRQ0 through the IOAPIC work?
2917                  */
2918                 if (no_pin1) {
2919                         add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2920                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2921                 }
2922                 unmask_IO_APIC_irq_desc(desc);
2923                 if (timer_irq_works()) {
2924                         if (nmi_watchdog == NMI_IO_APIC) {
2925                                 setup_nmi();
2926                                 enable_8259A_irq(0);
2927                         }
2928                         if (disable_timer_pin_1 > 0)
2929                                 clear_IO_APIC_pin(0, pin1);
2930                         goto out;
2931                 }
2932 #ifdef CONFIG_INTR_REMAP
2933                 if (intr_remapping_enabled)
2934                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2935 #endif
2936                 clear_IO_APIC_pin(apic1, pin1);
2937                 if (!no_pin1)
2938                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2939                                     "8254 timer not connected to IO-APIC\n");
2940
2941                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2942                             "(IRQ0) through the 8259A ...\n");
2943                 apic_printk(APIC_QUIET, KERN_INFO
2944                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2945                 /*
2946                  * legacy devices should be connected to IO APIC #0
2947                  */
2948                 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2949                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2950                 unmask_IO_APIC_irq_desc(desc);
2951                 enable_8259A_irq(0);
2952                 if (timer_irq_works()) {
2953                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2954                         timer_through_8259 = 1;
2955                         if (nmi_watchdog == NMI_IO_APIC) {
2956                                 disable_8259A_irq(0);
2957                                 setup_nmi();
2958                                 enable_8259A_irq(0);
2959                         }
2960                         goto out;
2961                 }
2962                 /*
2963                  * Cleanup, just in case ...
2964                  */
2965                 disable_8259A_irq(0);
2966                 clear_IO_APIC_pin(apic2, pin2);
2967                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2968         }
2969
2970         if (nmi_watchdog == NMI_IO_APIC) {
2971                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2972                             "through the IO-APIC - disabling NMI Watchdog!\n");
2973                 nmi_watchdog = NMI_NONE;
2974         }
2975 #ifdef CONFIG_X86_32
2976         timer_ack = 0;
2977 #endif
2978
2979         apic_printk(APIC_QUIET, KERN_INFO
2980                     "...trying to set up timer as Virtual Wire IRQ...\n");
2981
2982         lapic_register_intr(0, desc);
2983         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
2984         enable_8259A_irq(0);
2985
2986         if (timer_irq_works()) {
2987                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2988                 goto out;
2989         }
2990         disable_8259A_irq(0);
2991         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2992         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2993
2994         apic_printk(APIC_QUIET, KERN_INFO
2995                     "...trying to set up timer as ExtINT IRQ...\n");
2996
2997         init_8259A(0);
2998         make_8259A_irq(0);
2999         apic_write(APIC_LVT0, APIC_DM_EXTINT);
3000
3001         unlock_ExtINT_logic();
3002
3003         if (timer_irq_works()) {
3004                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3005                 goto out;
3006         }
3007         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3008         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
3009                 "report.  Then try booting with the 'noapic' option.\n");
3010 out:
3011         local_irq_restore(flags);
3012 }
3013
3014 /*
3015  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3016  * to devices.  However there may be an I/O APIC pin available for
3017  * this interrupt regardless.  The pin may be left unconnected, but
3018  * typically it will be reused as an ExtINT cascade interrupt for
3019  * the master 8259A.  In the MPS case such a pin will normally be
3020  * reported as an ExtINT interrupt in the MP table.  With ACPI
3021  * there is no provision for ExtINT interrupts, and in the absence
3022  * of an override it would be treated as an ordinary ISA I/O APIC
3023  * interrupt, that is edge-triggered and unmasked by default.  We
3024  * used to do this, but it caused problems on some systems because
3025  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3026  * the same ExtINT cascade interrupt to drive the local APIC of the
3027  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3028  * the I/O APIC in all cases now.  No actual device should request
3029  * it anyway.  --macro
3030  */
3031 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3032
3033 void __init setup_IO_APIC(void)
3034 {
3035
3036 #ifdef CONFIG_X86_32
3037         enable_IO_APIC();
3038 #else
3039         /*
3040          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3041          */
3042 #endif
3043
3044         io_apic_irqs = ~PIC_IRQS;
3045
3046         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3047         /*
3048          * Set up IO-APIC IRQ routing.
3049          */
3050 #ifdef CONFIG_X86_32
3051         if (!acpi_ioapic)
3052                 setup_ioapic_ids_from_mpc();
3053 #endif
3054         sync_Arb_IDs();
3055         setup_IO_APIC_irqs();
3056         init_IO_APIC_traps();
3057         check_timer();
3058 }
3059
3060 /*
3061  *      Called after all the initialization is done. If we didnt find any
3062  *      APIC bugs then we can allow the modify fast path
3063  */
3064
3065 static int __init io_apic_bug_finalize(void)
3066 {
3067         if (sis_apic_bug == -1)
3068                 sis_apic_bug = 0;
3069         return 0;
3070 }
3071
3072 late_initcall(io_apic_bug_finalize);
3073
3074 struct sysfs_ioapic_data {
3075         struct sys_device dev;
3076         struct IO_APIC_route_entry entry[0];
3077 };
3078 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3079
3080 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3081 {
3082         struct IO_APIC_route_entry *entry;
3083         struct sysfs_ioapic_data *data;
3084         int i;
3085
3086         data = container_of(dev, struct sysfs_ioapic_data, dev);
3087         entry = data->entry;
3088         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3089                 *entry = ioapic_read_entry(dev->id, i);
3090
3091         return 0;
3092 }
3093
3094 static int ioapic_resume(struct sys_device *dev)
3095 {
3096         struct IO_APIC_route_entry *entry;
3097         struct sysfs_ioapic_data *data;
3098         unsigned long flags;
3099         union IO_APIC_reg_00 reg_00;
3100         int i;
3101
3102         data = container_of(dev, struct sysfs_ioapic_data, dev);
3103         entry = data->entry;
3104
3105         spin_lock_irqsave(&ioapic_lock, flags);
3106         reg_00.raw = io_apic_read(dev->id, 0);
3107         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3108                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3109                 io_apic_write(dev->id, 0, reg_00.raw);
3110         }
3111         spin_unlock_irqrestore(&ioapic_lock, flags);
3112         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3113                 ioapic_write_entry(dev->id, i, entry[i]);
3114
3115         return 0;
3116 }
3117
3118 static struct sysdev_class ioapic_sysdev_class = {
3119         .name = "ioapic",
3120         .suspend = ioapic_suspend,
3121         .resume = ioapic_resume,
3122 };
3123
3124 static int __init ioapic_init_sysfs(void)
3125 {
3126         struct sys_device * dev;
3127         int i, size, error;
3128
3129         error = sysdev_class_register(&ioapic_sysdev_class);
3130         if (error)
3131                 return error;
3132
3133         for (i = 0; i < nr_ioapics; i++ ) {
3134                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3135                         * sizeof(struct IO_APIC_route_entry);
3136                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3137                 if (!mp_ioapic_data[i]) {
3138                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3139                         continue;
3140                 }
3141                 dev = &mp_ioapic_data[i]->dev;
3142                 dev->id = i;
3143                 dev->cls = &ioapic_sysdev_class;
3144                 error = sysdev_register(dev);
3145                 if (error) {
3146                         kfree(mp_ioapic_data[i]);
3147                         mp_ioapic_data[i] = NULL;
3148                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3149                         continue;
3150                 }
3151         }
3152
3153         return 0;
3154 }
3155
3156 device_initcall(ioapic_init_sysfs);
3157
3158 /*
3159  * Dynamic irq allocate and deallocation
3160  */
3161 unsigned int create_irq_nr(unsigned int irq_want)
3162 {
3163         /* Allocate an unused irq */
3164         unsigned int irq;
3165         unsigned int new;
3166         unsigned long flags;
3167         struct irq_cfg *cfg_new = NULL;
3168         int cpu = boot_cpu_id;
3169         struct irq_desc *desc_new = NULL;
3170
3171         irq = 0;
3172         spin_lock_irqsave(&vector_lock, flags);
3173         for (new = irq_want; new < nr_irqs; new++) {
3174                 if (platform_legacy_irq(new))
3175                         continue;
3176
3177                 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3178                 if (!desc_new) {
3179                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3180                         continue;
3181                 }
3182                 cfg_new = desc_new->chip_data;
3183
3184                 if (cfg_new->vector != 0)
3185                         continue;
3186                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3187                         irq = new;
3188                 break;
3189         }
3190         spin_unlock_irqrestore(&vector_lock, flags);
3191
3192         if (irq > 0) {
3193                 dynamic_irq_init(irq);
3194                 /* restore it, in case dynamic_irq_init clear it */
3195                 if (desc_new)
3196                         desc_new->chip_data = cfg_new;
3197         }
3198         return irq;
3199 }
3200
3201 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3202 int create_irq(void)
3203 {
3204         unsigned int irq_want;
3205         int irq;
3206
3207         irq_want = nr_irqs_gsi;
3208         irq = create_irq_nr(irq_want);
3209
3210         if (irq == 0)
3211                 irq = -1;
3212
3213         return irq;
3214 }
3215
3216 void destroy_irq(unsigned int irq)
3217 {
3218         unsigned long flags;
3219         struct irq_cfg *cfg;
3220         struct irq_desc *desc;
3221
3222         /* store it, in case dynamic_irq_cleanup clear it */
3223         desc = irq_to_desc(irq);
3224         cfg = desc->chip_data;
3225         dynamic_irq_cleanup(irq);
3226         /* connect back irq_cfg */
3227         if (desc)
3228                 desc->chip_data = cfg;
3229
3230 #ifdef CONFIG_INTR_REMAP
3231         free_irte(irq);
3232 #endif
3233         spin_lock_irqsave(&vector_lock, flags);
3234         __clear_irq_vector(irq, cfg);
3235         spin_unlock_irqrestore(&vector_lock, flags);
3236 }
3237
3238 /*
3239  * MSI message composition
3240  */
3241 #ifdef CONFIG_PCI_MSI
3242 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3243 {
3244         struct irq_cfg *cfg;
3245         int err;
3246         unsigned dest;
3247
3248         if (disable_apic)
3249                 return -ENXIO;
3250
3251         cfg = irq_cfg(irq);
3252         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3253         if (err)
3254                 return err;
3255
3256         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3257
3258 #ifdef CONFIG_INTR_REMAP
3259         if (irq_remapped(irq)) {
3260                 struct irte irte;
3261                 int ir_index;
3262                 u16 sub_handle;
3263
3264                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3265                 BUG_ON(ir_index == -1);
3266
3267                 memset (&irte, 0, sizeof(irte));
3268
3269                 irte.present = 1;
3270                 irte.dst_mode = apic->irq_dest_mode;
3271                 irte.trigger_mode = 0; /* edge */
3272                 irte.dlvry_mode = apic->irq_delivery_mode;
3273                 irte.vector = cfg->vector;
3274                 irte.dest_id = IRTE_DEST(dest);
3275
3276                 modify_irte(irq, &irte);
3277
3278                 msg->address_hi = MSI_ADDR_BASE_HI;
3279                 msg->data = sub_handle;
3280                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3281                                   MSI_ADDR_IR_SHV |
3282                                   MSI_ADDR_IR_INDEX1(ir_index) |
3283                                   MSI_ADDR_IR_INDEX2(ir_index);
3284         } else
3285 #endif
3286         {
3287                 msg->address_hi = MSI_ADDR_BASE_HI;
3288                 msg->address_lo =
3289                         MSI_ADDR_BASE_LO |
3290                         ((apic->irq_dest_mode == 0) ?
3291                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3292                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3293                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3294                                 MSI_ADDR_REDIRECTION_CPU:
3295                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3296                         MSI_ADDR_DEST_ID(dest);
3297
3298                 msg->data =
3299                         MSI_DATA_TRIGGER_EDGE |
3300                         MSI_DATA_LEVEL_ASSERT |
3301                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3302                                 MSI_DATA_DELIVERY_FIXED:
3303                                 MSI_DATA_DELIVERY_LOWPRI) |
3304                         MSI_DATA_VECTOR(cfg->vector);
3305         }
3306         return err;
3307 }
3308
3309 #ifdef CONFIG_SMP
3310 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3311 {
3312         struct irq_desc *desc = irq_to_desc(irq);
3313         struct irq_cfg *cfg;
3314         struct msi_msg msg;
3315         unsigned int dest;
3316
3317         dest = set_desc_affinity(desc, mask);
3318         if (dest == BAD_APICID)
3319                 return;
3320
3321         cfg = desc->chip_data;
3322
3323         read_msi_msg_desc(desc, &msg);
3324
3325         msg.data &= ~MSI_DATA_VECTOR_MASK;
3326         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3327         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3328         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3329
3330         write_msi_msg_desc(desc, &msg);
3331 }
3332 #ifdef CONFIG_INTR_REMAP
3333 /*
3334  * Migrate the MSI irq to another cpumask. This migration is
3335  * done in the process context using interrupt-remapping hardware.
3336  */
3337 static void
3338 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3339 {
3340         struct irq_desc *desc = irq_to_desc(irq);
3341         struct irq_cfg *cfg = desc->chip_data;
3342         unsigned int dest;
3343         struct irte irte;
3344
3345         if (get_irte(irq, &irte))
3346                 return;
3347
3348         dest = set_desc_affinity(desc, mask);
3349         if (dest == BAD_APICID)
3350                 return;
3351
3352         irte.vector = cfg->vector;
3353         irte.dest_id = IRTE_DEST(dest);
3354
3355         /*
3356          * atomically update the IRTE with the new destination and vector.
3357          */
3358         modify_irte(irq, &irte);
3359
3360         /*
3361          * After this point, all the interrupts will start arriving
3362          * at the new destination. So, time to cleanup the previous
3363          * vector allocation.
3364          */
3365         if (cfg->move_in_progress)
3366                 send_cleanup_vector(cfg);
3367 }
3368
3369 #endif
3370 #endif /* CONFIG_SMP */
3371
3372 /*
3373  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3374  * which implement the MSI or MSI-X Capability Structure.
3375  */
3376 static struct irq_chip msi_chip = {
3377         .name           = "PCI-MSI",
3378         .unmask         = unmask_msi_irq,
3379         .mask           = mask_msi_irq,
3380         .ack            = ack_apic_edge,
3381 #ifdef CONFIG_SMP
3382         .set_affinity   = set_msi_irq_affinity,
3383 #endif
3384         .retrigger      = ioapic_retrigger_irq,
3385 };
3386
3387 #ifdef CONFIG_INTR_REMAP
3388 static struct irq_chip msi_ir_chip = {
3389         .name           = "IR-PCI-MSI",
3390         .unmask         = unmask_msi_irq,
3391         .mask           = mask_msi_irq,
3392         .ack            = ack_x2apic_edge,
3393 #ifdef CONFIG_SMP
3394         .set_affinity   = ir_set_msi_irq_affinity,
3395 #endif
3396         .retrigger      = ioapic_retrigger_irq,
3397 };
3398
3399 /*
3400  * Map the PCI dev to the corresponding remapping hardware unit
3401  * and allocate 'nvec' consecutive interrupt-remapping table entries
3402  * in it.
3403  */
3404 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3405 {
3406         struct intel_iommu *iommu;
3407         int index;
3408
3409         iommu = map_dev_to_ir(dev);
3410         if (!iommu) {
3411                 printk(KERN_ERR
3412                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3413                 return -ENOENT;
3414         }
3415
3416         index = alloc_irte(iommu, irq, nvec);
3417         if (index < 0) {
3418                 printk(KERN_ERR
3419                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3420                        pci_name(dev));
3421                 return -ENOSPC;
3422         }
3423         return index;
3424 }
3425 #endif
3426
3427 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3428 {
3429         int ret;
3430         struct msi_msg msg;
3431
3432         ret = msi_compose_msg(dev, irq, &msg);
3433         if (ret < 0)
3434                 return ret;
3435
3436         set_irq_msi(irq, msidesc);
3437         write_msi_msg(irq, &msg);
3438
3439 #ifdef CONFIG_INTR_REMAP
3440         if (irq_remapped(irq)) {
3441                 struct irq_desc *desc = irq_to_desc(irq);
3442                 /*
3443                  * irq migration in process context
3444                  */
3445                 desc->status |= IRQ_MOVE_PCNTXT;
3446                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3447         } else
3448 #endif
3449                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3450
3451         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3452
3453         return 0;
3454 }
3455
3456 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3457 {
3458         unsigned int irq;
3459         int ret, sub_handle;
3460         struct msi_desc *msidesc;
3461         unsigned int irq_want;
3462
3463 #ifdef CONFIG_INTR_REMAP
3464         struct intel_iommu *iommu = 0;
3465         int index = 0;
3466 #endif
3467
3468         irq_want = nr_irqs_gsi;
3469         sub_handle = 0;
3470         list_for_each_entry(msidesc, &dev->msi_list, list) {
3471                 irq = create_irq_nr(irq_want);
3472                 irq_want++;
3473                 if (irq == 0)
3474                         return -1;
3475 #ifdef CONFIG_INTR_REMAP
3476                 if (!intr_remapping_enabled)
3477                         goto no_ir;
3478
3479                 if (!sub_handle) {
3480                         /*
3481                          * allocate the consecutive block of IRTE's
3482                          * for 'nvec'
3483                          */
3484                         index = msi_alloc_irte(dev, irq, nvec);
3485                         if (index < 0) {
3486                                 ret = index;
3487                                 goto error;
3488                         }
3489                 } else {
3490                         iommu = map_dev_to_ir(dev);
3491                         if (!iommu) {
3492                                 ret = -ENOENT;
3493                                 goto error;
3494                         }
3495                         /*
3496                          * setup the mapping between the irq and the IRTE
3497                          * base index, the sub_handle pointing to the
3498                          * appropriate interrupt remap table entry.
3499                          */
3500                         set_irte_irq(irq, iommu, index, sub_handle);
3501                 }
3502 no_ir:
3503 #endif
3504                 ret = setup_msi_irq(dev, msidesc, irq);
3505                 if (ret < 0)
3506                         goto error;
3507                 sub_handle++;
3508         }
3509         return 0;
3510
3511 error:
3512         destroy_irq(irq);
3513         return ret;
3514 }
3515
3516 void arch_teardown_msi_irq(unsigned int irq)
3517 {
3518         destroy_irq(irq);
3519 }
3520
3521 #ifdef CONFIG_DMAR
3522 #ifdef CONFIG_SMP
3523 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3524 {
3525         struct irq_desc *desc = irq_to_desc(irq);
3526         struct irq_cfg *cfg;
3527         struct msi_msg msg;
3528         unsigned int dest;
3529
3530         dest = set_desc_affinity(desc, mask);
3531         if (dest == BAD_APICID)
3532                 return;
3533
3534         cfg = desc->chip_data;
3535
3536         dmar_msi_read(irq, &msg);
3537
3538         msg.data &= ~MSI_DATA_VECTOR_MASK;
3539         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3540         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3541         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3542
3543         dmar_msi_write(irq, &msg);
3544 }
3545
3546 #endif /* CONFIG_SMP */
3547
3548 struct irq_chip dmar_msi_type = {
3549         .name = "DMAR_MSI",
3550         .unmask = dmar_msi_unmask,
3551         .mask = dmar_msi_mask,
3552         .ack = ack_apic_edge,
3553 #ifdef CONFIG_SMP
3554         .set_affinity = dmar_msi_set_affinity,
3555 #endif
3556         .retrigger = ioapic_retrigger_irq,
3557 };
3558
3559 int arch_setup_dmar_msi(unsigned int irq)
3560 {
3561         int ret;
3562         struct msi_msg msg;
3563
3564         ret = msi_compose_msg(NULL, irq, &msg);
3565         if (ret < 0)
3566                 return ret;
3567         dmar_msi_write(irq, &msg);
3568         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3569                 "edge");
3570         return 0;
3571 }
3572 #endif
3573
3574 #ifdef CONFIG_HPET_TIMER
3575
3576 #ifdef CONFIG_SMP
3577 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3578 {
3579         struct irq_desc *desc = irq_to_desc(irq);
3580         struct irq_cfg *cfg;
3581         struct msi_msg msg;
3582         unsigned int dest;
3583
3584         dest = set_desc_affinity(desc, mask);
3585         if (dest == BAD_APICID)
3586                 return;
3587
3588         cfg = desc->chip_data;
3589
3590         hpet_msi_read(irq, &msg);
3591
3592         msg.data &= ~MSI_DATA_VECTOR_MASK;
3593         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3594         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3595         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3596
3597         hpet_msi_write(irq, &msg);
3598 }
3599
3600 #endif /* CONFIG_SMP */
3601
3602 struct irq_chip hpet_msi_type = {
3603         .name = "HPET_MSI",
3604         .unmask = hpet_msi_unmask,
3605         .mask = hpet_msi_mask,
3606         .ack = ack_apic_edge,
3607 #ifdef CONFIG_SMP
3608         .set_affinity = hpet_msi_set_affinity,
3609 #endif
3610         .retrigger = ioapic_retrigger_irq,
3611 };
3612
3613 int arch_setup_hpet_msi(unsigned int irq)
3614 {
3615         int ret;
3616         struct msi_msg msg;
3617
3618         ret = msi_compose_msg(NULL, irq, &msg);
3619         if (ret < 0)
3620                 return ret;
3621
3622         hpet_msi_write(irq, &msg);
3623         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3624                 "edge");
3625
3626         return 0;
3627 }
3628 #endif
3629
3630 #endif /* CONFIG_PCI_MSI */
3631 /*
3632  * Hypertransport interrupt support
3633  */
3634 #ifdef CONFIG_HT_IRQ
3635
3636 #ifdef CONFIG_SMP
3637
3638 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3639 {
3640         struct ht_irq_msg msg;
3641         fetch_ht_irq_msg(irq, &msg);
3642
3643         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3644         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3645
3646         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3647         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3648
3649         write_ht_irq_msg(irq, &msg);
3650 }
3651
3652 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3653 {
3654         struct irq_desc *desc = irq_to_desc(irq);
3655         struct irq_cfg *cfg;
3656         unsigned int dest;
3657
3658         dest = set_desc_affinity(desc, mask);
3659         if (dest == BAD_APICID)
3660                 return;
3661
3662         cfg = desc->chip_data;
3663
3664         target_ht_irq(irq, dest, cfg->vector);
3665 }
3666
3667 #endif
3668
3669 static struct irq_chip ht_irq_chip = {
3670         .name           = "PCI-HT",
3671         .mask           = mask_ht_irq,
3672         .unmask         = unmask_ht_irq,
3673         .ack            = ack_apic_edge,
3674 #ifdef CONFIG_SMP
3675         .set_affinity   = set_ht_irq_affinity,
3676 #endif
3677         .retrigger      = ioapic_retrigger_irq,
3678 };
3679
3680 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3681 {
3682         struct irq_cfg *cfg;
3683         int err;
3684
3685         if (disable_apic)
3686                 return -ENXIO;
3687
3688         cfg = irq_cfg(irq);
3689         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3690         if (!err) {
3691                 struct ht_irq_msg msg;
3692                 unsigned dest;
3693
3694                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3695                                                     apic->target_cpus());
3696
3697                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3698
3699                 msg.address_lo =
3700                         HT_IRQ_LOW_BASE |
3701                         HT_IRQ_LOW_DEST_ID(dest) |
3702                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3703                         ((apic->irq_dest_mode == 0) ?
3704                                 HT_IRQ_LOW_DM_PHYSICAL :
3705                                 HT_IRQ_LOW_DM_LOGICAL) |
3706                         HT_IRQ_LOW_RQEOI_EDGE |
3707                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3708                                 HT_IRQ_LOW_MT_FIXED :
3709                                 HT_IRQ_LOW_MT_ARBITRATED) |
3710                         HT_IRQ_LOW_IRQ_MASKED;
3711
3712                 write_ht_irq_msg(irq, &msg);
3713
3714                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3715                                               handle_edge_irq, "edge");
3716
3717                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3718         }
3719         return err;
3720 }
3721 #endif /* CONFIG_HT_IRQ */
3722
3723 #ifdef CONFIG_X86_UV
3724 /*
3725  * Re-target the irq to the specified CPU and enable the specified MMR located
3726  * on the specified blade to allow the sending of MSIs to the specified CPU.
3727  */
3728 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3729                        unsigned long mmr_offset)
3730 {
3731         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3732         struct irq_cfg *cfg;
3733         int mmr_pnode;
3734         unsigned long mmr_value;
3735         struct uv_IO_APIC_route_entry *entry;
3736         unsigned long flags;
3737         int err;
3738
3739         cfg = irq_cfg(irq);
3740
3741         err = assign_irq_vector(irq, cfg, eligible_cpu);
3742         if (err != 0)
3743                 return err;
3744
3745         spin_lock_irqsave(&vector_lock, flags);
3746         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3747                                       irq_name);
3748         spin_unlock_irqrestore(&vector_lock, flags);
3749
3750         mmr_value = 0;
3751         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3752         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3753
3754         entry->vector = cfg->vector;
3755         entry->delivery_mode = apic->irq_delivery_mode;
3756         entry->dest_mode = apic->irq_dest_mode;
3757         entry->polarity = 0;
3758         entry->trigger = 0;
3759         entry->mask = 0;
3760         entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3761
3762         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3763         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3764
3765         return irq;
3766 }
3767
3768 /*
3769  * Disable the specified MMR located on the specified blade so that MSIs are
3770  * longer allowed to be sent.
3771  */
3772 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3773 {
3774         unsigned long mmr_value;
3775         struct uv_IO_APIC_route_entry *entry;
3776         int mmr_pnode;
3777
3778         mmr_value = 0;
3779         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3780         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3781
3782         entry->mask = 1;
3783
3784         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3785         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3786 }
3787 #endif /* CONFIG_X86_64 */
3788
3789 int __init io_apic_get_redir_entries (int ioapic)
3790 {
3791         union IO_APIC_reg_01    reg_01;
3792         unsigned long flags;
3793
3794         spin_lock_irqsave(&ioapic_lock, flags);
3795         reg_01.raw = io_apic_read(ioapic, 1);
3796         spin_unlock_irqrestore(&ioapic_lock, flags);
3797
3798         return reg_01.bits.entries;
3799 }
3800
3801 void __init probe_nr_irqs_gsi(void)
3802 {
3803         int idx;
3804         int nr = 0;
3805
3806         for (idx = 0; idx < nr_ioapics; idx++)
3807                 nr += io_apic_get_redir_entries(idx) + 1;
3808
3809         if (nr > nr_irqs_gsi)
3810                 nr_irqs_gsi = nr;
3811 }
3812
3813 #ifdef CONFIG_SPARSE_IRQ
3814 int __init arch_probe_nr_irqs(void)
3815 {
3816         int nr;
3817
3818         nr = ((8 * nr_cpu_ids) > (32 * nr_ioapics) ?
3819                 (NR_VECTORS + (8 * nr_cpu_ids)) :
3820                 (NR_VECTORS + (32 * nr_ioapics)));
3821
3822         if (nr < nr_irqs && nr > nr_irqs_gsi)
3823                 nr_irqs = nr;
3824
3825         return 0;
3826 }
3827 #endif
3828
3829 /* --------------------------------------------------------------------------
3830                           ACPI-based IOAPIC Configuration
3831    -------------------------------------------------------------------------- */
3832
3833 #ifdef CONFIG_ACPI
3834
3835 #ifdef CONFIG_X86_32
3836 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3837 {
3838         union IO_APIC_reg_00 reg_00;
3839         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3840         physid_mask_t tmp;
3841         unsigned long flags;
3842         int i = 0;
3843
3844         /*
3845          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3846          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3847          * supports up to 16 on one shared APIC bus.
3848          *
3849          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3850          *      advantage of new APIC bus architecture.
3851          */
3852
3853         if (physids_empty(apic_id_map))
3854                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3855
3856         spin_lock_irqsave(&ioapic_lock, flags);
3857         reg_00.raw = io_apic_read(ioapic, 0);
3858         spin_unlock_irqrestore(&ioapic_lock, flags);
3859
3860         if (apic_id >= get_physical_broadcast()) {
3861                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3862                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3863                 apic_id = reg_00.bits.ID;
3864         }
3865
3866         /*
3867          * Every APIC in a system must have a unique ID or we get lots of nice
3868          * 'stuck on smp_invalidate_needed IPI wait' messages.
3869          */
3870         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3871
3872                 for (i = 0; i < get_physical_broadcast(); i++) {
3873                         if (!apic->check_apicid_used(apic_id_map, i))
3874                                 break;
3875                 }
3876
3877                 if (i == get_physical_broadcast())
3878                         panic("Max apic_id exceeded!\n");
3879
3880                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3881                         "trying %d\n", ioapic, apic_id, i);
3882
3883                 apic_id = i;
3884         }
3885
3886         tmp = apic->apicid_to_cpu_present(apic_id);
3887         physids_or(apic_id_map, apic_id_map, tmp);
3888
3889         if (reg_00.bits.ID != apic_id) {
3890                 reg_00.bits.ID = apic_id;
3891
3892                 spin_lock_irqsave(&ioapic_lock, flags);
3893                 io_apic_write(ioapic, 0, reg_00.raw);
3894                 reg_00.raw = io_apic_read(ioapic, 0);
3895                 spin_unlock_irqrestore(&ioapic_lock, flags);
3896
3897                 /* Sanity check */
3898                 if (reg_00.bits.ID != apic_id) {
3899                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3900                         return -1;
3901                 }
3902         }
3903
3904         apic_printk(APIC_VERBOSE, KERN_INFO
3905                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3906
3907         return apic_id;
3908 }
3909
3910 int __init io_apic_get_version(int ioapic)
3911 {
3912         union IO_APIC_reg_01    reg_01;
3913         unsigned long flags;
3914
3915         spin_lock_irqsave(&ioapic_lock, flags);
3916         reg_01.raw = io_apic_read(ioapic, 1);
3917         spin_unlock_irqrestore(&ioapic_lock, flags);
3918
3919         return reg_01.bits.version;
3920 }
3921 #endif
3922
3923 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3924 {
3925         struct irq_desc *desc;
3926         struct irq_cfg *cfg;
3927         int cpu = boot_cpu_id;
3928
3929         if (!IO_APIC_IRQ(irq)) {
3930                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3931                         ioapic);
3932                 return -EINVAL;
3933         }
3934
3935         desc = irq_to_desc_alloc_cpu(irq, cpu);
3936         if (!desc) {
3937                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3938                 return 0;
3939         }
3940
3941         /*
3942          * IRQs < 16 are already in the irq_2_pin[] map
3943          */
3944         if (irq >= NR_IRQS_LEGACY) {
3945                 cfg = desc->chip_data;
3946                 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3947         }
3948
3949         setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3950
3951         return 0;
3952 }
3953
3954
3955 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3956 {
3957         int i;
3958
3959         if (skip_ioapic_setup)
3960                 return -1;
3961
3962         for (i = 0; i < mp_irq_entries; i++)
3963                 if (mp_irqs[i].irqtype == mp_INT &&
3964                     mp_irqs[i].srcbusirq == bus_irq)
3965                         break;
3966         if (i >= mp_irq_entries)
3967                 return -1;
3968
3969         *trigger = irq_trigger(i);
3970         *polarity = irq_polarity(i);
3971         return 0;
3972 }
3973
3974 #endif /* CONFIG_ACPI */
3975
3976 /*
3977  * This function currently is only a helper for the i386 smp boot process where
3978  * we need to reprogram the ioredtbls to cater for the cpus which have come online
3979  * so mask in all cases should simply be apic->target_cpus()
3980  */
3981 #ifdef CONFIG_SMP
3982 void __init setup_ioapic_dest(void)
3983 {
3984         int pin, ioapic, irq, irq_entry;
3985         struct irq_desc *desc;
3986         struct irq_cfg *cfg;
3987         const struct cpumask *mask;
3988
3989         if (skip_ioapic_setup == 1)
3990                 return;
3991
3992         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3993                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3994                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3995                         if (irq_entry == -1)
3996                                 continue;
3997                         irq = pin_2_irq(irq_entry, ioapic, pin);
3998
3999                         /* setup_IO_APIC_irqs could fail to get vector for some device
4000                          * when you have too many devices, because at that time only boot
4001                          * cpu is online.
4002                          */
4003                         desc = irq_to_desc(irq);
4004                         cfg = desc->chip_data;
4005                         if (!cfg->vector) {
4006                                 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4007                                                   irq_trigger(irq_entry),
4008                                                   irq_polarity(irq_entry));
4009                                 continue;
4010
4011                         }
4012
4013                         /*
4014                          * Honour affinities which have been set in early boot
4015                          */
4016                         if (desc->status &
4017                             (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4018                                 mask = desc->affinity;
4019                         else
4020                                 mask = apic->target_cpus();
4021
4022 #ifdef CONFIG_INTR_REMAP
4023                         if (intr_remapping_enabled)
4024                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
4025                         else
4026 #endif
4027                                 set_ioapic_affinity_irq_desc(desc, mask);
4028                 }
4029
4030         }
4031 }
4032 #endif
4033
4034 #define IOAPIC_RESOURCE_NAME_SIZE 11
4035
4036 static struct resource *ioapic_resources;
4037
4038 static struct resource * __init ioapic_setup_resources(void)
4039 {
4040         unsigned long n;
4041         struct resource *res;
4042         char *mem;
4043         int i;
4044
4045         if (nr_ioapics <= 0)
4046                 return NULL;
4047
4048         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4049         n *= nr_ioapics;
4050
4051         mem = alloc_bootmem(n);
4052         res = (void *)mem;
4053
4054         if (mem != NULL) {
4055                 mem += sizeof(struct resource) * nr_ioapics;
4056
4057                 for (i = 0; i < nr_ioapics; i++) {
4058                         res[i].name = mem;
4059                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4060                         sprintf(mem,  "IOAPIC %u", i);
4061                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4062                 }
4063         }
4064
4065         ioapic_resources = res;
4066
4067         return res;
4068 }
4069
4070 void __init ioapic_init_mappings(void)
4071 {
4072         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4073         struct resource *ioapic_res;
4074         int i;
4075
4076         ioapic_res = ioapic_setup_resources();
4077         for (i = 0; i < nr_ioapics; i++) {
4078                 if (smp_found_config) {
4079                         ioapic_phys = mp_ioapics[i].apicaddr;
4080 #ifdef CONFIG_X86_32
4081                         if (!ioapic_phys) {
4082                                 printk(KERN_ERR
4083                                        "WARNING: bogus zero IO-APIC "
4084                                        "address found in MPTABLE, "
4085                                        "disabling IO/APIC support!\n");
4086                                 smp_found_config = 0;
4087                                 skip_ioapic_setup = 1;
4088                                 goto fake_ioapic_page;
4089                         }
4090 #endif
4091                 } else {
4092 #ifdef CONFIG_X86_32
4093 fake_ioapic_page:
4094 #endif
4095                         ioapic_phys = (unsigned long)
4096                                 alloc_bootmem_pages(PAGE_SIZE);
4097                         ioapic_phys = __pa(ioapic_phys);
4098                 }
4099                 set_fixmap_nocache(idx, ioapic_phys);
4100                 apic_printk(APIC_VERBOSE,
4101                             "mapped IOAPIC to %08lx (%08lx)\n",
4102                             __fix_to_virt(idx), ioapic_phys);
4103                 idx++;
4104
4105                 if (ioapic_res != NULL) {
4106                         ioapic_res->start = ioapic_phys;
4107                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4108                         ioapic_res++;
4109                 }
4110         }
4111 }
4112
4113 static int __init ioapic_insert_resources(void)
4114 {
4115         int i;
4116         struct resource *r = ioapic_resources;
4117
4118         if (!r) {
4119                 printk(KERN_ERR
4120                        "IO APIC resources could be not be allocated.\n");
4121                 return -1;
4122         }
4123
4124         for (i = 0; i < nr_ioapics; i++) {
4125                 insert_resource(&iomem_resource, r);
4126                 r++;
4127         }
4128
4129         return 0;
4130 }
4131
4132 /* Insert the IO APIC resources after PCI initialization has occured to handle
4133  * IO APICS that are mapped in on a BAR in PCI space. */
4134 late_initcall(ioapic_insert_resources);