2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
8 #include <linux/module.h>
9 #include <linux/regset.h>
10 #include <linux/sched.h>
11 #include <linux/slab.h>
13 #include <asm/sigcontext.h>
14 #include <asm/processor.h>
15 #include <asm/math_emu.h>
16 #include <asm/uaccess.h>
17 #include <asm/ptrace.h>
22 # include <asm/sigcontext32.h>
23 # include <asm/user32.h>
25 # define save_i387_xstate_ia32 save_i387_xstate
26 # define restore_i387_xstate_ia32 restore_i387_xstate
27 # define _fpstate_ia32 _fpstate
28 # define _xstate_ia32 _xstate
29 # define sig_xstate_ia32_size sig_xstate_size
30 # define fx_sw_reserved_ia32 fx_sw_reserved
31 # define user_i387_ia32_struct user_i387_struct
32 # define user32_fxsr_struct user_fxsr_struct
35 #ifdef CONFIG_MATH_EMULATION
36 # define HAVE_HWFP (boot_cpu_data.hard_math)
41 static unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu;
42 unsigned int xstate_size;
43 unsigned int sig_xstate_ia32_size = sizeof(struct _fpstate_ia32);
44 static struct i387_fxsave_struct fx_scratch __cpuinitdata;
46 void __cpuinit mxcsr_feature_mask_init(void)
48 unsigned long mask = 0;
52 memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct));
53 asm volatile("fxsave %0" : : "m" (fx_scratch));
54 mask = fx_scratch.mxcsr_mask;
58 mxcsr_feature_mask &= mask;
62 static void __cpuinit init_thread_xstate(void)
65 * Note that xstate_size might be overwriten later during
71 * Disable xsave as we do not support it if i387
72 * emulation is enabled.
74 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
75 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
76 xstate_size = sizeof(struct i387_soft_struct);
81 xstate_size = sizeof(struct i387_fxsave_struct);
84 xstate_size = sizeof(struct i387_fsave_struct);
89 * Called at bootup to set up the initial FPU state that is later cloned
93 void __cpuinit fpu_init(void)
96 unsigned long cr4_mask = 0;
99 cr4_mask |= X86_CR4_OSFXSR;
101 cr4_mask |= X86_CR4_OSXMMEXCPT;
103 set_in_cr4(cr4_mask);
106 cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */
111 if (!smp_processor_id())
112 init_thread_xstate();
114 mxcsr_feature_mask_init();
115 /* clean state in init */
116 current_thread_info()->status = 0;
120 void fpu_finit(struct fpu *fpu)
124 finit_soft_fpu(&fpu->state->soft);
130 struct i387_fxsave_struct *fx = &fpu->state->fxsave;
132 memset(fx, 0, xstate_size);
135 fx->mxcsr = MXCSR_DEFAULT;
137 struct i387_fsave_struct *fp = &fpu->state->fsave;
138 memset(fp, 0, xstate_size);
139 fp->cwd = 0xffff037fu;
140 fp->swd = 0xffff0000u;
141 fp->twd = 0xffffffffu;
142 fp->fos = 0xffff0000u;
145 EXPORT_SYMBOL_GPL(fpu_finit);
148 * The _current_ task is using the FPU for the first time
149 * so initialize it and set the mxcsr to its default
150 * value at reset if we support XMM instructions and then
151 * remeber the current task has used the FPU.
153 int init_fpu(struct task_struct *tsk)
157 if (tsk_used_math(tsk)) {
158 if (HAVE_HWFP && tsk == current)
164 * Memory allocation at the first usage of the FPU and other state.
166 ret = fpu_alloc(&tsk->thread.fpu);
170 fpu_finit(&tsk->thread.fpu);
172 set_stopped_child_used_math(tsk);
177 * The xstateregs_active() routine is the same as the fpregs_active() routine,
178 * as the "regset->n" for the xstate regset will be updated based on the feature
179 * capabilites supported by the xsave.
181 int fpregs_active(struct task_struct *target, const struct user_regset *regset)
183 return tsk_used_math(target) ? regset->n : 0;
186 int xfpregs_active(struct task_struct *target, const struct user_regset *regset)
188 return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0;
191 int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
192 unsigned int pos, unsigned int count,
193 void *kbuf, void __user *ubuf)
200 ret = init_fpu(target);
204 sanitize_i387_state(target);
206 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
207 &target->thread.fpu.state->fxsave, 0, -1);
210 int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
211 unsigned int pos, unsigned int count,
212 const void *kbuf, const void __user *ubuf)
219 ret = init_fpu(target);
223 sanitize_i387_state(target);
225 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
226 &target->thread.fpu.state->fxsave, 0, -1);
229 * mxcsr reserved bits must be masked to zero for security reasons.
231 target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask;
234 * update the header bits in the xsave header, indicating the
235 * presence of FP and SSE state.
238 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE;
243 int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
244 unsigned int pos, unsigned int count,
245 void *kbuf, void __user *ubuf)
252 ret = init_fpu(target);
257 * Copy the 48bytes defined by the software first into the xstate
258 * memory layout in the thread struct, so that we can copy the entire
259 * xstateregs to the user using one user_regset_copyout().
261 memcpy(&target->thread.fpu.state->fxsave.sw_reserved,
262 xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
265 * Copy the xstate memory layout.
267 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
268 &target->thread.fpu.state->xsave, 0, -1);
272 int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
273 unsigned int pos, unsigned int count,
274 const void *kbuf, const void __user *ubuf)
277 struct xsave_hdr_struct *xsave_hdr;
282 ret = init_fpu(target);
286 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
287 &target->thread.fpu.state->xsave, 0, -1);
290 * mxcsr reserved bits must be masked to zero for security reasons.
292 target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask;
294 xsave_hdr = &target->thread.fpu.state->xsave.xsave_hdr;
296 xsave_hdr->xstate_bv &= pcntxt_mask;
298 * These bits must be zero.
300 xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0;
305 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
308 * FPU tag word conversions.
311 static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
313 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
315 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
317 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
318 /* and move the valid bits to the lower byte. */
319 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
320 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
321 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
326 #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16);
327 #define FP_EXP_TAG_VALID 0
328 #define FP_EXP_TAG_ZERO 1
329 #define FP_EXP_TAG_SPECIAL 2
330 #define FP_EXP_TAG_EMPTY 3
332 static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave)
335 u32 tos = (fxsave->swd >> 11) & 7;
336 u32 twd = (unsigned long) fxsave->twd;
338 u32 ret = 0xffff0000u;
341 for (i = 0; i < 8; i++, twd >>= 1) {
343 st = FPREG_ADDR(fxsave, (i - tos) & 7);
345 switch (st->exponent & 0x7fff) {
347 tag = FP_EXP_TAG_SPECIAL;
350 if (!st->significand[0] &&
351 !st->significand[1] &&
352 !st->significand[2] &&
354 tag = FP_EXP_TAG_ZERO;
356 tag = FP_EXP_TAG_SPECIAL;
359 if (st->significand[3] & 0x8000)
360 tag = FP_EXP_TAG_VALID;
362 tag = FP_EXP_TAG_SPECIAL;
366 tag = FP_EXP_TAG_EMPTY;
368 ret |= tag << (2 * i);
374 * FXSR floating point environment conversions.
378 convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
380 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
381 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
382 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
385 env->cwd = fxsave->cwd | 0xffff0000u;
386 env->swd = fxsave->swd | 0xffff0000u;
387 env->twd = twd_fxsr_to_i387(fxsave);
390 env->fip = fxsave->rip;
391 env->foo = fxsave->rdp;
392 if (tsk == current) {
394 * should be actually ds/cs at fpu exception time, but
395 * that information is not available in 64bit mode.
397 asm("mov %%ds, %[fos]" : [fos] "=r" (env->fos));
398 asm("mov %%cs, %[fcs]" : [fcs] "=r" (env->fcs));
400 struct pt_regs *regs = task_pt_regs(tsk);
402 env->fos = 0xffff0000 | tsk->thread.ds;
406 env->fip = fxsave->fip;
407 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
408 env->foo = fxsave->foo;
409 env->fos = fxsave->fos;
412 for (i = 0; i < 8; ++i)
413 memcpy(&to[i], &from[i], sizeof(to[0]));
416 static void convert_to_fxsr(struct task_struct *tsk,
417 const struct user_i387_ia32_struct *env)
420 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
421 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
422 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
425 fxsave->cwd = env->cwd;
426 fxsave->swd = env->swd;
427 fxsave->twd = twd_i387_to_fxsr(env->twd);
428 fxsave->fop = (u16) ((u32) env->fcs >> 16);
430 fxsave->rip = env->fip;
431 fxsave->rdp = env->foo;
432 /* cs and ds ignored */
434 fxsave->fip = env->fip;
435 fxsave->fcs = (env->fcs & 0xffff);
436 fxsave->foo = env->foo;
437 fxsave->fos = env->fos;
440 for (i = 0; i < 8; ++i)
441 memcpy(&to[i], &from[i], sizeof(from[0]));
444 int fpregs_get(struct task_struct *target, const struct user_regset *regset,
445 unsigned int pos, unsigned int count,
446 void *kbuf, void __user *ubuf)
448 struct user_i387_ia32_struct env;
451 ret = init_fpu(target);
456 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
459 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
460 &target->thread.fpu.state->fsave, 0,
464 sanitize_i387_state(target);
466 if (kbuf && pos == 0 && count == sizeof(env)) {
467 convert_from_fxsr(kbuf, target);
471 convert_from_fxsr(&env, target);
473 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
476 int fpregs_set(struct task_struct *target, const struct user_regset *regset,
477 unsigned int pos, unsigned int count,
478 const void *kbuf, const void __user *ubuf)
480 struct user_i387_ia32_struct env;
483 ret = init_fpu(target);
487 sanitize_i387_state(target);
490 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
493 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
494 &target->thread.fpu.state->fsave, 0, -1);
497 if (pos > 0 || count < sizeof(env))
498 convert_from_fxsr(&env, target);
500 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
502 convert_to_fxsr(target, &env);
505 * update the header bit in the xsave header, indicating the
509 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP;
514 * Signal frame handlers.
517 static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf)
519 struct task_struct *tsk = current;
520 struct i387_fsave_struct *fp = &tsk->thread.fpu.state->fsave;
522 fp->status = fp->swd;
523 if (__copy_to_user(buf, fp, sizeof(struct i387_fsave_struct)))
528 static int save_i387_fxsave(struct _fpstate_ia32 __user *buf)
530 struct task_struct *tsk = current;
531 struct i387_fxsave_struct *fx = &tsk->thread.fpu.state->fxsave;
532 struct user_i387_ia32_struct env;
535 convert_from_fxsr(&env, tsk);
536 if (__copy_to_user(buf, &env, sizeof(env)))
539 err |= __put_user(fx->swd, &buf->status);
540 err |= __put_user(X86_FXSR_MAGIC, &buf->magic);
544 if (__copy_to_user(&buf->_fxsr_env[0], fx, xstate_size))
549 static int save_i387_xsave(void __user *buf)
551 struct task_struct *tsk = current;
552 struct _fpstate_ia32 __user *fx = buf;
556 sanitize_i387_state(tsk);
559 * For legacy compatible, we always set FP/SSE bits in the bit
560 * vector while saving the state to the user context.
561 * This will enable us capturing any changes(during sigreturn) to
562 * the FP/SSE bits by the legacy applications which don't touch
563 * xstate_bv in the xsave header.
565 * xsave aware applications can change the xstate_bv in the xsave
566 * header as well as change any contents in the memory layout.
567 * xrestore as part of sigreturn will capture all the changes.
569 tsk->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE;
571 if (save_i387_fxsave(fx) < 0)
574 err = __copy_to_user(&fx->sw_reserved, &fx_sw_reserved_ia32,
575 sizeof(struct _fpx_sw_bytes));
576 err |= __put_user(FP_XSTATE_MAGIC2,
577 (__u32 __user *) (buf + sig_xstate_ia32_size
578 - FP_XSTATE_MAGIC2_SIZE));
585 int save_i387_xstate_ia32(void __user *buf)
587 struct _fpstate_ia32 __user *fp = (struct _fpstate_ia32 __user *) buf;
588 struct task_struct *tsk = current;
593 if (!access_ok(VERIFY_WRITE, buf, sig_xstate_ia32_size))
596 * This will cause a "finit" to be triggered by the next
597 * attempted FPU operation by the 'current' process.
602 return fpregs_soft_get(current, NULL,
603 0, sizeof(struct user_i387_ia32_struct),
610 return save_i387_xsave(fp);
612 return save_i387_fxsave(fp);
614 return save_i387_fsave(fp);
617 static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf)
619 struct task_struct *tsk = current;
621 return __copy_from_user(&tsk->thread.fpu.state->fsave, buf,
622 sizeof(struct i387_fsave_struct));
625 static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf,
628 struct task_struct *tsk = current;
629 struct user_i387_ia32_struct env;
632 err = __copy_from_user(&tsk->thread.fpu.state->fxsave, &buf->_fxsr_env[0],
634 /* mxcsr reserved bits must be masked to zero for security reasons */
635 tsk->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask;
636 if (err || __copy_from_user(&env, buf, sizeof(env)))
638 convert_to_fxsr(tsk, &env);
643 static int restore_i387_xsave(void __user *buf)
645 struct _fpx_sw_bytes fx_sw_user;
646 struct _fpstate_ia32 __user *fx_user =
647 ((struct _fpstate_ia32 __user *) buf);
648 struct i387_fxsave_struct __user *fx =
649 (struct i387_fxsave_struct __user *) &fx_user->_fxsr_env[0];
650 struct xsave_hdr_struct *xsave_hdr =
651 ¤t->thread.fpu.state->xsave.xsave_hdr;
655 if (check_for_xstate(fx, buf, &fx_sw_user))
658 mask = fx_sw_user.xstate_bv;
660 err = restore_i387_fxsave(buf, fx_sw_user.xstate_size);
662 xsave_hdr->xstate_bv &= pcntxt_mask;
664 * These bits must be zero.
666 xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0;
669 * Init the state that is not present in the memory layout
670 * and enabled by the OS.
672 mask = ~(pcntxt_mask & ~mask);
673 xsave_hdr->xstate_bv &= mask;
678 * Couldn't find the extended state information in the memory
679 * layout. Restore the FP/SSE and init the other extended state
682 xsave_hdr->xstate_bv = XSTATE_FPSSE;
683 return restore_i387_fxsave(buf, sizeof(struct i387_fxsave_struct));
686 int restore_i387_xstate_ia32(void __user *buf)
689 struct task_struct *tsk = current;
690 struct _fpstate_ia32 __user *fp = (struct _fpstate_ia32 __user *) buf;
703 if (!access_ok(VERIFY_READ, buf, sig_xstate_ia32_size))
714 err = restore_i387_xsave(buf);
715 else if (cpu_has_fxsr)
716 err = restore_i387_fxsave(fp, sizeof(struct
717 i387_fxsave_struct));
719 err = restore_i387_fsave(fp);
721 err = fpregs_soft_set(current, NULL,
722 0, sizeof(struct user_i387_ia32_struct),
731 * FPU state for core dumps.
732 * This is only used for a.out dumps now.
733 * It is declared generically using elf_fpregset_t (which is
734 * struct user_i387_struct) but is in fact only used for 32-bit
735 * dumps, so on 64-bit it is really struct user_i387_ia32_struct.
737 int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu)
739 struct task_struct *tsk = current;
742 fpvalid = !!used_math();
744 fpvalid = !fpregs_get(tsk, NULL,
745 0, sizeof(struct user_i387_ia32_struct),
750 EXPORT_SYMBOL(dump_fpu);
752 #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */