arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/export.h>
   5 #include <linux/sysdev.h>
   6 #include <linux/delay.h>
   7 #include <linux/errno.h>
   8 #include <linux/i8253.h>
   9 #include <linux/slab.h>
  10 #include <linux/hpet.h>
  11 #include <linux/init.h>
  12 #include <linux/cpu.h>
  13 #include <linux/pm.h>
  14 #include <linux/io.h>
  15 #include <linux/kaiser.h>
  16
  17 #include <asm/fixmap.h>
  18 #include <asm/hpet.h>
  19 #include <asm/time.h>
  20
  21 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
  22
  23 /* FSEC = 10^-15
  24    NSEC = 10^-9 */
  25 #define FSEC_PER_NSEC                   1000000L
  26
  27 #define HPET_DEV_USED_BIT               2
  28 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
  29 #define HPET_DEV_VALID                  0x8
  30 #define HPET_DEV_FSB_CAP                0x1000
  31 #define HPET_DEV_PERI_CAP               0x2000
  32
  33 #define HPET_MIN_CYCLES                 128
  34 #define HPET_MIN_PROG_DELTA             (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
  35
  36 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
  37
  38 /*
  39  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  40  */
  41 unsigned long                           hpet_address;
  42 u8                                      hpet_blockid; /* OS timer block num */
  43 u8                                      hpet_msi_disable;
  44
  45 #ifdef CONFIG_PCI_MSI
  46 static unsigned long                    hpet_num_timers;
  47 #endif
  48 static void __iomem                     *hpet_virt_address;
  49
  50 struct hpet_dev {
  51         struct clock_event_device       evt;
  52         unsigned int                    num;
  53         int                             cpu;
  54         unsigned int                    irq;
  55         unsigned int                    flags;
  56         char                            name[10];
  57 };
  58
  59 inline unsigned int hpet_readl(unsigned int a)
  60 {
  61         return readl(hpet_virt_address + a);
  62 }
  63
  64 static inline void hpet_writel(unsigned int d, unsigned int a)
  65 {
  66         writel(d, hpet_virt_address + a);
  67 }
  68
  69 #ifdef CONFIG_X86_64
  70 #include <asm/pgtable.h>
  71 #endif
  72
  73 static inline void hpet_set_mapping(void)
  74 {
  75         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  76 #ifdef CONFIG_X86_64
  77         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
  78         kaiser_add_mapping(__fix_to_virt(VSYSCALL_HPET), PAGE_SIZE,
  79                            __PAGE_KERNEL_VVAR_NOCACHE);
  80 #endif
  81 }
  82
  83 static inline void hpet_clear_mapping(void)
  84 {
  85         iounmap(hpet_virt_address);
  86         hpet_virt_address = NULL;
  87 }
  88
  89 /*
  90  * HPET command line enable / disable
  91  */
  92 static int boot_hpet_disable;
  93 int hpet_force_user;
  94 static int hpet_verbose;
  95
  96 static int __init hpet_setup(char *str)
  97 {
  98         if (str) {
  99                 if (!strncmp("disable", str, 7))
 100                         boot_hpet_disable = 1;
 101                 if (!strncmp("force", str, 5))
 102                         hpet_force_user = 1;
 103                 if (!strncmp("verbose", str, 7))
 104                         hpet_verbose = 1;
 105         }
 106         return 1;
 107 }
 108 __setup("hpet=", hpet_setup);
 109
 110 static int __init disable_hpet(char *str)
 111 {
 112         boot_hpet_disable = 1;
 113         return 1;
 114 }
 115 __setup("nohpet", disable_hpet);
 116
 117 static inline int is_hpet_capable(void)
 118 {
 119         return !boot_hpet_disable && hpet_address;
 120 }
 121
 122 /*
 123  * HPET timer interrupt enable / disable
 124  */
 125 static int hpet_legacy_int_enabled;
 126
 127 /**
 128  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 129  */
 130 int is_hpet_enabled(void)
 131 {
 132         return is_hpet_capable() && hpet_legacy_int_enabled;
 133 }
 134 EXPORT_SYMBOL_GPL(is_hpet_enabled);
 135
 136 static void _hpet_print_config(const char *function, int line)
 137 {
 138         u32 i, timers, l, h;
 139         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
 140         l = hpet_readl(HPET_ID);
 141         h = hpet_readl(HPET_PERIOD);
 142         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 143         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
 144         l = hpet_readl(HPET_CFG);
 145         h = hpet_readl(HPET_STATUS);
 146         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
 147         l = hpet_readl(HPET_COUNTER);
 148         h = hpet_readl(HPET_COUNTER+4);
 149         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
 150
 151         for (i = 0; i < timers; i++) {
 152                 l = hpet_readl(HPET_Tn_CFG(i));
 153                 h = hpet_readl(HPET_Tn_CFG(i)+4);
 154                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
 155                        i, l, h);
 156                 l = hpet_readl(HPET_Tn_CMP(i));
 157                 h = hpet_readl(HPET_Tn_CMP(i)+4);
 158                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
 159                        i, l, h);
 160                 l = hpet_readl(HPET_Tn_ROUTE(i));
 161                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
 162                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
 163                        i, l, h);
 164         }
 165 }
 166
 167 #define hpet_print_config()                                     \
 168 do {                                                            \
 169         if (hpet_verbose)                                       \
 170                 _hpet_print_config(__FUNCTION__, __LINE__);     \
 171 } while (0)
 172
 173 /*
 174  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 175  * timer 0 and timer 1 in case of RTC emulation.
 176  */
 177 #ifdef CONFIG_HPET
 178
 179 static void hpet_reserve_msi_timers(struct hpet_data *hd);
 180
 181 static void hpet_reserve_platform_timers(unsigned int id)
 182 {
 183         struct hpet __iomem *hpet = hpet_virt_address;
 184         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 185         unsigned int nrtimers, i;
 186         struct hpet_data hd;
 187
 188         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 189
 190         memset(&hd, 0, sizeof(hd));
 191         hd.hd_phys_address      = hpet_address;
 192         hd.hd_address           = hpet;
 193         hd.hd_nirqs             = nrtimers;
 194         hpet_reserve_timer(&hd, 0);
 195
 196 #ifdef CONFIG_HPET_EMULATE_RTC
 197         hpet_reserve_timer(&hd, 1);
 198 #endif
 199
 200         /*
 201          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
 202          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
 203          * don't bother configuring *any* comparator interrupts.
 204          */
 205         hd.hd_irq[0] = HPET_LEGACY_8254;
 206         hd.hd_irq[1] = HPET_LEGACY_RTC;
 207
 208         for (i = 2; i < nrtimers; timer++, i++) {
 209                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
 210                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
 211         }
 212
 213         hpet_reserve_msi_timers(&hd);
 214
 215         hpet_alloc(&hd);
 216
 217 }
 218 #else
 219 static void hpet_reserve_platform_timers(unsigned int id) { }
 220 #endif
 221
 222 /*
 223  * Common hpet info
 224  */
 225 static unsigned long hpet_freq;
 226
 227 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 228                           struct clock_event_device *evt);
 229 static int hpet_legacy_next_event(unsigned long delta,
 230                            struct clock_event_device *evt);
 231
 232 /*
 233  * The hpet clock event device
 234  */
 235 static struct clock_event_device hpet_clockevent = {
 236         .name           = "hpet",
 237         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 238         .set_mode       = hpet_legacy_set_mode,
 239         .set_next_event = hpet_legacy_next_event,
 240         .irq            = 0,
 241         .rating         = 50,
 242 };
 243
 244 static void hpet_stop_counter(void)
 245 {
 246         unsigned long cfg = hpet_readl(HPET_CFG);
 247         cfg &= ~HPET_CFG_ENABLE;
 248         hpet_writel(cfg, HPET_CFG);
 249 }
 250
 251 static void hpet_reset_counter(void)
 252 {
 253         hpet_writel(0, HPET_COUNTER);
 254         hpet_writel(0, HPET_COUNTER + 4);
 255 }
 256
 257 static void hpet_start_counter(void)
 258 {
 259         unsigned int cfg = hpet_readl(HPET_CFG);
 260         cfg |= HPET_CFG_ENABLE;
 261         hpet_writel(cfg, HPET_CFG);
 262 }
 263
 264 static void hpet_restart_counter(void)
 265 {
 266         hpet_stop_counter();
 267         hpet_reset_counter();
 268         hpet_start_counter();
 269 }
 270
 271 static void hpet_resume_device(void)
 272 {
 273         force_hpet_resume();
 274 }
 275
 276 static void hpet_resume_counter(struct clocksource *cs)
 277 {
 278         hpet_resume_device();
 279         hpet_restart_counter();
 280 }
 281
 282 static void hpet_enable_legacy_int(void)
 283 {
 284         unsigned int cfg = hpet_readl(HPET_CFG);
 285
 286         cfg |= HPET_CFG_LEGACY;
 287         hpet_writel(cfg, HPET_CFG);
 288         hpet_legacy_int_enabled = 1;
 289 }
 290
 291 static void hpet_legacy_clockevent_register(void)
 292 {
 293         /* Start HPET legacy interrupts */
 294         hpet_enable_legacy_int();
 295
 296         /*
 297          * Start hpet with the boot cpu mask and make it
 298          * global after the IO_APIC has been initialized.
 299          */
 300         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
 301         clockevents_config_and_register(&hpet_clockevent, hpet_freq,
 302                                         HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
 303         global_clock_event = &hpet_clockevent;
 304         printk(KERN_DEBUG "hpet clockevent registered\n");
 305 }
 306
 307 static int hpet_setup_msi_irq(unsigned int irq);
 308
 309 static void hpet_set_mode(enum clock_event_mode mode,
 310                           struct clock_event_device *evt, int timer)
 311 {
 312         unsigned int cfg, cmp, now;
 313         uint64_t delta;
 314
 315         switch (mode) {
 316         case CLOCK_EVT_MODE_PERIODIC:
 317                 hpet_stop_counter();
 318                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
 319                 delta >>= evt->shift;
 320                 now = hpet_readl(HPET_COUNTER);
 321                 cmp = now + (unsigned int) delta;
 322                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 323                 /* Make sure we use edge triggered interrupts */
 324                 cfg &= ~HPET_TN_LEVEL;
 325                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 326                        HPET_TN_SETVAL | HPET_TN_32BIT;
 327                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 328                 hpet_writel(cmp, HPET_Tn_CMP(timer));
 329                 udelay(1);
 330                 /*
 331                  * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
 332                  * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
 333                  * bit is automatically cleared after the first write.
 334                  * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
 335                  * Publication # 24674)
 336                  */
 337                 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
 338                 hpet_start_counter();
 339                 hpet_print_config();
 340                 break;
 341
 342         case CLOCK_EVT_MODE_ONESHOT:
 343                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 344                 cfg &= ~HPET_TN_PERIODIC;
 345                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 346                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 347                 break;
 348
 349         case CLOCK_EVT_MODE_UNUSED:
 350         case CLOCK_EVT_MODE_SHUTDOWN:
 351                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 352                 cfg &= ~HPET_TN_ENABLE;
 353                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 354                 break;
 355
 356         case CLOCK_EVT_MODE_RESUME:
 357                 if (timer == 0) {
 358                         hpet_enable_legacy_int();
 359                 } else {
 360                         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 361                         hpet_setup_msi_irq(hdev->irq);
 362                         disable_irq(hdev->irq);
 363                         irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
 364                         enable_irq(hdev->irq);
 365                 }
 366                 hpet_print_config();
 367                 break;
 368         }
 369 }
 370
 371 static int hpet_next_event(unsigned long delta,
 372                            struct clock_event_device *evt, int timer)
 373 {
 374         u32 cnt;
 375         s32 res;
 376
 377         cnt = hpet_readl(HPET_COUNTER);
 378         cnt += (u32) delta;
 379         hpet_writel(cnt, HPET_Tn_CMP(timer));
 380
 381         /*
 382          * HPETs are a complete disaster. The compare register is
 383          * based on a equal comparison and neither provides a less
 384          * than or equal functionality (which would require to take
 385          * the wraparound into account) nor a simple count down event
 386          * mode. Further the write to the comparator register is
 387          * delayed internally up to two HPET clock cycles in certain
 388          * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
 389          * longer delays. We worked around that by reading back the
 390          * compare register, but that required another workaround for
 391          * ICH9,10 chips where the first readout after write can
 392          * return the old stale value. We already had a minimum
 393          * programming delta of 5us enforced, but a NMI or SMI hitting
 394          * between the counter readout and the comparator write can
 395          * move us behind that point easily. Now instead of reading
 396          * the compare register back several times, we make the ETIME
 397          * decision based on the following: Return ETIME if the
 398          * counter value after the write is less than HPET_MIN_CYCLES
 399          * away from the event or if the counter is already ahead of
 400          * the event. The minimum programming delta for the generic
 401          * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
 402          */
 403         res = (s32)(cnt - hpet_readl(HPET_COUNTER));
 404
 405         return res < HPET_MIN_CYCLES ? -ETIME : 0;
 406 }
 407
 408 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 409                         struct clock_event_device *evt)
 410 {
 411         hpet_set_mode(mode, evt, 0);
 412 }
 413
 414 static int hpet_legacy_next_event(unsigned long delta,
 415                         struct clock_event_device *evt)
 416 {
 417         return hpet_next_event(delta, evt, 0);
 418 }
 419
 420 /*
 421  * HPET MSI Support
 422  */
 423 #ifdef CONFIG_PCI_MSI
 424
 425 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
 426 static struct hpet_dev  *hpet_devs;
 427
 428 void hpet_msi_unmask(struct irq_data *data)
 429 {
 430         struct hpet_dev *hdev = data->handler_data;
 431         unsigned int cfg;
 432
 433         /* unmask it */
 434         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 435         cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
 436         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 437 }
 438
 439 void hpet_msi_mask(struct irq_data *data)
 440 {
 441         struct hpet_dev *hdev = data->handler_data;
 442         unsigned int cfg;
 443
 444         /* mask it */
 445         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 446         cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
 447         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 448 }
 449
 450 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
 451 {
 452         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
 453         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
 454 }
 455
 456 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
 457 {
 458         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
 459         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
 460         msg->address_hi = 0;
 461 }
 462
 463 static void hpet_msi_set_mode(enum clock_event_mode mode,
 464                                 struct clock_event_device *evt)
 465 {
 466         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 467         hpet_set_mode(mode, evt, hdev->num);
 468 }
 469
 470 static int hpet_msi_next_event(unsigned long delta,
 471                                 struct clock_event_device *evt)
 472 {
 473         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 474         return hpet_next_event(delta, evt, hdev->num);
 475 }
 476
 477 static int hpet_setup_msi_irq(unsigned int irq)
 478 {
 479         if (arch_setup_hpet_msi(irq, hpet_blockid)) {
 480                 destroy_irq(irq);
 481                 return -EINVAL;
 482         }
 483         return 0;
 484 }
 485
 486 static int hpet_assign_irq(struct hpet_dev *dev)
 487 {
 488         unsigned int irq;
 489
 490         irq = create_irq_nr(0, -1);
 491         if (!irq)
 492                 return -EINVAL;
 493
 494         irq_set_handler_data(irq, dev);
 495
 496         if (hpet_setup_msi_irq(irq))
 497                 return -EINVAL;
 498
 499         dev->irq = irq;
 500         return 0;
 501 }
 502
 503 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
 504 {
 505         struct hpet_dev *dev = (struct hpet_dev *)data;
 506         struct clock_event_device *hevt = &dev->evt;
 507
 508         if (!hevt->event_handler) {
 509                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
 510                                 dev->num);
 511                 return IRQ_HANDLED;
 512         }
 513
 514         hevt->event_handler(hevt);
 515         return IRQ_HANDLED;
 516 }
 517
 518 static int hpet_setup_irq(struct hpet_dev *dev)
 519 {
 520
 521         if (request_irq(dev->irq, hpet_interrupt_handler,
 522                         IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
 523                         dev->name, dev))
 524                 return -1;
 525
 526         disable_irq(dev->irq);
 527         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
 528         enable_irq(dev->irq);
 529
 530         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
 531                          dev->name, dev->irq);
 532
 533         return 0;
 534 }
 535
 536 /* This should be called in specific @cpu */
 537 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 538 {
 539         struct clock_event_device *evt = &hdev->evt;
 540
 541         WARN_ON(cpu != smp_processor_id());
 542         if (!(hdev->flags & HPET_DEV_VALID))
 543                 return;
 544
 545         if (hpet_setup_msi_irq(hdev->irq))
 546                 return;
 547
 548         hdev->cpu = cpu;
 549         per_cpu(cpu_hpet_dev, cpu) = hdev;
 550         evt->name = hdev->name;
 551         hpet_setup_irq(hdev);
 552         evt->irq = hdev->irq;
 553
 554         evt->rating = 110;
 555         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 556         if (hdev->flags & HPET_DEV_PERI_CAP)
 557                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
 558
 559         evt->set_mode = hpet_msi_set_mode;
 560         evt->set_next_event = hpet_msi_next_event;
 561         evt->cpumask = cpumask_of(hdev->cpu);
 562
 563         clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
 564                                         0x7FFFFFFF);
 565 }
 566
 567 #ifdef CONFIG_HPET
 568 /* Reserve at least one timer for userspace (/dev/hpet) */
 569 #define RESERVE_TIMERS 1
 570 #else
 571 #define RESERVE_TIMERS 0
 572 #endif
 573
 574 static void hpet_msi_capability_lookup(unsigned int start_timer)
 575 {
 576         unsigned int id;
 577         unsigned int num_timers;
 578         unsigned int num_timers_used = 0;
 579         int i;
 580
 581         if (hpet_msi_disable)
 582                 return;
 583
 584         if (boot_cpu_has(X86_FEATURE_ARAT))
 585                 return;
 586         id = hpet_readl(HPET_ID);
 587
 588         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 589         num_timers++; /* Value read out starts from 0 */
 590         hpet_print_config();
 591
 592         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
 593         if (!hpet_devs)
 594                 return;
 595
 596         hpet_num_timers = num_timers;
 597
 598         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
 599                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
 600                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
 601
 602                 /* Only consider HPET timer with MSI support */
 603                 if (!(cfg & HPET_TN_FSB_CAP))
 604                         continue;
 605
 606                 hdev->flags = 0;
 607                 if (cfg & HPET_TN_PERIODIC_CAP)
 608                         hdev->flags |= HPET_DEV_PERI_CAP;
 609                 hdev->num = i;
 610
 611                 sprintf(hdev->name, "hpet%d", i);
 612                 if (hpet_assign_irq(hdev))
 613                         continue;
 614
 615                 hdev->flags |= HPET_DEV_FSB_CAP;
 616                 hdev->flags |= HPET_DEV_VALID;
 617                 num_timers_used++;
 618                 if (num_timers_used == num_possible_cpus())
 619                         break;
 620         }
 621
 622         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
 623                 num_timers, num_timers_used);
 624 }
 625
 626 #ifdef CONFIG_HPET
 627 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 628 {
 629         int i;
 630
 631         if (!hpet_devs)
 632                 return;
 633
 634         for (i = 0; i < hpet_num_timers; i++) {
 635                 struct hpet_dev *hdev = &hpet_devs[i];
 636
 637                 if (!(hdev->flags & HPET_DEV_VALID))
 638                         continue;
 639
 640                 hd->hd_irq[hdev->num] = hdev->irq;
 641                 hpet_reserve_timer(hd, hdev->num);
 642         }
 643 }
 644 #endif
 645
 646 static struct hpet_dev *hpet_get_unused_timer(void)
 647 {
 648         int i;
 649
 650         if (!hpet_devs)
 651                 return NULL;
 652
 653         for (i = 0; i < hpet_num_timers; i++) {
 654                 struct hpet_dev *hdev = &hpet_devs[i];
 655
 656                 if (!(hdev->flags & HPET_DEV_VALID))
 657                         continue;
 658                 if (test_and_set_bit(HPET_DEV_USED_BIT,
 659                         (unsigned long *)&hdev->flags))
 660                         continue;
 661                 return hdev;
 662         }
 663         return NULL;
 664 }
 665
 666 struct hpet_work_struct {
 667         struct delayed_work work;
 668         struct completion complete;
 669 };
 670
 671 static void hpet_work(struct work_struct *w)
 672 {
 673         struct hpet_dev *hdev;
 674         int cpu = smp_processor_id();
 675         struct hpet_work_struct *hpet_work;
 676
 677         hpet_work = container_of(w, struct hpet_work_struct, work.work);
 678
 679         hdev = hpet_get_unused_timer();
 680         if (hdev)
 681                 init_one_hpet_msi_clockevent(hdev, cpu);
 682
 683         complete(&hpet_work->complete);
 684 }
 685
 686 static int hpet_cpuhp_notify(struct notifier_block *n,
 687                 unsigned long action, void *hcpu)
 688 {
 689         unsigned long cpu = (unsigned long)hcpu;
 690         struct hpet_work_struct work;
 691         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
 692
 693         switch (action & 0xf) {
 694         case CPU_ONLINE:
 695                 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
 696                 init_completion(&work.complete);
 697                 /* FIXME: add schedule_work_on() */
 698                 schedule_delayed_work_on(cpu, &work.work, 0);
 699                 wait_for_completion(&work.complete);
 700                 destroy_timer_on_stack(&work.work.timer);
 701                 break;
 702         case CPU_DEAD:
 703                 if (hdev) {
 704                         free_irq(hdev->irq, hdev);
 705                         hdev->flags &= ~HPET_DEV_USED;
 706                         per_cpu(cpu_hpet_dev, cpu) = NULL;
 707                 }
 708                 break;
 709         }
 710         return NOTIFY_OK;
 711 }
 712 #else
 713
 714 static int hpet_setup_msi_irq(unsigned int irq)
 715 {
 716         return 0;
 717 }
 718 static void hpet_msi_capability_lookup(unsigned int start_timer)
 719 {
 720         return;
 721 }
 722
 723 #ifdef CONFIG_HPET
 724 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 725 {
 726         return;
 727 }
 728 #endif
 729
 730 static int hpet_cpuhp_notify(struct notifier_block *n,
 731                 unsigned long action, void *hcpu)
 732 {
 733         return NOTIFY_OK;
 734 }
 735
 736 #endif
 737
 738 /*
 739  * Clock source related code
 740  */
 741 static cycle_t read_hpet(struct clocksource *cs)
 742 {
 743         return (cycle_t)hpet_readl(HPET_COUNTER);
 744 }
 745
 746 static struct clocksource clocksource_hpet = {
 747         .name           = "hpet",
 748         .rating         = 250,
 749         .read           = read_hpet,
 750         .mask           = HPET_MASK,
 751         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 752         .resume         = hpet_resume_counter,
 753 #ifdef CONFIG_X86_64
 754         .archdata       = { .vclock_mode = VCLOCK_HPET },
 755 #endif
 756 };
 757
 758 static int hpet_clocksource_register(void)
 759 {
 760         u64 start, now;
 761         cycle_t t1;
 762
 763         /* Start the counter */
 764         hpet_restart_counter();
 765
 766         /* Verify whether hpet counter works */
 767         t1 = hpet_readl(HPET_COUNTER);
 768         rdtscll(start);
 769
 770         /*
 771          * We don't know the TSC frequency yet, but waiting for
 772          * 200000 TSC cycles is safe:
 773          * 4 GHz == 50us
 774          * 1 GHz == 200us
 775          */
 776         do {
 777                 rep_nop();
 778                 rdtscll(now);
 779         } while ((now - start) < 200000UL);
 780
 781         if (t1 == hpet_readl(HPET_COUNTER)) {
 782                 printk(KERN_WARNING
 783                        "HPET counter not counting. HPET disabled\n");
 784                 return -ENODEV;
 785         }
 786
 787         clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
 788         return 0;
 789 }
 790
 791 /**
 792  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 793  */
 794 int __init hpet_enable(void)
 795 {
 796         unsigned long hpet_period;
 797         unsigned int id;
 798         u64 freq;
 799         int i;
 800
 801         if (!is_hpet_capable())
 802                 return 0;
 803
 804         hpet_set_mapping();
 805
 806         /*
 807          * Read the period and check for a sane value:
 808          */
 809         hpet_period = hpet_readl(HPET_PERIOD);
 810
 811         /*
 812          * AMD SB700 based systems with spread spectrum enabled use a
 813          * SMM based HPET emulation to provide proper frequency
 814          * setting. The SMM code is initialized with the first HPET
 815          * register access and takes some time to complete. During
 816          * this time the config register reads 0xffffffff. We check
 817          * for max. 1000 loops whether the config register reads a non
 818          * 0xffffffff value to make sure that HPET is up and running
 819          * before we go further. A counting loop is safe, as the HPET
 820          * access takes thousands of CPU cycles. On non SB700 based
 821          * machines this check is only done once and has no side
 822          * effects.
 823          */
 824         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
 825                 if (i == 1000) {
 826                         printk(KERN_WARNING
 827                                "HPET config register value = 0xFFFFFFFF. "
 828                                "Disabling HPET\n");
 829                         goto out_nohpet;
 830                 }
 831         }
 832
 833         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 834                 goto out_nohpet;
 835
 836         /*
 837          * The period is a femto seconds value. Convert it to a
 838          * frequency.
 839          */
 840         freq = FSEC_PER_SEC;
 841         do_div(freq, hpet_period);
 842         hpet_freq = freq;
 843
 844         /*
 845          * Read the HPET ID register to retrieve the IRQ routing
 846          * information and the number of channels
 847          */
 848         id = hpet_readl(HPET_ID);
 849         hpet_print_config();
 850
 851 #ifdef CONFIG_HPET_EMULATE_RTC
 852         /*
 853          * The legacy routing mode needs at least two channels, tick timer
 854          * and the rtc emulation channel.
 855          */
 856         if (!(id & HPET_ID_NUMBER))
 857                 goto out_nohpet;
 858 #endif
 859
 860         if (hpet_clocksource_register())
 861                 goto out_nohpet;
 862
 863         if (id & HPET_ID_LEGSUP) {
 864                 hpet_legacy_clockevent_register();
 865                 return 1;
 866         }
 867         return 0;
 868
 869 out_nohpet:
 870         hpet_clear_mapping();
 871         hpet_address = 0;
 872         return 0;
 873 }
 874
 875 /*
 876  * Needs to be late, as the reserve_timer code calls kalloc !
 877  *
 878  * Not a problem on i386 as hpet_enable is called from late_time_init,
 879  * but on x86_64 it is necessary !
 880  */
 881 static __init int hpet_late_init(void)
 882 {
 883         int cpu;
 884
 885         if (boot_hpet_disable)
 886                 return -ENODEV;
 887
 888         if (!hpet_address) {
 889                 if (!force_hpet_address)
 890                         return -ENODEV;
 891
 892                 hpet_address = force_hpet_address;
 893                 hpet_enable();
 894         }
 895
 896         if (!hpet_virt_address)
 897                 return -ENODEV;
 898
 899         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
 900                 hpet_msi_capability_lookup(2);
 901         else
 902                 hpet_msi_capability_lookup(0);
 903
 904         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 905         hpet_print_config();
 906
 907         if (hpet_msi_disable)
 908                 return 0;
 909
 910         if (boot_cpu_has(X86_FEATURE_ARAT))
 911                 return 0;
 912
 913         for_each_online_cpu(cpu) {
 914                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
 915         }
 916
 917         /* This notifier should be called after workqueue is ready */
 918         hotcpu_notifier(hpet_cpuhp_notify, -20);
 919
 920         return 0;
 921 }
 922 fs_initcall(hpet_late_init);
 923
 924 void hpet_disable(void)
 925 {
 926         if (is_hpet_capable() && hpet_virt_address) {
 927                 unsigned int cfg = hpet_readl(HPET_CFG);
 928
 929                 if (hpet_legacy_int_enabled) {
 930                         cfg &= ~HPET_CFG_LEGACY;
 931                         hpet_legacy_int_enabled = 0;
 932                 }
 933                 cfg &= ~HPET_CFG_ENABLE;
 934                 hpet_writel(cfg, HPET_CFG);
 935         }
 936 }
 937
 938 #ifdef CONFIG_HPET_EMULATE_RTC
 939
 940 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 941  * is enabled, we support RTC interrupt functionality in software.
 942  * RTC has 3 kinds of interrupts:
 943  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 944  *    is updated
 945  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 946  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 947  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 948  * (1) and (2) above are implemented using polling at a frequency of
 949  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 950  * overhead. (DEFAULT_RTC_INT_FREQ)
 951  * For (3), we use interrupts at 64Hz or user specified periodic
 952  * frequency, whichever is higher.
 953  */
 954 #include <linux/mc146818rtc.h>
 955 #include <linux/rtc.h>
 956 #include <asm/rtc.h>
 957
 958 #define DEFAULT_RTC_INT_FREQ    64
 959 #define DEFAULT_RTC_SHIFT       6
 960 #define RTC_NUM_INTS            1
 961
 962 static unsigned long hpet_rtc_flags;
 963 static int hpet_prev_update_sec;
 964 static struct rtc_time hpet_alarm_time;
 965 static unsigned long hpet_pie_count;
 966 static u32 hpet_t1_cmp;
 967 static u32 hpet_default_delta;
 968 static u32 hpet_pie_delta;
 969 static unsigned long hpet_pie_limit;
 970
 971 static rtc_irq_handler irq_handler;
 972
 973 /*
 974  * Check that the hpet counter c1 is ahead of the c2
 975  */
 976 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
 977 {
 978         return (s32)(c2 - c1) < 0;
 979 }
 980
 981 /*
 982  * Registers a IRQ handler.
 983  */
 984 int hpet_register_irq_handler(rtc_irq_handler handler)
 985 {
 986         if (!is_hpet_enabled())
 987                 return -ENODEV;
 988         if (irq_handler)
 989                 return -EBUSY;
 990
 991         irq_handler = handler;
 992
 993         return 0;
 994 }
 995 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
 996
 997 /*
 998  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
 999  * and does cleanup.
1000  */
1001 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1002 {
1003         if (!is_hpet_enabled())
1004                 return;
1005
1006         irq_handler = NULL;
1007         hpet_rtc_flags = 0;
1008 }
1009 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1010
1011 /*
1012  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1013  * is not supported by all HPET implementations for timer 1.
1014  *
1015  * hpet_rtc_timer_init() is called when the rtc is initialized.
1016  */
1017 int hpet_rtc_timer_init(void)
1018 {
1019         unsigned int cfg, cnt, delta;
1020         unsigned long flags;
1021
1022         if (!is_hpet_enabled())
1023                 return 0;
1024
1025         if (!hpet_default_delta) {
1026                 uint64_t clc;
1027
1028                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1029                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1030                 hpet_default_delta = clc;
1031         }
1032
1033         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1034                 delta = hpet_default_delta;
1035         else
1036                 delta = hpet_pie_delta;
1037
1038         local_irq_save(flags);
1039
1040         cnt = delta + hpet_readl(HPET_COUNTER);
1041         hpet_writel(cnt, HPET_T1_CMP);
1042         hpet_t1_cmp = cnt;
1043
1044         cfg = hpet_readl(HPET_T1_CFG);
1045         cfg &= ~HPET_TN_PERIODIC;
1046         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1047         hpet_writel(cfg, HPET_T1_CFG);
1048
1049         local_irq_restore(flags);
1050
1051         return 1;
1052 }
1053 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1054
1055 static void hpet_disable_rtc_channel(void)
1056 {
1057         unsigned long cfg;
1058         cfg = hpet_readl(HPET_T1_CFG);
1059         cfg &= ~HPET_TN_ENABLE;
1060         hpet_writel(cfg, HPET_T1_CFG);
1061 }
1062
1063 /*
1064  * The functions below are called from rtc driver.
1065  * Return 0 if HPET is not being used.
1066  * Otherwise do the necessary changes and return 1.
1067  */
1068 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1069 {
1070         if (!is_hpet_enabled())
1071                 return 0;
1072
1073         hpet_rtc_flags &= ~bit_mask;
1074         if (unlikely(!hpet_rtc_flags))
1075                 hpet_disable_rtc_channel();
1076
1077         return 1;
1078 }
1079 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1080
1081 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1082 {
1083         unsigned long oldbits = hpet_rtc_flags;
1084
1085         if (!is_hpet_enabled())
1086                 return 0;
1087
1088         hpet_rtc_flags |= bit_mask;
1089
1090         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1091                 hpet_prev_update_sec = -1;
1092
1093         if (!oldbits)
1094                 hpet_rtc_timer_init();
1095
1096         return 1;
1097 }
1098 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1099
1100 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1101                         unsigned char sec)
1102 {
1103         if (!is_hpet_enabled())
1104                 return 0;
1105
1106         hpet_alarm_time.tm_hour = hrs;
1107         hpet_alarm_time.tm_min = min;
1108         hpet_alarm_time.tm_sec = sec;
1109
1110         return 1;
1111 }
1112 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1113
1114 int hpet_set_periodic_freq(unsigned long freq)
1115 {
1116         uint64_t clc;
1117
1118         if (!is_hpet_enabled())
1119                 return 0;
1120
1121         if (freq <= DEFAULT_RTC_INT_FREQ)
1122                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1123         else {
1124                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1125                 do_div(clc, freq);
1126                 clc >>= hpet_clockevent.shift;
1127                 hpet_pie_delta = clc;
1128                 hpet_pie_limit = 0;
1129         }
1130         return 1;
1131 }
1132 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1133
1134 int hpet_rtc_dropped_irq(void)
1135 {
1136         return is_hpet_enabled();
1137 }
1138 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1139
1140 static void hpet_rtc_timer_reinit(void)
1141 {
1142         unsigned int delta;
1143         int lost_ints = -1;
1144
1145         if (unlikely(!hpet_rtc_flags))
1146                 hpet_disable_rtc_channel();
1147
1148         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1149                 delta = hpet_default_delta;
1150         else
1151                 delta = hpet_pie_delta;
1152
1153         /*
1154          * Increment the comparator value until we are ahead of the
1155          * current count.
1156          */
1157         do {
1158                 hpet_t1_cmp += delta;
1159                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1160                 lost_ints++;
1161         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1162
1163         if (lost_ints) {
1164                 if (hpet_rtc_flags & RTC_PIE)
1165                         hpet_pie_count += lost_ints;
1166                 if (printk_ratelimit())
1167                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1168                                 lost_ints);
1169         }
1170 }
1171
1172 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1173 {
1174         struct rtc_time curr_time;
1175         unsigned long rtc_int_flag = 0;
1176
1177         hpet_rtc_timer_reinit();
1178         memset(&curr_time, 0, sizeof(struct rtc_time));
1179
1180         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1181                 get_rtc_time(&curr_time);
1182
1183         if (hpet_rtc_flags & RTC_UIE &&
1184             curr_time.tm_sec != hpet_prev_update_sec) {
1185                 if (hpet_prev_update_sec >= 0)
1186                         rtc_int_flag = RTC_UF;
1187                 hpet_prev_update_sec = curr_time.tm_sec;
1188         }
1189
1190         if (hpet_rtc_flags & RTC_PIE &&
1191             ++hpet_pie_count >= hpet_pie_limit) {
1192                 rtc_int_flag |= RTC_PF;
1193                 hpet_pie_count = 0;
1194         }
1195
1196         if (hpet_rtc_flags & RTC_AIE &&
1197             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1198             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1199             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1200                         rtc_int_flag |= RTC_AF;
1201
1202         if (rtc_int_flag) {
1203                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1204                 if (irq_handler)
1205                         irq_handler(rtc_int_flag, dev_id);
1206         }
1207         return IRQ_HANDLED;
1208 }
1209 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1210 #endif