arch/x86/kernel/early-quirks.c

   1 /* Various workarounds for chipset bugs.
   2    This code runs very early and can't use the regular PCI subsystem
   3    The entries are keyed to PCI bridges which usually identify chipsets
   4    uniquely.
   5    This is only for whole classes of chipsets with specific problems which
   6    need early invasive action (e.g. before the timers are initialized).
   7    Most PCI device specific workarounds can be done later and should be
   8    in standard PCI quirks
   9    Mainboard specific bugs should be handled by DMI entries.
  10    CPU specific bugs in setup.c */
  11
  12 #include <linux/pci.h>
  13 #include <linux/acpi.h>
  14 #include <linux/pci_ids.h>
  15 #include <asm/pci-direct.h>
  16 #include <asm/dma.h>
  17 #include <asm/io_apic.h>
  18 #include <asm/apic.h>
  19
  20 #ifdef CONFIG_GART_IOMMU
  21 #include <asm/gart.h>
  22 #endif
  23
  24 static void __init fix_hypertransport_config(int num, int slot, int func)
  25 {
  26         u32 htcfg;
  27         /*
  28          * we found a hypertransport bus
  29          * make sure that we are broadcasting
  30          * interrupts to all cpus on the ht bus
  31          * if we're using extended apic ids
  32          */
  33         htcfg = read_pci_config(num, slot, func, 0x68);
  34         if (htcfg & (1 << 18)) {
  35                 printk(KERN_INFO "Detected use of extended apic ids on hypertransport bus\n");
  36                 if ((htcfg & (1 << 17)) == 0) {
  37                         printk(KERN_INFO "Enabling hypertransport extended apic interrupt broadcast\n");
  38                         printk(KERN_INFO "Note this is a bios bug, please contact your hw vendor\n");
  39                         htcfg |= (1 << 17);
  40                         write_pci_config(num, slot, func, 0x68, htcfg);
  41                 }
  42         }
  43
  44
  45 }
  46
  47 static void __init via_bugs(int  num, int slot, int func)
  48 {
  49 #ifdef CONFIG_GART_IOMMU
  50         if ((end_pfn > MAX_DMA32_PFN ||  force_iommu) &&
  51             !gart_iommu_aperture_allowed) {
  52                 printk(KERN_INFO
  53                        "Looks like a VIA chipset. Disabling IOMMU."
  54                        " Override with iommu=allowed\n");
  55                 gart_iommu_aperture_disabled = 1;
  56         }
  57 #endif
  58 }
  59
  60 #ifdef CONFIG_ACPI
  61 #ifdef CONFIG_X86_IO_APIC
  62
  63 static int __init nvidia_hpet_check(struct acpi_table_header *header)
  64 {
  65         return 0;
  66 }
  67 #endif /* CONFIG_X86_IO_APIC */
  68 #endif /* CONFIG_ACPI */
  69
  70 static void __init nvidia_bugs(int num, int slot, int func)
  71 {
  72 #ifdef CONFIG_ACPI
  73 #ifdef CONFIG_X86_IO_APIC
  74         /*
  75          * All timer overrides on Nvidia are
  76          * wrong unless HPET is enabled.
  77          * Unfortunately that's not true on many Asus boards.
  78          * We don't know yet how to detect this automatically, but
  79          * at least allow a command line override.
  80          */
  81         if (acpi_use_timer_override)
  82                 return;
  83
  84         if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
  85                 acpi_skip_timer_override = 1;
  86                 printk(KERN_INFO "Nvidia board "
  87                        "detected. Ignoring ACPI "
  88                        "timer override.\n");
  89                 printk(KERN_INFO "If you got timer trouble "
  90                         "try acpi_use_timer_override\n");
  91         }
  92 #endif
  93 #endif
  94         /* RED-PEN skip them on mptables too? */
  95
  96 }
  97
  98 static void __init ati_bugs(int num, int slot, int func)
  99 {
 100 #ifdef CONFIG_X86_IO_APIC
 101         if (timer_over_8254 == 1) {
 102                 timer_over_8254 = 0;
 103                 printk(KERN_INFO
 104                 "ATI board detected. Disabling timer routing over 8254.\n");
 105         }
 106 #endif
 107 }
 108
 109 #define QFLAG_APPLY_ONCE        0x1
 110 #define QFLAG_APPLIED           0x2
 111 #define QFLAG_DONE              (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
 112 struct chipset {
 113         u32 vendor;
 114         u32 device;
 115         u32 class;
 116         u32 class_mask;
 117         u32 flags;
 118         void (*f)(int num, int slot, int func);
 119 };
 120
 121 static struct chipset early_qrk[] __initdata = {
 122         { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
 123           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
 124         { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
 125           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
 126         { PCI_VENDOR_ID_ATI, PCI_ANY_ID,
 127           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, ati_bugs },
 128         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
 129           PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
 130         {}
 131 };
 132
 133 void __init early_quirks(void)
 134 {
 135         int num, slot, func;
 136
 137         if (!early_pci_allowed())
 138                 return;
 139
 140         /* Poor man's PCI discovery */
 141         for (num = 0; num < 32; num++) {
 142                 for (slot = 0; slot < 32; slot++) {
 143                         for (func = 0; func < 8; func++) {
 144                                 u16 class;
 145                                 u16 vendor;
 146                                 u16 device;
 147                                 u8 type;
 148                                 int i;
 149
 150                                 class = read_pci_config_16(num,slot,func,
 151                                                         PCI_CLASS_REVISION);
 152                                 if (class == 0xffff)
 153                                         break;
 154
 155                                 vendor = read_pci_config_16(num, slot, func,
 156                                                          PCI_VENDOR_ID);
 157
 158                                 device = read_pci_config_16(num, slot, func,
 159                                                         PCI_DEVICE_ID);
 160
 161                                 for(i=0;early_qrk[i].f != NULL;i++) {
 162                                         if (((early_qrk[i].vendor == PCI_ANY_ID) ||
 163                                             (early_qrk[i].vendor == vendor)) &&
 164                                            ((early_qrk[i].device == PCI_ANY_ID) ||
 165                                             (early_qrk[i].device == device)) &&
 166                                            (!((early_qrk[i].class ^ class) &
 167                                              early_qrk[i].class_mask))) {
 168                                                 if ((early_qrk[i].flags & QFLAG_DONE) != QFLAG_DONE)
 169                                                         early_qrk[i].f(num, slot, func);
 170                                                 early_qrk[i].flags |= QFLAG_APPLIED;
 171
 172                                         }
 173                                 }
 174
 175                                 type = read_pci_config_byte(num, slot, func,
 176                                                             PCI_HEADER_TYPE);
 177                                 if (!(type & 0x80))
 178                                         break;
 179                         }
 180                 }
 181         }
 182 }