arch/x86/kernel/cpu/perfctr-watchdog.c

   1 /* local apic based NMI watchdog for various CPUs.
   2    This file also handles reservation of performance counters for coordination
   3    with other users (like oprofile).
   4
   5    Note that these events normally don't tick when the CPU idles. This means
   6    the frequency varies with CPU load.
   7
   8    Original code for K7/P6 written by Keith Owens */
   9
  10 #include <linux/percpu.h>
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/bitops.h>
  14 #include <linux/smp.h>
  15 #include <linux/nmi.h>
  16 #include <asm/apic.h>
  17 #include <asm/intel_arch_perfmon.h>
  18
  19 struct nmi_watchdog_ctlblk {
  20         unsigned int cccr_msr;
  21         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
  22         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
  23 };
  24
  25 /* Interface defining a CPU specific perfctr watchdog */
  26 struct wd_ops {
  27         int (*reserve)(void);
  28         void (*unreserve)(void);
  29         int (*setup)(unsigned nmi_hz);
  30         void (*rearm)(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz);
  31         void (*stop)(void);
  32         unsigned perfctr;
  33         unsigned evntsel;
  34         u64 checkbit;
  35 };
  36
  37 static const struct wd_ops *wd_ops;
  38
  39 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  40  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
  41  */
  42 #define NMI_MAX_COUNTER_BITS 66
  43
  44 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  45  * evtsel_nmi_owner tracks the ownership of the event selection
  46  * - different performance counters/ event selection may be reserved for
  47  *   different subsystems this reservation system just tries to coordinate
  48  *   things a little
  49  */
  50 static DECLARE_BITMAP(perfctr_nmi_owner, NMI_MAX_COUNTER_BITS);
  51 static DECLARE_BITMAP(evntsel_nmi_owner, NMI_MAX_COUNTER_BITS);
  52
  53 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  54
  55 /* converts an msr to an appropriate reservation bit */
  56 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  57 {
  58         /* returns the bit offset of the performance counter register */
  59         switch (boot_cpu_data.x86_vendor) {
  60         case X86_VENDOR_AMD:
  61                 return (msr - MSR_K7_PERFCTR0);
  62         case X86_VENDOR_INTEL:
  63                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
  64                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
  65
  66                 switch (boot_cpu_data.x86) {
  67                 case 6:
  68                         return (msr - MSR_P6_PERFCTR0);
  69                 case 15:
  70                         return (msr - MSR_P4_BPU_PERFCTR0);
  71                 }
  72         }
  73         return 0;
  74 }
  75
  76 /* converts an msr to an appropriate reservation bit */
  77 /* returns the bit offset of the event selection register */
  78 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
  79 {
  80         /* returns the bit offset of the event selection register */
  81         switch (boot_cpu_data.x86_vendor) {
  82         case X86_VENDOR_AMD:
  83                 return (msr - MSR_K7_EVNTSEL0);
  84         case X86_VENDOR_INTEL:
  85                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
  86                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
  87
  88                 switch (boot_cpu_data.x86) {
  89                 case 6:
  90                         return (msr - MSR_P6_EVNTSEL0);
  91                 case 15:
  92                         return (msr - MSR_P4_BSU_ESCR0);
  93                 }
  94         }
  95         return 0;
  96
  97 }
  98
  99 /* checks for a bit availability (hack for oprofile) */
 100 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 101 {
 102         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 103
 104         return (!test_bit(counter, perfctr_nmi_owner));
 105 }
 106
 107 /* checks the an msr for availability */
 108 int avail_to_resrv_perfctr_nmi(unsigned int msr)
 109 {
 110         unsigned int counter;
 111
 112         counter = nmi_perfctr_msr_to_bit(msr);
 113         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 114
 115         return (!test_bit(counter, perfctr_nmi_owner));
 116 }
 117
 118 int reserve_perfctr_nmi(unsigned int msr)
 119 {
 120         unsigned int counter;
 121
 122         counter = nmi_perfctr_msr_to_bit(msr);
 123         /* register not managed by the allocator? */
 124         if (counter > NMI_MAX_COUNTER_BITS)
 125                 return 1;
 126
 127         if (!test_and_set_bit(counter, perfctr_nmi_owner))
 128                 return 1;
 129         return 0;
 130 }
 131
 132 void release_perfctr_nmi(unsigned int msr)
 133 {
 134         unsigned int counter;
 135
 136         counter = nmi_perfctr_msr_to_bit(msr);
 137         /* register not managed by the allocator? */
 138         if (counter > NMI_MAX_COUNTER_BITS)
 139                 return;
 140
 141         clear_bit(counter, perfctr_nmi_owner);
 142 }
 143
 144 int reserve_evntsel_nmi(unsigned int msr)
 145 {
 146         unsigned int counter;
 147
 148         counter = nmi_evntsel_msr_to_bit(msr);
 149         /* register not managed by the allocator? */
 150         if (counter > NMI_MAX_COUNTER_BITS)
 151                 return 1;
 152
 153         if (!test_and_set_bit(counter, evntsel_nmi_owner))
 154                 return 1;
 155         return 0;
 156 }
 157
 158 void release_evntsel_nmi(unsigned int msr)
 159 {
 160         unsigned int counter;
 161
 162         counter = nmi_evntsel_msr_to_bit(msr);
 163         /* register not managed by the allocator? */
 164         if (counter > NMI_MAX_COUNTER_BITS)
 165                 return;
 166
 167         clear_bit(counter, evntsel_nmi_owner);
 168 }
 169
 170 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
 171 EXPORT_SYMBOL(reserve_perfctr_nmi);
 172 EXPORT_SYMBOL(release_perfctr_nmi);
 173 EXPORT_SYMBOL(reserve_evntsel_nmi);
 174 EXPORT_SYMBOL(release_evntsel_nmi);
 175
 176 void disable_lapic_nmi_watchdog(void)
 177 {
 178         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 179
 180         if (atomic_read(&nmi_active) <= 0)
 181                 return;
 182
 183         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 184
 185         if (wd_ops)
 186                 wd_ops->unreserve();
 187
 188         BUG_ON(atomic_read(&nmi_active) != 0);
 189 }
 190
 191 void enable_lapic_nmi_watchdog(void)
 192 {
 193         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 194
 195         /* are we already enabled */
 196         if (atomic_read(&nmi_active) != 0)
 197                 return;
 198
 199         /* are we lapic aware */
 200         if (!wd_ops)
 201                 return;
 202         if (!wd_ops->reserve()) {
 203                 printk(KERN_ERR "NMI watchdog: cannot reserve perfctrs\n");
 204                 return;
 205         }
 206
 207         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 208         touch_nmi_watchdog();
 209 }
 210
 211 /*
 212  * Activate the NMI watchdog via the local APIC.
 213  */
 214
 215 static unsigned int adjust_for_32bit_ctr(unsigned int hz)
 216 {
 217         u64 counter_val;
 218         unsigned int retval = hz;
 219
 220         /*
 221          * On Intel CPUs with P6/ARCH_PERFMON only 32 bits in the counter
 222          * are writable, with higher bits sign extending from bit 31.
 223          * So, we can only program the counter with 31 bit values and
 224          * 32nd bit should be 1, for 33.. to be 1.
 225          * Find the appropriate nmi_hz
 226          */
 227         counter_val = (u64)cpu_khz * 1000;
 228         do_div(counter_val, retval);
 229         if (counter_val > 0x7fffffffULL) {
 230                 u64 count = (u64)cpu_khz * 1000;
 231                 do_div(count, 0x7fffffffUL);
 232                 retval = count + 1;
 233         }
 234         return retval;
 235 }
 236
 237 static void
 238 write_watchdog_counter(unsigned int perfctr_msr, const char *descr, unsigned nmi_hz)
 239 {
 240         u64 count = (u64)cpu_khz * 1000;
 241
 242         do_div(count, nmi_hz);
 243         if(descr)
 244                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 245         wrmsrl(perfctr_msr, 0 - count);
 246 }
 247
 248 static void write_watchdog_counter32(unsigned int perfctr_msr,
 249                 const char *descr, unsigned nmi_hz)
 250 {
 251         u64 count = (u64)cpu_khz * 1000;
 252
 253         do_div(count, nmi_hz);
 254         if(descr)
 255                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 256         wrmsr(perfctr_msr, (u32)(-count), 0);
 257 }
 258
 259 /* AMD K7/K8/Family10h/Family11h support. AMD keeps this interface
 260    nicely stable so there is not much variety */
 261
 262 #define K7_EVNTSEL_ENABLE       (1 << 22)
 263 #define K7_EVNTSEL_INT          (1 << 20)
 264 #define K7_EVNTSEL_OS           (1 << 17)
 265 #define K7_EVNTSEL_USR          (1 << 16)
 266 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
 267 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 268
 269 static int setup_k7_watchdog(unsigned nmi_hz)
 270 {
 271         unsigned int perfctr_msr, evntsel_msr;
 272         unsigned int evntsel;
 273         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 274
 275         perfctr_msr = wd_ops->perfctr;
 276         evntsel_msr = wd_ops->evntsel;
 277
 278         wrmsrl(perfctr_msr, 0UL);
 279
 280         evntsel = K7_EVNTSEL_INT
 281                 | K7_EVNTSEL_OS
 282                 | K7_EVNTSEL_USR
 283                 | K7_NMI_EVENT;
 284
 285         /* setup the timer */
 286         wrmsr(evntsel_msr, evntsel, 0);
 287         write_watchdog_counter(perfctr_msr, "K7_PERFCTR0",nmi_hz);
 288         apic_write(APIC_LVTPC, APIC_DM_NMI);
 289         evntsel |= K7_EVNTSEL_ENABLE;
 290         wrmsr(evntsel_msr, evntsel, 0);
 291
 292         wd->perfctr_msr = perfctr_msr;
 293         wd->evntsel_msr = evntsel_msr;
 294         wd->cccr_msr = 0;  //unused
 295         return 1;
 296 }
 297
 298 static void single_msr_stop_watchdog(void)
 299 {
 300         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 301
 302         wrmsr(wd->evntsel_msr, 0, 0);
 303 }
 304
 305 static int single_msr_reserve(void)
 306 {
 307         if (!reserve_perfctr_nmi(wd_ops->perfctr))
 308                 return 0;
 309
 310         if (!reserve_evntsel_nmi(wd_ops->evntsel)) {
 311                 release_perfctr_nmi(wd_ops->perfctr);
 312                 return 0;
 313         }
 314         return 1;
 315 }
 316
 317 static void single_msr_unreserve(void)
 318 {
 319         release_evntsel_nmi(wd_ops->evntsel);
 320         release_perfctr_nmi(wd_ops->perfctr);
 321 }
 322
 323 static void single_msr_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
 324 {
 325         /* start the cycle over again */
 326         write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz);
 327 }
 328
 329 static const struct wd_ops k7_wd_ops = {
 330         .reserve = single_msr_reserve,
 331         .unreserve = single_msr_unreserve,
 332         .setup = setup_k7_watchdog,
 333         .rearm = single_msr_rearm,
 334         .stop = single_msr_stop_watchdog,
 335         .perfctr = MSR_K7_PERFCTR0,
 336         .evntsel = MSR_K7_EVNTSEL0,
 337         .checkbit = 1ULL<<47,
 338 };
 339
 340 /* Intel Model 6 (PPro+,P2,P3,P-M,Core1) */
 341
 342 #define P6_EVNTSEL0_ENABLE      (1 << 22)
 343 #define P6_EVNTSEL_INT          (1 << 20)
 344 #define P6_EVNTSEL_OS           (1 << 17)
 345 #define P6_EVNTSEL_USR          (1 << 16)
 346 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED  0x79
 347 #define P6_NMI_EVENT            P6_EVENT_CPU_CLOCKS_NOT_HALTED
 348
 349 static int setup_p6_watchdog(unsigned nmi_hz)
 350 {
 351         unsigned int perfctr_msr, evntsel_msr;
 352         unsigned int evntsel;
 353         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 354
 355         perfctr_msr = wd_ops->perfctr;
 356         evntsel_msr = wd_ops->evntsel;
 357
 358         /* KVM doesn't implement this MSR */
 359         if (wrmsr_safe(perfctr_msr, 0, 0) < 0)
 360                 return 0;
 361
 362         evntsel = P6_EVNTSEL_INT
 363                 | P6_EVNTSEL_OS
 364                 | P6_EVNTSEL_USR
 365                 | P6_NMI_EVENT;
 366
 367         /* setup the timer */
 368         wrmsr(evntsel_msr, evntsel, 0);
 369         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 370         write_watchdog_counter32(perfctr_msr, "P6_PERFCTR0",nmi_hz);
 371         apic_write(APIC_LVTPC, APIC_DM_NMI);
 372         evntsel |= P6_EVNTSEL0_ENABLE;
 373         wrmsr(evntsel_msr, evntsel, 0);
 374
 375         wd->perfctr_msr = perfctr_msr;
 376         wd->evntsel_msr = evntsel_msr;
 377         wd->cccr_msr = 0;  //unused
 378         return 1;
 379 }
 380
 381 static void p6_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
 382 {
 383         /* P6 based Pentium M need to re-unmask
 384          * the apic vector but it doesn't hurt
 385          * other P6 variant.
 386          * ArchPerfom/Core Duo also needs this */
 387         apic_write(APIC_LVTPC, APIC_DM_NMI);
 388         /* P6/ARCH_PERFMON has 32 bit counter write */
 389         write_watchdog_counter32(wd->perfctr_msr, NULL,nmi_hz);
 390 }
 391
 392 static const struct wd_ops p6_wd_ops = {
 393         .reserve = single_msr_reserve,
 394         .unreserve = single_msr_unreserve,
 395         .setup = setup_p6_watchdog,
 396         .rearm = p6_rearm,
 397         .stop = single_msr_stop_watchdog,
 398         .perfctr = MSR_P6_PERFCTR0,
 399         .evntsel = MSR_P6_EVNTSEL0,
 400         .checkbit = 1ULL<<39,
 401 };
 402
 403 /* Intel P4 performance counters. By far the most complicated of all. */
 404
 405 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
 406 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
 407 #define P4_ESCR_OS              (1<<3)
 408 #define P4_ESCR_USR             (1<<2)
 409 #define P4_CCCR_OVF_PMI0        (1<<26)
 410 #define P4_CCCR_OVF_PMI1        (1<<27)
 411 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
 412 #define P4_CCCR_COMPLEMENT      (1<<19)
 413 #define P4_CCCR_COMPARE         (1<<18)
 414 #define P4_CCCR_REQUIRED        (3<<16)
 415 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
 416 #define P4_CCCR_ENABLE          (1<<12)
 417 #define P4_CCCR_OVF             (1<<31)
 418
 419 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
 420    CRU_ESCR0 (with any non-null event selector) through a complemented
 421    max threshold. [IA32-Vol3, Section 14.9.9] */
 422
 423 static int setup_p4_watchdog(unsigned nmi_hz)
 424 {
 425         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
 426         unsigned int evntsel, cccr_val;
 427         unsigned int misc_enable, dummy;
 428         unsigned int ht_num;
 429         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 430
 431         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
 432         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 433                 return 0;
 434
 435 #ifdef CONFIG_SMP
 436         /* detect which hyperthread we are on */
 437         if (smp_num_siblings == 2) {
 438                 unsigned int ebx, apicid;
 439
 440                 ebx = cpuid_ebx(1);
 441                 apicid = (ebx >> 24) & 0xff;
 442                 ht_num = apicid & 1;
 443         } else
 444 #endif
 445                 ht_num = 0;
 446
 447         /* performance counters are shared resources
 448          * assign each hyperthread its own set
 449          * (re-use the ESCR0 register, seems safe
 450          * and keeps the cccr_val the same)
 451          */
 452         if (!ht_num) {
 453                 /* logical cpu 0 */
 454                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
 455                 evntsel_msr = MSR_P4_CRU_ESCR0;
 456                 cccr_msr = MSR_P4_IQ_CCCR0;
 457                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
 458         } else {
 459                 /* logical cpu 1 */
 460                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
 461                 evntsel_msr = MSR_P4_CRU_ESCR0;
 462                 cccr_msr = MSR_P4_IQ_CCCR1;
 463                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
 464         }
 465
 466         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
 467                 | P4_ESCR_OS
 468                 | P4_ESCR_USR;
 469
 470         cccr_val |= P4_CCCR_THRESHOLD(15)
 471                  | P4_CCCR_COMPLEMENT
 472                  | P4_CCCR_COMPARE
 473                  | P4_CCCR_REQUIRED;
 474
 475         wrmsr(evntsel_msr, evntsel, 0);
 476         wrmsr(cccr_msr, cccr_val, 0);
 477         write_watchdog_counter(perfctr_msr, "P4_IQ_COUNTER0", nmi_hz);
 478         apic_write(APIC_LVTPC, APIC_DM_NMI);
 479         cccr_val |= P4_CCCR_ENABLE;
 480         wrmsr(cccr_msr, cccr_val, 0);
 481         wd->perfctr_msr = perfctr_msr;
 482         wd->evntsel_msr = evntsel_msr;
 483         wd->cccr_msr = cccr_msr;
 484         return 1;
 485 }
 486
 487 static void stop_p4_watchdog(void)
 488 {
 489         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 490         wrmsr(wd->cccr_msr, 0, 0);
 491         wrmsr(wd->evntsel_msr, 0, 0);
 492 }
 493
 494 static int p4_reserve(void)
 495 {
 496         if (!reserve_perfctr_nmi(MSR_P4_IQ_PERFCTR0))
 497                 return 0;
 498 #ifdef CONFIG_SMP
 499         if (smp_num_siblings > 1 && !reserve_perfctr_nmi(MSR_P4_IQ_PERFCTR1))
 500                 goto fail1;
 501 #endif
 502         if (!reserve_evntsel_nmi(MSR_P4_CRU_ESCR0))
 503                 goto fail2;
 504         /* RED-PEN why is ESCR1 not reserved here? */
 505         return 1;
 506  fail2:
 507 #ifdef CONFIG_SMP
 508         if (smp_num_siblings > 1)
 509                 release_perfctr_nmi(MSR_P4_IQ_PERFCTR1);
 510  fail1:
 511 #endif
 512         release_perfctr_nmi(MSR_P4_IQ_PERFCTR0);
 513         return 0;
 514 }
 515
 516 static void p4_unreserve(void)
 517 {
 518 #ifdef CONFIG_SMP
 519         if (smp_num_siblings > 1)
 520                 release_perfctr_nmi(MSR_P4_IQ_PERFCTR1);
 521 #endif
 522         release_evntsel_nmi(MSR_P4_CRU_ESCR0);
 523         release_perfctr_nmi(MSR_P4_IQ_PERFCTR0);
 524 }
 525
 526 static void p4_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
 527 {
 528         unsigned dummy;
 529         /*
 530          * P4 quirks:
 531          * - An overflown perfctr will assert its interrupt
 532          *   until the OVF flag in its CCCR is cleared.
 533          * - LVTPC is masked on interrupt and must be
 534          *   unmasked by the LVTPC handler.
 535          */
 536         rdmsrl(wd->cccr_msr, dummy);
 537         dummy &= ~P4_CCCR_OVF;
 538         wrmsrl(wd->cccr_msr, dummy);
 539         apic_write(APIC_LVTPC, APIC_DM_NMI);
 540         /* start the cycle over again */
 541         write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz);
 542 }
 543
 544 static const struct wd_ops p4_wd_ops = {
 545         .reserve = p4_reserve,
 546         .unreserve = p4_unreserve,
 547         .setup = setup_p4_watchdog,
 548         .rearm = p4_rearm,
 549         .stop = stop_p4_watchdog,
 550         /* RED-PEN this is wrong for the other sibling */
 551         .perfctr = MSR_P4_BPU_PERFCTR0,
 552         .evntsel = MSR_P4_BSU_ESCR0,
 553         .checkbit = 1ULL<<39,
 554 };
 555
 556 /* Watchdog using the Intel architected PerfMon. Used for Core2 and hopefully
 557    all future Intel CPUs. */
 558
 559 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 560 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 561
 562 static struct wd_ops intel_arch_wd_ops;
 563
 564 static int setup_intel_arch_watchdog(unsigned nmi_hz)
 565 {
 566         unsigned int ebx;
 567         union cpuid10_eax eax;
 568         unsigned int unused;
 569         unsigned int perfctr_msr, evntsel_msr;
 570         unsigned int evntsel;
 571         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 572
 573         /*
 574          * Check whether the Architectural PerfMon supports
 575          * Unhalted Core Cycles Event or not.
 576          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 577          */
 578         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 579         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 580             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 581                 return 0;
 582
 583         perfctr_msr = wd_ops->perfctr;
 584         evntsel_msr = wd_ops->evntsel;
 585
 586         wrmsrl(perfctr_msr, 0UL);
 587
 588         evntsel = ARCH_PERFMON_EVENTSEL_INT
 589                 | ARCH_PERFMON_EVENTSEL_OS
 590                 | ARCH_PERFMON_EVENTSEL_USR
 591                 | ARCH_PERFMON_NMI_EVENT_SEL
 592                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 593
 594         /* setup the timer */
 595         wrmsr(evntsel_msr, evntsel, 0);
 596         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 597         write_watchdog_counter32(perfctr_msr, "INTEL_ARCH_PERFCTR0", nmi_hz);
 598         apic_write(APIC_LVTPC, APIC_DM_NMI);
 599         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 600         wrmsr(evntsel_msr, evntsel, 0);
 601
 602         wd->perfctr_msr = perfctr_msr;
 603         wd->evntsel_msr = evntsel_msr;
 604         wd->cccr_msr = 0;  //unused
 605         intel_arch_wd_ops.checkbit = 1ULL << (eax.split.bit_width - 1);
 606         return 1;
 607 }
 608
 609 static struct wd_ops intel_arch_wd_ops __read_mostly = {
 610         .reserve = single_msr_reserve,
 611         .unreserve = single_msr_unreserve,
 612         .setup = setup_intel_arch_watchdog,
 613         .rearm = p6_rearm,
 614         .stop = single_msr_stop_watchdog,
 615         .perfctr = MSR_ARCH_PERFMON_PERFCTR1,
 616         .evntsel = MSR_ARCH_PERFMON_EVENTSEL1,
 617 };
 618
 619 static void probe_nmi_watchdog(void)
 620 {
 621         switch (boot_cpu_data.x86_vendor) {
 622         case X86_VENDOR_AMD:
 623                 if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15 &&
 624                     boot_cpu_data.x86 != 16)
 625                         return;
 626                 wd_ops = &k7_wd_ops;
 627                 break;
 628         case X86_VENDOR_INTEL:
 629                 /* Work around Core Duo (Yonah) errata AE49 where perfctr1
 630                    doesn't have a working enable bit. */
 631                 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 14) {
 632                         intel_arch_wd_ops.perfctr = MSR_ARCH_PERFMON_PERFCTR0;
 633                         intel_arch_wd_ops.evntsel = MSR_ARCH_PERFMON_EVENTSEL0;
 634                 }
 635                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 636                         wd_ops = &intel_arch_wd_ops;
 637                         break;
 638                 }
 639                 switch (boot_cpu_data.x86) {
 640                 case 6:
 641                         if (boot_cpu_data.x86_model > 0xd)
 642                                 return;
 643
 644                         wd_ops = &p6_wd_ops;
 645                         break;
 646                 case 15:
 647                         wd_ops = &p4_wd_ops;
 648                         break;
 649                 default:
 650                         return;
 651                 }
 652                 break;
 653         }
 654 }
 655
 656 /* Interface to nmi.c */
 657
 658 int lapic_watchdog_init(unsigned nmi_hz)
 659 {
 660         if (!wd_ops) {
 661                 probe_nmi_watchdog();
 662                 if (!wd_ops) {
 663                         printk(KERN_INFO "NMI watchdog: CPU not supported\n");
 664                         return -1;
 665                 }
 666
 667                 if (!wd_ops->reserve()) {
 668                         printk(KERN_ERR
 669                                 "NMI watchdog: cannot reserve perfctrs\n");
 670                         return -1;
 671                 }
 672         }
 673
 674         if (!(wd_ops->setup(nmi_hz))) {
 675                 printk(KERN_ERR "Cannot setup NMI watchdog on CPU %d\n",
 676                        raw_smp_processor_id());
 677                 return -1;
 678         }
 679
 680         return 0;
 681 }
 682
 683 void lapic_watchdog_stop(void)
 684 {
 685         if (wd_ops)
 686                 wd_ops->stop();
 687 }
 688
 689 unsigned lapic_adjust_nmi_hz(unsigned hz)
 690 {
 691         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 692         if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
 693             wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1)
 694                 hz = adjust_for_32bit_ctr(hz);
 695         return hz;
 696 }
 697
 698 int lapic_wd_event(unsigned nmi_hz)
 699 {
 700         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 701         u64 ctr;
 702         rdmsrl(wd->perfctr_msr, ctr);
 703         if (ctr & wd_ops->checkbit) { /* perfctr still running? */
 704                 return 0;
 705         }
 706         wd_ops->rearm(wd, nmi_hz);
 707         return 1;
 708 }
 709
 710 int lapic_watchdog_ok(void)
 711 {
 712         return wd_ops != NULL;
 713 }