1 #include "perf_event_intel_uncore.h"
3 static struct intel_uncore_type *empty_uncore[] = { NULL, };
4 struct intel_uncore_type **uncore_msr_uncores = empty_uncore;
5 struct intel_uncore_type **uncore_pci_uncores = empty_uncore;
7 static bool pcidrv_registered;
8 struct pci_driver *uncore_pci_driver;
9 /* pci bus to socket mapping */
10 int uncore_pcibus_to_physid[256] = { [0 ... 255] = -1, };
11 struct pci_dev *uncore_extra_pci_dev[UNCORE_SOCKET_MAX][UNCORE_EXTRA_PCI_DEV_MAX];
13 static DEFINE_RAW_SPINLOCK(uncore_box_lock);
14 /* mask of cpus that collect uncore events */
15 static cpumask_t uncore_cpu_mask;
17 /* constraint for the fixed counter */
18 static struct event_constraint uncore_constraint_fixed =
19 EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
20 struct event_constraint uncore_constraint_empty =
21 EVENT_CONSTRAINT(0, 0, 0);
23 ssize_t uncore_event_show(struct kobject *kobj,
24 struct kobj_attribute *attr, char *buf)
26 struct uncore_event_desc *event =
27 container_of(attr, struct uncore_event_desc, attr);
28 return sprintf(buf, "%s", event->config);
31 struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
33 return container_of(event->pmu, struct intel_uncore_pmu, pmu);
36 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
38 struct intel_uncore_box *box;
40 box = *per_cpu_ptr(pmu->box, cpu);
44 raw_spin_lock(&uncore_box_lock);
45 /* Recheck in lock to handle races. */
46 if (*per_cpu_ptr(pmu->box, cpu))
48 list_for_each_entry(box, &pmu->box_list, list) {
49 if (box->phys_id == topology_physical_package_id(cpu)) {
50 atomic_inc(&box->refcnt);
51 *per_cpu_ptr(pmu->box, cpu) = box;
56 raw_spin_unlock(&uncore_box_lock);
58 return *per_cpu_ptr(pmu->box, cpu);
61 struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
64 * perf core schedules event on the basis of cpu, uncore events are
65 * collected by one of the cpus inside a physical package.
67 return uncore_pmu_to_box(uncore_event_to_pmu(event), smp_processor_id());
70 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
74 rdmsrl(event->hw.event_base, count);
80 * generic get constraint function for shared match/mask registers.
82 struct event_constraint *
83 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
85 struct intel_uncore_extra_reg *er;
86 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
87 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
92 * reg->alloc can be set due to existing state, so for fake box we
93 * need to ignore this, otherwise we might fail to allocate proper
94 * fake state for this extra reg constraint.
96 if (reg1->idx == EXTRA_REG_NONE ||
97 (!uncore_box_is_fake(box) && reg1->alloc))
100 er = &box->shared_regs[reg1->idx];
101 raw_spin_lock_irqsave(&er->lock, flags);
102 if (!atomic_read(&er->ref) ||
103 (er->config1 == reg1->config && er->config2 == reg2->config)) {
104 atomic_inc(&er->ref);
105 er->config1 = reg1->config;
106 er->config2 = reg2->config;
109 raw_spin_unlock_irqrestore(&er->lock, flags);
112 if (!uncore_box_is_fake(box))
117 return &uncore_constraint_empty;
120 void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
122 struct intel_uncore_extra_reg *er;
123 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
126 * Only put constraint if extra reg was actually allocated. Also
127 * takes care of event which do not use an extra shared reg.
129 * Also, if this is a fake box we shouldn't touch any event state
130 * (reg->alloc) and we don't care about leaving inconsistent box
131 * state either since it will be thrown out.
133 if (uncore_box_is_fake(box) || !reg1->alloc)
136 er = &box->shared_regs[reg1->idx];
137 atomic_dec(&er->ref);
141 u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx)
143 struct intel_uncore_extra_reg *er;
147 er = &box->shared_regs[idx];
149 raw_spin_lock_irqsave(&er->lock, flags);
151 raw_spin_unlock_irqrestore(&er->lock, flags);
156 static void uncore_assign_hw_event(struct intel_uncore_box *box, struct perf_event *event, int idx)
158 struct hw_perf_event *hwc = &event->hw;
161 hwc->last_tag = ++box->tags[idx];
163 if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
164 hwc->event_base = uncore_fixed_ctr(box);
165 hwc->config_base = uncore_fixed_ctl(box);
169 hwc->config_base = uncore_event_ctl(box, hwc->idx);
170 hwc->event_base = uncore_perf_ctr(box, hwc->idx);
173 void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
175 u64 prev_count, new_count, delta;
178 if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
179 shift = 64 - uncore_fixed_ctr_bits(box);
181 shift = 64 - uncore_perf_ctr_bits(box);
183 /* the hrtimer might modify the previous event value */
185 prev_count = local64_read(&event->hw.prev_count);
186 new_count = uncore_read_counter(box, event);
187 if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
190 delta = (new_count << shift) - (prev_count << shift);
193 local64_add(delta, &event->count);
197 * The overflow interrupt is unavailable for SandyBridge-EP, is broken
198 * for SandyBridge. So we use hrtimer to periodically poll the counter
201 static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
203 struct intel_uncore_box *box;
204 struct perf_event *event;
208 box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
209 if (!box->n_active || box->cpu != smp_processor_id())
210 return HRTIMER_NORESTART;
212 * disable local interrupt to prevent uncore_pmu_event_start/stop
213 * to interrupt the update process
215 local_irq_save(flags);
218 * handle boxes with an active event list as opposed to active
221 list_for_each_entry(event, &box->active_list, active_entry) {
222 uncore_perf_event_update(box, event);
225 for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
226 uncore_perf_event_update(box, box->events[bit]);
228 local_irq_restore(flags);
230 hrtimer_forward_now(hrtimer, ns_to_ktime(box->hrtimer_duration));
231 return HRTIMER_RESTART;
234 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
236 __hrtimer_start_range_ns(&box->hrtimer,
237 ns_to_ktime(box->hrtimer_duration), 0,
238 HRTIMER_MODE_REL_PINNED, 0);
241 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
243 hrtimer_cancel(&box->hrtimer);
246 static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
248 hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
249 box->hrtimer.function = uncore_pmu_hrtimer;
252 static struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, int node)
254 struct intel_uncore_box *box;
257 size = sizeof(*box) + type->num_shared_regs * sizeof(struct intel_uncore_extra_reg);
259 box = kzalloc_node(size, GFP_KERNEL, node);
263 for (i = 0; i < type->num_shared_regs; i++)
264 raw_spin_lock_init(&box->shared_regs[i].lock);
266 uncore_pmu_init_hrtimer(box);
267 atomic_set(&box->refcnt, 1);
271 /* set default hrtimer timeout */
272 box->hrtimer_duration = UNCORE_PMU_HRTIMER_INTERVAL;
274 INIT_LIST_HEAD(&box->active_list);
280 uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, bool dogrp)
282 struct perf_event *event;
285 max_count = box->pmu->type->num_counters;
286 if (box->pmu->type->fixed_ctl)
289 if (box->n_events >= max_count)
293 box->event_list[n] = leader;
298 list_for_each_entry(event, &leader->sibling_list, group_entry) {
299 if (event->state <= PERF_EVENT_STATE_OFF)
305 box->event_list[n] = event;
311 static struct event_constraint *
312 uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
314 struct intel_uncore_type *type = box->pmu->type;
315 struct event_constraint *c;
317 if (type->ops->get_constraint) {
318 c = type->ops->get_constraint(box, event);
323 if (event->attr.config == UNCORE_FIXED_EVENT)
324 return &uncore_constraint_fixed;
326 if (type->constraints) {
327 for_each_event_constraint(c, type->constraints) {
328 if ((event->hw.config & c->cmask) == c->code)
333 return &type->unconstrainted;
336 static void uncore_put_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
338 if (box->pmu->type->ops->put_constraint)
339 box->pmu->type->ops->put_constraint(box, event);
342 static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
344 unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
345 struct event_constraint *c;
346 int i, wmin, wmax, ret = 0;
347 struct hw_perf_event *hwc;
349 bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
351 for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
352 hwc = &box->event_list[i]->hw;
353 c = uncore_get_event_constraint(box, box->event_list[i]);
355 wmin = min(wmin, c->weight);
356 wmax = max(wmax, c->weight);
359 /* fastpath, try to reuse previous register */
360 for (i = 0; i < n; i++) {
361 hwc = &box->event_list[i]->hw;
368 /* constraint still honored */
369 if (!test_bit(hwc->idx, c->idxmsk))
372 /* not already used */
373 if (test_bit(hwc->idx, used_mask))
376 __set_bit(hwc->idx, used_mask);
378 assign[i] = hwc->idx;
382 ret = perf_assign_events(box->event_list, n,
385 if (!assign || ret) {
386 for (i = 0; i < n; i++)
387 uncore_put_event_constraint(box, box->event_list[i]);
389 return ret ? -EINVAL : 0;
392 static void uncore_pmu_event_start(struct perf_event *event, int flags)
394 struct intel_uncore_box *box = uncore_event_to_box(event);
395 int idx = event->hw.idx;
397 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
400 if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
404 box->events[idx] = event;
406 __set_bit(idx, box->active_mask);
408 local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
409 uncore_enable_event(box, event);
411 if (box->n_active == 1) {
412 uncore_enable_box(box);
413 uncore_pmu_start_hrtimer(box);
417 static void uncore_pmu_event_stop(struct perf_event *event, int flags)
419 struct intel_uncore_box *box = uncore_event_to_box(event);
420 struct hw_perf_event *hwc = &event->hw;
422 if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
423 uncore_disable_event(box, event);
425 box->events[hwc->idx] = NULL;
426 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
427 hwc->state |= PERF_HES_STOPPED;
429 if (box->n_active == 0) {
430 uncore_disable_box(box);
431 uncore_pmu_cancel_hrtimer(box);
435 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
437 * Drain the remaining delta count out of a event
438 * that we are disabling:
440 uncore_perf_event_update(box, event);
441 hwc->state |= PERF_HES_UPTODATE;
445 static int uncore_pmu_event_add(struct perf_event *event, int flags)
447 struct intel_uncore_box *box = uncore_event_to_box(event);
448 struct hw_perf_event *hwc = &event->hw;
449 int assign[UNCORE_PMC_IDX_MAX];
455 ret = n = uncore_collect_events(box, event, false);
459 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
460 if (!(flags & PERF_EF_START))
461 hwc->state |= PERF_HES_ARCH;
463 ret = uncore_assign_events(box, assign, n);
467 /* save events moving to new counters */
468 for (i = 0; i < box->n_events; i++) {
469 event = box->event_list[i];
472 if (hwc->idx == assign[i] &&
473 hwc->last_tag == box->tags[assign[i]])
476 * Ensure we don't accidentally enable a stopped
477 * counter simply because we rescheduled.
479 if (hwc->state & PERF_HES_STOPPED)
480 hwc->state |= PERF_HES_ARCH;
482 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
485 /* reprogram moved events into new counters */
486 for (i = 0; i < n; i++) {
487 event = box->event_list[i];
490 if (hwc->idx != assign[i] ||
491 hwc->last_tag != box->tags[assign[i]])
492 uncore_assign_hw_event(box, event, assign[i]);
493 else if (i < box->n_events)
496 if (hwc->state & PERF_HES_ARCH)
499 uncore_pmu_event_start(event, 0);
506 static void uncore_pmu_event_del(struct perf_event *event, int flags)
508 struct intel_uncore_box *box = uncore_event_to_box(event);
511 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
513 for (i = 0; i < box->n_events; i++) {
514 if (event == box->event_list[i]) {
515 uncore_put_event_constraint(box, event);
517 while (++i < box->n_events)
518 box->event_list[i - 1] = box->event_list[i];
526 event->hw.last_tag = ~0ULL;
529 void uncore_pmu_event_read(struct perf_event *event)
531 struct intel_uncore_box *box = uncore_event_to_box(event);
532 uncore_perf_event_update(box, event);
536 * validation ensures the group can be loaded onto the
537 * PMU if it was the only group available.
539 static int uncore_validate_group(struct intel_uncore_pmu *pmu,
540 struct perf_event *event)
542 struct perf_event *leader = event->group_leader;
543 struct intel_uncore_box *fake_box;
544 int ret = -EINVAL, n;
546 fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE);
552 * the event is not yet connected with its
553 * siblings therefore we must first collect
554 * existing siblings, then add the new event
555 * before we can simulate the scheduling
557 n = uncore_collect_events(fake_box, leader, true);
561 fake_box->n_events = n;
562 n = uncore_collect_events(fake_box, event, false);
566 fake_box->n_events = n;
568 ret = uncore_assign_events(fake_box, NULL, n);
574 static int uncore_pmu_event_init(struct perf_event *event)
576 struct intel_uncore_pmu *pmu;
577 struct intel_uncore_box *box;
578 struct hw_perf_event *hwc = &event->hw;
581 if (event->attr.type != event->pmu->type)
584 pmu = uncore_event_to_pmu(event);
585 /* no device found for this pmu */
586 if (pmu->func_id < 0)
590 * Uncore PMU does measure at all privilege level all the time.
591 * So it doesn't make sense to specify any exclude bits.
593 if (event->attr.exclude_user || event->attr.exclude_kernel ||
594 event->attr.exclude_hv || event->attr.exclude_idle)
597 /* Sampling not supported yet */
598 if (hwc->sample_period)
602 * Place all uncore events for a particular physical package
607 box = uncore_pmu_to_box(pmu, event->cpu);
608 if (!box || box->cpu < 0)
610 event->cpu = box->cpu;
613 event->hw.last_tag = ~0ULL;
614 event->hw.extra_reg.idx = EXTRA_REG_NONE;
615 event->hw.branch_reg.idx = EXTRA_REG_NONE;
617 if (event->attr.config == UNCORE_FIXED_EVENT) {
618 /* no fixed counter */
619 if (!pmu->type->fixed_ctl)
622 * if there is only one fixed counter, only the first pmu
623 * can access the fixed counter
625 if (pmu->type->single_fixed && pmu->pmu_idx > 0)
628 /* fixed counters have event field hardcoded to zero */
631 hwc->config = event->attr.config & pmu->type->event_mask;
632 if (pmu->type->ops->hw_config) {
633 ret = pmu->type->ops->hw_config(box, event);
639 if (event->group_leader != event)
640 ret = uncore_validate_group(pmu, event);
647 static ssize_t uncore_get_attr_cpumask(struct device *dev,
648 struct device_attribute *attr, char *buf)
650 int n = cpulist_scnprintf(buf, PAGE_SIZE - 2, &uncore_cpu_mask);
657 static DEVICE_ATTR(cpumask, S_IRUGO, uncore_get_attr_cpumask, NULL);
659 static struct attribute *uncore_pmu_attrs[] = {
660 &dev_attr_cpumask.attr,
664 static struct attribute_group uncore_pmu_attr_group = {
665 .attrs = uncore_pmu_attrs,
668 static int uncore_pmu_register(struct intel_uncore_pmu *pmu)
672 if (!pmu->type->pmu) {
673 pmu->pmu = (struct pmu) {
674 .attr_groups = pmu->type->attr_groups,
675 .task_ctx_nr = perf_invalid_context,
676 .event_init = uncore_pmu_event_init,
677 .add = uncore_pmu_event_add,
678 .del = uncore_pmu_event_del,
679 .start = uncore_pmu_event_start,
680 .stop = uncore_pmu_event_stop,
681 .read = uncore_pmu_event_read,
684 pmu->pmu = *pmu->type->pmu;
685 pmu->pmu.attr_groups = pmu->type->attr_groups;
688 if (pmu->type->num_boxes == 1) {
689 if (strlen(pmu->type->name) > 0)
690 sprintf(pmu->name, "uncore_%s", pmu->type->name);
692 sprintf(pmu->name, "uncore");
694 sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
698 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
702 static void __init uncore_type_exit(struct intel_uncore_type *type)
706 for (i = 0; i < type->num_boxes; i++)
707 free_percpu(type->pmus[i].box);
710 kfree(type->events_group);
711 type->events_group = NULL;
714 static void __init uncore_types_exit(struct intel_uncore_type **types)
717 for (i = 0; types[i]; i++)
718 uncore_type_exit(types[i]);
721 static int __init uncore_type_init(struct intel_uncore_type *type)
723 struct intel_uncore_pmu *pmus;
724 struct attribute_group *attr_group;
725 struct attribute **attrs;
728 pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL);
734 type->unconstrainted = (struct event_constraint)
735 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
736 0, type->num_counters, 0, 0);
738 for (i = 0; i < type->num_boxes; i++) {
739 pmus[i].func_id = -1;
742 INIT_LIST_HEAD(&pmus[i].box_list);
743 pmus[i].box = alloc_percpu(struct intel_uncore_box *);
748 if (type->event_descs) {
750 while (type->event_descs[i].attr.attr.name)
753 attr_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
754 sizeof(*attr_group), GFP_KERNEL);
758 attrs = (struct attribute **)(attr_group + 1);
759 attr_group->name = "events";
760 attr_group->attrs = attrs;
762 for (j = 0; j < i; j++)
763 attrs[j] = &type->event_descs[j].attr.attr;
765 type->events_group = attr_group;
768 type->pmu_group = &uncore_pmu_attr_group;
771 uncore_type_exit(type);
775 static int __init uncore_types_init(struct intel_uncore_type **types)
779 for (i = 0; types[i]; i++) {
780 ret = uncore_type_init(types[i]);
787 uncore_type_exit(types[i]);
792 * add a pci uncore device
794 static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
796 struct intel_uncore_pmu *pmu;
797 struct intel_uncore_box *box;
798 struct intel_uncore_type *type;
800 bool first_box = false;
802 phys_id = uncore_pcibus_to_physid[pdev->bus->number];
806 if (UNCORE_PCI_DEV_TYPE(id->driver_data) == UNCORE_EXTRA_PCI_DEV) {
807 int idx = UNCORE_PCI_DEV_IDX(id->driver_data);
808 uncore_extra_pci_dev[phys_id][idx] = pdev;
809 pci_set_drvdata(pdev, NULL);
813 type = uncore_pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)];
814 box = uncore_alloc_box(type, NUMA_NO_NODE);
819 * for performance monitoring unit with multiple boxes,
820 * each box has a different function id.
822 pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)];
823 if (pmu->func_id < 0)
824 pmu->func_id = pdev->devfn;
826 WARN_ON_ONCE(pmu->func_id != pdev->devfn);
828 box->phys_id = phys_id;
831 uncore_box_init(box);
832 pci_set_drvdata(pdev, box);
834 raw_spin_lock(&uncore_box_lock);
835 if (list_empty(&pmu->box_list))
837 list_add_tail(&box->list, &pmu->box_list);
838 raw_spin_unlock(&uncore_box_lock);
841 uncore_pmu_register(pmu);
845 static void uncore_pci_remove(struct pci_dev *pdev)
847 struct intel_uncore_box *box = pci_get_drvdata(pdev);
848 struct intel_uncore_pmu *pmu;
849 int i, cpu, phys_id = uncore_pcibus_to_physid[pdev->bus->number];
850 bool last_box = false;
852 box = pci_get_drvdata(pdev);
854 for (i = 0; i < UNCORE_EXTRA_PCI_DEV_MAX; i++) {
855 if (uncore_extra_pci_dev[phys_id][i] == pdev) {
856 uncore_extra_pci_dev[phys_id][i] = NULL;
860 WARN_ON_ONCE(i >= UNCORE_EXTRA_PCI_DEV_MAX);
865 if (WARN_ON_ONCE(phys_id != box->phys_id))
868 pci_set_drvdata(pdev, NULL);
870 raw_spin_lock(&uncore_box_lock);
871 list_del(&box->list);
872 if (list_empty(&pmu->box_list))
874 raw_spin_unlock(&uncore_box_lock);
876 for_each_possible_cpu(cpu) {
877 if (*per_cpu_ptr(pmu->box, cpu) == box) {
878 *per_cpu_ptr(pmu->box, cpu) = NULL;
879 atomic_dec(&box->refcnt);
883 WARN_ON_ONCE(atomic_read(&box->refcnt) != 1);
887 perf_pmu_unregister(&pmu->pmu);
890 static int __init uncore_pci_init(void)
894 switch (boot_cpu_data.x86_model) {
895 case 45: /* Sandy Bridge-EP */
896 ret = snbep_uncore_pci_init();
898 case 62: /* Ivy Bridge-EP */
899 ret = ivbep_uncore_pci_init();
901 case 63: /* Haswell-EP */
902 ret = hswep_uncore_pci_init();
904 case 42: /* Sandy Bridge */
905 ret = snb_uncore_pci_init();
907 case 58: /* Ivy Bridge */
908 ret = ivb_uncore_pci_init();
910 case 60: /* Haswell */
911 case 69: /* Haswell Celeron */
912 ret = hsw_uncore_pci_init();
921 ret = uncore_types_init(uncore_pci_uncores);
925 uncore_pci_driver->probe = uncore_pci_probe;
926 uncore_pci_driver->remove = uncore_pci_remove;
928 ret = pci_register_driver(uncore_pci_driver);
930 pcidrv_registered = true;
932 uncore_types_exit(uncore_pci_uncores);
937 static void __init uncore_pci_exit(void)
939 if (pcidrv_registered) {
940 pcidrv_registered = false;
941 pci_unregister_driver(uncore_pci_driver);
942 uncore_types_exit(uncore_pci_uncores);
946 /* CPU hot plug/unplug are serialized by cpu_add_remove_lock mutex */
947 static LIST_HEAD(boxes_to_free);
949 static void uncore_kfree_boxes(void)
951 struct intel_uncore_box *box;
953 while (!list_empty(&boxes_to_free)) {
954 box = list_entry(boxes_to_free.next,
955 struct intel_uncore_box, list);
956 list_del(&box->list);
961 static void uncore_cpu_dying(int cpu)
963 struct intel_uncore_type *type;
964 struct intel_uncore_pmu *pmu;
965 struct intel_uncore_box *box;
968 for (i = 0; uncore_msr_uncores[i]; i++) {
969 type = uncore_msr_uncores[i];
970 for (j = 0; j < type->num_boxes; j++) {
971 pmu = &type->pmus[j];
972 box = *per_cpu_ptr(pmu->box, cpu);
973 *per_cpu_ptr(pmu->box, cpu) = NULL;
974 if (box && atomic_dec_and_test(&box->refcnt))
975 list_add(&box->list, &boxes_to_free);
980 static int uncore_cpu_starting(int cpu)
982 struct intel_uncore_type *type;
983 struct intel_uncore_pmu *pmu;
984 struct intel_uncore_box *box, *exist;
985 int i, j, k, phys_id;
987 phys_id = topology_physical_package_id(cpu);
989 for (i = 0; uncore_msr_uncores[i]; i++) {
990 type = uncore_msr_uncores[i];
991 for (j = 0; j < type->num_boxes; j++) {
992 pmu = &type->pmus[j];
993 box = *per_cpu_ptr(pmu->box, cpu);
994 /* called by uncore_cpu_init? */
995 if (box && box->phys_id >= 0) {
996 uncore_box_init(box);
1000 for_each_online_cpu(k) {
1001 exist = *per_cpu_ptr(pmu->box, k);
1002 if (exist && exist->phys_id == phys_id) {
1003 atomic_inc(&exist->refcnt);
1004 *per_cpu_ptr(pmu->box, cpu) = exist;
1006 list_add(&box->list,
1015 box->phys_id = phys_id;
1016 uncore_box_init(box);
1023 static int uncore_cpu_prepare(int cpu, int phys_id)
1025 struct intel_uncore_type *type;
1026 struct intel_uncore_pmu *pmu;
1027 struct intel_uncore_box *box;
1030 for (i = 0; uncore_msr_uncores[i]; i++) {
1031 type = uncore_msr_uncores[i];
1032 for (j = 0; j < type->num_boxes; j++) {
1033 pmu = &type->pmus[j];
1034 if (pmu->func_id < 0)
1037 box = uncore_alloc_box(type, cpu_to_node(cpu));
1042 box->phys_id = phys_id;
1043 *per_cpu_ptr(pmu->box, cpu) = box;
1050 uncore_change_context(struct intel_uncore_type **uncores, int old_cpu, int new_cpu)
1052 struct intel_uncore_type *type;
1053 struct intel_uncore_pmu *pmu;
1054 struct intel_uncore_box *box;
1057 for (i = 0; uncores[i]; i++) {
1059 for (j = 0; j < type->num_boxes; j++) {
1060 pmu = &type->pmus[j];
1062 box = uncore_pmu_to_box(pmu, new_cpu);
1064 box = uncore_pmu_to_box(pmu, old_cpu);
1069 WARN_ON_ONCE(box->cpu != -1);
1074 WARN_ON_ONCE(box->cpu != old_cpu);
1076 uncore_pmu_cancel_hrtimer(box);
1077 perf_pmu_migrate_context(&pmu->pmu,
1087 static void uncore_event_exit_cpu(int cpu)
1089 int i, phys_id, target;
1091 /* if exiting cpu is used for collecting uncore events */
1092 if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
1095 /* find a new cpu to collect uncore events */
1096 phys_id = topology_physical_package_id(cpu);
1098 for_each_online_cpu(i) {
1101 if (phys_id == topology_physical_package_id(i)) {
1107 /* migrate uncore events to the new cpu */
1109 cpumask_set_cpu(target, &uncore_cpu_mask);
1111 uncore_change_context(uncore_msr_uncores, cpu, target);
1112 uncore_change_context(uncore_pci_uncores, cpu, target);
1115 static void uncore_event_init_cpu(int cpu)
1119 phys_id = topology_physical_package_id(cpu);
1120 for_each_cpu(i, &uncore_cpu_mask) {
1121 if (phys_id == topology_physical_package_id(i))
1125 cpumask_set_cpu(cpu, &uncore_cpu_mask);
1127 uncore_change_context(uncore_msr_uncores, -1, cpu);
1128 uncore_change_context(uncore_pci_uncores, -1, cpu);
1131 static int uncore_cpu_notifier(struct notifier_block *self,
1132 unsigned long action, void *hcpu)
1134 unsigned int cpu = (long)hcpu;
1136 /* allocate/free data structure for uncore box */
1137 switch (action & ~CPU_TASKS_FROZEN) {
1138 case CPU_UP_PREPARE:
1139 uncore_cpu_prepare(cpu, -1);
1142 uncore_cpu_starting(cpu);
1144 case CPU_UP_CANCELED:
1146 uncore_cpu_dying(cpu);
1150 uncore_kfree_boxes();
1156 /* select the cpu that collects uncore events */
1157 switch (action & ~CPU_TASKS_FROZEN) {
1158 case CPU_DOWN_FAILED:
1160 uncore_event_init_cpu(cpu);
1162 case CPU_DOWN_PREPARE:
1163 uncore_event_exit_cpu(cpu);
1172 static struct notifier_block uncore_cpu_nb = {
1173 .notifier_call = uncore_cpu_notifier,
1175 * to migrate uncore events, our notifier should be executed
1176 * before perf core's notifier.
1178 .priority = CPU_PRI_PERF + 1,
1181 static void __init uncore_cpu_setup(void *dummy)
1183 uncore_cpu_starting(smp_processor_id());
1186 static int __init uncore_cpu_init(void)
1190 switch (boot_cpu_data.x86_model) {
1191 case 26: /* Nehalem */
1193 case 37: /* Westmere */
1195 nhm_uncore_cpu_init();
1197 case 42: /* Sandy Bridge */
1198 case 58: /* Ivy Bridge */
1199 snb_uncore_cpu_init();
1201 case 45: /* Sandy Bridge-EP */
1202 snbep_uncore_cpu_init();
1204 case 46: /* Nehalem-EX */
1205 case 47: /* Westmere-EX aka. Xeon E7 */
1206 nhmex_uncore_cpu_init();
1208 case 62: /* Ivy Bridge-EP */
1209 ivbep_uncore_cpu_init();
1211 case 63: /* Haswell-EP */
1212 hswep_uncore_cpu_init();
1218 ret = uncore_types_init(uncore_msr_uncores);
1225 static int __init uncore_pmus_register(void)
1227 struct intel_uncore_pmu *pmu;
1228 struct intel_uncore_type *type;
1231 for (i = 0; uncore_msr_uncores[i]; i++) {
1232 type = uncore_msr_uncores[i];
1233 for (j = 0; j < type->num_boxes; j++) {
1234 pmu = &type->pmus[j];
1235 uncore_pmu_register(pmu);
1242 static void __init uncore_cpumask_init(void)
1247 * ony invoke once from msr or pci init code
1249 if (!cpumask_empty(&uncore_cpu_mask))
1252 cpu_notifier_register_begin();
1254 for_each_online_cpu(cpu) {
1255 int i, phys_id = topology_physical_package_id(cpu);
1257 for_each_cpu(i, &uncore_cpu_mask) {
1258 if (phys_id == topology_physical_package_id(i)) {
1266 uncore_cpu_prepare(cpu, phys_id);
1267 uncore_event_init_cpu(cpu);
1269 on_each_cpu(uncore_cpu_setup, NULL, 1);
1271 __register_cpu_notifier(&uncore_cpu_nb);
1273 cpu_notifier_register_done();
1277 static int __init intel_uncore_init(void)
1281 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
1284 if (cpu_has_hypervisor)
1287 ret = uncore_pci_init();
1290 ret = uncore_cpu_init();
1295 uncore_cpumask_init();
1297 uncore_pmus_register();
1302 device_initcall(intel_uncore_init);