arch/x86/kernel/cpu/perf_event_intel.c

   1 /*
   2  * Per core/cpu state
   3  *
   4  * Used to coordinate shared registers between HT threads or
   5  * among events on a single PMU.
   6  */
   7
   8 #include <linux/stddef.h>
   9 #include <linux/types.h>
  10 #include <linux/init.h>
  11 #include <linux/slab.h>
  12
  13 #include <asm/hardirq.h>
  14 #include <asm/apic.h>
  15
  16 #include "perf_event.h"
  17
  18 /*
  19  * Intel PerfMon, used on Core and later.
  20  */
  21 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  22 {
  23   [PERF_COUNT_HW_CPU_CYCLES]            = 0x003c,
  24   [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
  25   [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x4f2e,
  26   [PERF_COUNT_HW_CACHE_MISSES]          = 0x412e,
  27   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
  28   [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
  29   [PERF_COUNT_HW_BUS_CYCLES]            = 0x013c,
  30 };
  31
  32 static struct event_constraint intel_core_event_constraints[] __read_mostly =
  33 {
  34         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  35         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  36         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  37         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  38         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  39         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  40         EVENT_CONSTRAINT_END
  41 };
  42
  43 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  44 {
  45         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  46         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  47         /*
  48          * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
  49          * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
  50          * ratio between these counters.
  51          */
  52         /* FIXED_EVENT_CONSTRAINT(0x013c, 2),  CPU_CLK_UNHALTED.REF */
  53         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  54         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  55         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  56         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  57         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  58         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  59         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  60         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  61         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  62         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  63         EVENT_CONSTRAINT_END
  64 };
  65
  66 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  67 {
  68         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  69         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  70         /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  71         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  72         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  73         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  74         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  75         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  76         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  77         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  78         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  79         EVENT_CONSTRAINT_END
  80 };
  81
  82 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  83 {
  84         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  85         EVENT_EXTRA_END
  86 };
  87
  88 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  89 {
  90         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  91         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  92         /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  93         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  94         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
  95         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  96         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
  97         EVENT_CONSTRAINT_END
  98 };
  99
 100 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 101 {
 102         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 103         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 104         /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
 105         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 106         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 107         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 108         EVENT_CONSTRAINT_END
 109 };
 110
 111 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 112 {
 113         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
 114         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
 115         EVENT_EXTRA_END
 116 };
 117
 118 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 119 {
 120         EVENT_CONSTRAINT_END
 121 };
 122
 123 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 124 {
 125         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 126         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 127         /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
 128         EVENT_CONSTRAINT_END
 129 };
 130
 131 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 132         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
 133         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
 134         EVENT_EXTRA_END
 135 };
 136
 137 static u64 intel_pmu_event_map(int hw_event)
 138 {
 139         return intel_perfmon_event_map[hw_event];
 140 }
 141
 142 static __initconst const u64 snb_hw_cache_event_ids
 143                                 [PERF_COUNT_HW_CACHE_MAX]
 144                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 145                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 146 {
 147  [ C(L1D) ] = {
 148         [ C(OP_READ) ] = {
 149                 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS        */
 150                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPLACEMENT              */
 151         },
 152         [ C(OP_WRITE) ] = {
 153                 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES       */
 154                 [ C(RESULT_MISS)   ] = 0x0851, /* L1D.ALL_M_REPLACEMENT        */
 155         },
 156         [ C(OP_PREFETCH) ] = {
 157                 [ C(RESULT_ACCESS) ] = 0x0,
 158                 [ C(RESULT_MISS)   ] = 0x024e, /* HW_PRE_REQ.DL1_MISS          */
 159         },
 160  },
 161  [ C(L1I ) ] = {
 162         [ C(OP_READ) ] = {
 163                 [ C(RESULT_ACCESS) ] = 0x0,
 164                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACHE.MISSES */
 165         },
 166         [ C(OP_WRITE) ] = {
 167                 [ C(RESULT_ACCESS) ] = -1,
 168                 [ C(RESULT_MISS)   ] = -1,
 169         },
 170         [ C(OP_PREFETCH) ] = {
 171                 [ C(RESULT_ACCESS) ] = 0x0,
 172                 [ C(RESULT_MISS)   ] = 0x0,
 173         },
 174  },
 175  [ C(LL  ) ] = {
 176         [ C(OP_READ) ] = {
 177                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 178                 [ C(RESULT_ACCESS) ] = 0x01b7,
 179                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 180                 [ C(RESULT_MISS)   ] = 0x01b7,
 181         },
 182         [ C(OP_WRITE) ] = {
 183                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 184                 [ C(RESULT_ACCESS) ] = 0x01b7,
 185                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 186                 [ C(RESULT_MISS)   ] = 0x01b7,
 187         },
 188         [ C(OP_PREFETCH) ] = {
 189                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 190                 [ C(RESULT_ACCESS) ] = 0x01b7,
 191                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 192                 [ C(RESULT_MISS)   ] = 0x01b7,
 193         },
 194  },
 195  [ C(DTLB) ] = {
 196         [ C(OP_READ) ] = {
 197                 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
 198                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
 199         },
 200         [ C(OP_WRITE) ] = {
 201                 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
 202                 [ C(RESULT_MISS)   ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 203         },
 204         [ C(OP_PREFETCH) ] = {
 205                 [ C(RESULT_ACCESS) ] = 0x0,
 206                 [ C(RESULT_MISS)   ] = 0x0,
 207         },
 208  },
 209  [ C(ITLB) ] = {
 210         [ C(OP_READ) ] = {
 211                 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT         */
 212                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK    */
 213         },
 214         [ C(OP_WRITE) ] = {
 215                 [ C(RESULT_ACCESS) ] = -1,
 216                 [ C(RESULT_MISS)   ] = -1,
 217         },
 218         [ C(OP_PREFETCH) ] = {
 219                 [ C(RESULT_ACCESS) ] = -1,
 220                 [ C(RESULT_MISS)   ] = -1,
 221         },
 222  },
 223  [ C(BPU ) ] = {
 224         [ C(OP_READ) ] = {
 225                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 226                 [ C(RESULT_MISS)   ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
 227         },
 228         [ C(OP_WRITE) ] = {
 229                 [ C(RESULT_ACCESS) ] = -1,
 230                 [ C(RESULT_MISS)   ] = -1,
 231         },
 232         [ C(OP_PREFETCH) ] = {
 233                 [ C(RESULT_ACCESS) ] = -1,
 234                 [ C(RESULT_MISS)   ] = -1,
 235         },
 236  },
 237  [ C(NODE) ] = {
 238         [ C(OP_READ) ] = {
 239                 [ C(RESULT_ACCESS) ] = -1,
 240                 [ C(RESULT_MISS)   ] = -1,
 241         },
 242         [ C(OP_WRITE) ] = {
 243                 [ C(RESULT_ACCESS) ] = -1,
 244                 [ C(RESULT_MISS)   ] = -1,
 245         },
 246         [ C(OP_PREFETCH) ] = {
 247                 [ C(RESULT_ACCESS) ] = -1,
 248                 [ C(RESULT_MISS)   ] = -1,
 249         },
 250  },
 251
 252 };
 253
 254 static __initconst const u64 westmere_hw_cache_event_ids
 255                                 [PERF_COUNT_HW_CACHE_MAX]
 256                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 257                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 258 {
 259  [ C(L1D) ] = {
 260         [ C(OP_READ) ] = {
 261                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 262                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 263         },
 264         [ C(OP_WRITE) ] = {
 265                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 266                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 267         },
 268         [ C(OP_PREFETCH) ] = {
 269                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 270                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 271         },
 272  },
 273  [ C(L1I ) ] = {
 274         [ C(OP_READ) ] = {
 275                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 276                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 277         },
 278         [ C(OP_WRITE) ] = {
 279                 [ C(RESULT_ACCESS) ] = -1,
 280                 [ C(RESULT_MISS)   ] = -1,
 281         },
 282         [ C(OP_PREFETCH) ] = {
 283                 [ C(RESULT_ACCESS) ] = 0x0,
 284                 [ C(RESULT_MISS)   ] = 0x0,
 285         },
 286  },
 287  [ C(LL  ) ] = {
 288         [ C(OP_READ) ] = {
 289                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 290                 [ C(RESULT_ACCESS) ] = 0x01b7,
 291                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 292                 [ C(RESULT_MISS)   ] = 0x01b7,
 293         },
 294         /*
 295          * Use RFO, not WRITEBACK, because a write miss would typically occur
 296          * on RFO.
 297          */
 298         [ C(OP_WRITE) ] = {
 299                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 300                 [ C(RESULT_ACCESS) ] = 0x01b7,
 301                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 302                 [ C(RESULT_MISS)   ] = 0x01b7,
 303         },
 304         [ C(OP_PREFETCH) ] = {
 305                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 306                 [ C(RESULT_ACCESS) ] = 0x01b7,
 307                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 308                 [ C(RESULT_MISS)   ] = 0x01b7,
 309         },
 310  },
 311  [ C(DTLB) ] = {
 312         [ C(OP_READ) ] = {
 313                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 314                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 315         },
 316         [ C(OP_WRITE) ] = {
 317                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 318                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 319         },
 320         [ C(OP_PREFETCH) ] = {
 321                 [ C(RESULT_ACCESS) ] = 0x0,
 322                 [ C(RESULT_MISS)   ] = 0x0,
 323         },
 324  },
 325  [ C(ITLB) ] = {
 326         [ C(OP_READ) ] = {
 327                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 328                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
 329         },
 330         [ C(OP_WRITE) ] = {
 331                 [ C(RESULT_ACCESS) ] = -1,
 332                 [ C(RESULT_MISS)   ] = -1,
 333         },
 334         [ C(OP_PREFETCH) ] = {
 335                 [ C(RESULT_ACCESS) ] = -1,
 336                 [ C(RESULT_MISS)   ] = -1,
 337         },
 338  },
 339  [ C(BPU ) ] = {
 340         [ C(OP_READ) ] = {
 341                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 342                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 343         },
 344         [ C(OP_WRITE) ] = {
 345                 [ C(RESULT_ACCESS) ] = -1,
 346                 [ C(RESULT_MISS)   ] = -1,
 347         },
 348         [ C(OP_PREFETCH) ] = {
 349                 [ C(RESULT_ACCESS) ] = -1,
 350                 [ C(RESULT_MISS)   ] = -1,
 351         },
 352  },
 353  [ C(NODE) ] = {
 354         [ C(OP_READ) ] = {
 355                 [ C(RESULT_ACCESS) ] = 0x01b7,
 356                 [ C(RESULT_MISS)   ] = 0x01b7,
 357         },
 358         [ C(OP_WRITE) ] = {
 359                 [ C(RESULT_ACCESS) ] = 0x01b7,
 360                 [ C(RESULT_MISS)   ] = 0x01b7,
 361         },
 362         [ C(OP_PREFETCH) ] = {
 363                 [ C(RESULT_ACCESS) ] = 0x01b7,
 364                 [ C(RESULT_MISS)   ] = 0x01b7,
 365         },
 366  },
 367 };
 368
 369 /*
 370  * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
 371  * See IA32 SDM Vol 3B 30.6.1.3
 372  */
 373
 374 #define NHM_DMND_DATA_RD        (1 << 0)
 375 #define NHM_DMND_RFO            (1 << 1)
 376 #define NHM_DMND_IFETCH         (1 << 2)
 377 #define NHM_DMND_WB             (1 << 3)
 378 #define NHM_PF_DATA_RD          (1 << 4)
 379 #define NHM_PF_DATA_RFO         (1 << 5)
 380 #define NHM_PF_IFETCH           (1 << 6)
 381 #define NHM_OFFCORE_OTHER       (1 << 7)
 382 #define NHM_UNCORE_HIT          (1 << 8)
 383 #define NHM_OTHER_CORE_HIT_SNP  (1 << 9)
 384 #define NHM_OTHER_CORE_HITM     (1 << 10)
 385                                 /* reserved */
 386 #define NHM_REMOTE_CACHE_FWD    (1 << 12)
 387 #define NHM_REMOTE_DRAM         (1 << 13)
 388 #define NHM_LOCAL_DRAM          (1 << 14)
 389 #define NHM_NON_DRAM            (1 << 15)
 390
 391 #define NHM_ALL_DRAM            (NHM_REMOTE_DRAM|NHM_LOCAL_DRAM)
 392
 393 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
 394 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
 395 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
 396
 397 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
 398 #define NHM_L3_MISS     (NHM_NON_DRAM|NHM_ALL_DRAM|NHM_REMOTE_CACHE_FWD)
 399 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
 400
 401 static __initconst const u64 nehalem_hw_cache_extra_regs
 402                                 [PERF_COUNT_HW_CACHE_MAX]
 403                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 404                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 405 {
 406  [ C(LL  ) ] = {
 407         [ C(OP_READ) ] = {
 408                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
 409                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_L3_MISS,
 410         },
 411         [ C(OP_WRITE) ] = {
 412                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
 413                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_L3_MISS,
 414         },
 415         [ C(OP_PREFETCH) ] = {
 416                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
 417                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
 418         },
 419  },
 420  [ C(NODE) ] = {
 421         [ C(OP_READ) ] = {
 422                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_ALL_DRAM,
 423                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE_DRAM,
 424         },
 425         [ C(OP_WRITE) ] = {
 426                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_ALL_DRAM,
 427                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE_DRAM,
 428         },
 429         [ C(OP_PREFETCH) ] = {
 430                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_ALL_DRAM,
 431                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE_DRAM,
 432         },
 433  },
 434 };
 435
 436 static __initconst const u64 nehalem_hw_cache_event_ids
 437                                 [PERF_COUNT_HW_CACHE_MAX]
 438                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 439                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 440 {
 441  [ C(L1D) ] = {
 442         [ C(OP_READ) ] = {
 443                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 444                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 445         },
 446         [ C(OP_WRITE) ] = {
 447                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 448                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 449         },
 450         [ C(OP_PREFETCH) ] = {
 451                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 452                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 453         },
 454  },
 455  [ C(L1I ) ] = {
 456         [ C(OP_READ) ] = {
 457                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 458                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 459         },
 460         [ C(OP_WRITE) ] = {
 461                 [ C(RESULT_ACCESS) ] = -1,
 462                 [ C(RESULT_MISS)   ] = -1,
 463         },
 464         [ C(OP_PREFETCH) ] = {
 465                 [ C(RESULT_ACCESS) ] = 0x0,
 466                 [ C(RESULT_MISS)   ] = 0x0,
 467         },
 468  },
 469  [ C(LL  ) ] = {
 470         [ C(OP_READ) ] = {
 471                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 472                 [ C(RESULT_ACCESS) ] = 0x01b7,
 473                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 474                 [ C(RESULT_MISS)   ] = 0x01b7,
 475         },
 476         /*
 477          * Use RFO, not WRITEBACK, because a write miss would typically occur
 478          * on RFO.
 479          */
 480         [ C(OP_WRITE) ] = {
 481                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 482                 [ C(RESULT_ACCESS) ] = 0x01b7,
 483                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 484                 [ C(RESULT_MISS)   ] = 0x01b7,
 485         },
 486         [ C(OP_PREFETCH) ] = {
 487                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 488                 [ C(RESULT_ACCESS) ] = 0x01b7,
 489                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 490                 [ C(RESULT_MISS)   ] = 0x01b7,
 491         },
 492  },
 493  [ C(DTLB) ] = {
 494         [ C(OP_READ) ] = {
 495                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
 496                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 497         },
 498         [ C(OP_WRITE) ] = {
 499                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
 500                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 501         },
 502         [ C(OP_PREFETCH) ] = {
 503                 [ C(RESULT_ACCESS) ] = 0x0,
 504                 [ C(RESULT_MISS)   ] = 0x0,
 505         },
 506  },
 507  [ C(ITLB) ] = {
 508         [ C(OP_READ) ] = {
 509                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 510                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
 511         },
 512         [ C(OP_WRITE) ] = {
 513                 [ C(RESULT_ACCESS) ] = -1,
 514                 [ C(RESULT_MISS)   ] = -1,
 515         },
 516         [ C(OP_PREFETCH) ] = {
 517                 [ C(RESULT_ACCESS) ] = -1,
 518                 [ C(RESULT_MISS)   ] = -1,
 519         },
 520  },
 521  [ C(BPU ) ] = {
 522         [ C(OP_READ) ] = {
 523                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 524                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 525         },
 526         [ C(OP_WRITE) ] = {
 527                 [ C(RESULT_ACCESS) ] = -1,
 528                 [ C(RESULT_MISS)   ] = -1,
 529         },
 530         [ C(OP_PREFETCH) ] = {
 531                 [ C(RESULT_ACCESS) ] = -1,
 532                 [ C(RESULT_MISS)   ] = -1,
 533         },
 534  },
 535  [ C(NODE) ] = {
 536         [ C(OP_READ) ] = {
 537                 [ C(RESULT_ACCESS) ] = 0x01b7,
 538                 [ C(RESULT_MISS)   ] = 0x01b7,
 539         },
 540         [ C(OP_WRITE) ] = {
 541                 [ C(RESULT_ACCESS) ] = 0x01b7,
 542                 [ C(RESULT_MISS)   ] = 0x01b7,
 543         },
 544         [ C(OP_PREFETCH) ] = {
 545                 [ C(RESULT_ACCESS) ] = 0x01b7,
 546                 [ C(RESULT_MISS)   ] = 0x01b7,
 547         },
 548  },
 549 };
 550
 551 static __initconst const u64 core2_hw_cache_event_ids
 552                                 [PERF_COUNT_HW_CACHE_MAX]
 553                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 554                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 555 {
 556  [ C(L1D) ] = {
 557         [ C(OP_READ) ] = {
 558                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
 559                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
 560         },
 561         [ C(OP_WRITE) ] = {
 562                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
 563                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
 564         },
 565         [ C(OP_PREFETCH) ] = {
 566                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
 567                 [ C(RESULT_MISS)   ] = 0,
 568         },
 569  },
 570  [ C(L1I ) ] = {
 571         [ C(OP_READ) ] = {
 572                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
 573                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
 574         },
 575         [ C(OP_WRITE) ] = {
 576                 [ C(RESULT_ACCESS) ] = -1,
 577                 [ C(RESULT_MISS)   ] = -1,
 578         },
 579         [ C(OP_PREFETCH) ] = {
 580                 [ C(RESULT_ACCESS) ] = 0,
 581                 [ C(RESULT_MISS)   ] = 0,
 582         },
 583  },
 584  [ C(LL  ) ] = {
 585         [ C(OP_READ) ] = {
 586                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 587                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 588         },
 589         [ C(OP_WRITE) ] = {
 590                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 591                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 592         },
 593         [ C(OP_PREFETCH) ] = {
 594                 [ C(RESULT_ACCESS) ] = 0,
 595                 [ C(RESULT_MISS)   ] = 0,
 596         },
 597  },
 598  [ C(DTLB) ] = {
 599         [ C(OP_READ) ] = {
 600                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
 601                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
 602         },
 603         [ C(OP_WRITE) ] = {
 604                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
 605                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
 606         },
 607         [ C(OP_PREFETCH) ] = {
 608                 [ C(RESULT_ACCESS) ] = 0,
 609                 [ C(RESULT_MISS)   ] = 0,
 610         },
 611  },
 612  [ C(ITLB) ] = {
 613         [ C(OP_READ) ] = {
 614                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 615                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
 616         },
 617         [ C(OP_WRITE) ] = {
 618                 [ C(RESULT_ACCESS) ] = -1,
 619                 [ C(RESULT_MISS)   ] = -1,
 620         },
 621         [ C(OP_PREFETCH) ] = {
 622                 [ C(RESULT_ACCESS) ] = -1,
 623                 [ C(RESULT_MISS)   ] = -1,
 624         },
 625  },
 626  [ C(BPU ) ] = {
 627         [ C(OP_READ) ] = {
 628                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 629                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 630         },
 631         [ C(OP_WRITE) ] = {
 632                 [ C(RESULT_ACCESS) ] = -1,
 633                 [ C(RESULT_MISS)   ] = -1,
 634         },
 635         [ C(OP_PREFETCH) ] = {
 636                 [ C(RESULT_ACCESS) ] = -1,
 637                 [ C(RESULT_MISS)   ] = -1,
 638         },
 639  },
 640 };
 641
 642 static __initconst const u64 atom_hw_cache_event_ids
 643                                 [PERF_COUNT_HW_CACHE_MAX]
 644                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 645                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 646 {
 647  [ C(L1D) ] = {
 648         [ C(OP_READ) ] = {
 649                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
 650                 [ C(RESULT_MISS)   ] = 0,
 651         },
 652         [ C(OP_WRITE) ] = {
 653                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
 654                 [ C(RESULT_MISS)   ] = 0,
 655         },
 656         [ C(OP_PREFETCH) ] = {
 657                 [ C(RESULT_ACCESS) ] = 0x0,
 658                 [ C(RESULT_MISS)   ] = 0,
 659         },
 660  },
 661  [ C(L1I ) ] = {
 662         [ C(OP_READ) ] = {
 663                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
 664                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
 665         },
 666         [ C(OP_WRITE) ] = {
 667                 [ C(RESULT_ACCESS) ] = -1,
 668                 [ C(RESULT_MISS)   ] = -1,
 669         },
 670         [ C(OP_PREFETCH) ] = {
 671                 [ C(RESULT_ACCESS) ] = 0,
 672                 [ C(RESULT_MISS)   ] = 0,
 673         },
 674  },
 675  [ C(LL  ) ] = {
 676         [ C(OP_READ) ] = {
 677                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 678                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 679         },
 680         [ C(OP_WRITE) ] = {
 681                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 682                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 683         },
 684         [ C(OP_PREFETCH) ] = {
 685                 [ C(RESULT_ACCESS) ] = 0,
 686                 [ C(RESULT_MISS)   ] = 0,
 687         },
 688  },
 689  [ C(DTLB) ] = {
 690         [ C(OP_READ) ] = {
 691                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
 692                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
 693         },
 694         [ C(OP_WRITE) ] = {
 695                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
 696                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
 697         },
 698         [ C(OP_PREFETCH) ] = {
 699                 [ C(RESULT_ACCESS) ] = 0,
 700                 [ C(RESULT_MISS)   ] = 0,
 701         },
 702  },
 703  [ C(ITLB) ] = {
 704         [ C(OP_READ) ] = {
 705                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 706                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
 707         },
 708         [ C(OP_WRITE) ] = {
 709                 [ C(RESULT_ACCESS) ] = -1,
 710                 [ C(RESULT_MISS)   ] = -1,
 711         },
 712         [ C(OP_PREFETCH) ] = {
 713                 [ C(RESULT_ACCESS) ] = -1,
 714                 [ C(RESULT_MISS)   ] = -1,
 715         },
 716  },
 717  [ C(BPU ) ] = {
 718         [ C(OP_READ) ] = {
 719                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 720                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 721         },
 722         [ C(OP_WRITE) ] = {
 723                 [ C(RESULT_ACCESS) ] = -1,
 724                 [ C(RESULT_MISS)   ] = -1,
 725         },
 726         [ C(OP_PREFETCH) ] = {
 727                 [ C(RESULT_ACCESS) ] = -1,
 728                 [ C(RESULT_MISS)   ] = -1,
 729         },
 730  },
 731 };
 732
 733 static void intel_pmu_disable_all(void)
 734 {
 735         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 736
 737         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 738
 739         if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
 740                 intel_pmu_disable_bts();
 741
 742         intel_pmu_pebs_disable_all();
 743         intel_pmu_lbr_disable_all();
 744 }
 745
 746 static void intel_pmu_enable_all(int added)
 747 {
 748         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 749
 750         intel_pmu_pebs_enable_all();
 751         intel_pmu_lbr_enable_all();
 752         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
 753
 754         if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
 755                 struct perf_event *event =
 756                         cpuc->events[X86_PMC_IDX_FIXED_BTS];
 757
 758                 if (WARN_ON_ONCE(!event))
 759                         return;
 760
 761                 intel_pmu_enable_bts(event->hw.config);
 762         }
 763 }
 764
 765 /*
 766  * Workaround for:
 767  *   Intel Errata AAK100 (model 26)
 768  *   Intel Errata AAP53  (model 30)
 769  *   Intel Errata BD53   (model 44)
 770  *
 771  * The official story:
 772  *   These chips need to be 'reset' when adding counters by programming the
 773  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
 774  *   in sequence on the same PMC or on different PMCs.
 775  *
 776  * In practise it appears some of these events do in fact count, and
 777  * we need to programm all 4 events.
 778  */
 779 static void intel_pmu_nhm_workaround(void)
 780 {
 781         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 782         static const unsigned long nhm_magic[4] = {
 783                 0x4300B5,
 784                 0x4300D2,
 785                 0x4300B1,
 786                 0x4300B1
 787         };
 788         struct perf_event *event;
 789         int i;
 790
 791         /*
 792          * The Errata requires below steps:
 793          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
 794          * 2) Configure 4 PERFEVTSELx with the magic events and clear
 795          *    the corresponding PMCx;
 796          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
 797          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
 798          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
 799          */
 800
 801         /*
 802          * The real steps we choose are a little different from above.
 803          * A) To reduce MSR operations, we don't run step 1) as they
 804          *    are already cleared before this function is called;
 805          * B) Call x86_perf_event_update to save PMCx before configuring
 806          *    PERFEVTSELx with magic number;
 807          * C) With step 5), we do clear only when the PERFEVTSELx is
 808          *    not used currently.
 809          * D) Call x86_perf_event_set_period to restore PMCx;
 810          */
 811
 812         /* We always operate 4 pairs of PERF Counters */
 813         for (i = 0; i < 4; i++) {
 814                 event = cpuc->events[i];
 815                 if (event)
 816                         x86_perf_event_update(event);
 817         }
 818
 819         for (i = 0; i < 4; i++) {
 820                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
 821                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
 822         }
 823
 824         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
 825         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
 826
 827         for (i = 0; i < 4; i++) {
 828                 event = cpuc->events[i];
 829
 830                 if (event) {
 831                         x86_perf_event_set_period(event);
 832                         __x86_pmu_enable_event(&event->hw,
 833                                         ARCH_PERFMON_EVENTSEL_ENABLE);
 834                 } else
 835                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
 836         }
 837 }
 838
 839 static void intel_pmu_nhm_enable_all(int added)
 840 {
 841         if (added)
 842                 intel_pmu_nhm_workaround();
 843         intel_pmu_enable_all(added);
 844 }
 845
 846 static inline u64 intel_pmu_get_status(void)
 847 {
 848         u64 status;
 849
 850         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
 851
 852         return status;
 853 }
 854
 855 static inline void intel_pmu_ack_status(u64 ack)
 856 {
 857         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
 858 }
 859
 860 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
 861 {
 862         int idx = hwc->idx - X86_PMC_IDX_FIXED;
 863         u64 ctrl_val, mask;
 864
 865         mask = 0xfULL << (idx * 4);
 866
 867         rdmsrl(hwc->config_base, ctrl_val);
 868         ctrl_val &= ~mask;
 869         wrmsrl(hwc->config_base, ctrl_val);
 870 }
 871
 872 static void intel_pmu_disable_event(struct perf_event *event)
 873 {
 874         struct hw_perf_event *hwc = &event->hw;
 875
 876         if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
 877                 intel_pmu_disable_bts();
 878                 intel_pmu_drain_bts_buffer();
 879                 return;
 880         }
 881
 882         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
 883                 intel_pmu_disable_fixed(hwc);
 884                 return;
 885         }
 886
 887         x86_pmu_disable_event(event);
 888
 889         if (unlikely(event->attr.precise_ip))
 890                 intel_pmu_pebs_disable(event);
 891 }
 892
 893 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
 894 {
 895         int idx = hwc->idx - X86_PMC_IDX_FIXED;
 896         u64 ctrl_val, bits, mask;
 897
 898         /*
 899          * Enable IRQ generation (0x8),
 900          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
 901          * if requested:
 902          */
 903         bits = 0x8ULL;
 904         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
 905                 bits |= 0x2;
 906         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
 907                 bits |= 0x1;
 908
 909         /*
 910          * ANY bit is supported in v3 and up
 911          */
 912         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
 913                 bits |= 0x4;
 914
 915         bits <<= (idx * 4);
 916         mask = 0xfULL << (idx * 4);
 917
 918         rdmsrl(hwc->config_base, ctrl_val);
 919         ctrl_val &= ~mask;
 920         ctrl_val |= bits;
 921         wrmsrl(hwc->config_base, ctrl_val);
 922 }
 923
 924 static void intel_pmu_enable_event(struct perf_event *event)
 925 {
 926         struct hw_perf_event *hwc = &event->hw;
 927
 928         if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
 929                 if (!__this_cpu_read(cpu_hw_events.enabled))
 930                         return;
 931
 932                 intel_pmu_enable_bts(hwc->config);
 933                 return;
 934         }
 935
 936         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
 937                 intel_pmu_enable_fixed(hwc);
 938                 return;
 939         }
 940
 941         if (unlikely(event->attr.precise_ip))
 942                 intel_pmu_pebs_enable(event);
 943
 944         __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 945 }
 946
 947 /*
 948  * Save and restart an expired event. Called by NMI contexts,
 949  * so it has to be careful about preempting normal event ops:
 950  */
 951 int intel_pmu_save_and_restart(struct perf_event *event)
 952 {
 953         x86_perf_event_update(event);
 954         return x86_perf_event_set_period(event);
 955 }
 956
 957 static void intel_pmu_reset(void)
 958 {
 959         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
 960         unsigned long flags;
 961         int idx;
 962
 963         if (!x86_pmu.num_counters)
 964                 return;
 965
 966         local_irq_save(flags);
 967
 968         printk("clearing PMU state on CPU#%d\n", smp_processor_id());
 969
 970         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 971                 checking_wrmsrl(x86_pmu_config_addr(idx), 0ull);
 972                 checking_wrmsrl(x86_pmu_event_addr(idx),  0ull);
 973         }
 974         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
 975                 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
 976
 977         if (ds)
 978                 ds->bts_index = ds->bts_buffer_base;
 979
 980         local_irq_restore(flags);
 981 }
 982
 983 /*
 984  * This handler is triggered by the local APIC, so the APIC IRQ handling
 985  * rules apply:
 986  */
 987 static int intel_pmu_handle_irq(struct pt_regs *regs)
 988 {
 989         struct perf_sample_data data;
 990         struct cpu_hw_events *cpuc;
 991         int bit, loops;
 992         u64 status;
 993         int handled;
 994
 995         perf_sample_data_init(&data, 0);
 996
 997         cpuc = &__get_cpu_var(cpu_hw_events);
 998
 999         /*
1000          * Some chipsets need to unmask the LVTPC in a particular spot
1001          * inside the nmi handler.  As a result, the unmasking was pushed
1002          * into all the nmi handlers.
1003          *
1004          * This handler doesn't seem to have any issues with the unmasking
1005          * so it was left at the top.
1006          */
1007         apic_write(APIC_LVTPC, APIC_DM_NMI);
1008
1009         intel_pmu_disable_all();
1010         handled = intel_pmu_drain_bts_buffer();
1011         status = intel_pmu_get_status();
1012         if (!status) {
1013                 intel_pmu_enable_all(0);
1014                 return handled;
1015         }
1016
1017         loops = 0;
1018 again:
1019         intel_pmu_ack_status(status);
1020         if (++loops > 100) {
1021                 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1022                 perf_event_print_debug();
1023                 intel_pmu_reset();
1024                 goto done;
1025         }
1026
1027         inc_irq_stat(apic_perf_irqs);
1028
1029         intel_pmu_lbr_read();
1030
1031         /*
1032          * PEBS overflow sets bit 62 in the global status register
1033          */
1034         if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1035                 handled++;
1036                 x86_pmu.drain_pebs(regs);
1037         }
1038
1039         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1040                 struct perf_event *event = cpuc->events[bit];
1041
1042                 handled++;
1043
1044                 if (!test_bit(bit, cpuc->active_mask))
1045                         continue;
1046
1047                 if (!intel_pmu_save_and_restart(event))
1048                         continue;
1049
1050                 data.period = event->hw.last_period;
1051
1052                 if (perf_event_overflow(event, &data, regs))
1053                         x86_pmu_stop(event, 0);
1054         }
1055
1056         /*
1057          * Repeat if there is more work to be done:
1058          */
1059         status = intel_pmu_get_status();
1060         if (status)
1061                 goto again;
1062
1063 done:
1064         intel_pmu_enable_all(0);
1065         return handled;
1066 }
1067
1068 static struct event_constraint *
1069 intel_bts_constraints(struct perf_event *event)
1070 {
1071         struct hw_perf_event *hwc = &event->hw;
1072         unsigned int hw_event, bts_event;
1073
1074         if (event->attr.freq)
1075                 return NULL;
1076
1077         hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1078         bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1079
1080         if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1081                 return &bts_constraint;
1082
1083         return NULL;
1084 }
1085
1086 static bool intel_try_alt_er(struct perf_event *event, int orig_idx)
1087 {
1088         if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1089                 return false;
1090
1091         if (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) {
1092                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1093                 event->hw.config |= 0x01bb;
1094                 event->hw.extra_reg.idx = EXTRA_REG_RSP_1;
1095                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1096         } else if (event->hw.extra_reg.idx == EXTRA_REG_RSP_1) {
1097                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1098                 event->hw.config |= 0x01b7;
1099                 event->hw.extra_reg.idx = EXTRA_REG_RSP_0;
1100                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1101         }
1102
1103         if (event->hw.extra_reg.idx == orig_idx)
1104                 return false;
1105
1106         return true;
1107 }
1108
1109 /*
1110  * manage allocation of shared extra msr for certain events
1111  *
1112  * sharing can be:
1113  * per-cpu: to be shared between the various events on a single PMU
1114  * per-core: per-cpu + shared by HT threads
1115  */
1116 static struct event_constraint *
1117 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1118                                    struct perf_event *event)
1119 {
1120         struct event_constraint *c = &emptyconstraint;
1121         struct hw_perf_event_extra *reg = &event->hw.extra_reg;
1122         struct er_account *era;
1123         unsigned long flags;
1124         int orig_idx = reg->idx;
1125
1126         /* already allocated shared msr */
1127         if (reg->alloc)
1128                 return &unconstrained;
1129
1130 again:
1131         era = &cpuc->shared_regs->regs[reg->idx];
1132         /*
1133          * we use spin_lock_irqsave() to avoid lockdep issues when
1134          * passing a fake cpuc
1135          */
1136         raw_spin_lock_irqsave(&era->lock, flags);
1137
1138         if (!atomic_read(&era->ref) || era->config == reg->config) {
1139
1140                 /* lock in msr value */
1141                 era->config = reg->config;
1142                 era->reg = reg->reg;
1143
1144                 /* one more user */
1145                 atomic_inc(&era->ref);
1146
1147                 /* no need to reallocate during incremental event scheduling */
1148                 reg->alloc = 1;
1149
1150                 /*
1151                  * All events using extra_reg are unconstrained.
1152                  * Avoids calling x86_get_event_constraints()
1153                  *
1154                  * Must revisit if extra_reg controlling events
1155                  * ever have constraints. Worst case we go through
1156                  * the regular event constraint table.
1157                  */
1158                 c = &unconstrained;
1159         } else if (intel_try_alt_er(event, orig_idx)) {
1160                 raw_spin_unlock(&era->lock);
1161                 goto again;
1162         }
1163         raw_spin_unlock_irqrestore(&era->lock, flags);
1164
1165         return c;
1166 }
1167
1168 static void
1169 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1170                                    struct hw_perf_event_extra *reg)
1171 {
1172         struct er_account *era;
1173
1174         /*
1175          * only put constraint if extra reg was actually
1176          * allocated. Also takes care of event which do
1177          * not use an extra shared reg
1178          */
1179         if (!reg->alloc)
1180                 return;
1181
1182         era = &cpuc->shared_regs->regs[reg->idx];
1183
1184         /* one fewer user */
1185         atomic_dec(&era->ref);
1186
1187         /* allocate again next time */
1188         reg->alloc = 0;
1189 }
1190
1191 static struct event_constraint *
1192 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1193                               struct perf_event *event)
1194 {
1195         struct event_constraint *c = NULL;
1196
1197         if (event->hw.extra_reg.idx != EXTRA_REG_NONE)
1198                 c = __intel_shared_reg_get_constraints(cpuc, event);
1199
1200         return c;
1201 }
1202
1203 struct event_constraint *
1204 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1205 {
1206         struct event_constraint *c;
1207
1208         if (x86_pmu.event_constraints) {
1209                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1210                         if ((event->hw.config & c->cmask) == c->code)
1211                                 return c;
1212                 }
1213         }
1214
1215         return &unconstrained;
1216 }
1217
1218 static struct event_constraint *
1219 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1220 {
1221         struct event_constraint *c;
1222
1223         c = intel_bts_constraints(event);
1224         if (c)
1225                 return c;
1226
1227         c = intel_pebs_constraints(event);
1228         if (c)
1229                 return c;
1230
1231         c = intel_shared_regs_constraints(cpuc, event);
1232         if (c)
1233                 return c;
1234
1235         return x86_get_event_constraints(cpuc, event);
1236 }
1237
1238 static void
1239 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
1240                                         struct perf_event *event)
1241 {
1242         struct hw_perf_event_extra *reg;
1243
1244         reg = &event->hw.extra_reg;
1245         if (reg->idx != EXTRA_REG_NONE)
1246                 __intel_shared_reg_put_constraints(cpuc, reg);
1247 }
1248
1249 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1250                                         struct perf_event *event)
1251 {
1252         intel_put_shared_regs_event_constraints(cpuc, event);
1253 }
1254
1255 static int intel_pmu_hw_config(struct perf_event *event)
1256 {
1257         int ret = x86_pmu_hw_config(event);
1258
1259         if (ret)
1260                 return ret;
1261
1262         if (event->attr.precise_ip &&
1263             (event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1264                 /*
1265                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1266                  * (0x003c) so that we can use it with PEBS.
1267                  *
1268                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1269                  * PEBS capable. However we can use INST_RETIRED.ANY_P
1270                  * (0x00c0), which is a PEBS capable event, to get the same
1271                  * count.
1272                  *
1273                  * INST_RETIRED.ANY_P counts the number of cycles that retires
1274                  * CNTMASK instructions. By setting CNTMASK to a value (16)
1275                  * larger than the maximum number of instructions that can be
1276                  * retired per cycle (4) and then inverting the condition, we
1277                  * count all cycles that retire 16 or less instructions, which
1278                  * is every cycle.
1279                  *
1280                  * Thereby we gain a PEBS capable cycle counter.
1281                  */
1282                 u64 alt_config = 0x108000c0; /* INST_RETIRED.TOTAL_CYCLES */
1283
1284                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1285                 event->hw.config = alt_config;
1286         }
1287
1288         if (event->attr.type != PERF_TYPE_RAW)
1289                 return 0;
1290
1291         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1292                 return 0;
1293
1294         if (x86_pmu.version < 3)
1295                 return -EINVAL;
1296
1297         if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1298                 return -EACCES;
1299
1300         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1301
1302         return 0;
1303 }
1304
1305 static __initconst const struct x86_pmu core_pmu = {
1306         .name                   = "core",
1307         .handle_irq             = x86_pmu_handle_irq,
1308         .disable_all            = x86_pmu_disable_all,
1309         .enable_all             = x86_pmu_enable_all,
1310         .enable                 = x86_pmu_enable_event,
1311         .disable                = x86_pmu_disable_event,
1312         .hw_config              = x86_pmu_hw_config,
1313         .schedule_events        = x86_schedule_events,
1314         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
1315         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
1316         .event_map              = intel_pmu_event_map,
1317         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
1318         .apic                   = 1,
1319         /*
1320          * Intel PMCs cannot be accessed sanely above 32 bit width,
1321          * so we install an artificial 1<<31 period regardless of
1322          * the generic event period:
1323          */
1324         .max_period             = (1ULL << 31) - 1,
1325         .get_event_constraints  = intel_get_event_constraints,
1326         .put_event_constraints  = intel_put_event_constraints,
1327         .event_constraints      = intel_core_event_constraints,
1328 };
1329
1330 struct intel_shared_regs *allocate_shared_regs(int cpu)
1331 {
1332         struct intel_shared_regs *regs;
1333         int i;
1334
1335         regs = kzalloc_node(sizeof(struct intel_shared_regs),
1336                             GFP_KERNEL, cpu_to_node(cpu));
1337         if (regs) {
1338                 /*
1339                  * initialize the locks to keep lockdep happy
1340                  */
1341                 for (i = 0; i < EXTRA_REG_MAX; i++)
1342                         raw_spin_lock_init(&regs->regs[i].lock);
1343
1344                 regs->core_id = -1;
1345         }
1346         return regs;
1347 }
1348
1349 static int intel_pmu_cpu_prepare(int cpu)
1350 {
1351         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1352
1353         if (!x86_pmu.extra_regs)
1354                 return NOTIFY_OK;
1355
1356         cpuc->shared_regs = allocate_shared_regs(cpu);
1357         if (!cpuc->shared_regs)
1358                 return NOTIFY_BAD;
1359
1360         return NOTIFY_OK;
1361 }
1362
1363 static void intel_pmu_cpu_starting(int cpu)
1364 {
1365         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1366         int core_id = topology_core_id(cpu);
1367         int i;
1368
1369         init_debug_store_on_cpu(cpu);
1370         /*
1371          * Deal with CPUs that don't clear their LBRs on power-up.
1372          */
1373         intel_pmu_lbr_reset();
1374
1375         if (!cpuc->shared_regs || (x86_pmu.er_flags & ERF_NO_HT_SHARING))
1376                 return;
1377
1378         for_each_cpu(i, topology_thread_cpumask(cpu)) {
1379                 struct intel_shared_regs *pc;
1380
1381                 pc = per_cpu(cpu_hw_events, i).shared_regs;
1382                 if (pc && pc->core_id == core_id) {
1383                         cpuc->kfree_on_online = cpuc->shared_regs;
1384                         cpuc->shared_regs = pc;
1385                         break;
1386                 }
1387         }
1388
1389         cpuc->shared_regs->core_id = core_id;
1390         cpuc->shared_regs->refcnt++;
1391 }
1392
1393 static void intel_pmu_cpu_dying(int cpu)
1394 {
1395         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1396         struct intel_shared_regs *pc;
1397
1398         pc = cpuc->shared_regs;
1399         if (pc) {
1400                 if (pc->core_id == -1 || --pc->refcnt == 0)
1401                         kfree(pc);
1402                 cpuc->shared_regs = NULL;
1403         }
1404
1405         fini_debug_store_on_cpu(cpu);
1406 }
1407
1408 static __initconst const struct x86_pmu intel_pmu = {
1409         .name                   = "Intel",
1410         .handle_irq             = intel_pmu_handle_irq,
1411         .disable_all            = intel_pmu_disable_all,
1412         .enable_all             = intel_pmu_enable_all,
1413         .enable                 = intel_pmu_enable_event,
1414         .disable                = intel_pmu_disable_event,
1415         .hw_config              = intel_pmu_hw_config,
1416         .schedule_events        = x86_schedule_events,
1417         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
1418         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
1419         .event_map              = intel_pmu_event_map,
1420         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
1421         .apic                   = 1,
1422         /*
1423          * Intel PMCs cannot be accessed sanely above 32 bit width,
1424          * so we install an artificial 1<<31 period regardless of
1425          * the generic event period:
1426          */
1427         .max_period             = (1ULL << 31) - 1,
1428         .get_event_constraints  = intel_get_event_constraints,
1429         .put_event_constraints  = intel_put_event_constraints,
1430
1431         .cpu_prepare            = intel_pmu_cpu_prepare,
1432         .cpu_starting           = intel_pmu_cpu_starting,
1433         .cpu_dying              = intel_pmu_cpu_dying,
1434 };
1435
1436 static void intel_clovertown_quirks(void)
1437 {
1438         /*
1439          * PEBS is unreliable due to:
1440          *
1441          *   AJ67  - PEBS may experience CPL leaks
1442          *   AJ68  - PEBS PMI may be delayed by one event
1443          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1444          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1445          *
1446          * AJ67 could be worked around by restricting the OS/USR flags.
1447          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1448          *
1449          * AJ106 could possibly be worked around by not allowing LBR
1450          *       usage from PEBS, including the fixup.
1451          * AJ68  could possibly be worked around by always programming
1452          *       a pebs_event_reset[0] value and coping with the lost events.
1453          *
1454          * But taken together it might just make sense to not enable PEBS on
1455          * these chips.
1456          */
1457         printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
1458         x86_pmu.pebs = 0;
1459         x86_pmu.pebs_constraints = NULL;
1460 }
1461
1462 __init int intel_pmu_init(void)
1463 {
1464         union cpuid10_edx edx;
1465         union cpuid10_eax eax;
1466         unsigned int unused;
1467         unsigned int ebx;
1468         int version;
1469
1470         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
1471                 switch (boot_cpu_data.x86) {
1472                 case 0x6:
1473                         return p6_pmu_init();
1474                 case 0xf:
1475                         return p4_pmu_init();
1476                 }
1477                 return -ENODEV;
1478         }
1479
1480         /*
1481          * Check whether the Architectural PerfMon supports
1482          * Branch Misses Retired hw_event or not.
1483          */
1484         cpuid(10, &eax.full, &ebx, &unused, &edx.full);
1485         if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
1486                 return -ENODEV;
1487
1488         version = eax.split.version_id;
1489         if (version < 2)
1490                 x86_pmu = core_pmu;
1491         else
1492                 x86_pmu = intel_pmu;
1493
1494         x86_pmu.version                 = version;
1495         x86_pmu.num_counters            = eax.split.num_counters;
1496         x86_pmu.cntval_bits             = eax.split.bit_width;
1497         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
1498
1499         /*
1500          * Quirk: v2 perfmon does not report fixed-purpose events, so
1501          * assume at least 3 events:
1502          */
1503         if (version > 1)
1504                 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
1505
1506         /*
1507          * v2 and above have a perf capabilities MSR
1508          */
1509         if (version > 1) {
1510                 u64 capabilities;
1511
1512                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
1513                 x86_pmu.intel_cap.capabilities = capabilities;
1514         }
1515
1516         intel_ds_init();
1517
1518         /*
1519          * Install the hw-cache-events table:
1520          */
1521         switch (boot_cpu_data.x86_model) {
1522         case 14: /* 65 nm core solo/duo, "Yonah" */
1523                 pr_cont("Core events, ");
1524                 break;
1525
1526         case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1527                 x86_pmu.quirks = intel_clovertown_quirks;
1528         case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1529         case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1530         case 29: /* six-core 45 nm xeon "Dunnington" */
1531                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1532                        sizeof(hw_cache_event_ids));
1533
1534                 intel_pmu_lbr_init_core();
1535
1536                 x86_pmu.event_constraints = intel_core2_event_constraints;
1537                 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
1538                 pr_cont("Core2 events, ");
1539                 break;
1540
1541         case 26: /* 45 nm nehalem, "Bloomfield" */
1542         case 30: /* 45 nm nehalem, "Lynnfield" */
1543         case 46: /* 45 nm nehalem-ex, "Beckton" */
1544                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1545                        sizeof(hw_cache_event_ids));
1546                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1547                        sizeof(hw_cache_extra_regs));
1548
1549                 intel_pmu_lbr_init_nhm();
1550
1551                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
1552                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
1553                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
1554                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
1555
1556                 /* UOPS_ISSUED.STALLED_CYCLES */
1557                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1558                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
1559                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
1560
1561                 if (ebx & 0x40) {
1562                         /*
1563                          * Erratum AAJ80 detected, we work it around by using
1564                          * the BR_MISP_EXEC.ANY event. This will over-count
1565                          * branch-misses, but it's still much better than the
1566                          * architectural event which is often completely bogus:
1567                          */
1568                         intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
1569
1570                         pr_cont("erratum AAJ80 worked around, ");
1571                 }
1572                 pr_cont("Nehalem events, ");
1573                 break;
1574
1575         case 28: /* Atom */
1576                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
1577                        sizeof(hw_cache_event_ids));
1578
1579                 intel_pmu_lbr_init_atom();
1580
1581                 x86_pmu.event_constraints = intel_gen_event_constraints;
1582                 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
1583                 pr_cont("Atom events, ");
1584                 break;
1585
1586         case 37: /* 32 nm nehalem, "Clarkdale" */
1587         case 44: /* 32 nm nehalem, "Gulftown" */
1588         case 47: /* 32 nm Xeon E7 */
1589                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
1590                        sizeof(hw_cache_event_ids));
1591                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1592                        sizeof(hw_cache_extra_regs));
1593
1594                 intel_pmu_lbr_init_nhm();
1595
1596                 x86_pmu.event_constraints = intel_westmere_event_constraints;
1597                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
1598                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
1599                 x86_pmu.extra_regs = intel_westmere_extra_regs;
1600                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
1601
1602                 /* UOPS_ISSUED.STALLED_CYCLES */
1603                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1604                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
1605                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
1606
1607                 pr_cont("Westmere events, ");
1608                 break;
1609
1610         case 42: /* SandyBridge */
1611         case 45: /* SandyBridge, "Romely-EP" */
1612                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
1613                        sizeof(hw_cache_event_ids));
1614
1615                 intel_pmu_lbr_init_nhm();
1616
1617                 x86_pmu.event_constraints = intel_snb_event_constraints;
1618                 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
1619                 x86_pmu.extra_regs = intel_snb_extra_regs;
1620                 /* all extra regs are per-cpu when HT is on */
1621                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
1622                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
1623
1624                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
1625                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1626                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
1627                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
1628
1629                 pr_cont("SandyBridge events, ");
1630                 break;
1631
1632         default:
1633                 switch (x86_pmu.version) {
1634                 case 1:
1635                         x86_pmu.event_constraints = intel_v1_event_constraints;
1636                         pr_cont("generic architected perfmon v1, ");
1637                         break;
1638                 default:
1639                         /*
1640                          * default constraints for v2 and up
1641                          */
1642                         x86_pmu.event_constraints = intel_gen_event_constraints;
1643                         pr_cont("generic architected perfmon, ");
1644                         break;
1645                 }
1646         }
1647         return 0;
1648 }