arch/x86/kernel/cpu/perf_event_amd.c

   1 #include <linux/perf_event.h>
   2 #include <linux/types.h>
   3 #include <linux/init.h>
   4 #include <linux/slab.h>
   5
   6 #include "perf_event.h"
   7
   8 static __initconst const u64 amd_hw_cache_event_ids
   9                                 [PERF_COUNT_HW_CACHE_MAX]
  10                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  11                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  12 {
  13  [ C(L1D) ] = {
  14         [ C(OP_READ) ] = {
  15                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
  16                 [ C(RESULT_MISS)   ] = 0x0141, /* Data Cache Misses          */
  17         },
  18         [ C(OP_WRITE) ] = {
  19                 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
  20                 [ C(RESULT_MISS)   ] = 0,
  21         },
  22         [ C(OP_PREFETCH) ] = {
  23                 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts  */
  24                 [ C(RESULT_MISS)   ] = 0x0167, /* Data Prefetcher :cancelled */
  25         },
  26  },
  27  [ C(L1I ) ] = {
  28         [ C(OP_READ) ] = {
  29                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches  */
  30                 [ C(RESULT_MISS)   ] = 0x0081, /* Instruction cache misses   */
  31         },
  32         [ C(OP_WRITE) ] = {
  33                 [ C(RESULT_ACCESS) ] = -1,
  34                 [ C(RESULT_MISS)   ] = -1,
  35         },
  36         [ C(OP_PREFETCH) ] = {
  37                 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
  38                 [ C(RESULT_MISS)   ] = 0,
  39         },
  40  },
  41  [ C(LL  ) ] = {
  42         [ C(OP_READ) ] = {
  43                 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
  44                 [ C(RESULT_MISS)   ] = 0x037E, /* L2 Cache Misses : IC+DC     */
  45         },
  46         [ C(OP_WRITE) ] = {
  47                 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback           */
  48                 [ C(RESULT_MISS)   ] = 0,
  49         },
  50         [ C(OP_PREFETCH) ] = {
  51                 [ C(RESULT_ACCESS) ] = 0,
  52                 [ C(RESULT_MISS)   ] = 0,
  53         },
  54  },
  55  [ C(DTLB) ] = {
  56         [ C(OP_READ) ] = {
  57                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
  58                 [ C(RESULT_MISS)   ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
  59         },
  60         [ C(OP_WRITE) ] = {
  61                 [ C(RESULT_ACCESS) ] = 0,
  62                 [ C(RESULT_MISS)   ] = 0,
  63         },
  64         [ C(OP_PREFETCH) ] = {
  65                 [ C(RESULT_ACCESS) ] = 0,
  66                 [ C(RESULT_MISS)   ] = 0,
  67         },
  68  },
  69  [ C(ITLB) ] = {
  70         [ C(OP_READ) ] = {
  71                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes        */
  72                 [ C(RESULT_MISS)   ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
  73         },
  74         [ C(OP_WRITE) ] = {
  75                 [ C(RESULT_ACCESS) ] = -1,
  76                 [ C(RESULT_MISS)   ] = -1,
  77         },
  78         [ C(OP_PREFETCH) ] = {
  79                 [ C(RESULT_ACCESS) ] = -1,
  80                 [ C(RESULT_MISS)   ] = -1,
  81         },
  82  },
  83  [ C(BPU ) ] = {
  84         [ C(OP_READ) ] = {
  85                 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr.      */
  86                 [ C(RESULT_MISS)   ] = 0x00c3, /* Retired Mispredicted BI    */
  87         },
  88         [ C(OP_WRITE) ] = {
  89                 [ C(RESULT_ACCESS) ] = -1,
  90                 [ C(RESULT_MISS)   ] = -1,
  91         },
  92         [ C(OP_PREFETCH) ] = {
  93                 [ C(RESULT_ACCESS) ] = -1,
  94                 [ C(RESULT_MISS)   ] = -1,
  95         },
  96  },
  97  [ C(NODE) ] = {
  98         [ C(OP_READ) ] = {
  99                 [ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */
 100                 [ C(RESULT_MISS)   ] = 0x98e9, /* CPU Request to Memory, r   */
 101         },
 102         [ C(OP_WRITE) ] = {
 103                 [ C(RESULT_ACCESS) ] = -1,
 104                 [ C(RESULT_MISS)   ] = -1,
 105         },
 106         [ C(OP_PREFETCH) ] = {
 107                 [ C(RESULT_ACCESS) ] = -1,
 108                 [ C(RESULT_MISS)   ] = -1,
 109         },
 110  },
 111 };
 112
 113 /*
 114  * AMD Performance Monitor K7 and later.
 115  */
 116 static const u64 amd_perfmon_event_map[] =
 117 {
 118   [PERF_COUNT_HW_CPU_CYCLES]                    = 0x0076,
 119   [PERF_COUNT_HW_INSTRUCTIONS]                  = 0x00c0,
 120   [PERF_COUNT_HW_CACHE_REFERENCES]              = 0x0080,
 121   [PERF_COUNT_HW_CACHE_MISSES]                  = 0x0081,
 122   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]           = 0x00c2,
 123   [PERF_COUNT_HW_BRANCH_MISSES]                 = 0x00c3,
 124   [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]       = 0x00d0, /* "Decoder empty" event */
 125   [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]        = 0x00d1, /* "Dispatch stalls" event */
 126 };
 127
 128 static u64 amd_pmu_event_map(int hw_event)
 129 {
 130         return amd_perfmon_event_map[hw_event];
 131 }
 132
 133 static int amd_pmu_hw_config(struct perf_event *event)
 134 {
 135         int ret = x86_pmu_hw_config(event);
 136
 137         if (ret)
 138                 return ret;
 139
 140         if (event->attr.type != PERF_TYPE_RAW)
 141                 return 0;
 142
 143         event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
 144
 145         return 0;
 146 }
 147
 148 /*
 149  * AMD64 events are detected based on their event codes.
 150  */
 151 static inline unsigned int amd_get_event_code(struct hw_perf_event *hwc)
 152 {
 153         return ((hwc->config >> 24) & 0x0f00) | (hwc->config & 0x00ff);
 154 }
 155
 156 static inline int amd_is_nb_event(struct hw_perf_event *hwc)
 157 {
 158         return (hwc->config & 0xe0) == 0xe0;
 159 }
 160
 161 static inline int amd_has_nb(struct cpu_hw_events *cpuc)
 162 {
 163         struct amd_nb *nb = cpuc->amd_nb;
 164
 165         return nb && nb->nb_id != -1;
 166 }
 167
 168 static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
 169                                       struct perf_event *event)
 170 {
 171         struct hw_perf_event *hwc = &event->hw;
 172         struct amd_nb *nb = cpuc->amd_nb;
 173         int i;
 174
 175         /*
 176          * only care about NB events
 177          */
 178         if (!(amd_has_nb(cpuc) && amd_is_nb_event(hwc)))
 179                 return;
 180
 181         /*
 182          * need to scan whole list because event may not have
 183          * been assigned during scheduling
 184          *
 185          * no race condition possible because event can only
 186          * be removed on one CPU at a time AND PMU is disabled
 187          * when we come here
 188          */
 189         for (i = 0; i < x86_pmu.num_counters; i++) {
 190                 if (nb->owners[i] == event) {
 191                         cmpxchg(nb->owners+i, event, NULL);
 192                         break;
 193                 }
 194         }
 195 }
 196
 197  /*
 198   * AMD64 NorthBridge events need special treatment because
 199   * counter access needs to be synchronized across all cores
 200   * of a package. Refer to BKDG section 3.12
 201   *
 202   * NB events are events measuring L3 cache, Hypertransport
 203   * traffic. They are identified by an event code >= 0xe00.
 204   * They measure events on the NorthBride which is shared
 205   * by all cores on a package. NB events are counted on a
 206   * shared set of counters. When a NB event is programmed
 207   * in a counter, the data actually comes from a shared
 208   * counter. Thus, access to those counters needs to be
 209   * synchronized.
 210   *
 211   * We implement the synchronization such that no two cores
 212   * can be measuring NB events using the same counters. Thus,
 213   * we maintain a per-NB allocation table. The available slot
 214   * is propagated using the event_constraint structure.
 215   *
 216   * We provide only one choice for each NB event based on
 217   * the fact that only NB events have restrictions. Consequently,
 218   * if a counter is available, there is a guarantee the NB event
 219   * will be assigned to it. If no slot is available, an empty
 220   * constraint is returned and scheduling will eventually fail
 221   * for this event.
 222   *
 223   * Note that all cores attached the same NB compete for the same
 224   * counters to host NB events, this is why we use atomic ops. Some
 225   * multi-chip CPUs may have more than one NB.
 226   *
 227   * Given that resources are allocated (cmpxchg), they must be
 228   * eventually freed for others to use. This is accomplished by
 229   * calling amd_put_event_constraints().
 230   *
 231   * Non NB events are not impacted by this restriction.
 232   */
 233 static struct event_constraint *
 234 amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 235 {
 236         struct hw_perf_event *hwc = &event->hw;
 237         struct amd_nb *nb = cpuc->amd_nb;
 238         struct perf_event *old = NULL;
 239         int max = x86_pmu.num_counters;
 240         int i, j, k = -1;
 241
 242         /*
 243          * if not NB event or no NB, then no constraints
 244          */
 245         if (!(amd_has_nb(cpuc) && amd_is_nb_event(hwc)))
 246                 return &unconstrained;
 247
 248         /*
 249          * detect if already present, if so reuse
 250          *
 251          * cannot merge with actual allocation
 252          * because of possible holes
 253          *
 254          * event can already be present yet not assigned (in hwc->idx)
 255          * because of successive calls to x86_schedule_events() from
 256          * hw_perf_group_sched_in() without hw_perf_enable()
 257          */
 258         for (i = 0; i < max; i++) {
 259                 /*
 260                  * keep track of first free slot
 261                  */
 262                 if (k == -1 && !nb->owners[i])
 263                         k = i;
 264
 265                 /* already present, reuse */
 266                 if (nb->owners[i] == event)
 267                         goto done;
 268         }
 269         /*
 270          * not present, so grab a new slot
 271          * starting either at:
 272          */
 273         if (hwc->idx != -1) {
 274                 /* previous assignment */
 275                 i = hwc->idx;
 276         } else if (k != -1) {
 277                 /* start from free slot found */
 278                 i = k;
 279         } else {
 280                 /*
 281                  * event not found, no slot found in
 282                  * first pass, try again from the
 283                  * beginning
 284                  */
 285                 i = 0;
 286         }
 287         j = i;
 288         do {
 289                 old = cmpxchg(nb->owners+i, NULL, event);
 290                 if (!old)
 291                         break;
 292                 if (++i == max)
 293                         i = 0;
 294         } while (i != j);
 295 done:
 296         if (!old)
 297                 return &nb->event_constraints[i];
 298
 299         return &emptyconstraint;
 300 }
 301
 302 static struct amd_nb *amd_alloc_nb(int cpu)
 303 {
 304         struct amd_nb *nb;
 305         int i;
 306
 307         nb = kmalloc_node(sizeof(struct amd_nb), GFP_KERNEL | __GFP_ZERO,
 308                           cpu_to_node(cpu));
 309         if (!nb)
 310                 return NULL;
 311
 312         nb->nb_id = -1;
 313
 314         /*
 315          * initialize all possible NB constraints
 316          */
 317         for (i = 0; i < x86_pmu.num_counters; i++) {
 318                 __set_bit(i, nb->event_constraints[i].idxmsk);
 319                 nb->event_constraints[i].weight = 1;
 320         }
 321         return nb;
 322 }
 323
 324 static int amd_pmu_cpu_prepare(int cpu)
 325 {
 326         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
 327
 328         WARN_ON_ONCE(cpuc->amd_nb);
 329
 330         if (boot_cpu_data.x86_max_cores < 2)
 331                 return NOTIFY_OK;
 332
 333         cpuc->amd_nb = amd_alloc_nb(cpu);
 334         if (!cpuc->amd_nb)
 335                 return NOTIFY_BAD;
 336
 337         return NOTIFY_OK;
 338 }
 339
 340 static void amd_pmu_cpu_starting(int cpu)
 341 {
 342         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
 343         struct amd_nb *nb;
 344         int i, nb_id;
 345
 346         if (boot_cpu_data.x86_max_cores < 2)
 347                 return;
 348
 349         nb_id = amd_get_nb_id(cpu);
 350         WARN_ON_ONCE(nb_id == BAD_APICID);
 351
 352         for_each_online_cpu(i) {
 353                 nb = per_cpu(cpu_hw_events, i).amd_nb;
 354                 if (WARN_ON_ONCE(!nb))
 355                         continue;
 356
 357                 if (nb->nb_id == nb_id) {
 358                         cpuc->kfree_on_online = cpuc->amd_nb;
 359                         cpuc->amd_nb = nb;
 360                         break;
 361                 }
 362         }
 363
 364         cpuc->amd_nb->nb_id = nb_id;
 365         cpuc->amd_nb->refcnt++;
 366 }
 367
 368 static void amd_pmu_cpu_dead(int cpu)
 369 {
 370         struct cpu_hw_events *cpuhw;
 371
 372         if (boot_cpu_data.x86_max_cores < 2)
 373                 return;
 374
 375         cpuhw = &per_cpu(cpu_hw_events, cpu);
 376
 377         if (cpuhw->amd_nb) {
 378                 struct amd_nb *nb = cpuhw->amd_nb;
 379
 380                 if (nb->nb_id == -1 || --nb->refcnt == 0)
 381                         kfree(nb);
 382
 383                 cpuhw->amd_nb = NULL;
 384         }
 385 }
 386
 387 static __initconst const struct x86_pmu amd_pmu = {
 388         .name                   = "AMD",
 389         .handle_irq             = x86_pmu_handle_irq,
 390         .disable_all            = x86_pmu_disable_all,
 391         .enable_all             = x86_pmu_enable_all,
 392         .enable                 = x86_pmu_enable_event,
 393         .disable                = x86_pmu_disable_event,
 394         .hw_config              = amd_pmu_hw_config,
 395         .schedule_events        = x86_schedule_events,
 396         .eventsel               = MSR_K7_EVNTSEL0,
 397         .perfctr                = MSR_K7_PERFCTR0,
 398         .event_map              = amd_pmu_event_map,
 399         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
 400         .num_counters           = 4,
 401         .cntval_bits            = 48,
 402         .cntval_mask            = (1ULL << 48) - 1,
 403         .apic                   = 1,
 404         /* use highest bit to detect overflow */
 405         .max_period             = (1ULL << 47) - 1,
 406         .get_event_constraints  = amd_get_event_constraints,
 407         .put_event_constraints  = amd_put_event_constraints,
 408
 409         .cpu_prepare            = amd_pmu_cpu_prepare,
 410         .cpu_starting           = amd_pmu_cpu_starting,
 411         .cpu_dead               = amd_pmu_cpu_dead,
 412 };
 413
 414 /* AMD Family 15h */
 415
 416 #define AMD_EVENT_TYPE_MASK     0x000000F0ULL
 417
 418 #define AMD_EVENT_FP            0x00000000ULL ... 0x00000010ULL
 419 #define AMD_EVENT_LS            0x00000020ULL ... 0x00000030ULL
 420 #define AMD_EVENT_DC            0x00000040ULL ... 0x00000050ULL
 421 #define AMD_EVENT_CU            0x00000060ULL ... 0x00000070ULL
 422 #define AMD_EVENT_IC_DE         0x00000080ULL ... 0x00000090ULL
 423 #define AMD_EVENT_EX_LS         0x000000C0ULL
 424 #define AMD_EVENT_DE            0x000000D0ULL
 425 #define AMD_EVENT_NB            0x000000E0ULL ... 0x000000F0ULL
 426
 427 /*
 428  * AMD family 15h event code/PMC mappings:
 429  *
 430  * type = event_code & 0x0F0:
 431  *
 432  * 0x000        FP      PERF_CTL[5:3]
 433  * 0x010        FP      PERF_CTL[5:3]
 434  * 0x020        LS      PERF_CTL[5:0]
 435  * 0x030        LS      PERF_CTL[5:0]
 436  * 0x040        DC      PERF_CTL[5:0]
 437  * 0x050        DC      PERF_CTL[5:0]
 438  * 0x060        CU      PERF_CTL[2:0]
 439  * 0x070        CU      PERF_CTL[2:0]
 440  * 0x080        IC/DE   PERF_CTL[2:0]
 441  * 0x090        IC/DE   PERF_CTL[2:0]
 442  * 0x0A0        ---
 443  * 0x0B0        ---
 444  * 0x0C0        EX/LS   PERF_CTL[5:0]
 445  * 0x0D0        DE      PERF_CTL[2:0]
 446  * 0x0E0        NB      NB_PERF_CTL[3:0]
 447  * 0x0F0        NB      NB_PERF_CTL[3:0]
 448  *
 449  * Exceptions:
 450  *
 451  * 0x000        FP      PERF_CTL[3], PERF_CTL[5:3] (*)
 452  * 0x003        FP      PERF_CTL[3]
 453  * 0x004        FP      PERF_CTL[3], PERF_CTL[5:3] (*)
 454  * 0x00B        FP      PERF_CTL[3]
 455  * 0x00D        FP      PERF_CTL[3]
 456  * 0x023        DE      PERF_CTL[2:0]
 457  * 0x02D        LS      PERF_CTL[3]
 458  * 0x02E        LS      PERF_CTL[3,0]
 459  * 0x043        CU      PERF_CTL[2:0]
 460  * 0x045        CU      PERF_CTL[2:0]
 461  * 0x046        CU      PERF_CTL[2:0]
 462  * 0x054        CU      PERF_CTL[2:0]
 463  * 0x055        CU      PERF_CTL[2:0]
 464  * 0x08F        IC      PERF_CTL[0]
 465  * 0x187        DE      PERF_CTL[0]
 466  * 0x188        DE      PERF_CTL[0]
 467  * 0x0DB        EX      PERF_CTL[5:0]
 468  * 0x0DC        LS      PERF_CTL[5:0]
 469  * 0x0DD        LS      PERF_CTL[5:0]
 470  * 0x0DE        LS      PERF_CTL[5:0]
 471  * 0x0DF        LS      PERF_CTL[5:0]
 472  * 0x1D6        EX      PERF_CTL[5:0]
 473  * 0x1D8        EX      PERF_CTL[5:0]
 474  *
 475  * (*) depending on the umask all FPU counters may be used
 476  */
 477
 478 static struct event_constraint amd_f15_PMC0  = EVENT_CONSTRAINT(0, 0x01, 0);
 479 static struct event_constraint amd_f15_PMC20 = EVENT_CONSTRAINT(0, 0x07, 0);
 480 static struct event_constraint amd_f15_PMC3  = EVENT_CONSTRAINT(0, 0x08, 0);
 481 static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT(0, 0x09, 0);
 482 static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
 483 static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
 484
 485 static struct event_constraint *
 486 amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
 487 {
 488         struct hw_perf_event *hwc = &event->hw;
 489         unsigned int event_code = amd_get_event_code(hwc);
 490
 491         switch (event_code & AMD_EVENT_TYPE_MASK) {
 492         case AMD_EVENT_FP:
 493                 switch (event_code) {
 494                 case 0x000:
 495                         if (!(hwc->config & 0x0000F000ULL))
 496                                 break;
 497                         if (!(hwc->config & 0x00000F00ULL))
 498                                 break;
 499                         return &amd_f15_PMC3;
 500                 case 0x004:
 501                         if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
 502                                 break;
 503                         return &amd_f15_PMC3;
 504                 case 0x003:
 505                 case 0x00B:
 506                 case 0x00D:
 507                         return &amd_f15_PMC3;
 508                 }
 509                 return &amd_f15_PMC53;
 510         case AMD_EVENT_LS:
 511         case AMD_EVENT_DC:
 512         case AMD_EVENT_EX_LS:
 513                 switch (event_code) {
 514                 case 0x023:
 515                 case 0x043:
 516                 case 0x045:
 517                 case 0x046:
 518                 case 0x054:
 519                 case 0x055:
 520                         return &amd_f15_PMC20;
 521                 case 0x02D:
 522                         return &amd_f15_PMC3;
 523                 case 0x02E:
 524                         return &amd_f15_PMC30;
 525                 default:
 526                         return &amd_f15_PMC50;
 527                 }
 528         case AMD_EVENT_CU:
 529         case AMD_EVENT_IC_DE:
 530         case AMD_EVENT_DE:
 531                 switch (event_code) {
 532                 case 0x08F:
 533                 case 0x187:
 534                 case 0x188:
 535                         return &amd_f15_PMC0;
 536                 case 0x0DB ... 0x0DF:
 537                 case 0x1D6:
 538                 case 0x1D8:
 539                         return &amd_f15_PMC50;
 540                 default:
 541                         return &amd_f15_PMC20;
 542                 }
 543         case AMD_EVENT_NB:
 544                 /* not yet implemented */
 545                 return &emptyconstraint;
 546         default:
 547                 return &emptyconstraint;
 548         }
 549 }
 550
 551 static __initconst const struct x86_pmu amd_pmu_f15h = {
 552         .name                   = "AMD Family 15h",
 553         .handle_irq             = x86_pmu_handle_irq,
 554         .disable_all            = x86_pmu_disable_all,
 555         .enable_all             = x86_pmu_enable_all,
 556         .enable                 = x86_pmu_enable_event,
 557         .disable                = x86_pmu_disable_event,
 558         .hw_config              = amd_pmu_hw_config,
 559         .schedule_events        = x86_schedule_events,
 560         .eventsel               = MSR_F15H_PERF_CTL,
 561         .perfctr                = MSR_F15H_PERF_CTR,
 562         .event_map              = amd_pmu_event_map,
 563         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
 564         .num_counters           = 6,
 565         .cntval_bits            = 48,
 566         .cntval_mask            = (1ULL << 48) - 1,
 567         .apic                   = 1,
 568         /* use highest bit to detect overflow */
 569         .max_period             = (1ULL << 47) - 1,
 570         .get_event_constraints  = amd_get_event_constraints_f15h,
 571         /* nortbridge counters not yet implemented: */
 572 #if 0
 573         .put_event_constraints  = amd_put_event_constraints,
 574
 575         .cpu_prepare            = amd_pmu_cpu_prepare,
 576         .cpu_starting           = amd_pmu_cpu_starting,
 577         .cpu_dead               = amd_pmu_cpu_dead,
 578 #endif
 579 };
 580
 581 __init int amd_pmu_init(void)
 582 {
 583         /* Performance-monitoring supported from K7 and later: */
 584         if (boot_cpu_data.x86 < 6)
 585                 return -ENODEV;
 586
 587         /*
 588          * If core performance counter extensions exists, it must be
 589          * family 15h, otherwise fail. See x86_pmu_addr_offset().
 590          */
 591         switch (boot_cpu_data.x86) {
 592         case 0x15:
 593                 if (!cpu_has_perfctr_core)
 594                         return -ENODEV;
 595                 x86_pmu = amd_pmu_f15h;
 596                 break;
 597         default:
 598                 if (cpu_has_perfctr_core)
 599                         return -ENODEV;
 600                 x86_pmu = amd_pmu;
 601                 break;
 602         }
 603
 604         /* Events are common for all AMDs */
 605         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
 606                sizeof(hw_cache_event_ids));
 607
 608         return 0;
 609 }