arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         int type = in_nmi() ? KM_NMI : KM_IRQ0;
  53         unsigned long size, len = 0;
  54         struct page *page;
  55         void *map;
  56         int ret;
  57
  58         do {
  59                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  60                 if (!ret)
  61                         break;
  62
  63                 offset = addr & (PAGE_SIZE - 1);
  64                 size = min(PAGE_SIZE - offset, n - len);
  65
  66                 map = kmap_atomic(page, type);
  67                 memcpy(to, map+offset, size);
  68                 kunmap_atomic(map, type);
  69                 put_page(page);
  70
  71                 len  += size;
  72                 to   += size;
  73                 addr += size;
  74
  75         } while (len < n);
  76
  77         return len;
  78 }
  79
  80 struct event_constraint {
  81         union {
  82                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  83                 u64             idxmsk64;
  84         };
  85         u64     code;
  86         u64     cmask;
  87         int     weight;
  88 };
  89
  90 struct amd_nb {
  91         int nb_id;  /* NorthBridge id */
  92         int refcnt; /* reference count */
  93         struct perf_event *owners[X86_PMC_IDX_MAX];
  94         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  95 };
  96
  97 #define MAX_LBR_ENTRIES         16
  98
  99 struct cpu_hw_events {
 100         /*
 101          * Generic x86 PMC bits
 102          */
 103         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 104         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 106         int                     enabled;
 107
 108         int                     n_events;
 109         int                     n_added;
 110         int                     n_txn;
 111         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 112         u64                     tags[X86_PMC_IDX_MAX];
 113         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 114
 115         unsigned int            group_flag;
 116
 117         /*
 118          * Intel DebugStore bits
 119          */
 120         struct debug_store      *ds;
 121         u64                     pebs_enabled;
 122
 123         /*
 124          * Intel LBR bits
 125          */
 126         int                             lbr_users;
 127         void                            *lbr_context;
 128         struct perf_branch_stack        lbr_stack;
 129         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 130
 131         /*
 132          * AMD specific bits
 133          */
 134         struct amd_nb           *amd_nb;
 135 };
 136
 137 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 138         { .idxmsk64 = (n) },            \
 139         .code = (c),                    \
 140         .cmask = (m),                   \
 141         .weight = (w),                  \
 142 }
 143
 144 #define EVENT_CONSTRAINT(c, n, m)       \
 145         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 146
 147 /*
 148  * Constraint on the Event code.
 149  */
 150 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 151         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 152
 153 /*
 154  * Constraint on the Event code + UMask + fixed-mask
 155  *
 156  * filter mask to validate fixed counter events.
 157  * the following filters disqualify for fixed counters:
 158  *  - inv
 159  *  - edge
 160  *  - cnt-mask
 161  *  The other filters are supported by fixed counters.
 162  *  The any-thread option is supported starting with v3.
 163  */
 164 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 165         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 166
 167 /*
 168  * Constraint on the Event code + UMask
 169  */
 170 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 171         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 172
 173 #define EVENT_CONSTRAINT_END            \
 174         EVENT_CONSTRAINT(0, 0, 0)
 175
 176 #define for_each_event_constraint(e, c) \
 177         for ((e) = (c); (e)->weight; (e)++)
 178
 179 union perf_capabilities {
 180         struct {
 181                 u64     lbr_format    : 6;
 182                 u64     pebs_trap     : 1;
 183                 u64     pebs_arch_reg : 1;
 184                 u64     pebs_format   : 4;
 185                 u64     smm_freeze    : 1;
 186         };
 187         u64     capabilities;
 188 };
 189
 190 /*
 191  * struct x86_pmu - generic x86 pmu
 192  */
 193 struct x86_pmu {
 194         /*
 195          * Generic x86 PMC bits
 196          */
 197         const char      *name;
 198         int             version;
 199         int             (*handle_irq)(struct pt_regs *);
 200         void            (*disable_all)(void);
 201         void            (*enable_all)(int added);
 202         void            (*enable)(struct perf_event *);
 203         void            (*disable)(struct perf_event *);
 204         int             (*hw_config)(struct perf_event *event);
 205         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 206         unsigned        eventsel;
 207         unsigned        perfctr;
 208         u64             (*event_map)(int);
 209         int             max_events;
 210         int             num_counters;
 211         int             num_counters_fixed;
 212         int             cntval_bits;
 213         u64             cntval_mask;
 214         int             apic;
 215         u64             max_period;
 216         struct event_constraint *
 217                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 218                                                  struct perf_event *event);
 219
 220         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 221                                                  struct perf_event *event);
 222         struct event_constraint *event_constraints;
 223         void            (*quirks)(void);
 224         int             perfctr_second_write;
 225
 226         int             (*cpu_prepare)(int cpu);
 227         void            (*cpu_starting)(int cpu);
 228         void            (*cpu_dying)(int cpu);
 229         void            (*cpu_dead)(int cpu);
 230
 231         /*
 232          * Intel Arch Perfmon v2+
 233          */
 234         u64                     intel_ctrl;
 235         union perf_capabilities intel_cap;
 236
 237         /*
 238          * Intel DebugStore bits
 239          */
 240         int             bts, pebs;
 241         int             pebs_record_size;
 242         void            (*drain_pebs)(struct pt_regs *regs);
 243         struct event_constraint *pebs_constraints;
 244
 245         /*
 246          * Intel LBR
 247          */
 248         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 249         int             lbr_nr;                    /* hardware stack size */
 250 };
 251
 252 static struct x86_pmu x86_pmu __read_mostly;
 253
 254 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 255         .enabled = 1,
 256 };
 257
 258 static int x86_perf_event_set_period(struct perf_event *event);
 259
 260 /*
 261  * Generalized hw caching related hw_event table, filled
 262  * in on a per model basis. A value of 0 means
 263  * 'not supported', -1 means 'hw_event makes no sense on
 264  * this CPU', any other value means the raw hw_event
 265  * ID.
 266  */
 267
 268 #define C(x) PERF_COUNT_HW_CACHE_##x
 269
 270 static u64 __read_mostly hw_cache_event_ids
 271                                 [PERF_COUNT_HW_CACHE_MAX]
 272                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 273                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 274
 275 /*
 276  * Propagate event elapsed time into the generic event.
 277  * Can only be executed on the CPU where the event is active.
 278  * Returns the delta events processed.
 279  */
 280 static u64
 281 x86_perf_event_update(struct perf_event *event)
 282 {
 283         struct hw_perf_event *hwc = &event->hw;
 284         int shift = 64 - x86_pmu.cntval_bits;
 285         u64 prev_raw_count, new_raw_count;
 286         int idx = hwc->idx;
 287         s64 delta;
 288
 289         if (idx == X86_PMC_IDX_FIXED_BTS)
 290                 return 0;
 291
 292         /*
 293          * Careful: an NMI might modify the previous event value.
 294          *
 295          * Our tactic to handle this is to first atomically read and
 296          * exchange a new raw count - then add that new-prev delta
 297          * count to the generic event atomically:
 298          */
 299 again:
 300         prev_raw_count = local64_read(&hwc->prev_count);
 301         rdmsrl(hwc->event_base + idx, new_raw_count);
 302
 303         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 304                                         new_raw_count) != prev_raw_count)
 305                 goto again;
 306
 307         /*
 308          * Now we have the new raw value and have updated the prev
 309          * timestamp already. We can now calculate the elapsed delta
 310          * (event-)time and add that to the generic event.
 311          *
 312          * Careful, not all hw sign-extends above the physical width
 313          * of the count.
 314          */
 315         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 316         delta >>= shift;
 317
 318         local64_add(delta, &event->count);
 319         local64_sub(delta, &hwc->period_left);
 320
 321         return new_raw_count;
 322 }
 323
 324 static atomic_t active_events;
 325 static DEFINE_MUTEX(pmc_reserve_mutex);
 326
 327 #ifdef CONFIG_X86_LOCAL_APIC
 328
 329 static bool reserve_pmc_hardware(void)
 330 {
 331         int i;
 332
 333         if (nmi_watchdog == NMI_LOCAL_APIC)
 334                 disable_lapic_nmi_watchdog();
 335
 336         for (i = 0; i < x86_pmu.num_counters; i++) {
 337                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 338                         goto perfctr_fail;
 339         }
 340
 341         for (i = 0; i < x86_pmu.num_counters; i++) {
 342                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 343                         goto eventsel_fail;
 344         }
 345
 346         return true;
 347
 348 eventsel_fail:
 349         for (i--; i >= 0; i--)
 350                 release_evntsel_nmi(x86_pmu.eventsel + i);
 351
 352         i = x86_pmu.num_counters;
 353
 354 perfctr_fail:
 355         for (i--; i >= 0; i--)
 356                 release_perfctr_nmi(x86_pmu.perfctr + i);
 357
 358         if (nmi_watchdog == NMI_LOCAL_APIC)
 359                 enable_lapic_nmi_watchdog();
 360
 361         return false;
 362 }
 363
 364 static void release_pmc_hardware(void)
 365 {
 366         int i;
 367
 368         for (i = 0; i < x86_pmu.num_counters; i++) {
 369                 release_perfctr_nmi(x86_pmu.perfctr + i);
 370                 release_evntsel_nmi(x86_pmu.eventsel + i);
 371         }
 372
 373         if (nmi_watchdog == NMI_LOCAL_APIC)
 374                 enable_lapic_nmi_watchdog();
 375 }
 376
 377 #else
 378
 379 static bool reserve_pmc_hardware(void) { return true; }
 380 static void release_pmc_hardware(void) {}
 381
 382 #endif
 383
 384 static int reserve_ds_buffers(void);
 385 static void release_ds_buffers(void);
 386
 387 static void hw_perf_event_destroy(struct perf_event *event)
 388 {
 389         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 390                 release_pmc_hardware();
 391                 release_ds_buffers();
 392                 mutex_unlock(&pmc_reserve_mutex);
 393         }
 394 }
 395
 396 static inline int x86_pmu_initialized(void)
 397 {
 398         return x86_pmu.handle_irq != NULL;
 399 }
 400
 401 static inline int
 402 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 403 {
 404         unsigned int cache_type, cache_op, cache_result;
 405         u64 config, val;
 406
 407         config = attr->config;
 408
 409         cache_type = (config >>  0) & 0xff;
 410         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 411                 return -EINVAL;
 412
 413         cache_op = (config >>  8) & 0xff;
 414         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 415                 return -EINVAL;
 416
 417         cache_result = (config >> 16) & 0xff;
 418         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 419                 return -EINVAL;
 420
 421         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 422
 423         if (val == 0)
 424                 return -ENOENT;
 425
 426         if (val == -1)
 427                 return -EINVAL;
 428
 429         hwc->config |= val;
 430
 431         return 0;
 432 }
 433
 434 static int x86_setup_perfctr(struct perf_event *event)
 435 {
 436         struct perf_event_attr *attr = &event->attr;
 437         struct hw_perf_event *hwc = &event->hw;
 438         u64 config;
 439
 440         if (!hwc->sample_period) {
 441                 hwc->sample_period = x86_pmu.max_period;
 442                 hwc->last_period = hwc->sample_period;
 443                 local64_set(&hwc->period_left, hwc->sample_period);
 444         } else {
 445                 /*
 446                  * If we have a PMU initialized but no APIC
 447                  * interrupts, we cannot sample hardware
 448                  * events (user-space has to fall back and
 449                  * sample via a hrtimer based software event):
 450                  */
 451                 if (!x86_pmu.apic)
 452                         return -EOPNOTSUPP;
 453         }
 454
 455         if (attr->type == PERF_TYPE_RAW)
 456                 return 0;
 457
 458         if (attr->type == PERF_TYPE_HW_CACHE)
 459                 return set_ext_hw_attr(hwc, attr);
 460
 461         if (attr->config >= x86_pmu.max_events)
 462                 return -EINVAL;
 463
 464         /*
 465          * The generic map:
 466          */
 467         config = x86_pmu.event_map(attr->config);
 468
 469         if (config == 0)
 470                 return -ENOENT;
 471
 472         if (config == -1LL)
 473                 return -EINVAL;
 474
 475         /*
 476          * Branch tracing:
 477          */
 478         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 479             (hwc->sample_period == 1)) {
 480                 /* BTS is not supported by this architecture. */
 481                 if (!x86_pmu.bts)
 482                         return -EOPNOTSUPP;
 483
 484                 /* BTS is currently only allowed for user-mode. */
 485                 if (!attr->exclude_kernel)
 486                         return -EOPNOTSUPP;
 487         }
 488
 489         hwc->config |= config;
 490
 491         return 0;
 492 }
 493
 494 static int x86_pmu_hw_config(struct perf_event *event)
 495 {
 496         if (event->attr.precise_ip) {
 497                 int precise = 0;
 498
 499                 /* Support for constant skid */
 500                 if (x86_pmu.pebs) {
 501                         precise++;
 502
 503                         /* Support for IP fixup */
 504                         if (x86_pmu.lbr_nr)
 505                                 precise++;
 506                 }
 507
 508                 if (event->attr.precise_ip > precise)
 509                         return -EOPNOTSUPP;
 510         }
 511
 512         /*
 513          * Generate PMC IRQs:
 514          * (keep 'enabled' bit clear for now)
 515          */
 516         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 517
 518         /*
 519          * Count user and OS events unless requested not to
 520          */
 521         if (!event->attr.exclude_user)
 522                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 523         if (!event->attr.exclude_kernel)
 524                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 525
 526         if (event->attr.type == PERF_TYPE_RAW)
 527                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 528
 529         return x86_setup_perfctr(event);
 530 }
 531
 532 /*
 533  * Setup the hardware configuration for a given attr_type
 534  */
 535 static int __x86_pmu_event_init(struct perf_event *event)
 536 {
 537         int err;
 538
 539         if (!x86_pmu_initialized())
 540                 return -ENODEV;
 541
 542         err = 0;
 543         if (!atomic_inc_not_zero(&active_events)) {
 544                 mutex_lock(&pmc_reserve_mutex);
 545                 if (atomic_read(&active_events) == 0) {
 546                         if (!reserve_pmc_hardware())
 547                                 err = -EBUSY;
 548                         else {
 549                                 err = reserve_ds_buffers();
 550                                 if (err)
 551                                         release_pmc_hardware();
 552                         }
 553                 }
 554                 if (!err)
 555                         atomic_inc(&active_events);
 556                 mutex_unlock(&pmc_reserve_mutex);
 557         }
 558         if (err)
 559                 return err;
 560
 561         event->destroy = hw_perf_event_destroy;
 562
 563         event->hw.idx = -1;
 564         event->hw.last_cpu = -1;
 565         event->hw.last_tag = ~0ULL;
 566
 567         return x86_pmu.hw_config(event);
 568 }
 569
 570 static void x86_pmu_disable_all(void)
 571 {
 572         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 573         int idx;
 574
 575         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 576                 u64 val;
 577
 578                 if (!test_bit(idx, cpuc->active_mask))
 579                         continue;
 580                 rdmsrl(x86_pmu.eventsel + idx, val);
 581                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 582                         continue;
 583                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 584                 wrmsrl(x86_pmu.eventsel + idx, val);
 585         }
 586 }
 587
 588 static void x86_pmu_disable(struct pmu *pmu)
 589 {
 590         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 591
 592         if (!x86_pmu_initialized())
 593                 return;
 594
 595         if (!cpuc->enabled)
 596                 return;
 597
 598         cpuc->n_added = 0;
 599         cpuc->enabled = 0;
 600         barrier();
 601
 602         x86_pmu.disable_all();
 603 }
 604
 605 static void x86_pmu_enable_all(int added)
 606 {
 607         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 608         int idx;
 609
 610         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 611                 struct perf_event *event = cpuc->events[idx];
 612                 u64 val;
 613
 614                 if (!test_bit(idx, cpuc->active_mask))
 615                         continue;
 616
 617                 val = event->hw.config;
 618                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 619                 wrmsrl(x86_pmu.eventsel + idx, val);
 620         }
 621 }
 622
 623 static struct pmu pmu;
 624
 625 static inline int is_x86_event(struct perf_event *event)
 626 {
 627         return event->pmu == &pmu;
 628 }
 629
 630 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 631 {
 632         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 633         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 634         int i, j, w, wmax, num = 0;
 635         struct hw_perf_event *hwc;
 636
 637         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 638
 639         for (i = 0; i < n; i++) {
 640                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 641                 constraints[i] = c;
 642         }
 643
 644         /*
 645          * fastpath, try to reuse previous register
 646          */
 647         for (i = 0; i < n; i++) {
 648                 hwc = &cpuc->event_list[i]->hw;
 649                 c = constraints[i];
 650
 651                 /* never assigned */
 652                 if (hwc->idx == -1)
 653                         break;
 654
 655                 /* constraint still honored */
 656                 if (!test_bit(hwc->idx, c->idxmsk))
 657                         break;
 658
 659                 /* not already used */
 660                 if (test_bit(hwc->idx, used_mask))
 661                         break;
 662
 663                 __set_bit(hwc->idx, used_mask);
 664                 if (assign)
 665                         assign[i] = hwc->idx;
 666         }
 667         if (i == n)
 668                 goto done;
 669
 670         /*
 671          * begin slow path
 672          */
 673
 674         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 675
 676         /*
 677          * weight = number of possible counters
 678          *
 679          * 1    = most constrained, only works on one counter
 680          * wmax = least constrained, works on any counter
 681          *
 682          * assign events to counters starting with most
 683          * constrained events.
 684          */
 685         wmax = x86_pmu.num_counters;
 686
 687         /*
 688          * when fixed event counters are present,
 689          * wmax is incremented by 1 to account
 690          * for one more choice
 691          */
 692         if (x86_pmu.num_counters_fixed)
 693                 wmax++;
 694
 695         for (w = 1, num = n; num && w <= wmax; w++) {
 696                 /* for each event */
 697                 for (i = 0; num && i < n; i++) {
 698                         c = constraints[i];
 699                         hwc = &cpuc->event_list[i]->hw;
 700
 701                         if (c->weight != w)
 702                                 continue;
 703
 704                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 705                                 if (!test_bit(j, used_mask))
 706                                         break;
 707                         }
 708
 709                         if (j == X86_PMC_IDX_MAX)
 710                                 break;
 711
 712                         __set_bit(j, used_mask);
 713
 714                         if (assign)
 715                                 assign[i] = j;
 716                         num--;
 717                 }
 718         }
 719 done:
 720         /*
 721          * scheduling failed or is just a simulation,
 722          * free resources if necessary
 723          */
 724         if (!assign || num) {
 725                 for (i = 0; i < n; i++) {
 726                         if (x86_pmu.put_event_constraints)
 727                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 728                 }
 729         }
 730         return num ? -ENOSPC : 0;
 731 }
 732
 733 /*
 734  * dogrp: true if must collect siblings events (group)
 735  * returns total number of events and error code
 736  */
 737 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 738 {
 739         struct perf_event *event;
 740         int n, max_count;
 741
 742         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 743
 744         /* current number of events already accepted */
 745         n = cpuc->n_events;
 746
 747         if (is_x86_event(leader)) {
 748                 if (n >= max_count)
 749                         return -ENOSPC;
 750                 cpuc->event_list[n] = leader;
 751                 n++;
 752         }
 753         if (!dogrp)
 754                 return n;
 755
 756         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 757                 if (!is_x86_event(event) ||
 758                     event->state <= PERF_EVENT_STATE_OFF)
 759                         continue;
 760
 761                 if (n >= max_count)
 762                         return -ENOSPC;
 763
 764                 cpuc->event_list[n] = event;
 765                 n++;
 766         }
 767         return n;
 768 }
 769
 770 static inline void x86_assign_hw_event(struct perf_event *event,
 771                                 struct cpu_hw_events *cpuc, int i)
 772 {
 773         struct hw_perf_event *hwc = &event->hw;
 774
 775         hwc->idx = cpuc->assign[i];
 776         hwc->last_cpu = smp_processor_id();
 777         hwc->last_tag = ++cpuc->tags[i];
 778
 779         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 780                 hwc->config_base = 0;
 781                 hwc->event_base = 0;
 782         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 783                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 784                 /*
 785                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 786                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 787                  */
 788                 hwc->event_base =
 789                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 790         } else {
 791                 hwc->config_base = x86_pmu.eventsel;
 792                 hwc->event_base  = x86_pmu.perfctr;
 793         }
 794 }
 795
 796 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 797                                         struct cpu_hw_events *cpuc,
 798                                         int i)
 799 {
 800         return hwc->idx == cpuc->assign[i] &&
 801                 hwc->last_cpu == smp_processor_id() &&
 802                 hwc->last_tag == cpuc->tags[i];
 803 }
 804
 805 static void x86_pmu_start(struct perf_event *event, int flags);
 806 static void x86_pmu_stop(struct perf_event *event, int flags);
 807
 808 static void x86_pmu_enable(struct pmu *pmu)
 809 {
 810         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 811         struct perf_event *event;
 812         struct hw_perf_event *hwc;
 813         int i, added = cpuc->n_added;
 814
 815         if (!x86_pmu_initialized())
 816                 return;
 817
 818         if (cpuc->enabled)
 819                 return;
 820
 821         if (cpuc->n_added) {
 822                 int n_running = cpuc->n_events - cpuc->n_added;
 823                 /*
 824                  * apply assignment obtained either from
 825                  * hw_perf_group_sched_in() or x86_pmu_enable()
 826                  *
 827                  * step1: save events moving to new counters
 828                  * step2: reprogram moved events into new counters
 829                  */
 830                 for (i = 0; i < n_running; i++) {
 831                         event = cpuc->event_list[i];
 832                         hwc = &event->hw;
 833
 834                         /*
 835                          * we can avoid reprogramming counter if:
 836                          * - assigned same counter as last time
 837                          * - running on same CPU as last time
 838                          * - no other event has used the counter since
 839                          */
 840                         if (hwc->idx == -1 ||
 841                             match_prev_assignment(hwc, cpuc, i))
 842                                 continue;
 843
 844                         /*
 845                          * Ensure we don't accidentally enable a stopped
 846                          * counter simply because we rescheduled.
 847                          */
 848                         if (hwc->state & PERF_HES_STOPPED)
 849                                 hwc->state |= PERF_HES_ARCH;
 850
 851                         x86_pmu_stop(event, PERF_EF_UPDATE);
 852                 }
 853
 854                 for (i = 0; i < cpuc->n_events; i++) {
 855                         event = cpuc->event_list[i];
 856                         hwc = &event->hw;
 857
 858                         if (!match_prev_assignment(hwc, cpuc, i))
 859                                 x86_assign_hw_event(event, cpuc, i);
 860                         else if (i < n_running)
 861                                 continue;
 862
 863                         if (hwc->state & PERF_HES_ARCH)
 864                                 continue;
 865
 866                         x86_pmu_start(event, PERF_EF_RELOAD);
 867                 }
 868                 cpuc->n_added = 0;
 869                 perf_events_lapic_init();
 870         }
 871
 872         cpuc->enabled = 1;
 873         barrier();
 874
 875         x86_pmu.enable_all(added);
 876 }
 877
 878 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 879                                           u64 enable_mask)
 880 {
 881         wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
 882 }
 883
 884 static inline void x86_pmu_disable_event(struct perf_event *event)
 885 {
 886         struct hw_perf_event *hwc = &event->hw;
 887
 888         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 889 }
 890
 891 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 892
 893 /*
 894  * Set the next IRQ period, based on the hwc->period_left value.
 895  * To be called with the event disabled in hw:
 896  */
 897 static int
 898 x86_perf_event_set_period(struct perf_event *event)
 899 {
 900         struct hw_perf_event *hwc = &event->hw;
 901         s64 left = local64_read(&hwc->period_left);
 902         s64 period = hwc->sample_period;
 903         int ret = 0, idx = hwc->idx;
 904
 905         if (idx == X86_PMC_IDX_FIXED_BTS)
 906                 return 0;
 907
 908         /*
 909          * If we are way outside a reasonable range then just skip forward:
 910          */
 911         if (unlikely(left <= -period)) {
 912                 left = period;
 913                 local64_set(&hwc->period_left, left);
 914                 hwc->last_period = period;
 915                 ret = 1;
 916         }
 917
 918         if (unlikely(left <= 0)) {
 919                 left += period;
 920                 local64_set(&hwc->period_left, left);
 921                 hwc->last_period = period;
 922                 ret = 1;
 923         }
 924         /*
 925          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 926          */
 927         if (unlikely(left < 2))
 928                 left = 2;
 929
 930         if (left > x86_pmu.max_period)
 931                 left = x86_pmu.max_period;
 932
 933         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 934
 935         /*
 936          * The hw event starts counting from this event offset,
 937          * mark it to be able to extra future deltas:
 938          */
 939         local64_set(&hwc->prev_count, (u64)-left);
 940
 941         wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
 942
 943         /*
 944          * Due to erratum on certan cpu we need
 945          * a second write to be sure the register
 946          * is updated properly
 947          */
 948         if (x86_pmu.perfctr_second_write) {
 949                 wrmsrl(hwc->event_base + idx,
 950                         (u64)(-left) & x86_pmu.cntval_mask);
 951         }
 952
 953         perf_event_update_userpage(event);
 954
 955         return ret;
 956 }
 957
 958 static void x86_pmu_enable_event(struct perf_event *event)
 959 {
 960         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 961         if (cpuc->enabled)
 962                 __x86_pmu_enable_event(&event->hw,
 963                                        ARCH_PERFMON_EVENTSEL_ENABLE);
 964 }
 965
 966 /*
 967  * Add a single event to the PMU.
 968  *
 969  * The event is added to the group of enabled events
 970  * but only if it can be scehduled with existing events.
 971  */
 972 static int x86_pmu_add(struct perf_event *event, int flags)
 973 {
 974         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 975         struct hw_perf_event *hwc;
 976         int assign[X86_PMC_IDX_MAX];
 977         int n, n0, ret;
 978
 979         hwc = &event->hw;
 980
 981         perf_pmu_disable(event->pmu);
 982         n0 = cpuc->n_events;
 983         ret = n = collect_events(cpuc, event, false);
 984         if (ret < 0)
 985                 goto out;
 986
 987         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 988         if (!(flags & PERF_EF_START))
 989                 hwc->state |= PERF_HES_ARCH;
 990
 991         /*
 992          * If group events scheduling transaction was started,
 993          * skip the schedulability test here, it will be peformed
 994          * at commit time (->commit_txn) as a whole
 995          */
 996         if (cpuc->group_flag & PERF_EVENT_TXN)
 997                 goto done_collect;
 998
 999         ret = x86_pmu.schedule_events(cpuc, n, assign);
1000         if (ret)
1001                 goto out;
1002         /*
1003          * copy new assignment, now we know it is possible
1004          * will be used by hw_perf_enable()
1005          */
1006         memcpy(cpuc->assign, assign, n*sizeof(int));
1007
1008 done_collect:
1009         cpuc->n_events = n;
1010         cpuc->n_added += n - n0;
1011         cpuc->n_txn += n - n0;
1012
1013         ret = 0;
1014 out:
1015         perf_pmu_enable(event->pmu);
1016         return ret;
1017 }
1018
1019 static void x86_pmu_start(struct perf_event *event, int flags)
1020 {
1021         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1022         int idx = event->hw.idx;
1023
1024         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1025                 return;
1026
1027         if (WARN_ON_ONCE(idx == -1))
1028                 return;
1029
1030         if (flags & PERF_EF_RELOAD) {
1031                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1032                 x86_perf_event_set_period(event);
1033         }
1034
1035         event->hw.state = 0;
1036
1037         cpuc->events[idx] = event;
1038         __set_bit(idx, cpuc->active_mask);
1039         __set_bit(idx, cpuc->running);
1040         x86_pmu.enable(event);
1041         perf_event_update_userpage(event);
1042 }
1043
1044 void perf_event_print_debug(void)
1045 {
1046         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1047         u64 pebs;
1048         struct cpu_hw_events *cpuc;
1049         unsigned long flags;
1050         int cpu, idx;
1051
1052         if (!x86_pmu.num_counters)
1053                 return;
1054
1055         local_irq_save(flags);
1056
1057         cpu = smp_processor_id();
1058         cpuc = &per_cpu(cpu_hw_events, cpu);
1059
1060         if (x86_pmu.version >= 2) {
1061                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1062                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1063                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1064                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1065                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1066
1067                 pr_info("\n");
1068                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1069                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1070                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1071                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1072                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1073         }
1074         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1075
1076         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1077                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1078                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1079
1080                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1081
1082                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1083                         cpu, idx, pmc_ctrl);
1084                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1085                         cpu, idx, pmc_count);
1086                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1087                         cpu, idx, prev_left);
1088         }
1089         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1090                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1091
1092                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1093                         cpu, idx, pmc_count);
1094         }
1095         local_irq_restore(flags);
1096 }
1097
1098 static void x86_pmu_stop(struct perf_event *event, int flags)
1099 {
1100         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1101         struct hw_perf_event *hwc = &event->hw;
1102
1103         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1104                 x86_pmu.disable(event);
1105                 cpuc->events[hwc->idx] = NULL;
1106                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1107                 hwc->state |= PERF_HES_STOPPED;
1108         }
1109
1110         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1111                 /*
1112                  * Drain the remaining delta count out of a event
1113                  * that we are disabling:
1114                  */
1115                 x86_perf_event_update(event);
1116                 hwc->state |= PERF_HES_UPTODATE;
1117         }
1118 }
1119
1120 static void x86_pmu_del(struct perf_event *event, int flags)
1121 {
1122         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1123         int i;
1124
1125         /*
1126          * If we're called during a txn, we don't need to do anything.
1127          * The events never got scheduled and ->cancel_txn will truncate
1128          * the event_list.
1129          */
1130         if (cpuc->group_flag & PERF_EVENT_TXN)
1131                 return;
1132
1133         x86_pmu_stop(event, PERF_EF_UPDATE);
1134
1135         for (i = 0; i < cpuc->n_events; i++) {
1136                 if (event == cpuc->event_list[i]) {
1137
1138                         if (x86_pmu.put_event_constraints)
1139                                 x86_pmu.put_event_constraints(cpuc, event);
1140
1141                         while (++i < cpuc->n_events)
1142                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1143
1144                         --cpuc->n_events;
1145                         break;
1146                 }
1147         }
1148         perf_event_update_userpage(event);
1149 }
1150
1151 static int x86_pmu_handle_irq(struct pt_regs *regs)
1152 {
1153         struct perf_sample_data data;
1154         struct cpu_hw_events *cpuc;
1155         struct perf_event *event;
1156         int idx, handled = 0;
1157         u64 val;
1158
1159         perf_sample_data_init(&data, 0);
1160
1161         cpuc = &__get_cpu_var(cpu_hw_events);
1162
1163         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1164                 if (!test_bit(idx, cpuc->active_mask)) {
1165                         /*
1166                          * Though we deactivated the counter some cpus
1167                          * might still deliver spurious interrupts still
1168                          * in flight. Catch them:
1169                          */
1170                         if (__test_and_clear_bit(idx, cpuc->running))
1171                                 handled++;
1172                         continue;
1173                 }
1174
1175                 event = cpuc->events[idx];
1176
1177                 val = x86_perf_event_update(event);
1178                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1179                         continue;
1180
1181                 /*
1182                  * event overflow
1183                  */
1184                 handled++;
1185                 data.period     = event->hw.last_period;
1186
1187                 if (!x86_perf_event_set_period(event))
1188                         continue;
1189
1190                 if (perf_event_overflow(event, 1, &data, regs))
1191                         x86_pmu_stop(event, 0);
1192         }
1193
1194         if (handled)
1195                 inc_irq_stat(apic_perf_irqs);
1196
1197         return handled;
1198 }
1199
1200 void perf_events_lapic_init(void)
1201 {
1202         if (!x86_pmu.apic || !x86_pmu_initialized())
1203                 return;
1204
1205         /*
1206          * Always use NMI for PMU
1207          */
1208         apic_write(APIC_LVTPC, APIC_DM_NMI);
1209 }
1210
1211 struct pmu_nmi_state {
1212         unsigned int    marked;
1213         int             handled;
1214 };
1215
1216 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1217
1218 static int __kprobes
1219 perf_event_nmi_handler(struct notifier_block *self,
1220                          unsigned long cmd, void *__args)
1221 {
1222         struct die_args *args = __args;
1223         unsigned int this_nmi;
1224         int handled;
1225
1226         if (!atomic_read(&active_events))
1227                 return NOTIFY_DONE;
1228
1229         switch (cmd) {
1230         case DIE_NMI:
1231         case DIE_NMI_IPI:
1232                 break;
1233         case DIE_NMIUNKNOWN:
1234                 this_nmi = percpu_read(irq_stat.__nmi_count);
1235                 if (this_nmi != __get_cpu_var(pmu_nmi).marked)
1236                         /* let the kernel handle the unknown nmi */
1237                         return NOTIFY_DONE;
1238                 /*
1239                  * This one is a PMU back-to-back nmi. Two events
1240                  * trigger 'simultaneously' raising two back-to-back
1241                  * NMIs. If the first NMI handles both, the latter
1242                  * will be empty and daze the CPU. So, we drop it to
1243                  * avoid false-positive 'unknown nmi' messages.
1244                  */
1245                 return NOTIFY_STOP;
1246         default:
1247                 return NOTIFY_DONE;
1248         }
1249
1250         apic_write(APIC_LVTPC, APIC_DM_NMI);
1251
1252         handled = x86_pmu.handle_irq(args->regs);
1253         if (!handled)
1254                 return NOTIFY_DONE;
1255
1256         this_nmi = percpu_read(irq_stat.__nmi_count);
1257         if ((handled > 1) ||
1258                 /* the next nmi could be a back-to-back nmi */
1259             ((__get_cpu_var(pmu_nmi).marked == this_nmi) &&
1260              (__get_cpu_var(pmu_nmi).handled > 1))) {
1261                 /*
1262                  * We could have two subsequent back-to-back nmis: The
1263                  * first handles more than one counter, the 2nd
1264                  * handles only one counter and the 3rd handles no
1265                  * counter.
1266                  *
1267                  * This is the 2nd nmi because the previous was
1268                  * handling more than one counter. We will mark the
1269                  * next (3rd) and then drop it if unhandled.
1270                  */
1271                 __get_cpu_var(pmu_nmi).marked   = this_nmi + 1;
1272                 __get_cpu_var(pmu_nmi).handled  = handled;
1273         }
1274
1275         return NOTIFY_STOP;
1276 }
1277
1278 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1279         .notifier_call          = perf_event_nmi_handler,
1280         .next                   = NULL,
1281         .priority               = 1
1282 };
1283
1284 static struct event_constraint unconstrained;
1285 static struct event_constraint emptyconstraint;
1286
1287 static struct event_constraint *
1288 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1289 {
1290         struct event_constraint *c;
1291
1292         if (x86_pmu.event_constraints) {
1293                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1294                         if ((event->hw.config & c->cmask) == c->code)
1295                                 return c;
1296                 }
1297         }
1298
1299         return &unconstrained;
1300 }
1301
1302 #include "perf_event_amd.c"
1303 #include "perf_event_p6.c"
1304 #include "perf_event_p4.c"
1305 #include "perf_event_intel_lbr.c"
1306 #include "perf_event_intel_ds.c"
1307 #include "perf_event_intel.c"
1308
1309 static int __cpuinit
1310 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1311 {
1312         unsigned int cpu = (long)hcpu;
1313         int ret = NOTIFY_OK;
1314
1315         switch (action & ~CPU_TASKS_FROZEN) {
1316         case CPU_UP_PREPARE:
1317                 if (x86_pmu.cpu_prepare)
1318                         ret = x86_pmu.cpu_prepare(cpu);
1319                 break;
1320
1321         case CPU_STARTING:
1322                 if (x86_pmu.cpu_starting)
1323                         x86_pmu.cpu_starting(cpu);
1324                 break;
1325
1326         case CPU_DYING:
1327                 if (x86_pmu.cpu_dying)
1328                         x86_pmu.cpu_dying(cpu);
1329                 break;
1330
1331         case CPU_UP_CANCELED:
1332         case CPU_DEAD:
1333                 if (x86_pmu.cpu_dead)
1334                         x86_pmu.cpu_dead(cpu);
1335                 break;
1336
1337         default:
1338                 break;
1339         }
1340
1341         return ret;
1342 }
1343
1344 static void __init pmu_check_apic(void)
1345 {
1346         if (cpu_has_apic)
1347                 return;
1348
1349         x86_pmu.apic = 0;
1350         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1351         pr_info("no hardware sampling interrupt available.\n");
1352 }
1353
1354 void __init init_hw_perf_events(void)
1355 {
1356         struct event_constraint *c;
1357         int err;
1358
1359         pr_info("Performance Events: ");
1360
1361         switch (boot_cpu_data.x86_vendor) {
1362         case X86_VENDOR_INTEL:
1363                 err = intel_pmu_init();
1364                 break;
1365         case X86_VENDOR_AMD:
1366                 err = amd_pmu_init();
1367                 break;
1368         default:
1369                 return;
1370         }
1371         if (err != 0) {
1372                 pr_cont("no PMU driver, software events only.\n");
1373                 return;
1374         }
1375
1376         pmu_check_apic();
1377
1378         pr_cont("%s PMU driver.\n", x86_pmu.name);
1379
1380         if (x86_pmu.quirks)
1381                 x86_pmu.quirks();
1382
1383         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1384                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1385                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1386                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1387         }
1388         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1389
1390         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1391                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1392                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1393                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1394         }
1395
1396         x86_pmu.intel_ctrl |=
1397                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1398
1399         perf_events_lapic_init();
1400         register_die_notifier(&perf_event_nmi_notifier);
1401
1402         unconstrained = (struct event_constraint)
1403                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1404                                    0, x86_pmu.num_counters);
1405
1406         if (x86_pmu.event_constraints) {
1407                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1408                         if (c->cmask != X86_RAW_EVENT_MASK)
1409                                 continue;
1410
1411                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1412                         c->weight += x86_pmu.num_counters;
1413                 }
1414         }
1415
1416         pr_info("... version:                %d\n",     x86_pmu.version);
1417         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1418         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1419         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1420         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1421         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1422         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1423
1424         perf_pmu_register(&pmu);
1425         perf_cpu_notifier(x86_pmu_notifier);
1426 }
1427
1428 static inline void x86_pmu_read(struct perf_event *event)
1429 {
1430         x86_perf_event_update(event);
1431 }
1432
1433 /*
1434  * Start group events scheduling transaction
1435  * Set the flag to make pmu::enable() not perform the
1436  * schedulability test, it will be performed at commit time
1437  */
1438 static void x86_pmu_start_txn(struct pmu *pmu)
1439 {
1440         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1441
1442         perf_pmu_disable(pmu);
1443         cpuc->group_flag |= PERF_EVENT_TXN;
1444         cpuc->n_txn = 0;
1445 }
1446
1447 /*
1448  * Stop group events scheduling transaction
1449  * Clear the flag and pmu::enable() will perform the
1450  * schedulability test.
1451  */
1452 static void x86_pmu_cancel_txn(struct pmu *pmu)
1453 {
1454         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1455
1456         cpuc->group_flag &= ~PERF_EVENT_TXN;
1457         /*
1458          * Truncate the collected events.
1459          */
1460         cpuc->n_added -= cpuc->n_txn;
1461         cpuc->n_events -= cpuc->n_txn;
1462         perf_pmu_enable(pmu);
1463 }
1464
1465 /*
1466  * Commit group events scheduling transaction
1467  * Perform the group schedulability test as a whole
1468  * Return 0 if success
1469  */
1470 static int x86_pmu_commit_txn(struct pmu *pmu)
1471 {
1472         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1473         int assign[X86_PMC_IDX_MAX];
1474         int n, ret;
1475
1476         n = cpuc->n_events;
1477
1478         if (!x86_pmu_initialized())
1479                 return -EAGAIN;
1480
1481         ret = x86_pmu.schedule_events(cpuc, n, assign);
1482         if (ret)
1483                 return ret;
1484
1485         /*
1486          * copy new assignment, now we know it is possible
1487          * will be used by hw_perf_enable()
1488          */
1489         memcpy(cpuc->assign, assign, n*sizeof(int));
1490
1491         cpuc->group_flag &= ~PERF_EVENT_TXN;
1492         perf_pmu_enable(pmu);
1493         return 0;
1494 }
1495
1496 /*
1497  * validate that we can schedule this event
1498  */
1499 static int validate_event(struct perf_event *event)
1500 {
1501         struct cpu_hw_events *fake_cpuc;
1502         struct event_constraint *c;
1503         int ret = 0;
1504
1505         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1506         if (!fake_cpuc)
1507                 return -ENOMEM;
1508
1509         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1510
1511         if (!c || !c->weight)
1512                 ret = -ENOSPC;
1513
1514         if (x86_pmu.put_event_constraints)
1515                 x86_pmu.put_event_constraints(fake_cpuc, event);
1516
1517         kfree(fake_cpuc);
1518
1519         return ret;
1520 }
1521
1522 /*
1523  * validate a single event group
1524  *
1525  * validation include:
1526  *      - check events are compatible which each other
1527  *      - events do not compete for the same counter
1528  *      - number of events <= number of counters
1529  *
1530  * validation ensures the group can be loaded onto the
1531  * PMU if it was the only group available.
1532  */
1533 static int validate_group(struct perf_event *event)
1534 {
1535         struct perf_event *leader = event->group_leader;
1536         struct cpu_hw_events *fake_cpuc;
1537         int ret, n;
1538
1539         ret = -ENOMEM;
1540         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1541         if (!fake_cpuc)
1542                 goto out;
1543
1544         /*
1545          * the event is not yet connected with its
1546          * siblings therefore we must first collect
1547          * existing siblings, then add the new event
1548          * before we can simulate the scheduling
1549          */
1550         ret = -ENOSPC;
1551         n = collect_events(fake_cpuc, leader, true);
1552         if (n < 0)
1553                 goto out_free;
1554
1555         fake_cpuc->n_events = n;
1556         n = collect_events(fake_cpuc, event, false);
1557         if (n < 0)
1558                 goto out_free;
1559
1560         fake_cpuc->n_events = n;
1561
1562         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1563
1564 out_free:
1565         kfree(fake_cpuc);
1566 out:
1567         return ret;
1568 }
1569
1570 int x86_pmu_event_init(struct perf_event *event)
1571 {
1572         struct pmu *tmp;
1573         int err;
1574
1575         switch (event->attr.type) {
1576         case PERF_TYPE_RAW:
1577         case PERF_TYPE_HARDWARE:
1578         case PERF_TYPE_HW_CACHE:
1579                 break;
1580
1581         default:
1582                 return -ENOENT;
1583         }
1584
1585         err = __x86_pmu_event_init(event);
1586         if (!err) {
1587                 /*
1588                  * we temporarily connect event to its pmu
1589                  * such that validate_group() can classify
1590                  * it as an x86 event using is_x86_event()
1591                  */
1592                 tmp = event->pmu;
1593                 event->pmu = &pmu;
1594
1595                 if (event->group_leader != event)
1596                         err = validate_group(event);
1597                 else
1598                         err = validate_event(event);
1599
1600                 event->pmu = tmp;
1601         }
1602         if (err) {
1603                 if (event->destroy)
1604                         event->destroy(event);
1605         }
1606
1607         return err;
1608 }
1609
1610 static struct pmu pmu = {
1611         .pmu_enable     = x86_pmu_enable,
1612         .pmu_disable    = x86_pmu_disable,
1613
1614         .event_init     = x86_pmu_event_init,
1615
1616         .add            = x86_pmu_add,
1617         .del            = x86_pmu_del,
1618         .start          = x86_pmu_start,
1619         .stop           = x86_pmu_stop,
1620         .read           = x86_pmu_read,
1621
1622         .start_txn      = x86_pmu_start_txn,
1623         .cancel_txn     = x86_pmu_cancel_txn,
1624         .commit_txn     = x86_pmu_commit_txn,
1625 };
1626
1627 /*
1628  * callchain support
1629  */
1630
1631 static void
1632 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1633 {
1634         /* Ignore warnings */
1635 }
1636
1637 static void backtrace_warning(void *data, char *msg)
1638 {
1639         /* Ignore warnings */
1640 }
1641
1642 static int backtrace_stack(void *data, char *name)
1643 {
1644         return 0;
1645 }
1646
1647 static void backtrace_address(void *data, unsigned long addr, int reliable)
1648 {
1649         struct perf_callchain_entry *entry = data;
1650
1651         perf_callchain_store(entry, addr);
1652 }
1653
1654 static const struct stacktrace_ops backtrace_ops = {
1655         .warning                = backtrace_warning,
1656         .warning_symbol         = backtrace_warning_symbol,
1657         .stack                  = backtrace_stack,
1658         .address                = backtrace_address,
1659         .walk_stack             = print_context_stack_bp,
1660 };
1661
1662 void
1663 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1664 {
1665         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1666                 /* TODO: We don't support guest os callchain now */
1667                 return;
1668         }
1669
1670         perf_callchain_store(entry, regs->ip);
1671
1672         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1673 }
1674
1675 #ifdef CONFIG_COMPAT
1676 static inline int
1677 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1678 {
1679         /* 32-bit process in 64-bit kernel. */
1680         struct stack_frame_ia32 frame;
1681         const void __user *fp;
1682
1683         if (!test_thread_flag(TIF_IA32))
1684                 return 0;
1685
1686         fp = compat_ptr(regs->bp);
1687         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1688                 unsigned long bytes;
1689                 frame.next_frame     = 0;
1690                 frame.return_address = 0;
1691
1692                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1693                 if (bytes != sizeof(frame))
1694                         break;
1695
1696                 if (fp < compat_ptr(regs->sp))
1697                         break;
1698
1699                 perf_callchain_store(entry, frame.return_address);
1700                 fp = compat_ptr(frame.next_frame);
1701         }
1702         return 1;
1703 }
1704 #else
1705 static inline int
1706 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1707 {
1708     return 0;
1709 }
1710 #endif
1711
1712 void
1713 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1714 {
1715         struct stack_frame frame;
1716         const void __user *fp;
1717
1718         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1719                 /* TODO: We don't support guest os callchain now */
1720                 return;
1721         }
1722
1723         fp = (void __user *)regs->bp;
1724
1725         perf_callchain_store(entry, regs->ip);
1726
1727         if (perf_callchain_user32(regs, entry))
1728                 return;
1729
1730         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1731                 unsigned long bytes;
1732                 frame.next_frame             = NULL;
1733                 frame.return_address = 0;
1734
1735                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1736                 if (bytes != sizeof(frame))
1737                         break;
1738
1739                 if ((unsigned long)fp < regs->sp)
1740                         break;
1741
1742                 perf_callchain_store(entry, frame.return_address);
1743                 fp = frame.next_frame;
1744         }
1745 }
1746
1747 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1748 {
1749         unsigned long ip;
1750
1751         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1752                 ip = perf_guest_cbs->get_guest_ip();
1753         else
1754                 ip = instruction_pointer(regs);
1755
1756         return ip;
1757 }
1758
1759 unsigned long perf_misc_flags(struct pt_regs *regs)
1760 {
1761         int misc = 0;
1762
1763         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1764                 if (perf_guest_cbs->is_user_mode())
1765                         misc |= PERF_RECORD_MISC_GUEST_USER;
1766                 else
1767                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1768         } else {
1769                 if (user_mode(regs))
1770                         misc |= PERF_RECORD_MISC_USER;
1771                 else
1772                         misc |= PERF_RECORD_MISC_KERNEL;
1773         }
1774
1775         if (regs->flags & PERF_EFLAGS_EXACT)
1776                 misc |= PERF_RECORD_MISC_EXACT_IP;
1777
1778         return misc;
1779 }