arch/x86/kernel/cpu/perf_counter.c

   1 /*
   2  * Performance counter x86 architecture code
   3  *
   4  *  Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
   6  *  Copyright(C) 2009 Jaswinder Singh Rajput
   7  *  Copyright(C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *
   9  *  For licencing details see kernel-base/COPYING
  10  */
  11
  12 #include <linux/perf_counter.h>
  13 #include <linux/capability.h>
  14 #include <linux/notifier.h>
  15 #include <linux/hardirq.h>
  16 #include <linux/kprobes.h>
  17 #include <linux/module.h>
  18 #include <linux/kdebug.h>
  19 #include <linux/sched.h>
  20 #include <linux/uaccess.h>
  21
  22 #include <asm/apic.h>
  23 #include <asm/stacktrace.h>
  24 #include <asm/nmi.h>
  25
  26 static bool perf_counters_initialized __read_mostly;
  27 static u64 perf_counter_mask __read_mostly;
  28
  29 struct cpu_hw_counters {
  30         struct perf_counter     *counters[X86_PMC_IDX_MAX];
  31         unsigned long           used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  32         unsigned long           interrupts;
  33         u64                     throttle_ctrl;
  34         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  35         int                     enabled;
  36 };
  37
  38 /*
  39  * struct x86_pmu - generic x86 pmu
  40  */
  41 struct x86_pmu {
  42         const char      *name;
  43         int             version;
  44         int             (*handle_irq)(struct pt_regs *, int);
  45         u64             (*save_disable_all)(void);
  46         void            (*restore_all)(u64);
  47         void            (*enable)(int, u64);
  48         void            (*disable)(int, u64);
  49         unsigned        eventsel;
  50         unsigned        perfctr;
  51         u64             (*event_map)(int);
  52         u64             (*raw_event)(u64);
  53         int             max_events;
  54         int             num_counters;
  55         int             num_counters_fixed;
  56         int             counter_bits;
  57         u64             counter_mask;
  58 };
  59
  60 static struct x86_pmu x86_pmu __read_mostly;
  61
  62 static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
  63         .enabled = 1,
  64 };
  65
  66 /*
  67  * Intel PerfMon v3. Used on Core2 and later.
  68  */
  69 static const u64 intel_perfmon_event_map[] =
  70 {
  71   [PERF_COUNT_CPU_CYCLES]               = 0x003c,
  72   [PERF_COUNT_INSTRUCTIONS]             = 0x00c0,
  73   [PERF_COUNT_CACHE_REFERENCES]         = 0x4f2e,
  74   [PERF_COUNT_CACHE_MISSES]             = 0x412e,
  75   [PERF_COUNT_BRANCH_INSTRUCTIONS]      = 0x00c4,
  76   [PERF_COUNT_BRANCH_MISSES]            = 0x00c5,
  77   [PERF_COUNT_BUS_CYCLES]               = 0x013c,
  78 };
  79
  80 static u64 intel_pmu_event_map(int event)
  81 {
  82         return intel_perfmon_event_map[event];
  83 }
  84
  85 static u64 intel_pmu_raw_event(u64 event)
  86 {
  87 #define CORE_EVNTSEL_EVENT_MASK         0x000000FFULL
  88 #define CORE_EVNTSEL_UNIT_MASK          0x0000FF00ULL
  89 #define CORE_EVNTSEL_COUNTER_MASK       0xFF000000ULL
  90
  91 #define CORE_EVNTSEL_MASK               \
  92         (CORE_EVNTSEL_EVENT_MASK |      \
  93          CORE_EVNTSEL_UNIT_MASK  |      \
  94          CORE_EVNTSEL_COUNTER_MASK)
  95
  96         return event & CORE_EVNTSEL_MASK;
  97 }
  98
  99 /*
 100  * AMD Performance Monitor K7 and later.
 101  */
 102 static const u64 amd_perfmon_event_map[] =
 103 {
 104   [PERF_COUNT_CPU_CYCLES]               = 0x0076,
 105   [PERF_COUNT_INSTRUCTIONS]             = 0x00c0,
 106   [PERF_COUNT_CACHE_REFERENCES]         = 0x0080,
 107   [PERF_COUNT_CACHE_MISSES]             = 0x0081,
 108   [PERF_COUNT_BRANCH_INSTRUCTIONS]      = 0x00c4,
 109   [PERF_COUNT_BRANCH_MISSES]            = 0x00c5,
 110 };
 111
 112 static u64 amd_pmu_event_map(int event)
 113 {
 114         return amd_perfmon_event_map[event];
 115 }
 116
 117 static u64 amd_pmu_raw_event(u64 event)
 118 {
 119 #define K7_EVNTSEL_EVENT_MASK   0x7000000FFULL
 120 #define K7_EVNTSEL_UNIT_MASK    0x00000FF00ULL
 121 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
 122
 123 #define K7_EVNTSEL_MASK                 \
 124         (K7_EVNTSEL_EVENT_MASK |        \
 125          K7_EVNTSEL_UNIT_MASK  |        \
 126          K7_EVNTSEL_COUNTER_MASK)
 127
 128         return event & K7_EVNTSEL_MASK;
 129 }
 130
 131 /*
 132  * Propagate counter elapsed time into the generic counter.
 133  * Can only be executed on the CPU where the counter is active.
 134  * Returns the delta events processed.
 135  */
 136 static void
 137 x86_perf_counter_update(struct perf_counter *counter,
 138                         struct hw_perf_counter *hwc, int idx)
 139 {
 140         u64 prev_raw_count, new_raw_count, delta;
 141
 142         /*
 143          * Careful: an NMI might modify the previous counter value.
 144          *
 145          * Our tactic to handle this is to first atomically read and
 146          * exchange a new raw count - then add that new-prev delta
 147          * count to the generic counter atomically:
 148          */
 149 again:
 150         prev_raw_count = atomic64_read(&hwc->prev_count);
 151         rdmsrl(hwc->counter_base + idx, new_raw_count);
 152
 153         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 154                                         new_raw_count) != prev_raw_count)
 155                 goto again;
 156
 157         /*
 158          * Now we have the new raw value and have updated the prev
 159          * timestamp already. We can now calculate the elapsed delta
 160          * (counter-)time and add that to the generic counter.
 161          *
 162          * Careful, not all hw sign-extends above the physical width
 163          * of the count, so we do that by clipping the delta to 32 bits:
 164          */
 165         delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count);
 166
 167         atomic64_add(delta, &counter->count);
 168         atomic64_sub(delta, &hwc->period_left);
 169 }
 170
 171 static atomic_t num_counters;
 172 static DEFINE_MUTEX(pmc_reserve_mutex);
 173
 174 static bool reserve_pmc_hardware(void)
 175 {
 176         int i;
 177
 178         if (nmi_watchdog == NMI_LOCAL_APIC)
 179                 disable_lapic_nmi_watchdog();
 180
 181         for (i = 0; i < x86_pmu.num_counters; i++) {
 182                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 183                         goto perfctr_fail;
 184         }
 185
 186         for (i = 0; i < x86_pmu.num_counters; i++) {
 187                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 188                         goto eventsel_fail;
 189         }
 190
 191         return true;
 192
 193 eventsel_fail:
 194         for (i--; i >= 0; i--)
 195                 release_evntsel_nmi(x86_pmu.eventsel + i);
 196
 197         i = x86_pmu.num_counters;
 198
 199 perfctr_fail:
 200         for (i--; i >= 0; i--)
 201                 release_perfctr_nmi(x86_pmu.perfctr + i);
 202
 203         if (nmi_watchdog == NMI_LOCAL_APIC)
 204                 enable_lapic_nmi_watchdog();
 205
 206         return false;
 207 }
 208
 209 static void release_pmc_hardware(void)
 210 {
 211         int i;
 212
 213         for (i = 0; i < x86_pmu.num_counters; i++) {
 214                 release_perfctr_nmi(x86_pmu.perfctr + i);
 215                 release_evntsel_nmi(x86_pmu.eventsel + i);
 216         }
 217
 218         if (nmi_watchdog == NMI_LOCAL_APIC)
 219                 enable_lapic_nmi_watchdog();
 220 }
 221
 222 static void hw_perf_counter_destroy(struct perf_counter *counter)
 223 {
 224         if (atomic_dec_and_mutex_lock(&num_counters, &pmc_reserve_mutex)) {
 225                 release_pmc_hardware();
 226                 mutex_unlock(&pmc_reserve_mutex);
 227         }
 228 }
 229
 230 /*
 231  * Setup the hardware configuration for a given hw_event_type
 232  */
 233 static int __hw_perf_counter_init(struct perf_counter *counter)
 234 {
 235         struct perf_counter_hw_event *hw_event = &counter->hw_event;
 236         struct hw_perf_counter *hwc = &counter->hw;
 237         int err;
 238
 239         /* disable temporarily */
 240         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
 241                 return -ENOSYS;
 242
 243         if (unlikely(!perf_counters_initialized))
 244                 return -EINVAL;
 245
 246         err = 0;
 247         if (atomic_inc_not_zero(&num_counters)) {
 248                 mutex_lock(&pmc_reserve_mutex);
 249                 if (atomic_read(&num_counters) == 0 && !reserve_pmc_hardware())
 250                         err = -EBUSY;
 251                 else
 252                         atomic_inc(&num_counters);
 253                 mutex_unlock(&pmc_reserve_mutex);
 254         }
 255         if (err)
 256                 return err;
 257
 258         /*
 259          * Generate PMC IRQs:
 260          * (keep 'enabled' bit clear for now)
 261          */
 262         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
 263
 264         /*
 265          * Count user and OS events unless requested not to.
 266          */
 267         if (!hw_event->exclude_user)
 268                 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
 269         if (!hw_event->exclude_kernel)
 270                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
 271
 272         /*
 273          * If privileged enough, allow NMI events:
 274          */
 275         hwc->nmi = 0;
 276         if (capable(CAP_SYS_ADMIN) && hw_event->nmi)
 277                 hwc->nmi = 1;
 278
 279         hwc->irq_period         = hw_event->irq_period;
 280         /*
 281          * Intel PMCs cannot be accessed sanely above 32 bit width,
 282          * so we install an artificial 1<<31 period regardless of
 283          * the generic counter period:
 284          */
 285         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
 286                 if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF)
 287                         hwc->irq_period = 0x7FFFFFFF;
 288
 289         atomic64_set(&hwc->period_left, hwc->irq_period);
 290
 291         /*
 292          * Raw event type provide the config in the event structure
 293          */
 294         if (perf_event_raw(hw_event)) {
 295                 hwc->config |= x86_pmu.raw_event(perf_event_config(hw_event));
 296         } else {
 297                 if (perf_event_id(hw_event) >= x86_pmu.max_events)
 298                         return -EINVAL;
 299                 /*
 300                  * The generic map:
 301                  */
 302                 hwc->config |= x86_pmu.event_map(perf_event_id(hw_event));
 303         }
 304
 305         counter->destroy = hw_perf_counter_destroy;
 306
 307         return 0;
 308 }
 309
 310 static u64 intel_pmu_save_disable_all(void)
 311 {
 312         u64 ctrl;
 313
 314         rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
 315         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 316
 317         return ctrl;
 318 }
 319
 320 static u64 amd_pmu_save_disable_all(void)
 321 {
 322         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 323         int enabled, idx;
 324
 325         enabled = cpuc->enabled;
 326         cpuc->enabled = 0;
 327         /*
 328          * ensure we write the disable before we start disabling the
 329          * counters proper, so that amd_pmu_enable_counter() does the
 330          * right thing.
 331          */
 332         barrier();
 333
 334         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 335                 u64 val;
 336
 337                 if (!test_bit(idx, cpuc->active_mask))
 338                         continue;
 339                 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
 340                 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
 341                         continue;
 342                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
 343                 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
 344         }
 345
 346         return enabled;
 347 }
 348
 349 u64 hw_perf_save_disable(void)
 350 {
 351         if (unlikely(!perf_counters_initialized))
 352                 return 0;
 353
 354         return x86_pmu.save_disable_all();
 355 }
 356 /*
 357  * Exported because of ACPI idle
 358  */
 359 EXPORT_SYMBOL_GPL(hw_perf_save_disable);
 360
 361 static void intel_pmu_restore_all(u64 ctrl)
 362 {
 363         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
 364 }
 365
 366 static void amd_pmu_restore_all(u64 ctrl)
 367 {
 368         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 369         int idx;
 370
 371         cpuc->enabled = ctrl;
 372         barrier();
 373         if (!ctrl)
 374                 return;
 375
 376         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 377                 u64 val;
 378
 379                 if (!test_bit(idx, cpuc->active_mask))
 380                         continue;
 381                 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
 382                 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
 383                         continue;
 384                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 385                 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
 386         }
 387 }
 388
 389 void hw_perf_restore(u64 ctrl)
 390 {
 391         if (unlikely(!perf_counters_initialized))
 392                 return;
 393
 394         x86_pmu.restore_all(ctrl);
 395 }
 396 /*
 397  * Exported because of ACPI idle
 398  */
 399 EXPORT_SYMBOL_GPL(hw_perf_restore);
 400
 401 static inline u64 intel_pmu_get_status(u64 mask)
 402 {
 403         u64 status;
 404
 405         if (unlikely(!perf_counters_initialized))
 406                 return 0;
 407         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
 408
 409         return status;
 410 }
 411
 412 static inline void intel_pmu_ack_status(u64 ack)
 413 {
 414         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
 415 }
 416
 417 static void intel_pmu_enable_counter(int idx, u64 config)
 418 {
 419         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx,
 420                         config | ARCH_PERFMON_EVENTSEL0_ENABLE);
 421 }
 422
 423 static void amd_pmu_enable_counter(int idx, u64 config)
 424 {
 425         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 426
 427         set_bit(idx, cpuc->active_mask);
 428         if (cpuc->enabled)
 429                 config |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 430
 431         wrmsrl(MSR_K7_EVNTSEL0 + idx, config);
 432 }
 433
 434 static void hw_perf_enable(int idx, u64 config)
 435 {
 436         if (unlikely(!perf_counters_initialized))
 437                 return;
 438
 439         x86_pmu.enable(idx, config);
 440 }
 441
 442 static void intel_pmu_disable_counter(int idx, u64 config)
 443 {
 444         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, config);
 445 }
 446
 447 static void amd_pmu_disable_counter(int idx, u64 config)
 448 {
 449         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 450
 451         clear_bit(idx, cpuc->active_mask);
 452         wrmsrl(MSR_K7_EVNTSEL0 + idx, config);
 453
 454 }
 455
 456 static void hw_perf_disable(int idx, u64 config)
 457 {
 458         if (unlikely(!perf_counters_initialized))
 459                 return;
 460
 461         x86_pmu.disable(idx, config);
 462 }
 463
 464 static inline void
 465 __pmc_fixed_disable(struct perf_counter *counter,
 466                     struct hw_perf_counter *hwc, unsigned int __idx)
 467 {
 468         int idx = __idx - X86_PMC_IDX_FIXED;
 469         u64 ctrl_val, mask;
 470         int err;
 471
 472         mask = 0xfULL << (idx * 4);
 473
 474         rdmsrl(hwc->config_base, ctrl_val);
 475         ctrl_val &= ~mask;
 476         err = checking_wrmsrl(hwc->config_base, ctrl_val);
 477 }
 478
 479 static inline void
 480 __x86_pmu_disable(struct perf_counter *counter,
 481                   struct hw_perf_counter *hwc, unsigned int idx)
 482 {
 483         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL))
 484                 __pmc_fixed_disable(counter, hwc, idx);
 485         else
 486                 hw_perf_disable(idx, hwc->config);
 487 }
 488
 489 static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
 490
 491 /*
 492  * Set the next IRQ period, based on the hwc->period_left value.
 493  * To be called with the counter disabled in hw:
 494  */
 495 static void
 496 x86_perf_counter_set_period(struct perf_counter *counter,
 497                              struct hw_perf_counter *hwc, int idx)
 498 {
 499         s64 left = atomic64_read(&hwc->period_left);
 500         s64 period = hwc->irq_period;
 501         int err;
 502
 503         /*
 504          * If we are way outside a reasoable range then just skip forward:
 505          */
 506         if (unlikely(left <= -period)) {
 507                 left = period;
 508                 atomic64_set(&hwc->period_left, left);
 509         }
 510
 511         if (unlikely(left <= 0)) {
 512                 left += period;
 513                 atomic64_set(&hwc->period_left, left);
 514         }
 515
 516         per_cpu(prev_left[idx], smp_processor_id()) = left;
 517
 518         /*
 519          * The hw counter starts counting from this counter offset,
 520          * mark it to be able to extra future deltas:
 521          */
 522         atomic64_set(&hwc->prev_count, (u64)-left);
 523
 524         err = checking_wrmsrl(hwc->counter_base + idx,
 525                              (u64)(-left) & x86_pmu.counter_mask);
 526 }
 527
 528 static inline void
 529 __pmc_fixed_enable(struct perf_counter *counter,
 530                    struct hw_perf_counter *hwc, unsigned int __idx)
 531 {
 532         int idx = __idx - X86_PMC_IDX_FIXED;
 533         u64 ctrl_val, bits, mask;
 534         int err;
 535
 536         /*
 537          * Enable IRQ generation (0x8),
 538          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
 539          * if requested:
 540          */
 541         bits = 0x8ULL;
 542         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
 543                 bits |= 0x2;
 544         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
 545                 bits |= 0x1;
 546         bits <<= (idx * 4);
 547         mask = 0xfULL << (idx * 4);
 548
 549         rdmsrl(hwc->config_base, ctrl_val);
 550         ctrl_val &= ~mask;
 551         ctrl_val |= bits;
 552         err = checking_wrmsrl(hwc->config_base, ctrl_val);
 553 }
 554
 555 static void
 556 __x86_pmu_enable(struct perf_counter *counter,
 557                  struct hw_perf_counter *hwc, int idx)
 558 {
 559         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL))
 560                 __pmc_fixed_enable(counter, hwc, idx);
 561         else
 562                 hw_perf_enable(idx, hwc->config);
 563 }
 564
 565 static int
 566 fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
 567 {
 568         unsigned int event;
 569
 570         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
 571                 return -1;
 572
 573         if (unlikely(hwc->nmi))
 574                 return -1;
 575
 576         event = hwc->config & ARCH_PERFMON_EVENT_MASK;
 577
 578         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS)))
 579                 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
 580         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES)))
 581                 return X86_PMC_IDX_FIXED_CPU_CYCLES;
 582         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES)))
 583                 return X86_PMC_IDX_FIXED_BUS_CYCLES;
 584
 585         return -1;
 586 }
 587
 588 /*
 589  * Find a PMC slot for the freshly enabled / scheduled in counter:
 590  */
 591 static int x86_pmu_enable(struct perf_counter *counter)
 592 {
 593         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 594         struct hw_perf_counter *hwc = &counter->hw;
 595         int idx;
 596
 597         idx = fixed_mode_idx(counter, hwc);
 598         if (idx >= 0) {
 599                 /*
 600                  * Try to get the fixed counter, if that is already taken
 601                  * then try to get a generic counter:
 602                  */
 603                 if (test_and_set_bit(idx, cpuc->used))
 604                         goto try_generic;
 605
 606                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 607                 /*
 608                  * We set it so that counter_base + idx in wrmsr/rdmsr maps to
 609                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 610                  */
 611                 hwc->counter_base =
 612                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 613                 hwc->idx = idx;
 614         } else {
 615                 idx = hwc->idx;
 616                 /* Try to get the previous generic counter again */
 617                 if (test_and_set_bit(idx, cpuc->used)) {
 618 try_generic:
 619                         idx = find_first_zero_bit(cpuc->used,
 620                                                   x86_pmu.num_counters);
 621                         if (idx == x86_pmu.num_counters)
 622                                 return -EAGAIN;
 623
 624                         set_bit(idx, cpuc->used);
 625                         hwc->idx = idx;
 626                 }
 627                 hwc->config_base  = x86_pmu.eventsel;
 628                 hwc->counter_base = x86_pmu.perfctr;
 629         }
 630
 631         perf_counters_lapic_init(hwc->nmi);
 632
 633         __x86_pmu_disable(counter, hwc, idx);
 634
 635         cpuc->counters[idx] = counter;
 636         /*
 637          * Make it visible before enabling the hw:
 638          */
 639         barrier();
 640
 641         x86_perf_counter_set_period(counter, hwc, idx);
 642         __x86_pmu_enable(counter, hwc, idx);
 643
 644         return 0;
 645 }
 646
 647 void perf_counter_print_debug(void)
 648 {
 649         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
 650         struct cpu_hw_counters *cpuc;
 651         int cpu, idx;
 652
 653         if (!x86_pmu.num_counters)
 654                 return;
 655
 656         local_irq_disable();
 657
 658         cpu = smp_processor_id();
 659         cpuc = &per_cpu(cpu_hw_counters, cpu);
 660
 661         if (x86_pmu.version >= 2) {
 662                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
 663                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
 664                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
 665                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
 666
 667                 pr_info("\n");
 668                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
 669                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
 670                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
 671                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
 672         }
 673         pr_info("CPU#%d: used:       %016llx\n", cpu, *(u64 *)cpuc->used);
 674
 675         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 676                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
 677                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
 678
 679                 prev_left = per_cpu(prev_left[idx], cpu);
 680
 681                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
 682                         cpu, idx, pmc_ctrl);
 683                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
 684                         cpu, idx, pmc_count);
 685                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
 686                         cpu, idx, prev_left);
 687         }
 688         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
 689                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
 690
 691                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
 692                         cpu, idx, pmc_count);
 693         }
 694         local_irq_enable();
 695 }
 696
 697 static void x86_pmu_disable(struct perf_counter *counter)
 698 {
 699         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 700         struct hw_perf_counter *hwc = &counter->hw;
 701         unsigned int idx = hwc->idx;
 702
 703         __x86_pmu_disable(counter, hwc, idx);
 704
 705         clear_bit(idx, cpuc->used);
 706         cpuc->counters[idx] = NULL;
 707         /*
 708          * Make sure the cleared pointer becomes visible before we
 709          * (potentially) free the counter:
 710          */
 711         barrier();
 712
 713         /*
 714          * Drain the remaining delta count out of a counter
 715          * that we are disabling:
 716          */
 717         x86_perf_counter_update(counter, hwc, idx);
 718 }
 719
 720 /*
 721  * Save and restart an expired counter. Called by NMI contexts,
 722  * so it has to be careful about preempting normal counter ops:
 723  */
 724 static void intel_pmu_save_and_restart(struct perf_counter *counter)
 725 {
 726         struct hw_perf_counter *hwc = &counter->hw;
 727         int idx = hwc->idx;
 728
 729         x86_perf_counter_update(counter, hwc, idx);
 730         x86_perf_counter_set_period(counter, hwc, idx);
 731
 732         if (counter->state == PERF_COUNTER_STATE_ACTIVE)
 733                 __x86_pmu_enable(counter, hwc, idx);
 734 }
 735
 736 /*
 737  * Maximum interrupt frequency of 100KHz per CPU
 738  */
 739 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
 740
 741 /*
 742  * This handler is triggered by the local APIC, so the APIC IRQ handling
 743  * rules apply:
 744  */
 745 static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi)
 746 {
 747         int bit, cpu = smp_processor_id();
 748         u64 ack, status;
 749         struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
 750         int ret = 0;
 751
 752         cpuc->throttle_ctrl = intel_pmu_save_disable_all();
 753
 754         status = intel_pmu_get_status(cpuc->throttle_ctrl);
 755         if (!status)
 756                 goto out;
 757
 758         ret = 1;
 759 again:
 760         inc_irq_stat(apic_perf_irqs);
 761         ack = status;
 762         for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
 763                 struct perf_counter *counter = cpuc->counters[bit];
 764
 765                 clear_bit(bit, (unsigned long *) &status);
 766                 if (!counter)
 767                         continue;
 768
 769                 intel_pmu_save_and_restart(counter);
 770                 if (perf_counter_overflow(counter, nmi, regs, 0))
 771                         __x86_pmu_disable(counter, &counter->hw, bit);
 772         }
 773
 774         intel_pmu_ack_status(ack);
 775
 776         /*
 777          * Repeat if there is more work to be done:
 778          */
 779         status = intel_pmu_get_status(cpuc->throttle_ctrl);
 780         if (status)
 781                 goto again;
 782 out:
 783         /*
 784          * Restore - do not reenable when global enable is off or throttled:
 785          */
 786         if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS)
 787                 intel_pmu_restore_all(cpuc->throttle_ctrl);
 788
 789         return ret;
 790 }
 791
 792 static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi) { return 0; }
 793
 794 void perf_counter_unthrottle(void)
 795 {
 796         struct cpu_hw_counters *cpuc;
 797
 798         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 799                 return;
 800
 801         if (unlikely(!perf_counters_initialized))
 802                 return;
 803
 804         cpuc = &__get_cpu_var(cpu_hw_counters);
 805         if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) {
 806                 if (printk_ratelimit())
 807                         printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n");
 808                 hw_perf_restore(cpuc->throttle_ctrl);
 809         }
 810         cpuc->interrupts = 0;
 811 }
 812
 813 void smp_perf_counter_interrupt(struct pt_regs *regs)
 814 {
 815         irq_enter();
 816         apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
 817         ack_APIC_irq();
 818         x86_pmu.handle_irq(regs, 0);
 819         irq_exit();
 820 }
 821
 822 void smp_perf_pending_interrupt(struct pt_regs *regs)
 823 {
 824         irq_enter();
 825         ack_APIC_irq();
 826         inc_irq_stat(apic_pending_irqs);
 827         perf_counter_do_pending();
 828         irq_exit();
 829 }
 830
 831 void set_perf_counter_pending(void)
 832 {
 833         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
 834 }
 835
 836 void perf_counters_lapic_init(int nmi)
 837 {
 838         u32 apic_val;
 839
 840         if (!perf_counters_initialized)
 841                 return;
 842         /*
 843          * Enable the performance counter vector in the APIC LVT:
 844          */
 845         apic_val = apic_read(APIC_LVTERR);
 846
 847         apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED);
 848         if (nmi)
 849                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 850         else
 851                 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
 852         apic_write(APIC_LVTERR, apic_val);
 853 }
 854
 855 static int __kprobes
 856 perf_counter_nmi_handler(struct notifier_block *self,
 857                          unsigned long cmd, void *__args)
 858 {
 859         struct die_args *args = __args;
 860         struct pt_regs *regs;
 861         int ret;
 862
 863         switch (cmd) {
 864         case DIE_NMI:
 865         case DIE_NMI_IPI:
 866                 break;
 867
 868         default:
 869                 return NOTIFY_DONE;
 870         }
 871
 872         regs = args->regs;
 873
 874         apic_write(APIC_LVTPC, APIC_DM_NMI);
 875         ret = x86_pmu.handle_irq(regs, 1);
 876
 877         return ret ? NOTIFY_STOP : NOTIFY_OK;
 878 }
 879
 880 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
 881         .notifier_call          = perf_counter_nmi_handler,
 882         .next                   = NULL,
 883         .priority               = 1
 884 };
 885
 886 static struct x86_pmu intel_pmu = {
 887         .name                   = "Intel",
 888         .handle_irq             = intel_pmu_handle_irq,
 889         .save_disable_all       = intel_pmu_save_disable_all,
 890         .restore_all            = intel_pmu_restore_all,
 891         .enable                 = intel_pmu_enable_counter,
 892         .disable                = intel_pmu_disable_counter,
 893         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
 894         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
 895         .event_map              = intel_pmu_event_map,
 896         .raw_event              = intel_pmu_raw_event,
 897         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
 898 };
 899
 900 static struct x86_pmu amd_pmu = {
 901         .name                   = "AMD",
 902         .handle_irq             = amd_pmu_handle_irq,
 903         .save_disable_all       = amd_pmu_save_disable_all,
 904         .restore_all            = amd_pmu_restore_all,
 905         .enable                 = amd_pmu_enable_counter,
 906         .disable                = amd_pmu_disable_counter,
 907         .eventsel               = MSR_K7_EVNTSEL0,
 908         .perfctr                = MSR_K7_PERFCTR0,
 909         .event_map              = amd_pmu_event_map,
 910         .raw_event              = amd_pmu_raw_event,
 911         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
 912         .num_counters           = 4,
 913         .counter_bits           = 48,
 914         .counter_mask           = (1ULL << 48) - 1,
 915 };
 916
 917 static int intel_pmu_init(void)
 918 {
 919         union cpuid10_edx edx;
 920         union cpuid10_eax eax;
 921         unsigned int unused;
 922         unsigned int ebx;
 923         int version;
 924
 925         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 926                 return -ENODEV;
 927
 928         /*
 929          * Check whether the Architectural PerfMon supports
 930          * Branch Misses Retired Event or not.
 931          */
 932         cpuid(10, &eax.full, &ebx, &unused, &edx.full);
 933         if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
 934                 return -ENODEV;
 935
 936         version = eax.split.version_id;
 937         if (version < 2)
 938                 return -ENODEV;
 939
 940         x86_pmu = intel_pmu;
 941         x86_pmu.version = version;
 942         x86_pmu.num_counters = eax.split.num_counters;
 943         x86_pmu.num_counters_fixed = edx.split.num_counters_fixed;
 944         x86_pmu.counter_bits = eax.split.bit_width;
 945         x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1;
 946
 947         return 0;
 948 }
 949
 950 static int amd_pmu_init(void)
 951 {
 952         x86_pmu = amd_pmu;
 953         return 0;
 954 }
 955
 956 void __init init_hw_perf_counters(void)
 957 {
 958         int err;
 959
 960         switch (boot_cpu_data.x86_vendor) {
 961         case X86_VENDOR_INTEL:
 962                 err = intel_pmu_init();
 963                 break;
 964         case X86_VENDOR_AMD:
 965                 err = amd_pmu_init();
 966                 break;
 967         default:
 968                 return;
 969         }
 970         if (err != 0)
 971                 return;
 972
 973         pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name);
 974         pr_info("... version:         %d\n", x86_pmu.version);
 975         pr_info("... bit width:       %d\n", x86_pmu.counter_bits);
 976
 977         pr_info("... num counters:    %d\n", x86_pmu.num_counters);
 978         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
 979                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
 980                 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
 981                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
 982         }
 983         perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
 984         perf_max_counters = x86_pmu.num_counters;
 985
 986         pr_info("... value mask:      %016Lx\n", x86_pmu.counter_mask);
 987
 988         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
 989                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
 990                 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
 991                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
 992         }
 993         pr_info("... fixed counters:  %d\n", x86_pmu.num_counters_fixed);
 994
 995         perf_counter_mask |=
 996                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
 997
 998         pr_info("... counter mask:    %016Lx\n", perf_counter_mask);
 999         perf_counters_initialized = true;
1000
1001         perf_counters_lapic_init(0);
1002         register_die_notifier(&perf_counter_nmi_notifier);
1003 }
1004
1005 static void x86_pmu_read(struct perf_counter *counter)
1006 {
1007         x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
1008 }
1009
1010 static const struct pmu pmu = {
1011         .enable         = x86_pmu_enable,
1012         .disable        = x86_pmu_disable,
1013         .read           = x86_pmu_read,
1014 };
1015
1016 const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1017 {
1018         int err;
1019
1020         err = __hw_perf_counter_init(counter);
1021         if (err)
1022                 return ERR_PTR(err);
1023
1024         return &pmu;
1025 }
1026
1027 /*
1028  * callchain support
1029  */
1030
1031 static inline
1032 void callchain_store(struct perf_callchain_entry *entry, unsigned long ip)
1033 {
1034         if (entry->nr < MAX_STACK_DEPTH)
1035                 entry->ip[entry->nr++] = ip;
1036 }
1037
1038 static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
1039 static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
1040
1041
1042 static void
1043 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1044 {
1045         /* Ignore warnings */
1046 }
1047
1048 static void backtrace_warning(void *data, char *msg)
1049 {
1050         /* Ignore warnings */
1051 }
1052
1053 static int backtrace_stack(void *data, char *name)
1054 {
1055         /* Don't bother with IRQ stacks for now */
1056         return -1;
1057 }
1058
1059 static void backtrace_address(void *data, unsigned long addr, int reliable)
1060 {
1061         struct perf_callchain_entry *entry = data;
1062
1063         if (reliable)
1064                 callchain_store(entry, addr);
1065 }
1066
1067 static const struct stacktrace_ops backtrace_ops = {
1068         .warning                = backtrace_warning,
1069         .warning_symbol         = backtrace_warning_symbol,
1070         .stack                  = backtrace_stack,
1071         .address                = backtrace_address,
1072 };
1073
1074 static void
1075 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1076 {
1077         unsigned long bp;
1078         char *stack;
1079         int nr = entry->nr;
1080
1081         callchain_store(entry, instruction_pointer(regs));
1082
1083         stack = ((char *)regs + sizeof(struct pt_regs));
1084 #ifdef CONFIG_FRAME_POINTER
1085         bp = frame_pointer(regs);
1086 #else
1087         bp = 0;
1088 #endif
1089
1090         dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry);
1091
1092         entry->kernel = entry->nr - nr;
1093 }
1094
1095
1096 struct stack_frame {
1097         const void __user       *next_fp;
1098         unsigned long           return_address;
1099 };
1100
1101 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1102 {
1103         int ret;
1104
1105         if (!access_ok(VERIFY_READ, fp, sizeof(*frame)))
1106                 return 0;
1107
1108         ret = 1;
1109         pagefault_disable();
1110         if (__copy_from_user_inatomic(frame, fp, sizeof(*frame)))
1111                 ret = 0;
1112         pagefault_enable();
1113
1114         return ret;
1115 }
1116
1117 static void
1118 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1119 {
1120         struct stack_frame frame;
1121         const void __user *fp;
1122         int nr = entry->nr;
1123
1124         regs = (struct pt_regs *)current->thread.sp0 - 1;
1125         fp   = (void __user *)regs->bp;
1126
1127         callchain_store(entry, regs->ip);
1128
1129         while (entry->nr < MAX_STACK_DEPTH) {
1130                 frame.next_fp        = NULL;
1131                 frame.return_address = 0;
1132
1133                 if (!copy_stack_frame(fp, &frame))
1134                         break;
1135
1136                 if ((unsigned long)fp < user_stack_pointer(regs))
1137                         break;
1138
1139                 callchain_store(entry, frame.return_address);
1140                 fp = frame.next_fp;
1141         }
1142
1143         entry->user = entry->nr - nr;
1144 }
1145
1146 static void
1147 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1148 {
1149         int is_user;
1150
1151         if (!regs)
1152                 return;
1153
1154         is_user = user_mode(regs);
1155
1156         if (!current || current->pid == 0)
1157                 return;
1158
1159         if (is_user && current->state != TASK_RUNNING)
1160                 return;
1161
1162         if (!is_user)
1163                 perf_callchain_kernel(regs, entry);
1164
1165         if (current->mm)
1166                 perf_callchain_user(regs, entry);
1167 }
1168
1169 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1170 {
1171         struct perf_callchain_entry *entry;
1172
1173         if (in_nmi())
1174                 entry = &__get_cpu_var(nmi_entry);
1175         else
1176                 entry = &__get_cpu_var(irq_entry);
1177
1178         entry->nr = 0;
1179         entry->hv = 0;
1180         entry->kernel = 0;
1181         entry->user = 0;
1182
1183         perf_do_callchain(regs, entry);
1184
1185         return entry;
1186 }