1 /* Generic MTRR (Memory Type Range Register) driver.
3 Copyright (C) 1997-2000 Richard Gooch
4 Copyright (c) 2002 Patrick Mochel
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Library General Public
8 License as published by the Free Software Foundation; either
9 version 2 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Library General Public License for more details.
16 You should have received a copy of the GNU Library General Public
17 License along with this library; if not, write to the Free
18 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
21 The postal address is:
22 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
24 Source: "Pentium Pro Family Developer's Manual, Volume 3:
25 Operating System Writer's Guide" (Intel document number 242692),
28 This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
30 Source: Intel Architecture Software Developers Manual, Volume 3:
31 System Programming Guide; Section 9.11. (1997 edition - PPro).
36 #include <linux/types.h> /* FIXME: kvm_para.h needs this */
38 #include <linux/stop_machine.h>
39 #include <linux/kvm_para.h>
40 #include <linux/uaccess.h>
41 #include <linux/module.h>
42 #include <linux/mutex.h>
43 #include <linux/init.h>
44 #include <linux/sort.h>
45 #include <linux/cpu.h>
46 #include <linux/pci.h>
47 #include <linux/smp.h>
48 #include <linux/syscore_ops.h>
50 #include <asm/processor.h>
59 unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
60 static DEFINE_MUTEX(mtrr_mutex);
62 u64 size_or_mask, size_and_mask;
63 static bool mtrr_aps_delayed_init;
65 static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM];
67 const struct mtrr_ops *mtrr_if;
69 static void set_mtrr(unsigned int reg, unsigned long base,
70 unsigned long size, mtrr_type type);
72 void set_mtrr_ops(const struct mtrr_ops *ops)
74 if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
75 mtrr_ops[ops->vendor] = ops;
78 /* Returns non-zero if we have the write-combining memory type */
79 static int have_wrcomb(void)
84 dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL);
87 * ServerWorks LE chipsets < rev 6 have problems with
88 * write-combining. Don't allow it and leave room for other
89 * chipsets to be tagged
91 if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
92 dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
93 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
95 pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
101 * Intel 450NX errata # 23. Non ascending cacheline evictions to
102 * write combining memory may resulting in data corruption
104 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
105 dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
106 pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
112 return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;
115 /* This function returns the number of variable MTRRs */
116 static void __init set_num_var_ranges(void)
118 unsigned long config = 0, dummy;
121 rdmsr(MSR_MTRRcap, config, dummy);
122 else if (is_cpu(AMD))
124 else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
127 num_var_ranges = config & 0xff;
130 static void __init init_table(void)
134 max = num_var_ranges;
135 for (i = 0; i < max; i++)
136 mtrr_usage_table[i] = 1;
139 struct set_mtrr_data {
142 unsigned long smp_base;
143 unsigned long smp_size;
144 unsigned int smp_reg;
148 static DEFINE_PER_CPU(struct cpu_stop_work, mtrr_work);
151 * mtrr_work_handler - Synchronisation handler. Executed by "other" CPUs.
152 * @info: pointer to mtrr configuration data
156 static int mtrr_work_handler(void *info)
159 struct set_mtrr_data *data = info;
162 atomic_dec(&data->count);
163 while (!atomic_read(&data->gate))
166 local_irq_save(flags);
168 atomic_dec(&data->count);
169 while (atomic_read(&data->gate))
172 /* The master has cleared me to execute */
173 if (data->smp_reg != ~0U) {
174 mtrr_if->set(data->smp_reg, data->smp_base,
175 data->smp_size, data->smp_type);
176 } else if (mtrr_aps_delayed_init) {
178 * Initialize the MTRRs inaddition to the synchronisation.
183 atomic_dec(&data->count);
184 while (!atomic_read(&data->gate))
187 atomic_dec(&data->count);
188 local_irq_restore(flags);
193 static inline int types_compatible(mtrr_type type1, mtrr_type type2)
195 return type1 == MTRR_TYPE_UNCACHABLE ||
196 type2 == MTRR_TYPE_UNCACHABLE ||
197 (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) ||
198 (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH);
202 * set_mtrr - update mtrrs on all processors
203 * @reg: mtrr in question
208 * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
210 * 1. Queue work to do the following on all processors:
211 * 2. Disable Interrupts
212 * 3. Wait for all procs to do so
213 * 4. Enter no-fill cache mode
217 * 8. Disable all range registers
218 * 9. Update the MTRRs
219 * 10. Enable all range registers
220 * 11. Flush all TLBs and caches again
221 * 12. Enter normal cache mode and reenable caching
223 * 14. Wait for buddies to catch up
224 * 15. Enable interrupts.
226 * What does that mean for us? Well, first we set data.count to the number
227 * of CPUs. As each CPU announces that it started the rendezvous handler by
228 * decrementing the count, We reset data.count and set the data.gate flag
229 * allowing all the cpu's to proceed with the work. As each cpu disables
230 * interrupts, it'll decrement data.count once. We wait until it hits 0 and
231 * proceed. We clear the data.gate flag and reset data.count. Meanwhile, they
232 * are waiting for that flag to be cleared. Once it's cleared, each
233 * CPU goes through the transition of updating MTRRs.
234 * The CPU vendors may each do it differently,
235 * so we call mtrr_if->set() callback and let them take care of it.
236 * When they're done, they again decrement data->count and wait for data.gate
238 * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag
239 * Everyone then enables interrupts and we all continue on.
241 * Note that the mechanism is the same for UP systems, too; all the SMP stuff
245 set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
247 struct set_mtrr_data data;
254 data.smp_base = base;
255 data.smp_size = size;
256 data.smp_type = type;
257 atomic_set(&data.count, num_booting_cpus() - 1);
259 /* Make sure data.count is visible before unleashing other CPUs */
261 atomic_set(&data.gate, 0);
263 /* Start the ball rolling on other CPUs */
264 for_each_online_cpu(cpu) {
265 struct cpu_stop_work *work = &per_cpu(mtrr_work, cpu);
267 if (cpu == smp_processor_id())
270 stop_one_cpu_nowait(cpu, mtrr_work_handler, &data, work);
274 while (atomic_read(&data.count))
277 /* Ok, reset count and toggle gate */
278 atomic_set(&data.count, num_booting_cpus() - 1);
280 atomic_set(&data.gate, 1);
282 local_irq_save(flags);
284 while (atomic_read(&data.count))
287 /* Ok, reset count and toggle gate */
288 atomic_set(&data.count, num_booting_cpus() - 1);
290 atomic_set(&data.gate, 0);
292 /* Do our MTRR business */
296 * We use this same function to initialize the mtrrs on boot.
297 * The state of the boot cpu's mtrrs has been saved, and we want
298 * to replicate across all the APs.
299 * If we're doing that @reg is set to something special...
302 mtrr_if->set(reg, base, size, type);
303 else if (!mtrr_aps_delayed_init)
306 /* Wait for the others */
307 while (atomic_read(&data.count))
310 atomic_set(&data.count, num_booting_cpus() - 1);
312 atomic_set(&data.gate, 1);
315 * Wait here for everyone to have seen the gate change
316 * So we're the last ones to touch 'data'
318 while (atomic_read(&data.count))
321 local_irq_restore(flags);
326 * mtrr_add_page - Add a memory type region
327 * @base: Physical base address of region in pages (in units of 4 kB!)
328 * @size: Physical size of region in pages (4 kB)
329 * @type: Type of MTRR desired
330 * @increment: If this is true do usage counting on the region
332 * Memory type region registers control the caching on newer Intel and
333 * non Intel processors. This function allows drivers to request an
334 * MTRR is added. The details and hardware specifics of each processor's
335 * implementation are hidden from the caller, but nevertheless the
336 * caller should expect to need to provide a power of two size on an
337 * equivalent power of two boundary.
339 * If the region cannot be added either because all regions are in use
340 * or the CPU cannot support it a negative value is returned. On success
341 * the register number for this entry is returned, but should be treated
344 * On a multiprocessor machine the changes are made to all processors.
345 * This is required on x86 by the Intel processors.
347 * The available types are
349 * %MTRR_TYPE_UNCACHABLE - No caching
351 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
353 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
355 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
357 * BUGS: Needs a quiet flag for the cases where drivers do not mind
358 * failures and do not wish system log messages to be sent.
360 int mtrr_add_page(unsigned long base, unsigned long size,
361 unsigned int type, bool increment)
363 unsigned long lbase, lsize;
364 int i, replace, error;
370 error = mtrr_if->validate_add_page(base, size, type);
374 if (type >= MTRR_NUM_TYPES) {
375 pr_warning("mtrr: type: %u invalid\n", type);
379 /* If the type is WC, check that this processor supports it */
380 if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
381 pr_warning("mtrr: your processor doesn't support write-combining\n");
386 pr_warning("mtrr: zero sized request\n");
390 if (base & size_or_mask || size & size_or_mask) {
391 pr_warning("mtrr: base or size exceeds the MTRR width\n");
398 /* No CPU hotplug when we change MTRR entries */
401 /* Search for existing MTRR */
402 mutex_lock(&mtrr_mutex);
403 for (i = 0; i < num_var_ranges; ++i) {
404 mtrr_if->get(i, &lbase, &lsize, <ype);
405 if (!lsize || base > lbase + lsize - 1 ||
406 base + size - 1 < lbase)
409 * At this point we know there is some kind of
412 if (base < lbase || base + size - 1 > lbase + lsize - 1) {
414 base + size - 1 >= lbase + lsize - 1) {
415 /* New region encloses an existing region */
417 replace = replace == -1 ? i : -2;
419 } else if (types_compatible(type, ltype))
422 pr_warning("mtrr: 0x%lx000,0x%lx000 overlaps existing"
423 " 0x%lx000,0x%lx000\n", base, size, lbase,
427 /* New region is enclosed by an existing region */
429 if (types_compatible(type, ltype))
431 pr_warning("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
432 base, size, mtrr_attrib_to_str(ltype),
433 mtrr_attrib_to_str(type));
437 ++mtrr_usage_table[i];
441 /* Search for an empty MTRR */
442 i = mtrr_if->get_free_region(base, size, replace);
444 set_mtrr(i, base, size, type);
445 if (likely(replace < 0)) {
446 mtrr_usage_table[i] = 1;
448 mtrr_usage_table[i] = mtrr_usage_table[replace];
450 mtrr_usage_table[i]++;
451 if (unlikely(replace != i)) {
452 set_mtrr(replace, 0, 0, 0);
453 mtrr_usage_table[replace] = 0;
457 pr_info("mtrr: no more MTRRs available\n");
461 mutex_unlock(&mtrr_mutex);
466 static int mtrr_check(unsigned long base, unsigned long size)
468 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
469 pr_warning("mtrr: size and base must be multiples of 4 kiB\n");
470 pr_debug("mtrr: size: 0x%lx base: 0x%lx\n", size, base);
478 * mtrr_add - Add a memory type region
479 * @base: Physical base address of region
480 * @size: Physical size of region
481 * @type: Type of MTRR desired
482 * @increment: If this is true do usage counting on the region
484 * Memory type region registers control the caching on newer Intel and
485 * non Intel processors. This function allows drivers to request an
486 * MTRR is added. The details and hardware specifics of each processor's
487 * implementation are hidden from the caller, but nevertheless the
488 * caller should expect to need to provide a power of two size on an
489 * equivalent power of two boundary.
491 * If the region cannot be added either because all regions are in use
492 * or the CPU cannot support it a negative value is returned. On success
493 * the register number for this entry is returned, but should be treated
496 * On a multiprocessor machine the changes are made to all processors.
497 * This is required on x86 by the Intel processors.
499 * The available types are
501 * %MTRR_TYPE_UNCACHABLE - No caching
503 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
505 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
507 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
509 * BUGS: Needs a quiet flag for the cases where drivers do not mind
510 * failures and do not wish system log messages to be sent.
512 int mtrr_add(unsigned long base, unsigned long size, unsigned int type,
515 if (mtrr_check(base, size))
517 return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
520 EXPORT_SYMBOL(mtrr_add);
523 * mtrr_del_page - delete a memory type region
524 * @reg: Register returned by mtrr_add
525 * @base: Physical base address
526 * @size: Size of region
528 * If register is supplied then base and size are ignored. This is
529 * how drivers should call it.
531 * Releases an MTRR region. If the usage count drops to zero the
532 * register is freed and the region returns to default state.
533 * On success the register is returned, on failure a negative error
536 int mtrr_del_page(int reg, unsigned long base, unsigned long size)
540 unsigned long lbase, lsize;
546 max = num_var_ranges;
547 /* No CPU hotplug when we change MTRR entries */
549 mutex_lock(&mtrr_mutex);
551 /* Search for existing MTRR */
552 for (i = 0; i < max; ++i) {
553 mtrr_if->get(i, &lbase, &lsize, <ype);
554 if (lbase == base && lsize == size) {
560 pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n",
566 pr_warning("mtrr: register: %d too big\n", reg);
569 mtrr_if->get(reg, &lbase, &lsize, <ype);
571 pr_warning("mtrr: MTRR %d not used\n", reg);
574 if (mtrr_usage_table[reg] < 1) {
575 pr_warning("mtrr: reg: %d has count=0\n", reg);
578 if (--mtrr_usage_table[reg] < 1)
579 set_mtrr(reg, 0, 0, 0);
582 mutex_unlock(&mtrr_mutex);
588 * mtrr_del - delete a memory type region
589 * @reg: Register returned by mtrr_add
590 * @base: Physical base address
591 * @size: Size of region
593 * If register is supplied then base and size are ignored. This is
594 * how drivers should call it.
596 * Releases an MTRR region. If the usage count drops to zero the
597 * register is freed and the region returns to default state.
598 * On success the register is returned, on failure a negative error
601 int mtrr_del(int reg, unsigned long base, unsigned long size)
603 if (mtrr_check(base, size))
605 return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
607 EXPORT_SYMBOL(mtrr_del);
611 * These should be called implicitly, but we can't yet until all the initcall
614 static void __init init_ifs(void)
616 #ifndef CONFIG_X86_64
623 /* The suspend/resume methods are only for CPU without MTRR. CPU using generic
624 * MTRR driver doesn't require this
632 static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES];
634 static int mtrr_save(void)
638 for (i = 0; i < num_var_ranges; i++) {
639 mtrr_if->get(i, &mtrr_value[i].lbase,
640 &mtrr_value[i].lsize,
641 &mtrr_value[i].ltype);
646 static void mtrr_restore(void)
650 for (i = 0; i < num_var_ranges; i++) {
651 if (mtrr_value[i].lsize) {
652 set_mtrr(i, mtrr_value[i].lbase,
654 mtrr_value[i].ltype);
661 static struct syscore_ops mtrr_syscore_ops = {
662 .suspend = mtrr_save,
663 .resume = mtrr_restore,
666 int __initdata changed_by_mtrr_cleanup;
669 * mtrr_bp_init - initialize mtrrs on the boot CPU
671 * This needs to be called early; before any of the other CPUs are
672 * initialized (i.e. before smp_init()).
675 void __init mtrr_bp_init(void)
684 mtrr_if = &generic_mtrr_ops;
685 size_or_mask = 0xff000000; /* 36 bits */
686 size_and_mask = 0x00f00000;
690 * This is an AMD specific MSR, but we assume(hope?) that
691 * Intel will implement it to when they extend the address
694 if (cpuid_eax(0x80000000) >= 0x80000008) {
695 phys_addr = cpuid_eax(0x80000008) & 0xff;
696 /* CPUID workaround for Intel 0F33/0F34 CPU */
697 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
698 boot_cpu_data.x86 == 0xF &&
699 boot_cpu_data.x86_model == 0x3 &&
700 (boot_cpu_data.x86_mask == 0x3 ||
701 boot_cpu_data.x86_mask == 0x4))
704 size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1);
705 size_and_mask = ~size_or_mask & 0xfffff00000ULL;
706 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
707 boot_cpu_data.x86 == 6) {
709 * VIA C* family have Intel style MTRRs,
710 * but don't support PAE
712 size_or_mask = 0xfff00000; /* 32 bits */
717 switch (boot_cpu_data.x86_vendor) {
719 if (cpu_has_k6_mtrr) {
720 /* Pre-Athlon (K6) AMD CPU MTRRs */
721 mtrr_if = mtrr_ops[X86_VENDOR_AMD];
722 size_or_mask = 0xfff00000; /* 32 bits */
726 case X86_VENDOR_CENTAUR:
727 if (cpu_has_centaur_mcr) {
728 mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
729 size_or_mask = 0xfff00000; /* 32 bits */
733 case X86_VENDOR_CYRIX:
734 if (cpu_has_cyrix_arr) {
735 mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
736 size_or_mask = 0xfff00000; /* 32 bits */
746 set_num_var_ranges();
751 if (mtrr_cleanup(phys_addr)) {
752 changed_by_mtrr_cleanup = 1;
759 void mtrr_ap_init(void)
761 if (!use_intel() || mtrr_aps_delayed_init)
764 * Ideally we should hold mtrr_mutex here to avoid mtrr entries
765 * changed, but this routine will be called in cpu boot time,
766 * holding the lock breaks it.
768 * This routine is called in two cases:
770 * 1. very earily time of software resume, when there absolutely
771 * isn't mtrr entry changes;
773 * 2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug
774 * lock to prevent mtrr entry changes
776 set_mtrr(~0U, 0, 0, 0);
780 * Save current fixed-range MTRR state of the BSP
782 void mtrr_save_state(void)
784 smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1);
787 void set_mtrr_aps_delayed_init(void)
792 mtrr_aps_delayed_init = true;
796 * Delayed MTRR initialization for all AP's
798 void mtrr_aps_init(void)
804 * Check if someone has requested the delay of AP MTRR initialization,
805 * by doing set_mtrr_aps_delayed_init(), prior to this point. If not,
808 if (!mtrr_aps_delayed_init)
811 set_mtrr(~0U, 0, 0, 0);
812 mtrr_aps_delayed_init = false;
815 void mtrr_bp_restore(void)
823 static int __init mtrr_init_finialize(void)
829 if (!changed_by_mtrr_cleanup)
835 * The CPU has no MTRR and seems to not support SMP. They have
836 * specific drivers, we use a tricky method to support
837 * suspend/resume for them.
839 * TBD: is there any system with such CPU which supports
840 * suspend/resume? If no, we should remove the code.
842 register_syscore_ops(&mtrr_syscore_ops);
846 subsys_initcall(mtrr_init_finialize);