2 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
3 * because MTRRs can span upto 40 bits (36bits on most modern x86)
7 #include <linux/module.h>
8 #include <linux/init.h>
12 #include <asm/processor-flags.h>
13 #include <asm/cpufeature.h>
14 #include <asm/tlbflush.h>
15 #include <asm/system.h>
22 struct fixed_range_block {
23 int base_msr; /* start address of an MTRR block */
24 int ranges; /* number of MTRRs in this block */
27 static struct fixed_range_block fixed_range_blocks[] = {
28 { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */
29 { MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */
30 { MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */
34 static unsigned long smp_changes_mask;
35 static int mtrr_state_set;
38 struct mtrr_state_type mtrr_state;
39 EXPORT_SYMBOL_GPL(mtrr_state);
42 * BIOS is expected to clear MtrrFixDramModEn bit, see for example
43 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
44 * Opteron Processors" (26094 Rev. 3.30 February 2006), section
45 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set
46 * to 1 during BIOS initalization of the fixed MTRRs, then cleared to
49 static inline void k8_check_syscfg_dram_mod_en(void)
53 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
54 (boot_cpu_data.x86 >= 0x0f)))
57 rdmsr(MSR_K8_SYSCFG, lo, hi);
58 if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
59 printk(KERN_ERR FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
60 " not cleared by BIOS, clearing this bit\n",
62 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
63 mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi);
68 * Returns the effective MTRR type for the region
70 * - 0xFE - when the range is "not entirely covered" by _any_ var range MTRR
71 * - 0xFF - when MTRR is not enabled
73 u8 mtrr_type_lookup(u64 start, u64 end)
77 u8 prev_match, curr_match;
82 if (!mtrr_state.enabled)
85 /* Make end inclusive end, instead of exclusive */
88 /* Look in fixed ranges. Just return the type as per start */
89 if (mtrr_state.have_fixed && (start < 0x100000)) {
92 if (start < 0x80000) {
95 return mtrr_state.fixed_ranges[idx];
96 } else if (start < 0xC0000) {
98 idx += ((start - 0x80000) >> 14);
99 return mtrr_state.fixed_ranges[idx];
100 } else if (start < 0x1000000) {
102 idx += ((start - 0xC0000) >> 12);
103 return mtrr_state.fixed_ranges[idx];
108 * Look in variable ranges
109 * Look of multiple ranges matching this address and pick type
110 * as per MTRR precedence
112 if (!(mtrr_state.enabled & 2))
113 return mtrr_state.def_type;
116 for (i = 0; i < num_var_ranges; ++i) {
117 unsigned short start_state, end_state;
119 if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11)))
122 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) +
123 (mtrr_state.var_ranges[i].base_lo & PAGE_MASK);
124 mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) +
125 (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK);
127 start_state = ((start & mask) == (base & mask));
128 end_state = ((end & mask) == (base & mask));
129 if (start_state != end_state)
132 if ((start & mask) != (base & mask))
135 curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;
136 if (prev_match == 0xFF) {
137 prev_match = curr_match;
141 if (prev_match == MTRR_TYPE_UNCACHABLE ||
142 curr_match == MTRR_TYPE_UNCACHABLE) {
143 return MTRR_TYPE_UNCACHABLE;
146 if ((prev_match == MTRR_TYPE_WRBACK &&
147 curr_match == MTRR_TYPE_WRTHROUGH) ||
148 (prev_match == MTRR_TYPE_WRTHROUGH &&
149 curr_match == MTRR_TYPE_WRBACK)) {
150 prev_match = MTRR_TYPE_WRTHROUGH;
151 curr_match = MTRR_TYPE_WRTHROUGH;
154 if (prev_match != curr_match)
155 return MTRR_TYPE_UNCACHABLE;
159 if (start >= (1ULL<<32) && (end < mtrr_tom2))
160 return MTRR_TYPE_WRBACK;
163 if (prev_match != 0xFF)
166 return mtrr_state.def_type;
169 /* Get the MSR pair relating to a var range */
171 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
173 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
174 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
177 /* Fill the MSR pair relating to a var range */
178 void fill_mtrr_var_range(unsigned int index,
179 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
181 struct mtrr_var_range *vr;
183 vr = mtrr_state.var_ranges;
185 vr[index].base_lo = base_lo;
186 vr[index].base_hi = base_hi;
187 vr[index].mask_lo = mask_lo;
188 vr[index].mask_hi = mask_hi;
191 static void get_fixed_ranges(mtrr_type *frs)
193 unsigned int *p = (unsigned int *)frs;
196 k8_check_syscfg_dram_mod_en();
198 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]);
200 for (i = 0; i < 2; i++)
201 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
202 for (i = 0; i < 8; i++)
203 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
206 void mtrr_save_fixed_ranges(void *info)
209 get_fixed_ranges(mtrr_state.fixed_ranges);
212 static unsigned __initdata last_fixed_start;
213 static unsigned __initdata last_fixed_end;
214 static mtrr_type __initdata last_fixed_type;
216 static void __init print_fixed_last(void)
221 pr_debug(" %05X-%05X %s\n", last_fixed_start,
222 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
227 static void __init update_fixed_last(unsigned base, unsigned end,
230 last_fixed_start = base;
231 last_fixed_end = end;
232 last_fixed_type = type;
236 print_fixed(unsigned base, unsigned step, const mtrr_type *types)
240 for (i = 0; i < 8; ++i, ++types, base += step) {
241 if (last_fixed_end == 0) {
242 update_fixed_last(base, base + step, *types);
245 if (last_fixed_end == base && last_fixed_type == *types) {
246 last_fixed_end = base + step;
249 /* new segments: gap or different type */
251 update_fixed_last(base, base + step, *types);
255 static void prepare_set(void);
256 static void post_set(void);
258 static void __init print_mtrr_state(void)
263 pr_debug("MTRR default type: %s\n",
264 mtrr_attrib_to_str(mtrr_state.def_type));
265 if (mtrr_state.have_fixed) {
266 pr_debug("MTRR fixed ranges %sabled:\n",
267 mtrr_state.enabled & 1 ? "en" : "dis");
268 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);
269 for (i = 0; i < 2; ++i)
270 print_fixed(0x80000 + i * 0x20000, 0x04000,
271 mtrr_state.fixed_ranges + (i + 1) * 8);
272 for (i = 0; i < 8; ++i)
273 print_fixed(0xC0000 + i * 0x08000, 0x01000,
274 mtrr_state.fixed_ranges + (i + 3) * 8);
279 pr_debug("MTRR variable ranges %sabled:\n",
280 mtrr_state.enabled & 2 ? "en" : "dis");
281 if (size_or_mask & 0xffffffffUL)
282 high_width = ffs(size_or_mask & 0xffffffffUL) - 1;
284 high_width = ffs(size_or_mask>>32) + 32 - 1;
285 high_width = (high_width - (32 - PAGE_SHIFT) + 3) / 4;
287 for (i = 0; i < num_var_ranges; ++i) {
288 if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
289 pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n",
292 mtrr_state.var_ranges[i].base_hi,
293 mtrr_state.var_ranges[i].base_lo >> 12,
295 mtrr_state.var_ranges[i].mask_hi,
296 mtrr_state.var_ranges[i].mask_lo >> 12,
297 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));
299 pr_debug(" %u disabled\n", i);
302 pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
305 /* Grab all of the MTRR state for this CPU into *state */
306 void __init get_mtrr_state(void)
308 struct mtrr_var_range *vrs;
313 vrs = mtrr_state.var_ranges;
315 rdmsr(MSR_MTRRcap, lo, dummy);
316 mtrr_state.have_fixed = (lo >> 8) & 1;
318 for (i = 0; i < num_var_ranges; i++)
319 get_mtrr_var_range(i, &vrs[i]);
320 if (mtrr_state.have_fixed)
321 get_fixed_ranges(mtrr_state.fixed_ranges);
323 rdmsr(MSR_MTRRdefType, lo, dummy);
324 mtrr_state.def_type = (lo & 0xff);
325 mtrr_state.enabled = (lo & 0xc00) >> 10;
327 if (amd_special_default_mtrr()) {
331 rdmsr(MSR_K8_TOP_MEM2, low, high);
335 mtrr_tom2 &= 0xffffff800000ULL;
342 /* PAT setup for BP. We need to go through sync steps here */
343 local_irq_save(flags);
349 local_irq_restore(flags);
352 /* Some BIOS's are messed up and don't set all MTRRs the same! */
353 void __init mtrr_state_warn(void)
355 unsigned long mask = smp_changes_mask;
359 if (mask & MTRR_CHANGE_MASK_FIXED)
360 pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n");
361 if (mask & MTRR_CHANGE_MASK_VARIABLE)
362 pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n");
363 if (mask & MTRR_CHANGE_MASK_DEFTYPE)
364 pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n");
366 printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
367 printk(KERN_INFO "mtrr: corrected configuration.\n");
371 * Doesn't attempt to pass an error out to MTRR users
372 * because it's quite complicated in some cases and probably not
373 * worth it because the best error handling is to ignore it.
375 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
377 if (wrmsr_safe(msr, a, b) < 0) {
379 "MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
380 smp_processor_id(), msr, a, b);
385 * set_fixed_range - checks & updates a fixed-range MTRR if it
386 * differs from the value it should have
387 * @msr: MSR address of the MTTR which should be checked and updated
388 * @changed: pointer which indicates whether the MTRR needed to be changed
389 * @msrwords: pointer to the MSR values which the MSR should have
391 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
397 if (lo != msrwords[0] || hi != msrwords[1]) {
398 mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
404 * generic_get_free_region - Get a free MTRR.
405 * @base: The starting (base) address of the region.
406 * @size: The size (in bytes) of the region.
407 * @replace_reg: mtrr index to be replaced; set to invalid value if none.
409 * Returns: The index of the region on success, else negative on error.
412 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
414 unsigned long lbase, lsize;
418 max = num_var_ranges;
419 if (replace_reg >= 0 && replace_reg < max)
422 for (i = 0; i < max; ++i) {
423 mtrr_if->get(i, &lbase, &lsize, <ype);
431 static void generic_get_mtrr(unsigned int reg, unsigned long *base,
432 unsigned long *size, mtrr_type *type)
434 unsigned int mask_lo, mask_hi, base_lo, base_hi;
435 unsigned int tmp, hi;
439 * get_mtrr doesn't need to update mtrr_state, also it could be called
440 * from any cpu, so try to print it out directly.
444 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
446 if ((mask_lo & 0x800) == 0) {
447 /* Invalid (i.e. free) range */
454 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
456 /* Work out the shifted address mask: */
457 tmp = mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
458 mask_lo = size_or_mask | tmp;
460 /* Expand tmp with high bits to all 1s: */
463 tmp |= ~((1<<(hi - 1)) - 1);
465 if (tmp != mask_lo) {
466 printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
472 * This works correctly if size is a power of two, i.e. a
476 *base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
477 *type = base_lo & 0xff;
484 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they
485 * differ from the saved set
486 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
488 static int set_fixed_ranges(mtrr_type *frs)
490 unsigned long long *saved = (unsigned long long *)frs;
491 bool changed = false;
492 int block = -1, range;
494 k8_check_syscfg_dram_mod_en();
496 while (fixed_range_blocks[++block].ranges) {
497 for (range = 0; range < fixed_range_blocks[block].ranges; range++)
498 set_fixed_range(fixed_range_blocks[block].base_msr + range,
499 &changed, (unsigned int *)saved++);
506 * Set the MSR pair relating to a var range.
507 * Returns true if changes are made.
509 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
512 bool changed = false;
514 rdmsr(MTRRphysBase_MSR(index), lo, hi);
515 if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
516 || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
517 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
519 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
523 rdmsr(MTRRphysMask_MSR(index), lo, hi);
525 if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
526 || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
527 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
528 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
534 static u32 deftype_lo, deftype_hi;
537 * set_mtrr_state - Set the MTRR state for this CPU.
539 * NOTE: The CPU must already be in a safe state for MTRR changes.
540 * RETURNS: 0 if no changes made, else a mask indicating what was changed.
542 static unsigned long set_mtrr_state(void)
544 unsigned long change_mask = 0;
547 for (i = 0; i < num_var_ranges; i++) {
548 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
549 change_mask |= MTRR_CHANGE_MASK_VARIABLE;
552 if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
553 change_mask |= MTRR_CHANGE_MASK_FIXED;
556 * Set_mtrr_restore restores the old value of MTRRdefType,
557 * so to set it we fiddle with the saved value:
559 if ((deftype_lo & 0xff) != mtrr_state.def_type
560 || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
562 deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type |
563 (mtrr_state.enabled << 10);
564 change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
571 static unsigned long cr4;
572 static DEFINE_RAW_SPINLOCK(set_atomicity_lock);
575 * Since we are disabling the cache don't allow any interrupts,
576 * they would run extremely slow and would only increase the pain.
578 * The caller must ensure that local interrupts are disabled and
579 * are reenabled after post_set() has been called.
581 static void prepare_set(void) __acquires(set_atomicity_lock)
586 * Note that this is not ideal
587 * since the cache is only flushed/disabled for this CPU while the
588 * MTRRs are changed, but changing this requires more invasive
589 * changes to the way the kernel boots
592 raw_spin_lock(&set_atomicity_lock);
594 /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
595 cr0 = read_cr0() | X86_CR0_CD;
599 /* Save value of CR4 and clear Page Global Enable (bit 7) */
602 write_cr4(cr4 & ~X86_CR4_PGE);
605 /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
608 /* Save MTRR state */
609 rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
611 /* Disable MTRRs, and set the default type to uncached */
612 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
615 static void post_set(void) __releases(set_atomicity_lock)
617 /* Flush TLBs (no need to flush caches - they are disabled) */
620 /* Intel (P6) standard MTRRs */
621 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
624 write_cr0(read_cr0() & 0xbfffffff);
626 /* Restore value of CR4 */
629 raw_spin_unlock(&set_atomicity_lock);
632 static void generic_set_all(void)
634 unsigned long mask, count;
637 local_irq_save(flags);
640 /* Actually set the state */
641 mask = set_mtrr_state();
647 local_irq_restore(flags);
649 /* Use the atomic bitops to update the global mask */
650 for (count = 0; count < sizeof mask * 8; ++count) {
652 set_bit(count, &smp_changes_mask);
659 * generic_set_mtrr - set variable MTRR register on the local CPU.
661 * @reg: The register to set.
662 * @base: The base address of the region.
663 * @size: The size of the region. If this is 0 the region is disabled.
664 * @type: The type of the region.
668 static void generic_set_mtrr(unsigned int reg, unsigned long base,
669 unsigned long size, mtrr_type type)
672 struct mtrr_var_range *vr;
674 vr = &mtrr_state.var_ranges[reg];
676 local_irq_save(flags);
681 * The invalid bit is kept in the mask, so we simply
682 * clear the relevant mask register to disable a range.
684 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
685 memset(vr, 0, sizeof(struct mtrr_var_range));
687 vr->base_lo = base << PAGE_SHIFT | type;
688 vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
689 vr->mask_lo = -size << PAGE_SHIFT | 0x800;
690 vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
692 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi);
693 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi);
697 local_irq_restore(flags);
700 int generic_validate_add_page(unsigned long base, unsigned long size,
703 unsigned long lbase, last;
706 * For Intel PPro stepping <= 7
707 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF
709 if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
710 boot_cpu_data.x86_model == 1 &&
711 boot_cpu_data.x86_mask <= 7) {
712 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
713 pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
716 if (!(base + size < 0x70000 || base > 0x7003F) &&
717 (type == MTRR_TYPE_WRCOMB
718 || type == MTRR_TYPE_WRBACK)) {
719 pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
725 * Check upper bits of base and last are equal and lower bits are 0
726 * for base and 1 for last
728 last = base + size - 1;
729 for (lbase = base; !(lbase & 1) && (last & 1);
730 lbase = lbase >> 1, last = last >> 1)
733 pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);
739 static int generic_have_wrcomb(void)
741 unsigned long config, dummy;
742 rdmsr(MSR_MTRRcap, config, dummy);
743 return config & (1 << 10);
746 int positive_have_wrcomb(void)
752 * Generic structure...
754 const struct mtrr_ops generic_mtrr_ops = {
756 .set_all = generic_set_all,
757 .get = generic_get_mtrr,
758 .get_free_region = generic_get_free_region,
759 .set = generic_set_mtrr,
760 .validate_add_page = generic_validate_add_page,
761 .have_wrcomb = generic_have_wrcomb,