2 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
3 * because MTRRs can span upto 40 bits (36bits on most modern x86)
7 #include <linux/module.h>
8 #include <linux/init.h>
9 #include <linux/slab.h>
13 #include <asm/processor-flags.h>
14 #include <asm/cpufeature.h>
15 #include <asm/tlbflush.h>
16 #include <asm/system.h>
23 struct fixed_range_block {
24 int base_msr; /* start address of an MTRR block */
25 int ranges; /* number of MTRRs in this block */
28 static struct fixed_range_block fixed_range_blocks[] = {
29 { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */
30 { MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */
31 { MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */
35 static unsigned long smp_changes_mask;
36 static int mtrr_state_set;
39 struct mtrr_state_type mtrr_state;
40 EXPORT_SYMBOL_GPL(mtrr_state);
43 * BIOS is expected to clear MtrrFixDramModEn bit, see for example
44 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
45 * Opteron Processors" (26094 Rev. 3.30 February 2006), section
46 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set
47 * to 1 during BIOS initalization of the fixed MTRRs, then cleared to
50 static inline void k8_check_syscfg_dram_mod_en(void)
54 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
55 (boot_cpu_data.x86 >= 0x0f)))
58 rdmsr(MSR_K8_SYSCFG, lo, hi);
59 if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
60 printk(KERN_ERR FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
61 " not cleared by BIOS, clearing this bit\n",
63 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
64 mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi);
69 * Returns the effective MTRR type for the region
71 * - 0xFE - when the range is "not entirely covered" by _any_ var range MTRR
72 * - 0xFF - when MTRR is not enabled
74 u8 mtrr_type_lookup(u64 start, u64 end)
78 u8 prev_match, curr_match;
83 if (!mtrr_state.enabled)
86 /* Make end inclusive end, instead of exclusive */
89 /* Look in fixed ranges. Just return the type as per start */
90 if (mtrr_state.have_fixed && (start < 0x100000)) {
93 if (start < 0x80000) {
96 return mtrr_state.fixed_ranges[idx];
97 } else if (start < 0xC0000) {
99 idx += ((start - 0x80000) >> 14);
100 return mtrr_state.fixed_ranges[idx];
101 } else if (start < 0x1000000) {
103 idx += ((start - 0xC0000) >> 12);
104 return mtrr_state.fixed_ranges[idx];
109 * Look in variable ranges
110 * Look of multiple ranges matching this address and pick type
111 * as per MTRR precedence
113 if (!(mtrr_state.enabled & 2))
114 return mtrr_state.def_type;
117 for (i = 0; i < num_var_ranges; ++i) {
118 unsigned short start_state, end_state;
120 if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11)))
123 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) +
124 (mtrr_state.var_ranges[i].base_lo & PAGE_MASK);
125 mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) +
126 (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK);
128 start_state = ((start & mask) == (base & mask));
129 end_state = ((end & mask) == (base & mask));
130 if (start_state != end_state)
133 if ((start & mask) != (base & mask))
136 curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;
137 if (prev_match == 0xFF) {
138 prev_match = curr_match;
142 if (prev_match == MTRR_TYPE_UNCACHABLE ||
143 curr_match == MTRR_TYPE_UNCACHABLE) {
144 return MTRR_TYPE_UNCACHABLE;
147 if ((prev_match == MTRR_TYPE_WRBACK &&
148 curr_match == MTRR_TYPE_WRTHROUGH) ||
149 (prev_match == MTRR_TYPE_WRTHROUGH &&
150 curr_match == MTRR_TYPE_WRBACK)) {
151 prev_match = MTRR_TYPE_WRTHROUGH;
152 curr_match = MTRR_TYPE_WRTHROUGH;
155 if (prev_match != curr_match)
156 return MTRR_TYPE_UNCACHABLE;
160 if (start >= (1ULL<<32) && (end < mtrr_tom2))
161 return MTRR_TYPE_WRBACK;
164 if (prev_match != 0xFF)
167 return mtrr_state.def_type;
170 /* Get the MSR pair relating to a var range */
172 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
174 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
175 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
178 /* Fill the MSR pair relating to a var range */
179 void fill_mtrr_var_range(unsigned int index,
180 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
182 struct mtrr_var_range *vr;
184 vr = mtrr_state.var_ranges;
186 vr[index].base_lo = base_lo;
187 vr[index].base_hi = base_hi;
188 vr[index].mask_lo = mask_lo;
189 vr[index].mask_hi = mask_hi;
192 static void get_fixed_ranges(mtrr_type *frs)
194 unsigned int *p = (unsigned int *)frs;
197 k8_check_syscfg_dram_mod_en();
199 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]);
201 for (i = 0; i < 2; i++)
202 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
203 for (i = 0; i < 8; i++)
204 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
207 void mtrr_save_fixed_ranges(void *info)
210 get_fixed_ranges(mtrr_state.fixed_ranges);
213 static unsigned __initdata last_fixed_start;
214 static unsigned __initdata last_fixed_end;
215 static mtrr_type __initdata last_fixed_type;
217 static void __init print_fixed_last(void)
222 pr_debug(" %05X-%05X %s\n", last_fixed_start,
223 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
228 static void __init update_fixed_last(unsigned base, unsigned end,
231 last_fixed_start = base;
232 last_fixed_end = end;
233 last_fixed_type = type;
237 print_fixed(unsigned base, unsigned step, const mtrr_type *types)
241 for (i = 0; i < 8; ++i, ++types, base += step) {
242 if (last_fixed_end == 0) {
243 update_fixed_last(base, base + step, *types);
246 if (last_fixed_end == base && last_fixed_type == *types) {
247 last_fixed_end = base + step;
250 /* new segments: gap or different type */
252 update_fixed_last(base, base + step, *types);
256 static void prepare_set(void);
257 static void post_set(void);
259 static void __init print_mtrr_state(void)
264 pr_debug("MTRR default type: %s\n",
265 mtrr_attrib_to_str(mtrr_state.def_type));
266 if (mtrr_state.have_fixed) {
267 pr_debug("MTRR fixed ranges %sabled:\n",
268 mtrr_state.enabled & 1 ? "en" : "dis");
269 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);
270 for (i = 0; i < 2; ++i)
271 print_fixed(0x80000 + i * 0x20000, 0x04000,
272 mtrr_state.fixed_ranges + (i + 1) * 8);
273 for (i = 0; i < 8; ++i)
274 print_fixed(0xC0000 + i * 0x08000, 0x01000,
275 mtrr_state.fixed_ranges + (i + 3) * 8);
280 pr_debug("MTRR variable ranges %sabled:\n",
281 mtrr_state.enabled & 2 ? "en" : "dis");
282 if (size_or_mask & 0xffffffffUL)
283 high_width = ffs(size_or_mask & 0xffffffffUL) - 1;
285 high_width = ffs(size_or_mask>>32) + 32 - 1;
286 high_width = (high_width - (32 - PAGE_SHIFT) + 3) / 4;
288 for (i = 0; i < num_var_ranges; ++i) {
289 if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
290 pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n",
293 mtrr_state.var_ranges[i].base_hi,
294 mtrr_state.var_ranges[i].base_lo >> 12,
296 mtrr_state.var_ranges[i].mask_hi,
297 mtrr_state.var_ranges[i].mask_lo >> 12,
298 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));
300 pr_debug(" %u disabled\n", i);
303 pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
306 /* Grab all of the MTRR state for this CPU into *state */
307 void __init get_mtrr_state(void)
309 struct mtrr_var_range *vrs;
314 vrs = mtrr_state.var_ranges;
316 rdmsr(MSR_MTRRcap, lo, dummy);
317 mtrr_state.have_fixed = (lo >> 8) & 1;
319 for (i = 0; i < num_var_ranges; i++)
320 get_mtrr_var_range(i, &vrs[i]);
321 if (mtrr_state.have_fixed)
322 get_fixed_ranges(mtrr_state.fixed_ranges);
324 rdmsr(MSR_MTRRdefType, lo, dummy);
325 mtrr_state.def_type = (lo & 0xff);
326 mtrr_state.enabled = (lo & 0xc00) >> 10;
328 if (amd_special_default_mtrr()) {
332 rdmsr(MSR_K8_TOP_MEM2, low, high);
336 mtrr_tom2 &= 0xffffff800000ULL;
343 /* PAT setup for BP. We need to go through sync steps here */
344 local_irq_save(flags);
350 local_irq_restore(flags);
353 /* Some BIOS's are messed up and don't set all MTRRs the same! */
354 void __init mtrr_state_warn(void)
356 unsigned long mask = smp_changes_mask;
360 if (mask & MTRR_CHANGE_MASK_FIXED)
361 pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n");
362 if (mask & MTRR_CHANGE_MASK_VARIABLE)
363 pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n");
364 if (mask & MTRR_CHANGE_MASK_DEFTYPE)
365 pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n");
367 printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
368 printk(KERN_INFO "mtrr: corrected configuration.\n");
372 * Doesn't attempt to pass an error out to MTRR users
373 * because it's quite complicated in some cases and probably not
374 * worth it because the best error handling is to ignore it.
376 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
378 if (wrmsr_safe(msr, a, b) < 0) {
380 "MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
381 smp_processor_id(), msr, a, b);
386 * set_fixed_range - checks & updates a fixed-range MTRR if it
387 * differs from the value it should have
388 * @msr: MSR address of the MTTR which should be checked and updated
389 * @changed: pointer which indicates whether the MTRR needed to be changed
390 * @msrwords: pointer to the MSR values which the MSR should have
392 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
398 if (lo != msrwords[0] || hi != msrwords[1]) {
399 mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
405 * generic_get_free_region - Get a free MTRR.
406 * @base: The starting (base) address of the region.
407 * @size: The size (in bytes) of the region.
408 * @replace_reg: mtrr index to be replaced; set to invalid value if none.
410 * Returns: The index of the region on success, else negative on error.
413 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
415 unsigned long lbase, lsize;
419 max = num_var_ranges;
420 if (replace_reg >= 0 && replace_reg < max)
423 for (i = 0; i < max; ++i) {
424 mtrr_if->get(i, &lbase, &lsize, <ype);
432 static void generic_get_mtrr(unsigned int reg, unsigned long *base,
433 unsigned long *size, mtrr_type *type)
435 unsigned int mask_lo, mask_hi, base_lo, base_hi;
436 unsigned int tmp, hi;
440 * get_mtrr doesn't need to update mtrr_state, also it could be called
441 * from any cpu, so try to print it out directly.
445 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
447 if ((mask_lo & 0x800) == 0) {
448 /* Invalid (i.e. free) range */
455 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
457 /* Work out the shifted address mask: */
458 tmp = mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
459 mask_lo = size_or_mask | tmp;
461 /* Expand tmp with high bits to all 1s: */
464 tmp |= ~((1<<(hi - 1)) - 1);
466 if (tmp != mask_lo) {
467 printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
473 * This works correctly if size is a power of two, i.e. a
477 *base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
478 *type = base_lo & 0xff;
485 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they
486 * differ from the saved set
487 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
489 static int set_fixed_ranges(mtrr_type *frs)
491 unsigned long long *saved = (unsigned long long *)frs;
492 bool changed = false;
493 int block = -1, range;
495 k8_check_syscfg_dram_mod_en();
497 while (fixed_range_blocks[++block].ranges) {
498 for (range = 0; range < fixed_range_blocks[block].ranges; range++)
499 set_fixed_range(fixed_range_blocks[block].base_msr + range,
500 &changed, (unsigned int *)saved++);
507 * Set the MSR pair relating to a var range.
508 * Returns true if changes are made.
510 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
513 bool changed = false;
515 rdmsr(MTRRphysBase_MSR(index), lo, hi);
516 if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
517 || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
518 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
520 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
524 rdmsr(MTRRphysMask_MSR(index), lo, hi);
526 if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
527 || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
528 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
529 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
535 static u32 deftype_lo, deftype_hi;
538 * set_mtrr_state - Set the MTRR state for this CPU.
540 * NOTE: The CPU must already be in a safe state for MTRR changes.
541 * RETURNS: 0 if no changes made, else a mask indicating what was changed.
543 static unsigned long set_mtrr_state(void)
545 unsigned long change_mask = 0;
548 for (i = 0; i < num_var_ranges; i++) {
549 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
550 change_mask |= MTRR_CHANGE_MASK_VARIABLE;
553 if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
554 change_mask |= MTRR_CHANGE_MASK_FIXED;
557 * Set_mtrr_restore restores the old value of MTRRdefType,
558 * so to set it we fiddle with the saved value:
560 if ((deftype_lo & 0xff) != mtrr_state.def_type
561 || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
563 deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type |
564 (mtrr_state.enabled << 10);
565 change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
572 static unsigned long cr4;
573 static DEFINE_RAW_SPINLOCK(set_atomicity_lock);
576 * Since we are disabling the cache don't allow any interrupts,
577 * they would run extremely slow and would only increase the pain.
579 * The caller must ensure that local interrupts are disabled and
580 * are reenabled after post_set() has been called.
582 static void prepare_set(void) __acquires(set_atomicity_lock)
587 * Note that this is not ideal
588 * since the cache is only flushed/disabled for this CPU while the
589 * MTRRs are changed, but changing this requires more invasive
590 * changes to the way the kernel boots
593 raw_spin_lock(&set_atomicity_lock);
595 /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
596 cr0 = read_cr0() | X86_CR0_CD;
600 /* Save value of CR4 and clear Page Global Enable (bit 7) */
603 write_cr4(cr4 & ~X86_CR4_PGE);
606 /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
609 /* Save MTRR state */
610 rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
612 /* Disable MTRRs, and set the default type to uncached */
613 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
616 static void post_set(void) __releases(set_atomicity_lock)
618 /* Flush TLBs (no need to flush caches - they are disabled) */
621 /* Intel (P6) standard MTRRs */
622 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
625 write_cr0(read_cr0() & 0xbfffffff);
627 /* Restore value of CR4 */
630 raw_spin_unlock(&set_atomicity_lock);
633 static void generic_set_all(void)
635 unsigned long mask, count;
638 local_irq_save(flags);
641 /* Actually set the state */
642 mask = set_mtrr_state();
648 local_irq_restore(flags);
650 /* Use the atomic bitops to update the global mask */
651 for (count = 0; count < sizeof mask * 8; ++count) {
653 set_bit(count, &smp_changes_mask);
660 * generic_set_mtrr - set variable MTRR register on the local CPU.
662 * @reg: The register to set.
663 * @base: The base address of the region.
664 * @size: The size of the region. If this is 0 the region is disabled.
665 * @type: The type of the region.
669 static void generic_set_mtrr(unsigned int reg, unsigned long base,
670 unsigned long size, mtrr_type type)
673 struct mtrr_var_range *vr;
675 vr = &mtrr_state.var_ranges[reg];
677 local_irq_save(flags);
682 * The invalid bit is kept in the mask, so we simply
683 * clear the relevant mask register to disable a range.
685 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
686 memset(vr, 0, sizeof(struct mtrr_var_range));
688 vr->base_lo = base << PAGE_SHIFT | type;
689 vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
690 vr->mask_lo = -size << PAGE_SHIFT | 0x800;
691 vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
693 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi);
694 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi);
698 local_irq_restore(flags);
701 int generic_validate_add_page(unsigned long base, unsigned long size,
704 unsigned long lbase, last;
707 * For Intel PPro stepping <= 7
708 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF
710 if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
711 boot_cpu_data.x86_model == 1 &&
712 boot_cpu_data.x86_mask <= 7) {
713 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
714 pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
717 if (!(base + size < 0x70000 || base > 0x7003F) &&
718 (type == MTRR_TYPE_WRCOMB
719 || type == MTRR_TYPE_WRBACK)) {
720 pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
726 * Check upper bits of base and last are equal and lower bits are 0
727 * for base and 1 for last
729 last = base + size - 1;
730 for (lbase = base; !(lbase & 1) && (last & 1);
731 lbase = lbase >> 1, last = last >> 1)
734 pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);
740 static int generic_have_wrcomb(void)
742 unsigned long config, dummy;
743 rdmsr(MSR_MTRRcap, config, dummy);
744 return config & (1 << 10);
747 int positive_have_wrcomb(void)
753 * Generic structure...
755 const struct mtrr_ops generic_mtrr_ops = {
757 .set_all = generic_set_all,
758 .get = generic_get_mtrr,
759 .get_free_region = generic_get_free_region,
760 .set = generic_set_mtrr,
761 .validate_add_page = generic_validate_add_page,
762 .have_wrcomb = generic_have_wrcomb,